Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same, and provides a semiconductor device capable of reducing stress from a sealing resin to a semiconductor element. A semiconductor element (1) is mounted on a wafer pad (5), and an electrode pad (6) disposed on the outer periphery of the upper surface of the semiconductor element (1) is electrically connected to a lead (4) via a wire (3). In the semiconductor element (1), there are a highly stress-sensitive element region (1a) and a low stress-sensitive element region (1b). A low stress resin film (51) is provided over the highly stress-sensitive element region (1a), and the semiconductor element (1), the low stress resin film (51), the wafer pad (5), and the lead (4) are covered with a sealing resin (2).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the demand for smaller, lighter, and higher-performance electronic devices, surface-mount packages that can mount semiconductor devices at high density on the surface of electronic devices are widely used. In analog ICs and the like, further high-precision electrical characteristics have been required in recent years. However, in mounting processes such as the packaging process, stress may be applied to semiconductor elements, resulting in variations in electrical characteristics, and the target electrical characteristics cannot be obtained. By providing a low-stress resin film having a Young's modulus smaller than that of the casting resin between the casting resin and the semiconductor element, the stress applied to the semiconductor element can be reduced (for example, refer to Patent Document 1).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2014-27266. Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] However, in an environment where requirements for variations in electrical characteristics are further tightened, it is required to further reduce the stress applied to semiconductor elements. The present invention has been made in view of this problem, and an object thereof is to provide a semiconductor device capable of reducing the stress on semiconductor elements.

[0008] Means for Solving the Problems

[0009] To solve the above problems, the following means are used in the present invention.

[0010] A semiconductor device, characterized by comprising: a semiconductor element; a wafer pad on which the semiconductor element is placed; leads disposed separately from the wafer pad; a low-stress resin film provided on the element surface of the semiconductor element; and a sealing resin covering the semiconductor element, the low-stress resin film, the wafer pad, and the leads; the low-stress resin film has a Young's modulus smaller than that of the sealing resin, and a first concave curved surface is provided on the opposite surface of the low-stress resin film that is in contact with the semiconductor element.

[0011] In addition, a manufacturing method of a semiconductor device is used. The semiconductor device includes: a semiconductor element; a wafer pad on which the semiconductor element is placed; leads that are arranged separately from the wafer pad; a low-stress resin film provided on the element surface of the semiconductor element; and a sealing resin that covers the semiconductor element, the low-stress resin film, the wafer pad, and the leads. It is characterized by consisting of the following steps: a step of preparing the wafer pad and the leads arranged separately from the wafer pad, and mounting the semiconductor element on the wafer pad; a step of forming a low-stress resin film on the element surface of the semiconductor element, where the first back surface is flat and the first main surface, which is the surface opposite to the first back surface, is a first concave curved surface; and a step of forming a sealing resin that covers the semiconductor element, the low-stress resin film, the wafer pad, and the leads.

[0012] Advantages of the Invention

[0013] By using the above means, a semiconductor device capable of reducing the stress from the sealing resin to the semiconductor element can be achieved. Description of the Drawings

[0014] Figure 1 It is a structural diagram of the semiconductor device according to the first embodiment of the present invention.

[0015] Figure 2 It is a structural diagram of the semiconductor device according to the second embodiment of the present invention.

[0016] Figure 3 It is a structural diagram of the semiconductor device according to the third embodiment of the present invention.

[0017] Figure 4 It is a structural diagram of the semiconductor device according to the fourth embodiment of the present invention.

[0018] Figure 5 It is a structural diagram of the semiconductor device according to the fifth embodiment of the present invention.

[0019] Figure 6 It is a structural diagram showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

[0020] Figure 7 It is a structural diagram showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

[0021] Figure 8 It is a structural diagram showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

[0022] Figure 9 It is a structural diagram showing the semiconductor device according to the first embodiment of the present invention and a comparative example.

[0023] Figure 10 This is a diagram showing the effects of the semiconductor device according to the first embodiment of the present invention. Detailed implementation mode

[0024] Hereinafter, the embodiments of the semiconductor device of the present invention will be described in detail.

[0025] Figure 1 This is a structural diagram of the semiconductor device according to the first embodiment of the present invention. As Figure 1 shown in the cross-sectional view of (a), the semiconductor element 1 is mounted on the wafer pad 5. Around the wafer pad 5, leads 4 are provided separately from the wafer pad 5. Moreover, an electrode pad (not shown) provided on the upper surface of the semiconductor element 1 is electrically connected to the upper surface of the lead 4 via a wire 3 as a connecting member. As the material of the wire 3, gold (Au) or copper (Cu) can be used. In addition, the electrical connection between the semiconductor element 1 and the lead 4 is not limited to the wire method, and a flip chip bonding method via bumps can also be used.

[0026] The periphery of the semiconductor element 1, the wafer pad 5, and the wire 3 is covered with a sealing resin 2, and the back surface of the wafer pad 5 on the side opposite to the mounting surface of the semiconductor element 1 is exposed from the sealing resin 2. The back surface of the wafer pad 5 is covered with a plating layer 12 and has a shape with excellent heat dissipation. The bottom surface and the outer side surface of the lead 4 are also exposed from the sealing resin 2, and the exposed surface of the bottom surface of the lead 4 is also configured to be covered with the plating layer 12. The outer side surface of the lead 4 does not protrude from the side surface of the sealing resin, and a leadless semiconductor device 21 is formed. In addition, the plating layer 12 is composed of any one metal or an alloy of a plurality of metals among lead (Pb), bismuth (Bi), tin (Sn), copper (Cu), silver (Ag), palladium (Pd), and gold (Au), and is formed by an electrolytic plating method or an electroless plating method.

[0027] On the element surface of the semiconductor element 1 that constitutes the semiconductor device 21, there is an element region 1a that is highly sensitive to stress, and a low-stress resin film 51 is provided to cover it. The back surface of the low-stress resin film 51 is in contact with the element surface of the semiconductor element 1, and the main surface, which is the opposite surface of the back surface in the thickness direction, forms a concave spherical surface 16. Moreover, the wafer pad 5, the semiconductor element 1, the low-stress resin film 51, and the lead 4 are sealed by the sealing resin 2. The upper surface of the sealing resin 2 is parallel to the element surface of the semiconductor element 1. By having such a shape, the stress from the sealing resin 2 is dispersed on the concave spherical surface 16, and the stress applied to the element region 1a that is highly sensitive to stress becomes a smaller force. Here, the Young's modulus of the low-stress resin film 51 is smaller than the Young's modulus of the sealing resin 2. In addition, although a relatively shallow concave spherical surface is illustrated in the figure, the radius of curvature of the spherical surface can also be made smaller to form a deeper concave spherical surface. Further, even if the concave spherical surface 16 is a concave curved surface having multiple curvatures, it has the same effect.

[0028] As shown in the figure, it is desirable that the height of the highest part of the main surface of the low-stress resin film 51 be the same as or less than the arc height of the wire 3. In this example, since the concave spherical surface is formed on the main surface of the low-stress resin film 51, the outermost end portion becomes the highest part, and this part is made the same as the arc height. By having such a shape, the thickness T1 from the upper surface of the sealing resin 2 to the end portion of the main surface of the low-stress resin film 51 becomes the same as the thickness of the sealing resin 2 on the wire 3. Thereby, a reduction in reliability caused by the provision of the low-stress resin film 51 is avoided.

[0029] Figure 1 (b) is a plan view seen through from the upper surface of the semiconductor device. The wafer pad 5 is disposed in the central region of the rectangular sealing resin 2. A plurality of leads 4 are disposed along one side (side surface) of the sealing resin 2, and a plurality of leads 4 are disposed along the other side (side surface) opposite to one side. Moreover, the leads 4 disposed along the side (side surface) face each other with the wafer pad 5 interposed therebetween. The semiconductor element 1 is mounted on the wafer pad 5, and the electrode pads 6 and the leads 4 disposed on the outer periphery of the semiconductor element 1 are electrically connected via the wire 3. In the semiconductor element 1, there are an element region 1a that is highly sensitive to stress and an element region 1b that is relatively less sensitive to stress and is opposite to it.

[0030] If stress such as compression and shear is applied to the semiconductor element 1 made of silicon due to the shrinkage of the molten resin in the high-temperature injection molding die when it hardens and returns to room temperature, a piezoelectric effect may occur in the silicon single crystal, causing changes in the electrical characteristics of the semiconductor integrated circuit elements formed on the surface of the semiconductor element. However, even in such semiconductor integrated circuit elements, elements with electrical characteristics that are easily changed under the influence of the piezoelectric effect are comparable to elements with high sensitivity to stress. For example, a current mirror circuit utilizes the fact that the same current flows between paired P-channel MOS transistors and operates to make the currents in the two current paths equal. However, if stress is applied to this circuit, the currents in the two current paths deviate. Such paired transistors need to have similar characteristics and are preferably formed in the element region 1a with high sensitivity to stress described above.

[0031] The low-stress resin film 51 is formed to cover the element region 1a with high sensitivity to stress, and the shape of its peripheral portion is circular. The electrode pad 6 is disposed in the outer peripheral region of the semiconductor element 1, and it is desirable that the low-stress resin film 51 does not overlap with the region where the electrode pad 6 is disposed. By having such a shape, the resin covering the wire 3 is only the sealing resin 2, and breakage of the wire 3 can be avoided.

[0032] As described above, by providing the low-stress resin film 51 over the element region 1a with high sensitivity to stress, the stress from the sealing resin 2 is dispersed in the concave spherical surface 16, and the stress applied to the element region 1a with high sensitivity to stress becomes a smaller force. As a result, it is possible to reduce the deviation of the electrical characteristic value obtained from the circuit formed in this element region 1a from its original value. Thus, by having the above structure, a semiconductor element 21 capable of reducing the stress from the sealing resin to the semiconductor element 1 can be realized. Above, an example of a DFN (Dual Flat Non-leaded) package in which leads 4 are provided on each of the two sides of the sealing resin 2 has been described, but the present technology can also be applied to a QFN (Quad Flat Non-leaded) package in which leads 4 are provided on each of the four sides of the sealing resin 2. In addition, the present technology is not limited to semiconductor devices in which the wafer pads are exposed from the sealing resin, and can also be applied to fully molded semiconductor devices.

[0033] Figure 2 is a structural diagram of a semiconductor device according to the second embodiment of the present invention and is a plan view showing various shapes of the low-stress resin film. In Figure 2 (a) shows an example of the semiconductor device 22 in which the peripheral portion of the low-stress resin film 52 is elliptical, and the element region 1a with high sensitivity to stress is disposed near the center of the region surrounded by the ellipse. In Figure 2In the semiconductor device 23 shown in (b), an example is shown in which the peripheral portion of the low-stress resin film 53 is polygonal and all interior angles are obtuse angles, and the element region 1a that is highly sensitive to stress is provided near the center of the peripheral portion of the polygon. In Figure 2 In the semiconductor device 24 shown in (c), an example is shown in which the peripheral portion of the low-stress resin film 54 is a quadrilateral with rounded corners, and the element region 1a that is highly sensitive to stress is provided near the center of the region surrounded by the quadrilateral with rounded corners. As described above, none of the shapes have an acute-angle region in a part of the peripheral portions of the low-stress resin films 52, 53, and 54. By having such a shape, a structure can be achieved in which cracks do not occur in the sealing resin 2 itself that is in contact with the peripheral portion of the low-stress resin.

[0034] Figure 3 It is a structural diagram of a semiconductor device according to the third embodiment of the present invention. Different from Figure 1 the semiconductor device 21 shown is that the acute-angle portions of the main surface ends located at the outer ends of the main surface of the low-stress resin film 55 are removed. In Figure 3 the semiconductor device 25 shown in (a), the following shape is formed: the main surface end is a plane, and a concave spherical surface 16 is provided inside the plane region. Further, in Figure 3 the semiconductor device 26 shown in (b), the upper end portion of the low-stress resin film 56 is formed into a circular shape. By having such a shape, there is no portion that protrudes from the low-stress resin films 55 and 56 with an acute angle with respect to the sealing resin 2, and the sealing resin 2 itself can be a crack-resistant structure. Even if the shape of the main surface end changes as described above, by providing the low-stress resin films 55 and 56 having the concave spherical surface 16 above the element region 1a that is highly sensitive to stress, the stress from the sealing resin 2 is dispersed obliquely downward at the concave spherical surface 16, and the stress applied to the element region 1a that is highly sensitive to stress becomes a smaller force. As a result, it is possible to avoid the electrical characteristic values obtained from the circuit formed in the element region 1a deviating from the original values, which is the same as the semiconductor device 21 of the first embodiment.

[0035] Figure 4 It is a structural diagram of a semiconductor device according to the fourth embodiment of the present invention. Different from Figure 1 the semiconductor device 21 of the first embodiment shown is that the cross-sectional shape of the upper surface of the sealing resin 2 is different. An example of a leadless semiconductor device using a lead structure different from that of the first embodiment will be described below.

[0036] The semiconductor element 1 is mounted on the wafer pad 5, and the lead 4 is separated from the wafer pad 5 and disposed around the wafer pad 5. An electrode pad (not shown) on the semiconductor element 1 is electrically connected to the lead 4 via a wire 3. The lead 4 is composed of an inner lead portion 4a and an outer lead portion 4b, and is bent so that the inner lead portion 4a becomes higher than the outer lead portion 4b. Moreover, the semiconductor element 1, the wire 3, and the lead 4 on the wafer pad 5 are sealed with a sealing resin 2. The back surface of the wafer pad 5, which is on the side opposite to the mounting surface of the semiconductor element 1, is exposed from the sealing resin 2, and this exposed surface is covered with a plating layer 12, having excellent heat dissipation. The following structure is formed: a thin-walled portion 5a with a thinner thickness of the wafer pad 5 is provided at the upper end portion of the wafer pad 5, and the sealing resin 2 wraps around the back surface of the thin-walled portion 5a, making it difficult for the wafer pad 5 to be pulled out from the sealing resin. The inner lead portion 4a of the lead 4 is sealed with the sealing resin 2, but the back surface of the wafer pad 5 and the bottom surface of the outer lead portion 4b, which are on the same plane as the bottom surface of the sealing resin 2, are exposed from the sealing resin 2 and covered with the plating layer 12.

[0037] In contrast to the first embodiment where the upper surface of the sealing resin 2 is parallel to the element surface of the semiconductor element 1, in this embodiment, a part of the upper surface of the sealing resin 2 is formed into a concave spherical surface 19. The concave spherical surface 19 provided in the sealing resin 2 is located above the concave spherical surface 16 provided in the low-stress resin film 57. When viewed from above, the concave spherical surface 19 overlaps with the concave spherical surface 16 and has the same or larger size. When the curvature of the concave spherical surface 19 of the sealing resin 2 is the same as that of the concave spherical surface 16 of the low-stress resin film 57, the thickness of the sealing resin 2 provided above the low-stress resin film 57 is uniform, and the stress applied from the sealing resin 2 to the main surface of the low-stress resin film 57 becomes almost uniform. Moreover, this stress is dispersed via the concave spherical surface 16 of the low-stress resin film 57, and the stress applied to the element region 1a, which is highly sensitive to stress, becomes a smaller force compared to the case where the upper surface of the sealing resin 2 is flat. As a result, it is possible to reduce the deviation of the electrical characteristic value obtained from the circuit formed in this element region 1a from the original value. Thus, by adopting the above structure, a semiconductor device 27 capable of reducing the stress from the sealing resin 2 to the semiconductor element 1 can be realized.

[0038] In this embodiment, a leadless semiconductor device with the lead 4 set upward has been described, but the provision of the concave spherical surface 19 in the sealing resin 2 can also be applied to Figure 1 the other leadless semiconductor device shown in Figure 4 Moreover, in

[0039] Figure 5This is a structural diagram of a semiconductor device according to the fifth embodiment of the present invention. The difference from the first embodiment is that the flip chip bonding method is used instead of the wire bonding method. In contrast to the structure in the first embodiment where the element surface of the semiconductor element 1 faces the opposite direction to the lead 4, in the present embodiment, as shown in the cross-sectional view of Figure 5 (a), the element surface of the semiconductor element 1 fixed to the lower surface of the heat sink 13 made of a metal material faces the lead 4. The bump electrodes 11 are provided on the element surface of the semiconductor element 1, and the element surface of the semiconductor element 1 faces and is electrically connected to the lead 4 via the bump electrodes 11. The bump electrodes 11 are made of metal materials such as tin (Sn) and gold (Au).

[0040] The heat sink 13 and the lead 4 sandwich the semiconductor element 1 from above and below, and the semiconductor element 1, the heat sink 13, and the lead 4 are covered with the sealing resin 2. However, the back surface of the heat sink 13, that is, the surface corresponding to the upper surface of the heat sink 13 in this figure, is exposed from the sealing resin 2 and covered with the plating 12. In addition, the following configuration is adopted: the bottom surface and the outer side surface of the lead 4 are also exposed from the sealing resin 2, and the exposed surface of the bottom surface of the lead 4 is also covered with the plating 12. A leadless semiconductor device 28 is formed in which the outer side surface of the lead 4 does not protrude from the side surface of the sealing resin. In a part of the element surface of the semiconductor element 1, there is an element region 1a that is highly sensitive to stress, and a low-stress resin film 58 is provided below it. The low-stress resin film 58 is selectively provided under the element region 1a that is highly sensitive to stress, and is not provided to overlap the entire region of the semiconductor element 1.

[0041] Figure 5 (b) is a plan view of the semiconductor device 28 from the bottom side. The plating 12 is not shown. The heat sink 13 made of copper is disposed in the central region of the rectangular sealing resin 2. A plurality of leads 4 are disposed along one side (side surface) of the sealing resin 2, and a plurality of leads 4 are disposed along the other side (side surface) opposite to the one side. Moreover, the leads 4 disposed along the side (side surface) face each other with the heat sink 13 as the center. The semiconductor element 1 is fixed to the heat sink 13, and the pad electrodes 11 disposed on the outer periphery of the semiconductor element 1 overlap and are electrically connected to the leads 4. In the semiconductor element 1, there are an element region 1a that is highly sensitive to stress and an element region 1b that is relatively less sensitive to stress relative to it. For example, a current mirror circuit uses the same current to flow between paired P-channel MOS transistors and uses an action to make the currents in the two current paths equal, but if stress is applied to this circuit, the currents in the two current paths deviate. Such paired transistors need to have similar characteristics and are preferably formed in the above-mentioned element region 1a that is highly sensitive to stress.

[0042] The low-stress resin film 58 is formed to cover the element region 1a that is highly sensitive to stress, and the shape of its peripheral portion is circular. Moreover, the element region 1a that is highly sensitive to stress is provided near the center of the region surrounded by this circle. The pad electrode 11 is disposed in the outer peripheral region of the semiconductor element 1, and the lead 4 overlaps with the pad electrode 11. Therefore, the low-stress resin film 58 does not overlap with the region where the pad electrode 11 is disposed. As described above, by providing the low-stress resin film 58 having the concave spherical surface 16 on the main surface under the element region 1a that is highly sensitive to stress, the stress applied to the element region 1a can be reduced. As a result, the deviation of the electrical characteristic value obtained from the circuit formed in the element region 1a from the original value can be reduced. Thus, by adopting the above structure, the semiconductor device 28 capable of reducing the stress from the sealing resin to the semiconductor element 1 can be realized. Above, the example of the DFN (Dual Flat Non-leaded) package in which the leads 4 are provided on each of the two side surfaces of the sealing resin 2 has been described, but the present technology can also be applied to the QFN (Quad Flat Non-leaded) package in which the leads 4 are provided on each of the four side surfaces of the sealing resin 2. In addition, the planar shape and cross-sectional shape described in Figures 1 to 3 can be applied to the low-stress resin film.

[0043] Figure 6 is a structural diagram showing a manufacturing method of a semiconductor device according to a first embodiment of the present invention. First, as shown in Figure 6 (a), a wafer pad 5 and a lead frame 7 in which a plurality of leads 4 are separately arranged around the wafer pad 5 are prepared. The lead frame 7 has a rectangular wafer pad 5 and a plurality of leads 4 separately arranged from the wafer pad 5 as a unit 7a, and has a shape with a plurality of such units 7a. The unit 7a illustrated by the dotted line is surrounded by a frame 7b, the lead 4 is connected to the frame 7b, and the wafer pad 5 is connected to the frame 7b via a suspension lead 7c. In addition, the lead frame 7 is mainly composed of copper material. Figure 6 (b) is a cross-sectional view along the X-X line shown in Figure 6 (a). At this stage, the leads 4 of adjacent units 7a are coupled to each other via the frame 7b. Next, as shown in Figure 6 (c), the semiconductor element 1 is mounted on the wafer pad 5, and the electrode pads (not shown) provided on the semiconductor element 1 are electrically connected to the leads 4 via the wires 3.

[0044] Figure 7 is a structural diagram showing a manufacturing method of a semiconductor device according to a first embodiment of the present invention that continues Figure 6 . As shown in Figure 7As shown in (a), the low-stress resin film 51 is adhered to the element surface of the semiconductor element 1 by thermocompression bonding. The low-stress resin film 51 is a pre-molded film-shaped low-stress resin film 51, having a flat back surface and a concave spherical main surface. Incidentally, the Young's modulus of the low-stress resin film 51 is 0.1 GPa, which is an extremely low value compared to the Young's modulus of 20 GPa of the sealing resin 2.

[0045] Next, as shown in Figure 7 (b), a mold 8 for sealing the lead frame 7 on which the semiconductor element 1 is mounted is prepared. The mold 8 is composed of an upper mold 8a and a lower mold 8b, and has a cavity 9 therebetween. Then, the sealing resin 2 is caused to flow into the cavity 9, and the semiconductor element 1, the chip pad 5, the wire 3, and the lead 4 are sealed with the sealing resin 2.

[0046] As shown in Figure 7 (c), the sealed body 15 is taken out from the mold 8, and a plating layer 12 is formed on the back surface of the chip pad 5 and the bottom surface of the lead 4. Thereafter, the sealed body 15 is cut along the frame 7b using a rotary blade 14. At this time, by making the width of the rotary blade 14 larger than the width of the frame 7b, the frame 7b can be completely removed. In addition, the cutting direction based on the rotary blade 14 can be either the direction from the bottom surface of the sealed body 15 upward or the direction from the top surface downward.

[0047] After cutting, the separated semiconductor devices 21 as shown in Figure 8 can be obtained. Figure 8 (a) is a cross-sectional view, Figure 8 (b) is a plan view, and is illustrated as an aggregate of a plurality of semiconductor devices 21. In addition, in the above, a method of obtaining a plurality of semiconductor devices from one cavity of the mold has been described, but a sealing method of obtaining one semiconductor device from one cavity can also be adopted.

[0048] Next, use Figure 9 and Figure 10 to explain the effects of the present embodiment.

[0049] Figure 9 is a structural diagram showing the semiconductor device and the comparative example according to the first embodiment of the present invention. In Figure 9 (a), the semiconductor device A according to the first embodiment of the present invention is illustrated, and in Figure 9 (b), the semiconductor device B as a comparative example is illustrated. In Figure 9(c) The semiconductor device C shown in the figure is a comparative example. In semiconductor device A, a low-stress resin film 10a with a concave spherical main surface 16 is placed on the element surface of semiconductor element 1, and an electrode pad (not shown) provided on semiconductor element 1 is electrically connected to lead 4 via a wire (not shown). Moreover, it is configured such that semiconductor element 1, low-stress resin film 10a, chip pad 5, and lead 4 are sealed by sealing resin 2. In addition, in this figure, the wire that electrically connects the electrode pad provided on semiconductor element 1 and lead 4 is not shown. The thickness T2 of the sealing resin 2 between the element surface of semiconductor element 1 and the upper surface of the sealing resin 2 is 0.17 mm, the thickness of the low-stress resin film 10a on the element region 1a that is highly sensitive to stress is 0.1 mm, the thickness at the main surface end of the low-stress resin film 10a is 0.135 mm, the width L1 of the low-stress resin film 10a is 0.9 mm, and the radius of curvature of the concave spherical surface is 2.9 mm. Additionally, the Young's modulus of the low-stress resin film 51 is 0.1 GPa, and the Young's modulus of the sealing resin 2 is 20 GPa.

[0050] In semiconductor device B, a low-stress resin film 10b with a flat main surface 17 is placed on the element surface of semiconductor element 1, and an electrode pad (not shown) provided on semiconductor element 1 is electrically connected to lead 4 via a wire (not shown). Moreover, it is configured such that semiconductor element 1, low-stress resin film 10b, chip pad 5, and lead 4 are covered by sealing resin 2. The thickness T2 of the sealing resin 2 between the element surface of semiconductor element 1 and the upper surface of the sealing resin 2 is 0.17 mm, the thickness of the low-stress resin film 10b on the element region 1a that is highly sensitive to stress is 0.1 mm, the thickness at the main surface end of the low-stress resin film 10b is 0.135 mm, and the width L1 of the low-stress resin film 10b is 0.9 mm. Additionally, the Young's modulus of the low-stress resin film 51 is 0.1 GPa, and the Young's modulus of the sealing resin 2 is 20 GPa.

[0051] In the semiconductor device C, a low-stress resin film 10c with a convex spherical main surface 18 is placed on the element surface of the semiconductor element 1, and the electrode pads (not shown) provided on the semiconductor element 1 and the lead 4 are electrically connected via a wire (not shown). Further, the semiconductor element 1, the low-stress resin film 10c, the chip pad 5, and the lead 4 are covered with the sealing resin 2. The thickness T2 of the sealing resin 2 between the element surface of the semiconductor element 1 and the upper surface of the sealing resin 2 is 0.17 mm, the thickness of the low-stress resin film 10c on the element region 1a which is highly sensitive to stress is 0.1 mm, the width L1 of the low-stress resin film 10c is 0.9 mm, and the radius of curvature of the convex spherical surface 18 is 1.6 mm. Further, the Young's modulus of the low-stress resin film 51 is 0.1 GPa, and the Young's modulus of the sealing resin 2 is 20 GPa. As described above, the semiconductor devices A, B, and C have low-stress resin films 10a, 10b, and 10c. Except for the different main surface shapes, the other dimensions are the same.

[0052] For each of the above semiconductor devices A, B, and C, the results of checking the stress applied to the element region 1a which is highly sensitive to stress are shown in Figure 10 A stress of 27.5 MPa is applied to the element region 1a which is highly sensitive to stress in the semiconductor device A, a stress of 39.8 MPa is applied in the semiconductor device B, and a stress of 51.4 MPa is applied in the semiconductor device C. Thus, it can be seen that the manner of applying stress to the semiconductor element 1 varies significantly depending on the shape of the main surface of the low-stress resin film. A smaller stress is applied when the main surface is a concave spherical surface 16 than when it is a flat surface 17, and a larger stress is applied when the main surface is a convex spherical surface 18 than when it is a flat surface 17.

[0053] When forming a low-stress resin film on the semiconductor element 1, a method of dropping a liquid low-stress resin is generally used, and its main surface shape often becomes a convex spherical surface 18 as in the semiconductor device C. If it is such a shape, the stress from the sealing resin 2 becomes concentrated in the semiconductor element 1 via the convex spherical surface 18, particularly in the element region 1a which is highly sensitive to stress and is disposed near the center thereof, and a larger stress is applied than when the main surface is a flat surface 17. On the other hand, in the semiconductor device A having the low-stress resin film 10a with a concave spherical main surface 16, the stress from the sealing resin 2 is dispersed in the concave spherical surface 16, and it is considered that a smaller stress is applied than when the main surface is a flat surface 17.

[0054] As described above, a semiconductor device can be obtained in which by making the main surface of the low-stress resin film a concave spherical surface, the stress applied to the semiconductor element 1 can be significantly reduced, and even when the semiconductor element is sealed, the variation in electrical characteristics is small.

[0055] Symbol Explanation

[0056] 1 Semiconductor element

[0057] 1a Element region with high sensitivity to stress

[0058] 1b Element region with low sensitivity to stress

[0059] 2 Sealing resin

[0060] 3 Lead wire

[0061] 4 Lead

[0062] 4a Inner lead portion

[0063] 4b Outer lead portion

[0064] 5 Chip pad

[0065] 5a Thin wall portion

[0066] 6 Electrode pad

[0067] 7 Lead frame

[0068] 7a Unit

[0069] 7b Frame

[0070] 7c Suspension lead

[0071] 8 Mold

[0072] 8a Upper mold

[0073] 8b Lower mold

[0074] 9 Cavity

[0075] 10a, 10b, 10c Low stress resin film

[0076] 11 Bump electrode

[0077] 12 Coating

[0078] 13 Heat sink

[0079] 14 Rotary blade

[0080] 15 Sealing body

[0081] 16 Concave spherical surface

[0082] 17 Plane

[0083] 18 Convex spherical surface

[0084] 19 Concave spherical surface

[0085] 21, 22, 23, 24, 25, 26, 27, 28 Semiconductor device

[0086] 51, 52, 53, 54, 55, 56, 57, 58 Low-stress resin films

[0087] A, B, C Semiconductor devices

[0088] T1, T2, T3 Thickness

[0089] L1 Length.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor element having an element region on an element surface that is highly sensitive to stress; A wafer pad on which the semiconductor element is placed; Leads disposed separately from the wafer pad; A low-stress resin film provided to cover the element region; And A sealing resin that covers the semiconductor element, the low-stress resin film, the wafer pad, and the leads; The low-stress resin film has a Young's modulus smaller than that of the sealing resin, and has a first concave curved surface on the opposite surface of the surface of the low-stress resin film that is in contact with the semiconductor element.

2. The semiconductor device according to claim 1, wherein In a top view, the peripheral portion of the low-stress resin film is polygonal, and all of its interior angles are obtuse angles.

3. The semiconductor device according to claim 1, wherein In a top view, the peripheral portion of the low-stress resin film is circular or elliptical.

4. The semiconductor device according to claim 1, wherein The element surface of the semiconductor element is parallel to the upper surface of the sealing resin.

5. The semiconductor device according to claim 2, wherein The element surface of the semiconductor element is parallel to the upper surface of the sealing resin.

6. The semiconductor device according to claim 3, wherein, The element surface of the semiconductor element is parallel to the upper surface of the sealing resin.

7. The semiconductor device according to claim 1, wherein The upper surface of the sealing resin has a second concave curved surface.

8. The semiconductor device according to claim 2, wherein, The upper surface of the sealing resin has a second concave curved surface.

9. The semiconductor device according to claim 3, wherein The upper surface of the sealing resin has a second concave curved surface.

10. A method for manufacturing a semiconductor device, the semiconductor device comprising: A semiconductor element having an element region on an element surface that is highly sensitive to stress; A wafer pad on which the semiconductor element is placed; Leads disposed separately from the wafer pad; A low-stress resin film provided to cover the element region; And A sealing resin that covers the semiconductor element, the low-stress resin film, the wafer pad, and the leads; Characterized by comprising the following steps: A step of preparing the wafer pad and the leads disposed separately from the wafer pad, and mounting the semiconductor element on the wafer pad; A step of forming a low-stress resin film on the element surface of the semiconductor element, the first back surface of which is flat and the first main surface, which is the surface opposite to the first back surface, is a first concave curved surface; and A step of forming a sealing resin that covers the semiconductor element, the low-stress resin film, the wafer pad, and the leads.

11. The manufacturing method of the semiconductor device according to claim 10, characterized in that, In the step of forming the low-stress resin film on the element surface of the semiconductor element, a method of adhering a film-shaped low-stress resin film is used.

Images