Vertical field effect transistor (VFET) devices and methods of manufacturing the same

Abstract

A vertical field effect transistor (VFET) device and a method of fabricating the same are provided. The method includes: providing an intermediate VFET structure including a substrate and, on the substrate, fin structures, gate structures, and a bottom epitaxial layer, the gate structures formed on the fin structures and the bottom epitaxial layer, respectively, each of the fin structures including a fin and a mask thereon; filling an interlayer dielectric (ILD) layer between and on sides of the gate structures; forming an ILD protection layer on the ILD layer, respectively, the ILD protection layer having an upper portion and a lower portion and including a material that prevents oxide loss at the ILD layer; removing the fin structures, the gate structures, and the ILD protection layer above the lower portion of the ILD protection layer; removing the mask of the fin structures and a top portion of the gate structures such that a top surface of the fin structures and a top surface of the gate structures after the removing are lower than a top surface of the ILD layer; forming a top spacer on the gate structures whose top portions are removed and a top epitaxial layer on the fin structures whose masks are removed; and forming a contact structure connected to the top epitaxial layer.

Description

TECHNICAL FIELD

[0001] Apparatuses and methods consistent with example embodiments of the present inventive concepts relate to structures of vertical field effect transistors (VFETs) and methods of manufacturing the same. BACKGROUND

[0002] VFETs are fabricated or manufactured by forming vertical fins for channels for current flow on a semiconductor substrate, bottom source / drain (S / D) regions and top S / D regions under and on the vertical fins, and gate structures on sidewalls of the vertical fins. Thus, unlike lateral current flow in prior art planar FETs or finFETs, current flows in a direction perpendicular to the semiconductor substrate in VFETs.

[0003] Since VFET devices formed by VFETs are known to have various advantages, including high-density structures superior to planar FET or finFET devices, more improved structures and methods of manufacturing VFET devices have been sought. SUMMARY

[0004] Various embodiments of the present inventive concepts can provide improved methods for manufacturing VFET devices and VFET devices manufactured thereby.

[0005] According to an aspect of an example embodiment, a method for manufacturing a VFET device can include the steps of: (a) providing an intermediate VFET structure including a substrate and fin structures, gate structures, and a bottom epitaxial layer on the substrate, the gate structures being formed on the fin structures and the bottom epitaxial layer, respectively, each of the fin structures including a fin and a mask thereon; (b) filling an interlayer dielectric (ILD) layer between and on sides of the gate structures; (c) forming an ILD protective layer on the ILD layer, respectively, the ILD protective layer having an upper portion and a lower portion and including a material that prevents oxide loss at the ILD layer; (d) removing the fin structures, the gate structures, and the ILD protective layer above the lower portion of the ILD protective layer; (e) removing the masks of the fin structures and the top portions of the gate structures such that top surfaces of the fin structures and top surfaces of the gate structures after the removing are lower than a top surface of the ILD layer; (f) forming a top spacer on the gate structures whose top portions are removed and a top epitaxial layer on the fin structures whose masks are removed; and (g) forming a contact structure connected to the top epitaxial layer.

[0006] According to an aspect of an example embodiment, there is provided a VFET device that can include a plurality of VFETs formed on a substrate; an interlayer dielectric (ILD) layer formed between and on sides of gate structures of the VFETs; a contact structure formed on top source / drain regions of the VFETs; and a contact structure ILD layer formed on sides of the contact structure, wherein an ILD protective layer formed on a top surface of the ILD layer on the sides of the gate structures includes a silicon nitride layer.

[0007] According to an aspect of an example embodiment, there is provided a VFET device that can include a plurality of VFETs formed on a substrate; an interlayer dielectric (ILD) layer formed between and on sides of gate structures of the VFETs; a contact structure formed on top source / drain regions of the VFETs; and a contact structure ILD layer formed on sides of the contact structure, wherein an ILD protective layer formed on a top surface of the ILD layer includes a dielectric material having an etch selectivity of 1 :3 or greater relative to either of silicon oxide and silicon nitride. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other aspects of the present inventive concept will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings, in which:

[0009] Figures 1A-1I A cross-sectional side view of a method of fabricating a VFET device according to an embodiment is shown;

[0010] Figures 2A-2I A cross-sectional side view of a method of fabricating a VFET device according to an embodiment is shown;

[0011] Figures 3A-3C A cross-sectional side view of a method of fabricating a VFET device according to an embodiment is shown;

[0012] Figures 4A-4F A cross-sectional side view of a method of fabricating a VFET device according to an embodiment is shown; and

[0013] Figure 5 An electronic device including a VFET device according to an embodiment is shown. DETAILED DESCRIPTION

[0014] Various embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. These embodiments are merely exemplary and can be embodied in many different forms and should not be interpreted as limiting the inventive concept. Rather, these embodiments are provided as illustrative examples so that a thorough and complete disclosure of the inventive concept will be achieved and fully conveyed to those skilled in the art. In the drawings, the sizes and relative sizes of the various layers and regions can be exaggerated for clarity. Accordingly, the drawings are not necessarily drawn to scale, and some features can be exaggerated to show details that would otherwise be difficult to see. Thus, the particular structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to employ the inventive concept in a variety of ways.

[0015] It is not excluded that an embodiment provided herein is associated with one or more features of another example or another embodiment provided herein or not provided herein but consistent with the inventive concept. For example, even if a matter described in a particular embodiment is not described in a different embodiment, it can be understood that the matter is relevant or incorporated with the different embodiment unless otherwise mentioned in its description.

[0016] For purposes of the description hereinafter, the terms "upper", "lower", "top", "bottom", "left", and "right", and derivatives thereof shall relate to the disclosed structures as they are oriented in the drawings. The same reference numbers in different drawings can identify the same structural components or elements in the figures.

[0017] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present.

[0018] The term "and / or", as used herein, includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of", when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" is intended to mean A, B, C, A-B, A-C, B-C, or A-B-C. Expressions such as "at least one of", when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0020] Figures 1A-1I A cross-sectional side view of a method of fabricating a VFET device is shown in accordance with an embodiment.

[0021] Figure 1A An intermediate VFET structure 10 is shown in which a plurality of fin structures 102-1, 102-2, 102-3, and 102-4 are formed vertically on a substrate 101. Each of the fin structures 102-1 to 102-4 includes a fin 102F and a mask 102M formed thereon. The intermediate VFET structure 10 also includes a bottom epitaxial layer 103 formed by epitaxially growing a semiconductor layer on the substrate 101 and incorporating impurities in the semiconductor layer. The material forming the bottom epitaxial layer 103 can be similar to the material forming the substrate 101. When the intermediate VFET structure 10 is completed, the impurities incorporated into the bottom epitaxial layer 103 can be boron to form a p-type VFET or can be phosphorus, arsenic, indium, or a combination thereof to form an n-type VFET. The bottom epitaxial layer 103 is provided to form a bottom source / drain region of a VFET formed from the intermediate VFET structure 10.

[0022] Figure 1A A bottom spacer 104, a dielectric layer 105, and a shallow trench isolation (STI) structure 106 are further shown. The bottom spacer 104 is deposited on a top surface of the bottom epitaxial layer 103 between the fin structures 102-1 to 102-4 and on sides of the fin structures 102-1 to 102-4 to insulate the bottom epitaxial layer 103 from adjacent elements, such as a gate structure to be discussed later. The bottom spacer 104 can include a low-k dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), silicon oxynitride (SiON), silicon boron carbon nitride (SiBCN), silicon oxygen carbon nitride (SiOCN), or a combination thereof, but is not limited thereto. The bottom spacer 104 can be formed on the bottom epitaxial layer 103 by at least one of methods such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), anisotropic deposition, etc., but is not limited thereto.

[0023] In Figure 1AIn some embodiments, the dielectric layer 105 can be formed from a material such as SiN and deposited by a method such as atomic layer deposition (ALD) (but not limited to) along the outer surfaces of the fin structures 102-1 to 102-4, the top surface of the bottom spacer 104 between the fin structures 102-1 to 102-4, the side surfaces of the bottom spacer 104, the side surfaces of the bottom epitaxial layer 103, and the side surfaces of the substrate 101 to prevent damage such as oxidation of these elements from a subsequent STI process that uses an oxide material to form the STI structure 106. The STI structure 106 is provided on both sides of the intermediate VFET structure 10 and the dielectric layer 105 is formed therebetween to insulate the fin structures 102-1 to 102-4 from another set of fin structures adjacent to the fin structures 102-1 to 102-4. The STI structure 106 can be formed from a dielectric oxide material such as SiO, silicon dioxide (SiO2), silicon oxynitride (SiON), or a combination thereof, but not limited to, that is etch selective with respect to the dielectric layer 105. x N y ) or a combination thereof, but not limited to.

[0024] Figure 1B It is shown that after the dielectric layer 105 is lifted off (not shown) from the outer surfaces of the fin structures 102-1 to 102-4 and the top surface of the bottom spacer 104, a plurality of gate structures 107 are formed thereon and on the top surface of the STI structure 106. The formation of the gate structures 107 can be performed by a method such as ALD (but not limited to). Each gate structure 107 can include a conductor layer 107-1 formed from a metal or a metal compound such as Cu, Al, Ti, Ta, W, Co, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, or a combination thereof, but not limited to, and a high-k layer 107-2 formed from a metal oxide material or a metal silicate of a metal such as Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof, but not limited to.

[0025] Figure 1C It is shown that after the dielectric layer 105 is lifted off (not shown) from the outer surfaces of the fin structures 102-1 to 102-4 and the top surface of the bottom spacer 104, a plurality of gate structures 107 are formed thereon and on the top surface of the STI structure 106. The formation of the gate structures 107 can be performed by a method such as ALD (but not limited to). Each gate structure 107 can include a conductor layer 107-1 formed from a metal or a metal compound such as Cu, Al, Ti, Ta, W, Co, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, or a combination thereof, but not limited to, and a high-k layer 107-2 formed from a metal oxide material or a metal silicate of a metal such as Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof, but not limited to. Figure 1BThe gate structure 107 formed in the process is etched to expose the fin structures 102-1 to 102-4, the bottom spacer 104 between the fin structures 102-1 to 102-4, and the top surface of the STI structure 106. Subsequently, a gate encapsulation pad 108 is conformally deposited around the gate structure 107 along the exposed top surfaces of the fin structures 102-1 to 102-4, the outer surface of the gate structure 107, the top surface of the bottom spacer 104 between the fin structures 102-1 to 102-4, and the top surface of the STI structure 106. The gate encapsulation pad 108 may be formed of a dielectric material such as SiN, SiCN, and / or SiBCN (but not limited to these).

[0026] Figure 1D An interlayer dielectric (ILD) layer 109 is shown to surround a gate encapsulation pad 108 surrounding a gate structure 107. Then, the ILD layer 109, together with fin structures 102-1 to 102-4, the gate structure 107, and the gate encapsulation pad 108, is planarized such that, after planarization, the top surfaces of the ILD layer 109, the gate structure 107, and the fin structures 102-1 to 102-4 are substantially coplanar. Planarization can be performed by chemical mechanical planarization (CMP) and / or dry etching, but is not limited thereto. The ILD layer 109 can be made of materials including SiO2, Si3N4, SiO2, etc. x N y Materials of SiC, SiCO, SiCOH or SiCH compounds (but not limited to) are formed to insulate the gate structures 107 from each other and from another set of gate structures.

[0027] Figure 1E It shows in Figure 1D After planarization, the remaining fin structures 102-1 to 102-4 and gate structure 107 are etched to remove at least the mask 102M from the fin structures 102-1 to 102-4 and the top of the gate structure 107 corresponding to the mask 102M, thereby leaving the ILD layer 109 and the gate encapsulation pad 108 in the form of protrusions between and on the sides of the gate structure 107. Note that in order to form the top spacer and the top epitaxial layer on the gate structure 107 and the fin structures 102-1 to 102-4 respectively in a later step, only the fin structures 102-1 to 102-4 and the gate structure 107 are etched. Therefore, after etching, the top surface of the gate structure 107 and the top surface of the fin structures 102-1 to 102-4 are lower than the top surface of the ILD layer 109 and the top surface of the gate encapsulation pad 108 therebetween.

[0028] Figure 1FIt is shown that only the gate structures 107 among the gate structures 107 and the fin structures 102-1 to 102-4 are further etched to provide space for the top spacers 110 to be deposited thereon. After the top spacers 110 are deposited on the top surfaces of the etched gate structures 107, the top surfaces of the top spacers 110 and the top surfaces of the fin structures 102-1 to 102-4 can become substantially coplanar. The top spacers 110 can be formed of a material similar to or different from that of the bottom spacers 104 to electrically isolate the gate structures 107 from the respective top epitaxial layers described below. The top spacers 110 can be deposited by using at least one of CVD, PECVD, and ALD, but are not limited thereto.

[0029] Referring back to the above description Figure 1E and Figure 1F of the embodiments described above, the top surfaces of the gate structures 107 and the top surfaces of the fin structures 102-1 to 102-4 can become substantially coplanar after etching Figure 1E ) is performed, and then the gate structures 107 are further etched to provide space for the top spacers 110 Figure 1F ) to be deposited thereon. According to an embodiment, the etching steps performed in Figure 1E and Figure 1F may not be two steps as described above, but can be a single continuous step in which the gate structures 107 are further etched down or over-etched than the fin structures 102-1 to 102-4.

[0030] Figure 1G It is shown that the top epitaxial layers 111 are formed by epitaxially growing semiconductor layers on the fin structures 102-1 to 102-4 from which the mask 102M is removed and incorporating impurities in the semiconductor layers. The top epitaxial layers 111 will become top source / drain regions of the VFETs to be formed from the intermediate VFET structure 10.

[0031] Figure 1H It is shown that the contact structure landing pad 112 is deposited to cover the top and side surfaces of the top epitaxial layers 111, and the contact structure ILD layer 113 is deposited on the contact structure landing pad 112.

[0032] Figure 1I It is shown that the contact structure ILD layer 113 and the contact structure landing pad 112 are etched from top to bottom on the top epitaxial layers 111 to open the top surfaces of the top epitaxial layers 111, thereby forming the top source / drain regions 111-1 of the VFETs. Next, the contact pad 114 and the contact structure 115 formed of a metal or a compound thereof and connecting the top source / drain regions 111-1 to external elements are deposited to form the VFET devices.

[0033] However, the above steps of fabricating the VFET structure have a disadvantage that oxide loss occurs during the step of forming the ILD layer 109 Figure 1D ), the step of removing the gate structure 107 including the high-k layer 107-2 Figure 1E ), the step of over-etching the gate structure 107 to deposit the top spacers 110 thereon Figure 1F ), and the step of forming the top epitaxial layer 111 Figure 1G ). The oxide loss can cause a decrease in the height of the ILD layer 109, thereby decreasing an ILD bucket volume Figure 1G ), which subsequently causes an overgrowth of the top epitaxial layer 111 and merging of the overgrown top epitaxial layer 111 with each other Figures 1G-1I , which should be prevented in order for the top epitaxial layer 111 to be insulated from each other. In addition, a difference between a level of a top surface of the top source / drain region 111-1 and a level of a top surface of the ILD layer 109 causes a difference between a level of a bottom surface of the contact structure 115 and a level of a bottom surface of the contact structure ILD layer 113 left on sides of the contact structure 115, which can cause a loss of a process margin, thereby making it difficult to form the VFET.

[0034] Therefore, in order to solve the above disadvantage, another method of fabricating a VFET device is introduced below.

[0035] Figures 2A-2I A cross-sectional side view of a method of fabricating a VFET structure according to an embodiment is shown.

[0036] In the present embodiment, the same steps shown in the previous embodiments with reference to Figure 1A and Figure 1B are performed to produce an intermediate VFET structure 20 shown in Figure 2A , which can be the same as the intermediate VFET structure 10 shown in Figure 1C . Therefore, a repeated description thereof is omitted here. In addition, the intermediate VFET structure 20 according to the present embodiment includes the same elements as those of the intermediate VFET structure 10, and therefore, a repeated description thereof is also omitted here. Therefore, the intermediate VFET structure 20 shown in Figure 2A includes a substrate 201, a plurality of fin structures 202-1, 202-2, 202-3, and 202-4 each including a fin 202F and a mask 202M, a bottom epitaxial layer 203, a bottom spacer 204, a dielectric layer 205, an STI structure 206, a gate structure 207 each including a conductor layer 207-1 and a high-k layer 207-2, and a gate capping liner 208.

[0037] Figure 2BIt is shown that an ILD layer 209-1 is filled or deposited between and on the sides of the gate structures 207 surrounded by the gate encapsulation spacers 208, and then the ILD layer 209-1 is partially etched back to provide or define shallow trenches 209-2 above the partially etched back ILD layer 209-1 and between and on the sides of the gate structures 207 surrounded by the gate encapsulation spacers 208, in a next step a layer of ILD protective layer 209-3 is deposited or formed along the gate encapsulation spacers 208. The partial etch back of the ILD layer 209-1 can stop at a level above the boundary between the fin 202F and the mask 202M such that the top surface of the ILD layer 209-1 is located above the boundary between the fin 202F and the mask 202M. However, according to an embodiment, instead of the deposition and partial etch back, the ILD layer 209-1 can be only filled or deposited to a level above the boundary between the fin 202F and the mask 202M.

[0038] Figure 2C It is shown that in order to prevent the height loss of the ILD layer 209-1 that can occur in subsequent steps of VFET fabrication as described in previous embodiments, the ILD protective layer 209-3 is conformally deposited on the top surface of the etched back ILD layer 209-1 and the gate encapsulation spacers 208 exposed above the etched back ILD layer 209-1. To this end, the ILD protective layer 209-3 can be a bilayer formed of a first layer 209-3N (such as SiN layer) and a second layer 209-3O (such as SiO2 layer) formed on the first layer 209-3N. For example, the ILD protective layer 209-3 can be a SiN / SiO2 bilayer. However, the present inventive concept is not limited to the SiN and SiO2 bilayers, and thus, a bilayer formed of different materials (e.g., a bilayer of silicon nitride layer and oxide layer) that can prevent the height loss of the ILD layer 209-1 can be used instead of the SiN and SiO2 bilayers. x N x x x N x x x N x x

[0039] Figure 2D ​​​​​​The diagram shows that fin structures 202-1 to 202-4 and gate structure 207, along with the gate encapsulation pad 208 covered by the ILD protective layer 209-3, are planarized horizontally above the lower portion 209-3L of the ILD protective layer 209-3, such that after planarization, the top surfaces of the lower portion 209-3L of the ILD protective layer 209-3, the top surface of the gate encapsulation pad 208, the top surface of the gate structure 207, and the top surfaces of the fin structures 202-1 to 202-4 are substantially coplanar with each other. The planarization used herein can be performed by CMP and / or dry etching, but is not limited to these methods. Here, the lower portion 209-3L of the ILD protective layer 209-3 may still include portions of the first layer 209-3N and the second layer 209-3O of the ILD protective layer 209-3.

[0040] Figure 2E Etching in Figure 2D After planarization, the fin structures 202-1 to 202-4 and the gate structure 207 are retained. At least the mask 202M and the top of the gate structure 207 corresponding to the mask 202M are removed from the fin structures 202-1 to 202-4, leaving the ILD layer 209-1, the lower portion 209-3L of the ILD protective layer 209-3, and the gate encapsulation pad 208 remaining between and on the sides of the gate structures 207 in a protruding form. Note that in order to form the top spacer and top epitaxial layer on the gate structure 207 and the fin structures 202-1 to 202-4 respectively in later steps, only the fin structures 202-1 to 202-4 and the gate structure 207 are etched. Therefore, after etching, the top surface of the gate structure 207 and the top surface of the fin structures 202-1 to 202-4 are lower than the top surface of the ILD layer 209-1.

[0041] Figure 2F The diagram shows only the gate structure 207 further etched, along with one of the fin structures 202-1 to 202-4, to provide space for the top spacer 210 to be deposited thereon. After the top spacer 210 is deposited on the top surface of the etched gate structure 207, the top surface of the top spacer 210 and the top surfaces of the fin structures 202-1 to 202-4 can become substantially coplanar. The top spacer 210 can be formed of a material similar to or different from that of the bottom spacer 204 to provide electrical isolation between the gate structure 207 and the respective top epitaxial layers described below. The top spacer 210 can be deposited using at least one of CVD, PECVD, and ALD, but is not limited thereto.

[0042] Refer back to the reference above Figure 2E and Figure 2F The described implementation method involves etching ( Figure 2Etop surfaces of the fin structures 202-1 to 202-4 can be substantially coplanar, then the gate structure 207 is further etched to provide space for the top spacers 210 Figure 2F The etching steps performed in Figure 2E and Figure 2F may not be two steps as described above, but can be a single continuous step in which the gate structure 207 is further etched down or over-etched than the fin structures 202-1 to 202-4.

[0043] Figure 2G The formation of the top epitaxial layer 211 is shown by epitaxially growing a semiconductor layer on the fin structures 202-1 to 202-4 from which the mask 202M has been removed and incorporating impurities in the semiconductor layer. The top epitaxial layer 211 will become the top source / drain region of the VFET to be formed from the intermediate VFET structure 20.

[0044] Here, note that the step of forming the top epitaxial layer 111 in Figure 1G is different from the step of forming the top epitaxial layer 211 in the present embodiment in Figure 2G due to the ILD protection layer 209-3 including the first layer 209-3N. Specifically, after the deposition of the top spacers 210 in the step of Figure 2F due to the oxide loss that occurs during the step of over-etching the gate structure 207 to deposit the top spacers 210 thereon ( Figure 2F ) and the step of forming the top epitaxial layer 211 ( Figure 2G ), the second layers 209-3O above and to the sides of the first layer 209-3N that remain in the lower portion 209-3L of the ILD protection layer 209-3, and the first layers 209-3N formed to the sides of these second layers 209-3O are removed as shown in Figure 2G . However, at least the first layer 209-3N below the second layers 209-3O in the lower portion 209-3L of the ILD protection layer 209-3 can withstand the oxide loss to prevent the reduction of the height and the bucket volume of the ILD layer 209-1 formed thereunder. Thus, the ILD protection layer 209-3 can enable the prevention of overgrowth of the top epitaxial layer 211 above the ILD layer 209-1 and control the top surface of the top epitaxial layer 211 to be substantially coplanar with the top surface of the first layer 209-3N that remains in the lower portion 209-3L of the ILD protection layer 209-3 after the formation of the top epitaxial layer 211.

[0045] Figure 2HIt is shown that after forming the top epitaxial layer 211, a contact structure landing pad 212 is deposited on the top surface of the top epitaxial layer 211 and the top surface of the first layer 209-3N included in the lower portion 209-3L of the ILD protection layer 209-3 remaining in the lower portion 209-3L of the ILD protection layer 209-3, and a contact structure ILD layer 213 is deposited on the contact structure landing pad 212.

[0046] Figure 2I It is shown that after forming the top epitaxial layer 211, a contact structure landing pad 212 is deposited on the top surface of the top epitaxial layer 211 and the top surface of the first layer 209-3N included in the lower portion 209-3L of the ILD protection layer 209-3 remaining in the lower portion 209-3L of the ILD protection layer 209-3, and a contact structure ILD layer 213 is deposited on the contact structure landing pad 212.

[0047] Therefore, compared with the previous embodiments shown in Figures 1A-1I Compared with the previous embodiments shown in Figures 2A-2I The present embodiment shown has the following advantages: it can prevent overgrowth of the top epitaxial layer 211 and control the height of the ILD layer 209-1 to be substantially the same as the top surface of the top source / drain region 211-1. Therefore, for better insulation, the top epitaxial layer 211 can not be formed above the ILD layer 209-1. In addition, the present embodiment makes it possible to remove the difference between the level of the bottom surface of the contact structure 215 and the level of the bottom surface of the contact structure ILD layer 213 remaining on the side surface of the contact structure 215, thereby preventing the loss of process margin that makes it difficult to form a VFET.

[0048] Referring back to Figure 2F and Figure 2GDuring the steps of depositing the top spacer 210 and the top epitaxial layer 211, the second layer 209-3O above and on the sides of the first layer 209-3N retained in the lower 209-3L of the ILD protective layer 209-3, as well as the first layer 209-3N formed on the sides of these second layers 209-3O, are removed by the aforementioned oxide loss. However, as Figures 3A-3C As shown, during the same steps of depositing the top spacer 210 and the top epitaxial layer 211, and the further steps of forming the top source / drain region 211-1, contact pad 214, and contact structure 215 according to one embodiment, all or part of the lower portion 209-3L of the ILD protective layer 209-3 can still be retained to maintain oxide distribution therein, for example, such that the top surface of the retained portion of the second layer 209-3O of the lower portion 209-3L of the ILD protective layer 209-3 is substantially coplanar with the top surface of the top epitaxial layer 211 or the top source / drain region 211-1.

[0049] However, even Figures 3A-3C The illustrated implementation also prevents the top epitaxial layer 211 from overgrowing on the ILD layer 209-1. The height of the top surface of the lower part 209-3L of the ILD protective layer 209-3 is controlled to be substantially the same as the top surface of the top epitaxial layer 211 or the top source / drain region 211-1. Furthermore, the difference between the level of the bottom surface of the contact structure 215 and the level of the bottom surface of the contact structure ILD layer 213 remaining on the side of the contact structure 215 is eliminated, thereby preventing the loss of process margin that makes it difficult to form a VFET.

[0050] exist Figures 2A-2I and Figures 3A-3C In the embodiments shown above, the ILD protective layer 209-3, used to prevent height loss of the ILD layer 209-1, is a bilayer that can be formed from SiN and SiO2. However, the inventive concept is not limited thereto. According to one embodiment, the ILD protective layer 209-3 may be a monolayer comprising SiN without oxides, or it may be a layer comprising a dielectric material (such as silicon carbide (SiC) or silicon oxycarbide (SiOC)) having an etch selectivity of 1:3 or greater relative to either SiN or SiO2 as described below.

[0051] Figures 4A-4F A cross-sectional side view of a method for manufacturing a VFET device according to one embodiment is shown.

[0052] In this embodiment, the same procedure as in the previous embodiment is performed. Figure 2A and Figure 2B The same steps shown are used to produce Figure 4A The intermediate VFET structure 40 shown is related to... Figure 2BThe intermediate VFET structure 20 shown is the same. Thus, a repeated description thereof is omitted here. Further, the intermediate VFET structure 40 according to the present embodiment includes the same elements that form the intermediate VFET structure 20, and thus a repeated description thereof is also omitted here. Thus, Figure 4A The intermediate VFET structure 40 shown includes a substrate 401, a plurality of fin structures 402-1 to 402-4 each containing a fin 402F and a mask 402M, a bottom epitaxial layer 403, a bottom spacer 404, a dielectric layer 405, an STI structure 406, a gate structure 407 each containing a conductor layer 407-1 and a high-k layer 407-2, a gate encapsulation liner 408, an ILD layer 409-1, and a shallow trench 409-2. Here, the ILD layer 409-1 has been etch-back to expose the gate encapsulation liner 408 above the ILD layer 409-1 as well as the top surface of the etch-back ILD layer 409-1 as shown in FIG. 4B. Figure 2A and Figure 2B The shallow trench 409-2 is provided from the previous steps as described in

[0053] Figure 4B The following steps in the fabrication of the VFET as described in the embodiment of Figures 1A-1I to prevent the height loss of the ILD layer 409-1 that can occur in the following steps, the gate encapsulation liner 408 exposed above the etch-back ILD layer 409-1 and the top surface of the etch-back ILD layer 409-1 are conformally deposited with an ILD protection layer 409-3. Unlike the double-layered ILD protection layer 209-3, the ILD protection layer 409-3 can be a single layer formed of a silicon nitride such as SiN or a dielectric material such as SiC or SiOC that has an etch selectivity of 1:3 or more with respect to any one of SiN and SiO2.

[0054] Figure 4C The fin structures 402-1 to 402-4 and the gate structure 407 along with the gate encapsulation liner 408 covered by the ILD protection layer 409-3 are planarized at a level above the lower portion 409-3L of the ILD protection layer 409-3 such that after the planarization, the top surface of the lower portion 409-3L of the ILD protection layer 409-3, the top surface of the gate encapsulation liner 408, the top surface of the gate structure 407, and the top surfaces of the fin structures 402-1 to 402-4 are substantially coplanar with each other. The planarization used here can be performed by chemical mechanical planarization (CMP) and / or dry etching, but is not limited thereto.

[0055] Figure 4D The etching of the shallow trench 409-2 in the ILD protection layer 409-3 is shown in Figure 4CThe fin structures 402-1 to 402-4 and the gate structures 407 that remain after planarization of the mask 402M. The ILD layer 409-1, the lower portion 409-3L of the ILD protective layer 409-3, and the gate encapsulation spacers 408 that remain between and on the sides of the gate structures 407 are left in a protruding form. Figure 4D It is further shown that the gate structures 407 are further etched than the fin structures 402-1 to 402-4, and that a top spacer 410 is formed on the further etched spaces on the gate structures 407, after which the top surface of the top spacer 410 and the top surfaces of the etched fin structures 402-1 to 402-4 are substantially coplanar.

[0056] Figure 4E It is shown that a top epitaxial layer 411 is formed by epitaxially growing a semiconductor layer on the fin structures 402-1 to 402-4 from which the mask 402M has been removed and by incorporating impurities in the semiconductor layer. The top epitaxial layer 411 will become the top source / drain region of the VFET that will be formed from the intermediate VFET structure 40. Figure 4E It is further shown that a contact structure ILD layer 413 is deposited on the top surface of the top epitaxial layer 411.

[0057] Here, it is noted that, in contrast to Figure 2G The step of forming the top epitaxial layer 411 in the present embodiment does not reduce the height and the bucket volume of the ILD layer 409-1 due to the lower portion 409-3L of the ILD protective layer 409-3, similar to the step of forming the top epitaxial layer 211 in the intermediate VFET structure 40. Thus, the ILD protective layer 409-3 can enable to prevent excessive growth of the top epitaxial layer 411 above the ILD layer 409-1 and control the top surface of the top epitaxial layer 411 to be substantially coplanar with the top surface of the lower portion 409-3L of the ILD protective layer 409-3.

[0058] Figure 4F It is shown that the contact structure ILD layer 413 is etched from top to bottom on the top epitaxial layer 411 to open the top surface of the top epitaxial layer 411, thereby forming a top source / drain region 411-1 of the VFET. Next, a contact pad 414 and a contact structure 415 formed of a metal or a compound thereof that connect the top source / drain region 411-1 to external elements are deposited to form a VFET device.

[0059] Reference is made to Figures 4A-4F The present embodiment described also has the same advantages as the embodiments of the intermediate VFET structure 40 described above with reference to Figures 1A-1I However, it is noted here that, in contrast to Figures 2A-2I and Figures 3A-3CIn the previous embodiments described, there is a possibility that an oxide distribution remains in the lower portion 209-3L of the ILD protective layer 209-3 during the same step of depositing the top spacer 210 and the top epitaxial layer 211, and the further steps of forming the top source / drain region 211-1, the contact pad 214, and the contact structure 215. This oxide distribution can cause additional oxide loss during the aforementioned steps and further steps of fabricating the VFET. However, the present embodiments can be able to prevent such oxide distribution remaining because the ILD protective layer 409-3 is a single layer that includes a material such as SiN that has no oxide, or a material such as SiC or SiOC that has an etch selectivity of 1:3 or more with respect to either of SiN and SiO2 that form the double layer used in the previous embodiments. Thus, the present embodiments are more advantageous than the previous embodiments in better maintaining the height of the top epitaxial layer 411 or the top source / drain region 411-1 and better preventing a difference between the level of the bottom surface of the contact structure 415 and the level of the bottom surface of the contact structure ILD layer 413 remaining on the side surface of the contact structure 415, thereby preventing a loss of process margin that makes it difficult to form the VFET.

[0060] The VFET device designed according to the above embodiments can be used in various components of an electronic device as described below.

[0061] Referring to Figure 5 The electronic device 100 can include at least one controller such as a microprocessor, a communication interface, an input interface, a storage, and a buffer memory, in which the VFET device described above can be included.

[0062] The controller can control the operation of the electronic device 100. The communication interface is implemented to perform wireless or wired communication with an external device. The input interface is implemented to output data processed by the controller in the form of audio and / or video, and to receive input data. The storage is implemented to store various data including user data. The storage can be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash (UFS) memory device, or the like. The storage can perform caching of the data described above.

[0063] The buffer memory can temporarily store data for processing operations of the electronic device 100. For example, the buffer memory can be a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double rate data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a rambus dynamic random access memory (RDRAM), or the like.

[0064] At least one component in an electronic device can include at least one of the VFET devices provided according to the above embodiments. The above embodiments can be applied to any electronic device and system. For example, the embodiments can be applied to systems such as a memory card, a solid state drive (SSD), an embedded multimedia card (eMMC), a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book, a virtual reality (VR) device, an augmented reality (AR) device, etc.

[0065] The foregoing is a summary of example embodiments, and is not to be construed as a limitation. Although a few example embodiments have been described, it will be readily apparent to those skilled in the art that many modifications are possible in the embodiments without materially departing from the present inventive concepts.

[0066] This application claims priority to U.S. Provisional Application No. 62 / 970,381, filed February 5, 2020, in the U.S. Patent and Trademark Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a vertical field-effect transistor device, the method comprising: (a) Provides an intermediate vertical field-effect transistor structure, which includes a substrate and a fin structure, a gate structure and a bottom epitaxial layer on the substrate, the gate structure being formed on the fin structure and the bottom epitaxial layer, respectively, each fin structure including a fin and a mask thereon; (b) Filling the spaces between and on the sides of the gate structure with an interlayer dielectric layer; (c) An interlayer dielectric protective layer is formed on the interlayer dielectric layer, the interlayer dielectric protective layer having an upper part and a lower part, and including a material to prevent oxide loss at the interlayer dielectric layer; (d) Remove the fin structure, the gate structure, and the interlayer dielectric protective layer above the lower portion of the interlayer dielectric protective layer; (e) Remove the mask of the fin structure and the top of the gate structure such that the top surface of the fin structure and the top surface of the gate structure after the removal are lower than the top surface of the interlayer dielectric layer; (f) A top spacer is formed on the gate structure where its top is removed, and a top epitaxial layer is formed on the fin structure where its mask is removed; as well as (g) Forming a contact structure connected to the top epitaxial layer.

2. The method according to claim 1, wherein, After step (f), the top surface of the lower portion of the interlayer dielectric protective layer is substantially coplanar with the top surface of the top epitaxial layer.

3. The method according to claim 1, wherein step (g) comprises: (g)-1) A contact structure interlayer dielectric layer is formed on the top surface of the top epitaxial layer and on the top surface of the interlayer dielectric layer; as well as (g)-2) Etch the interlayer dielectric layer of the contact structure to form the contact structure. In step (g)-2), the bottom surface of the contact structure and the bottom surface of the interlayer dielectric layer of the contact structure are substantially coplanar.

4. The method of claim 1, wherein the material included in the interlayer dielectric protective layer comprises a bilayer formed of a silicon nitride layer and a silicon oxide layer thereon.

5. The method of claim 4, wherein the lower portion of the interlayer dielectric protective layer comprises a portion of the silicon nitride layer and a portion of the silicon oxide layer thereon.

6. The method according to claim 5, wherein, After step (f), the portion of the silicon oxide layer included in the lower part of the interlayer dielectric protective layer is removed.

7. The method according to claim 6, wherein, After step (f), the portion of the silicon nitride layer below the removed portion of the silicon oxide layer included in the lower portion of the interlayer dielectric protective layer remains on the interlayer dielectric layer.

8. The method according to claim 7, wherein, After step (f), the top surface of the portion of the silicon nitride layer included in the lower part of the interlayer dielectric protective layer, below the portion of the silicon oxide layer that has been removed, is substantially coplanar with the top surface of the top epitaxial layer.

9. The method according to claim 5, wherein, After step (f), at least a portion of the silicon oxide layer included in the lower part of the interlayer dielectric protective layer is retained therein, such that the top surface of the retained portion of the silicon oxide layer is substantially coplanar with the top surface of the top epitaxial layer.

10. The method of claim 1, wherein the material included in the interlayer dielectric protective layer comprises silicon nitride and does not include oxides.

11. The method of claim 1, wherein the material included in the interlayer dielectric protective layer has an etch selectivity of 1:3 or greater relative to either SiN or SiO2.

12. The method of claim 1, wherein the material included in the interlayer dielectric protective layer comprises at least one of silicon carbide or silicon oxycarbide.

13. A vertical field-effect transistor device, comprising: Multiple vertical field-effect transistors formed on a substrate; An interlayer dielectric layer is formed between and on the sides of the gate structure of the vertical field-effect transistor; A contact structure is formed on the top source / drain region of the vertical field-effect transistor; as well as An interlayer dielectric layer is formed on the side of the contact structure. This includes an interlayer dielectric protective layer of silicon nitride layer formed on the top surface of the interlayer dielectric layer at the side of the gate structure, and which does not overlap the gate structure in the vertical direction.

14. The vertical field-effect transistor device of claim 13, wherein the interlayer dielectric protective layer is formed on the top surface of the interlayer dielectric layer between the gate structures.

15. The vertical field-effect transistor device of claim 14, wherein the interlayer dielectric protective layer is a bilayer comprising a silicon nitride layer and an oxide layer.

16. The vertical field-effect transistor device of claim 15, wherein the top surface of the oxide layer and the top surface of the top source / drain region are substantially coplanar.

17. The vertical field-effect transistor device of claim 13, wherein the top surface of the interlayer dielectric layer and the top surface of the top source / drain region are substantially coplanar.

18. The vertical field-effect transistor device of claim 13, wherein the horizontal plane of the bottom surface of the contact structure and the horizontal plane of the bottom surface of the interlayer dielectric layer of the contact structure are substantially coplanar.

19. The vertical field-effect transistor device of claim 13, wherein the top source / drain region is not formed over the interlayer dielectric layer.

20. A vertical field-effect transistor device, comprising: Multiple vertical field-effect transistors formed on a substrate; An interlayer dielectric layer is formed between and on the sides of the gate structure of the vertical field-effect transistor; A contact structure is formed on the top source / drain region of the vertical field-effect transistor; as well as An interlayer dielectric layer is formed on the side of the contact structure. An interlayer dielectric protective layer is formed on the top surface of the interlayer dielectric layer, and the interlayer dielectric protective layer comprises a dielectric material having an etch selectivity of 1:3 or greater relative to either silicon oxide or silicon nitride. The interlayer dielectric protective layer does not overlap the gate structure in the vertical direction.

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