Drift compensation

Abstract

The present disclosure relates to drift compensation, and in particular to a method for controlling an apparatus comprising an oscillating circuit and an antenna, wherein the oscillating circuit is configured to provide a clock signal to a radio frequency circuit, wherein a passage of the enabling signal from the circuit to the antenna is delayed relative to a moment of enabling a power amplifier of the circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Application No. 2001754, filed on February 21, 2020, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic devices and methods, and more particularly to electronic devices including oscillatory circuits and related methods. Background Art

[0004] Electronic devices often include an oscillator circuit in order to generate a desired center frequency.

[0005] Quartz crystals are often used in oscillation circuits. In fact, one of the characteristics of quartz crystals is that when a voltage is applied to them, they produce relatively stable oscillations. Summary of the invention

[0006] One embodiment addresses all or some of the disadvantages of known electronic devices that include quartz crystals.

[0007] One embodiment provides a method for controlling a device, the device comprising an oscillator circuit and an antenna, the oscillator circuit being configured to provide a clock signal to a radio frequency circuit, wherein enabling of a signal path from the circuit to the antenna is delayed relative to a moment when a power amplifier of the circuit is enabled.

[0008] According to one embodiment, enabling passage of the signal from the circuit to the antenna corresponds to shifting the switch from a first position configured to enable no transmission to be sent via the antenna to a second position configured to enable transmission to be sent via the antenna.

[0009] According to one embodiment, a single control signal is generated to enable a power amplifier and passage of a signal from the circuit to the antenna, and a delay is added to the single control signal before the control signal reaches a switch coupled between the circuit and the antenna relative to the control signal reaching the amplifier.

[0010] According to one embodiment, the duration of the delay is less than one second.

[0011] According to one embodiment, the duration of the delay is greater than 5 ms.

[0012] According to one embodiment, the duration of the delay depends on the temperature measured by a temperature sensor of the device.

[0013] According to one embodiment, the or each temperature is indicative of an ambient temperature.

[0014] According to one embodiment, the device comprises a plurality of duration values ​​of the delay stored in a memory, each duration value corresponding to a temperature range.

[0015] According to one embodiment, the duration values ​​associated with some of the temperatures are zero.

[0016] According to one embodiment, the duration value associated with at least one temperature is different from zero.

[0017] According to one embodiment, the radio frequency circuit is a radio frequency transmitter.

[0018] According to one embodiment, an apparatus includes a first variable capacitor, a first capacitor, a quartz crystal, and a second variable capacitor coupled in series, including controlling the capacitance of the first variable capacitor and the second variable capacitor to be greater than 50% of their maximum capacitance.

[0019] According to one embodiment, the method comprises the following steps: A) preheating the quartz; B) enabling the transmission signal when the temperature of the quartz decreases.

[0020] Another embodiment provides a device including: a radio frequency circuit and an antenna; an oscillation circuit configured to provide a clock signal to the RF circuit; and a control circuit configured to enable a power amplifier of the radio frequency circuit and enable a path of a signal from the circuit to the antenna, wherein the path of the enable signal from the circuit to the antenna is delayed relative to the moment of enabling the power amplifier.

[0021] According to one embodiment, a device comprises a sensor configured to measure a temperature or a value representative of a temperature.

[0022] According to one embodiment, a device comprises a memory configured to store duration values ​​of delays corresponding to temperature ranges.

[0023] According to one embodiment, an apparatus includes a first variable capacitor, a first capacitor, a quartz crystal, and a second variable capacitor coupled in series.

[0024] According to one embodiment, the apparatus includes a heater configured to increase the temperature of the quartz.

[0025] Another embodiment provides an electronic device, comprising: a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first node and the second node; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and a third node.

[0026] According to one embodiment, the value of the first capacitor is selected based on the target frequency to reduce the equivalent capacitance seen by the quartz relative to the capacitance produced by the two variable capacitors alone.

[0027] According to one embodiment, a first variable capacitor, a capacitor, a quartz crystal, and a second variable capacitor are included in an oscillation circuit.

[0028] According to one embodiment, the oscillation circuit is configured to provide a clock signal to the circuit.

[0029] According to one embodiment, the circuit is an RF transmitter.

[0030] According to one embodiment, the variable capacitor is part of an integrated circuit and wherein the quartz crystal and the capacitor are not part of the integrated circuit.

[0031] According to one embodiment, the capacitance value of the first capacitor is constant.

[0032] According to one embodiment, an apparatus includes a second capacitor coupled between the quartz and a second variable capacitor.

[0033] According to one embodiment, a device includes a radio frequency circuit and an antenna; an oscillation circuit configured to provide a clock signal to the RF circuit; and a control circuit configured to enable a power amplifier of the radio frequency circuit and enable a path of a signal from the circuit to the antenna, wherein the enabling of the path of the signal from the circuit to the antenna is delayed relative to the moment of enabling the power amplifier.

[0034] According to one embodiment, the apparatus includes a heater configured to increase the temperature of the quartz.

[0035] Another embodiment provides a method for controlling the aforementioned apparatus, the method comprising controlling the capacitance of the first variable capacitor and the second variable capacitor to be more than 50% of their maximum capacitance.

[0036] According to one embodiment, a method includes controlling capacitances of a first variable capacitor and a second variable capacitor to be substantially equal.

[0037] According to one embodiment, a method includes an oscillator circuit and an antenna, the oscillator circuit being configured to provide a clock signal to a radio frequency circuit, wherein enabling of a path of a signal from the circuit to the antenna is delayed relative to a time of enabling a power amplifier of the circuit.

[0038] According to one embodiment, the method comprises the steps of: A) preheating the quartz; B) enabling the emission of a signal when the temperature of the quartz decreases.

[0039] Another embodiment provides an apparatus comprising: an electronic circuit; an oscillating circuit including quartz, the oscillating circuit configured to provide a clock signal to the electronic circuit; and a heater configured to increase a temperature of the quartz.

[0040] According to one embodiment, the electronic circuit is a radio frequency transmitter and is coupled to an antenna.

[0041] According to one embodiment, an apparatus comprises a control circuit configured to control a heater.

[0042] According to one embodiment, the heater is dedicated to preheating quartz.

[0043] According to one embodiment, the heater is less than 10 mm from the quartz.

[0044] According to one embodiment, the heater is a resistor.

[0045] According to one embodiment, a device includes: an antenna; a control circuit configured to enable a power amplifier of the circuit and enable a path of a signal from the circuit to the antenna, wherein the enabling of the path of the signal from the circuit to the antenna is delayed relative to the moment of enabling the power amplifier.

[0046] According to one embodiment, an apparatus includes a first variable capacitor, a first capacitor, a quartz crystal, and a second variable capacitor coupled in series.

[0047] Another embodiment provides a method of controlling a prior device, comprising the steps of: A) preheating quartz; and B) enabling a signal to be emitted when the temperature of the quartz decreases.

[0048] According to one embodiment, step A) comprises increasing the current flowing through the resistor.

[0049] According to one embodiment, at least the temperature is multiplied during step A).

[0050] According to one embodiment, the passage of the enable signal from the circuit to the antenna is delayed relative to the moment of enabling the power amplifier of the circuit.

[0051] According to one embodiment, the method comprises controlling the capacitance of the first variable capacitor and the second variable capacitor to be greater than 50% of their maximum capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0053] Figure 1 An example of an electronic device capable of transmitting RF signals is shown very schematically;

[0054] Figure 2 It is shown Figure 1 a graph of the frequency drift of a device relative to a desired center frequency as a function of time;

[0055] Figure 3 It is shown Figure 1 A plot of the device's frequency drift relative to the desired center frequency over time and Figure 1 Two signals of the device;

[0056] Figure 4 is shown at multiple ambient temperatures Figure 1 A graph of the frequency drift of a device relative to a desired center frequency versus time;

[0057] Figure 5 Schematically shows the control Figure 1 Methods of equipment;

[0058] Figure 6 schematically illustrates an embodiment of a device comprising an oscillating circuit;

[0059] Figure 7 yes Figure 6 The frequency drift of the device depends on Figure 6 The relationship diagram of the capacitance value of the capacitor of the oscillation circuit;

[0060] Figure 8 An example of an electronic device capable of transmitting RF signals is shown very schematically;

[0061] Fig. 9 is a graph showing the effect of temperature change on quartz during the first 300 ms;

[0062] Fig.10 It shows the use of Figure 8 A graph of an example of drift obtained by an embodiment of the present invention; and

[0063] Fig.11 Shows the command Figure 8 Embodiments of the method of the device. DETAILED DESCRIPTION

[0064] The same features are marked by the same references in the various drawings. In particular, common structural and / or functional features in various embodiments may have the same references and may be provided with the same structures, dimensions, and material properties.

[0065] For clarity, only operations and elements useful for understanding the embodiments described herein are explained and described in detail.

[0066] Unless otherwise indicated, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0067] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers such as terms "upper", "lower", "high", "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figures.

[0068] Unless otherwise stated, the expressions "about", "approximately", substantially and "on the order of..." mean within 10%, preferably within 5%.

[0069] Figure 1 An example of an electronic device 10 capable of transmitting RF signals is shown very schematically. For example, the device 10 is suitable for low power and long range transmission. Preferably, the device is suitable for operating with a technology called LoRa (Long Range).

[0070] The device 10 comprises an oscillating circuit 12. The oscillating circuit 12 comprises a quartz crystal 14 and an oscillator (OSC) 16. The output of the oscillator 16 is coupled, preferably connected, to a transmitting circuit (RF) 20. The oscillating circuit 16 provides a clock signal having a center frequency f to the circuit 20. The desired value of the center frequency f is, for example, equal to 32 MHz.

[0071] The oscillator 16 and the transmit circuit 20 are integrated in a single circuit or chip 24 , while the quartz 14 constitutes an external component of the circuit 24 .

[0072] The circuit 20 is coupled to the antenna 22. The circuit 20 is, for example, an RF transmitter. In other words, the circuit 20 is, for example, a transmitter capable of sending (transmitting and receiving) signals at radio frequency (RF) (in other words, RF signals). The circuit 20 can transmit and receive radio frequency signals. The circuit 20 constitutes a transmitting and / or receiving head coupled to the antenna 22 through various analog front-end circuits 19 (matching networks, converters, switches, balanced-unbalanced converters, etc.). The front-end circuit is external to the chip 24.

[0073] The circuit 20 comprises an output TX at which a signal to be transmitted is provided. The output TX is provided by a power amplifier 21 (PA) of the circuit 20. The power amplifier 21 comprises an input at which a signal T representing the signal to be transmitted is provided. The power amplifier 21 comprises an enable input receiving a control signal EN1 or an enable signal EN1. The signal EN1 is a signal configured to enable or disable the power amplifier 21. The signal EN1 is, for example, a binary signal. A first value of the signal EN1, for example a high value "1", enables the power amplifier 21 and thus allows the output signal TX. A second value of the signal EN1, for example a low value "0", disables the power amplifier 21. Therefore, when the signal EN1 takes the second value, no signal can be transmitted by the circuit 20.

[0074] The circuit 20 comprises an input RX at which a signal can be received from an antenna 22. More precisely, the signal received by the antenna 22 is provided to the input RX via the front-end circuit 19. The input RX is for example coupled to, preferably connected to, an input of a low noise amplifier 25 of the circuit 20. The output of the low noise amplifier provides a signal R representing the received signal RX.

[0075] The chip 24 comprises a processing unit 27 (PU). The processing unit 27 is coupled to, preferably connected to, the circuit 20. The output of the low noise amplifier 25 and the input of the power amplifier 21 are coupled to the processing unit 27, for example. The processing unit 27 is configured to process the data to be transmitted, i.e. the signal T to be transmitted, and to process the received data, i.e. the signal R. The links between the processing unit 27 and the power amplifier 21 and between the processing unit 27 and the low noise amplifier 25 are Figure 1 No detailed description is given.

[0076] Figure 1 The device 10 is a half-duplex system. Therefore, the device can both transmit and receive signals, but not both at the same time. The output TX and the input RX of the circuit 20 are coupled to the antenna 22 via a switch 29 (SW). The switch 29 is coupled to the output TX and the input RX on one side and to the antenna on the other side. In a first state of the switch 29, the antenna is coupled to the output TX. In this first state, signals can be transmitted via the antenna 22. However, receiving signals is not feasible. In a second state of the switch 29, the antenna is coupled to the input Rx. In this second state, signals can be received from the antenna 22. However, transmitting signals is not feasible.

[0077] The switch 29 may also include a third state (not shown) in which the antenna is coupled to a high impedance node.

[0078] According to one embodiment, the switch 29 receives a control signal EN2 or an enable signal EN2 that is different from the control signal EN1. Depending on the desired state of the switch, the control signal EN2 takes different values. For example, a first value of the signal EN2 ensures that the switch 29 is in a first state, and a second value of the signal EN2 ensures that the switch 29 is in a second state. If the switch can be in more than two states, the control signal EN2 can take more than two values.

[0079] Switch 29 is part of circuit 19 and is coupled to antenna 22 and circuit 24 via block 31 and blocks 33 and 35 respectively.

[0080] like Figure 1 As shown, block 31 couples the common node of switch 29 to antenna 22, while blocks 33 and 35 couple the switch nodes of switch 29 to circuit 21 and circuit 25, respectively.

[0081] Device 10 further comprises a control circuit (CTRL) 32. Control circuit 32 is configured to control different elements of device 10. In particular, control circuit 32 provides control signals EN1 and EN2 to circuit 20 and switch 29, respectively. Circuit 32 is integrated into chip 24, for example.

[0082] When the power amplifier 21 is enabled, a signal can be output at the output TX. However, once the power amplifier is enabled, its temperature rises significantly, which causes the temperature of the circuit 24 to rise. The increase in the temperature of the circuit 24 causes at least in part a drift in the frequency of the clock signal provided by the oscillator 16 to the circuit 20. This drift corresponds to the difference between the actual center frequency of the signal that the transmitter 20 can use to transmit the signal and the desired center frequency. The drift can also be caused at least in part by heating of the quartz crystal. This drift is caused by Figure 2 shown.

[0083] Figure 2 It shows Figure 1 A graph of the drift (Drift (32 MHz) (Hz)) of the frequency of a device relative to a desired center frequency as a function of time (Time (Sec)). Figure 2 The graph of φ shows the effect of heating of the power amplifier 21 of the circuit 20. The heating of the power amplifier 21 causes a drift in the frequency f provided by the oscillating circuit 12 to the RF transmitter 20.

[0084] The drift is calculated by comparing it to the desired center frequency of 32 MHz. The drift is therefore equal to the difference between the actual value of the center frequency and the 32 MHz value.

[0085] Before time t0, the power amplifier is disabled and cannot transmit, so the temperature is substantially constant and has no significant drift. Therefore, the drift is substantially equal to zero.

[0086] At time t0, the power amplifier 21 included in the RF circuit 20 is enabled. Therefore, the temperature of the chip 24 increases, and the frequency f of the clock signal deviates from the desired center frequency.

[0087] After time t0, the drift value decreases and becomes negative. In other words, the absolute value of the drift increases.

[0088] Figure 2 ] represents the drift over a period of approximately one second after enabling the power amplifier 21. During this initial operating second, the drift decreases and reaches a value substantially equal to -4 Hz. The drift value reaches a value of -1.4 Hz at the instant t1.

[0089] It is particularly important, for an RF transmitter, such as circuit 20, that the frequency of the clock signal is as constant as possible during operation of the transmitter (or receiver or transmitter), in particular during transmission or reception.

[0090] During the initial phase of the transmission, drift can be particularly problematic. In some applications, such as in the case of the wide area network LoRa (LoRaWAN) Cl, it is preferred, for example specified in the standard, that for a desired center frequency of 915 MHz, during the initial seconds of the transmission, the absolute value of the drift is less than a threshold value th of 40 Hz. However, the drift is proportional to the desired center frequency. Thus, for a desired center frequency of 915 MHz, a threshold value of 40 Hz corresponds to a drift threshold of around 1.4 Hz for a desired center frequency of 32 MHz. This threshold value is in the range of 1.4 Hz to 1.4 Hz. Figure 2 The exemplary time t1 is crossed.

[0091] A negative value of the drift means that the actual value of the frequency of the clock signal provided to the RF transmitter 20 is lower than the expected value. A positive value of the drift means that the actual value of the frequency is higher than the expected value. A value of the drift equal to zero means that the actual value of the frequency of the clock signal provided to the RF transmitter is equal to the expected value.

[0092] According to one embodiment, the control circuit is configured to ensure a delay between the enabling of the power amplifier 21 and the enabling of the channel of the signal to be sent from the output TX to the antenna. For example, the enabling of the signal channel corresponds to placing the switch 29 in a state that allows the channel of the signal to be transmitted but does not allow the channel of the signal to be received. In other words, the control signal EN2 of the switch 29 is set to the first value "1" after the power amplifier 21 is enabled. Therefore, the signals EN1 and EN2 do not take their first values ​​at the same moment. The control signal EN1 takes its first value, and after a delay, the control signal EN2 takes its first value. In combination Figure 3 This method of controlling the device 10 is described in more detail.

[0093] Figure 3 It is shown Figure 1 A graph of the frequency f of a device as a function of time (t) relative to the desired center frequency (Drift) and Figure 1 The amplifier 21 and the switch 29 of the device have two corresponding enable signals (EN1, EN2).

[0094] The drift value is calculated by comparing it to the desired center frequency of 32 MHz. The drift is therefore equal to the difference between the actual value of the center frequency and the 32 MHz value.

[0095] Before time t0, control signals EN1 and EN2 have the second value. In other words, before time t0, power amplifier 21 is disabled and switch 29 is configured to allow reception of signals but not transmission. When the power amplifier is disabled, it does not generate heat and the drift is substantially equal to zero.

[0096] More generally, before the instant t0, the switch 29 may be in any state. In fact, when the power amplifier is disabled, no signal can be sent via the output TX, whatever the state of the switch 29.

[0097] At time t0, enable Figure 1 In other words, the control signal generated by the control circuit 32 changes from the second value ('0') to the first value ('1'). In addition, the passage of the signal from the output TX to the antenna is blocked. Figure 2 In the example of , the control signal EN2 maintains the second value "0" corresponding to the receiving state. However, the switch may be in any state that does not allow a signal to be sent from the output TX to the channel of the antenna.

[0098] As the temperature of the power amplifier increases, the drift decreases. In other words, the absolute value of the drift increases. However, since the signal EN2 has the second value, there is no transmission.

[0099] At time t2, which is later than time t0 and is separated from time t0 by a delay D, the control signal EN2 takes the first value. Therefore, at time t2, the signal to be transmitted can reach the antenna to be sent to the receiving device.

[0100] At instant t2, the transmission starts and the receiving device starts receiving the transmitted signal. The drift of the transmitted signal is the drift A2, corresponding to the difference between the actual frequency of the transmitted signal and the value of the frequency at the start of the transmission.

[0101] The delay D is chosen to ensure that the drift A2 is below the threshold th described previously. Furthermore, the delay D is preferably chosen to be as small as possible while respecting the threshold th.

[0102] For example, the delay D is pre-programmed in the device, such as in a memory.

[0103] According to another embodiment, a single enable signal is generated by control circuit 32 but is delayed before reaching switch 29. For example, device 10 includes a component configured to add a delay equal to D to the single control signal before the control signal reaches switch 29 relative to the control signal reaching amplifier 21.

[0104] One might have considered using a temperature compensated quartz crystal (TCXO or Temperature Controlled Crystal Oscillator) to compensate for the drift caused by the enabled power amplifier. However, the cost of such quartz would be considered too high in many applications.

[0105] The device 10 is preferably configured to operate using LoRa technology. In this case, it is desirable to use a standard chip 24 whose hardware cannot be modified. Any modification or improvement must involve programming of components of the chip 24 and / or components external to the chip 24, but not modification of components of the chip 24.

[0106] Figure 4 is shown at various ambient temperatures Figure 1 A graph of the frequency f of a clock signal of a device as a function of time (t(s)).

[0107] Figure 4 The diagram includes three curves 41, 43, and 45, each of which represents the frequency f at a different ambient temperature. Curve 41 corresponds to an ambient temperature of -40°C. Curve 43 corresponds to an ambient temperature of 80°C. Curve 45 corresponds to an ambient temperature of 25°C.

[0108] It can be seen that, depending on the temperature, the drift has a different behavior depending on the ambient temperature. For example, the curve 41 corresponding to a temperature of 85°C shows a more significant variation than the other curves.

[0109] The value of the instant t1 may be different for each value of the ambient temperature. For some values ​​of the temperature, the instant t1 may be equal to the instant t0. Thus, for some temperatures but not all temperatures, the delay may be equal to zero. In fact, for some temperatures, the absolute value of the drift remains below the threshold t during the first second after the instant t1.

[0110] According to one embodiment, the device 10 is programmed with a single value for the delay D. This value is preferably chosen based on the worst case scenario at the instant t1 corresponding to the temperature at which the device is expected to operate.

[0111] According to a preferred embodiment, the delay D between the enabling of the power amplifier 21 and the enabling of the switch 29 is selected based on a temperature value measured by a temperature sensor. The sensor is integrated in the chip 24. The temperature measured by the sensor is, for example, the temperature at the outer surface of the device, thus, for example, indicating the ambient temperature around the device. Alternatively, the temperature measured by the sensor is the temperature inside the device 10, for example, the temperature on the chip 24.

[0112] Multiple values ​​of delay D can be programmed into device 10. For example, each value of delay D can be associated with a range of ambient temperatures.

[0113] The different instants t1 and the corresponding temperature ranges, for example programmed in a memory of the device, are preferably generated during manufacturing or during a calibration process. For example, the variation of the drift is determined for a plurality of temperatures, each of the plurality of temperatures corresponding to a temperature range. This step is performed on each device, or on one device representing a batch of devices. Alternatively, the calibration process may not be implemented. The different instants t1 and the corresponding temperature ranges are, for example, predetermined values.

[0114] Figure 5 Schematic representation of the control Figure 1 Preferably, the steps of the method are continuous. The method is implemented, for example, by hardware or software. The method is implemented, for example, by a state engine.

[0115] about Figure 5 The described method is performed, for example, starting at the transmission of each transmitted signal or at the transmission of each group of signals (block 60, START).

[0116] During the first step of the method, the temperature sensor measures the temperature (block 62, measure T°). This temperature is then compared with a value or range of values ​​programmed in the device 10 and the value of the delay D is determined from this value or range of temperatures (block 64, determine D).

[0117] During the subsequent steps, the control circuit ensures that the power amplifier is enabled (block 66, EN1), while the path of the signal from the output TX to the antenna is disabled. For example, the control circuit ensures that the signal EN1 takes a first value ('1'), while the signal EN2 has a second value ('0'). When the signal EN1 has the first value and the signal EN2 has the second value, for example, a dummy signal T is applied to the input of the power amplifier 21.

[0118] The delay D starts from the enablement of the power amplifier. For example, the counter starts counting when the power amplifier is enabled. When the value of the delay D is reached, the passage of the signal to be transmitted is allowed (block 68, EN2). For example, when the counter reaches the value D, the control signal EN2 takes a first value '1', while the control signal EN1 maintains the first value. One or more transmissions can be performed (block 70, transmission).

[0119] Once one or more signals are transmitted (block 72, end), the power amplifier may be disabled, for example by setting the value of the control signal EN2 to a second value, and the passage of the signal from the output TX to the antenna may be blocked.

[0120] Combination Figures 1 to 5 An advantage of the described embodiments is that the drift seen by a receiving device is reduced.

[0121] Combination Figures 1 to 5 Another advantage of the described embodiment is that it can be implemented without structural modifications to the circuit 24 .

[0122] Combination Figures 6 to 8 Another aspect of the specification is described.

[0123] Figure 6 An embodiment of a device 30 including an oscillating circuit is schematically shown. Although some elements may not be shown, the device 30 preferably includes an integrated circuit. Figure 1 All elements described in the description will not be described in detail. Specifically, the device 30 includes a quartz crystal 14 and an integrated circuit 24, and the integrated circuit 24 includes an RF transmitter 20. The device 30 may also include Figure 6 The antenna 22, the front-end circuit 19, the processing unit 27, etc. are not shown.

[0124] The oscillator circuit 12 provides a clock signal (v f ). The oscillation circuit 12 is, for example, a Pierce oscillator.

[0125] The oscillator circuit 12 comprises an oscillator 16. The oscillator 16 comprises an inverter 47. The output of the inverter 47 is coupled to, preferably connected to, the first node 34. The input of the inverter is coupled to, preferably connected to, the second node 36. The second node 36 constitutes the output node of the oscillator. The second node 36 is coupled to, preferably connected to, the input of the transmitter 20. The clock signal v f is provided at the second node 36 .

[0126] The first node 34 is coupled to, preferably connected to, a terminal of a variable capacitor (C1) 38. The other end of the capacitor 38 is coupled to, preferably connected to, a reference node 39 receiving a reference voltage or a reference voltage application node. Preferably, the reference node 39 is ground.

[0127] The second node 36 is coupled, preferably connected, to a terminal of a variable capacitor (C2) 40. The other end of the capacitor 40 is coupled, preferably connected, to a reference node 39 that receives a reference voltage.

[0128] The variable capacitor 38 , the inverter 47 , and the variable capacitor 40 are coupled in series to each other in this order, preferably connected.

[0129] Capacitor 38 and capacitor 40 are foot capacitors. Capacitor 38 and capacitor 40 are used to modify the capacitance seen by quartz crystal 14 during the calibration phase of the assembly in order to compensate for manufacturing dispersion of quartz 14. Capacitor 38 and capacitor 40 are preferably identical to each other (except for manufacturing tolerances).

[0130] The control circuit 32 is configured to control the variable capacitor 38 and the variable capacitor 40 .

[0131] If combined Figure 7 As shown in more detail, an increase in the capacitance value of variable capacitor 38 and variable capacitor 40 advantageously results in a reduction in the absolute value of the frequency drift of the clock signal provided to circuit 20. However, an increase in the capacitance value of capacitor 38 and capacitor 40 also affects the capacitance value seen by the quartz and, therefore, the value of the center frequency f of the clock signal.

[0132] To compensate for the modification in the capacitance value seen by the quartz, capacitor 42 (C SERIE ) is coupled in series with the quartz crystal 14, preferably connected in series. Capacitor 42 allows the use of higher capacitance values ​​for capacitors 38 and 40 while keeping the capacitance value seen by the quartz substantially equal to the target capacitance C L .

[0133] The quartz crystal 14 and the capacitor 42 are coupled in series between the first node 34 and the second node 36. The terminal of the quartz crystal 14 is coupled to, preferably connected to, the terminal of the capacitor 42. The other end of the quartz crystal is coupled to, for example, preferably connected to the second node 36. The other end of the capacitor 42 is coupled to, for example, preferably connected to the first node 34. As a result, the variable capacitor 38, the capacitor 42, the quartz crystal 14, and the variable capacitor 40 are coupled in series in this order, preferably connected in series. The inverter is coupled in parallel to the assembly of the quartz 14 and the capacitor 42, preferably connected in parallel.

[0134] Alternatively, the variable capacitor 38, the quartz crystal 14, the capacitor 42, and the variable capacitor 40 may be coupled in series with each other in this order, preferably connected in series.

[0135] Alternatively, capacitor 42 may be replaced by two capacitors located on each side of quartz 14, one between quartz and node 34 and the other between quartz and node 36. The values ​​of the two capacitors are, for example, chosen to be together equal to the value of capacitor 42.

[0136] Capacitor 42 preferably has a constant capacitance value C SERIE The capacitor is preferably not a variable capacitor. In other words, the value of capacitor 42 is preferably not controlled by control circuit 32. The value of first capacitor 42 is preferably selected based on the target frequency to reduce the equivalent capacitance seen by the quartz relative to the capacitance produced by only two variable capacitors.

[0137] Preferably, capacitor 38 and capacitor 40 are controlled in such a way that their capacitances are substantially equal.

[0138] In this example, the target capacitance C seen by the quartz crystal 14 L equal:

[0139] [Mathematical formula 1]

[0140]

[0141] Where C1 is the capacitance value of capacitor 38, C2 is the capacitance value of capacitor 40, and C SERIE is the capacitance value of capacitor 42, and C STRAY is the capacitance value of stray or parasitic capacitance.

[0142] Therefore, the capacitance C of capacitor 42 is SERIE equal:

[0143] [Mathematical formula 2]

[0144]

[0145] Among them CL is the target value of capacitance seen by the quartz crystal, and C B is equal to the value C1 and also equal to the value C2 (C B =C1=C2).

[0146] For example, if the target value is approximately equal to 10 pF, if capacitors C1 and C2 are each equal to 27 pF, and capacitor C STRAY is equal to 5pF, then the capacitance C SERIE Equal to 60pF. More generally, capacitors C1, C2, and C SERIE In order to obtain a capacitance C in the range of 8pF to 15pF L .

[0147] Since chip 24 cannot usually be modified to operate using LoRa technology, capacitor 42 is not located in chip 24, but is located outside chip 24 (external to chip 24). In some other embodiments, capacitor 42 may be located in chip 24, for example.

[0148] Figure 7 yes Figure 6 A functional relationship diagram of the frequency drift of the device (Drift (32 MHz) (Hz)) and the capacitance value of the foot capacitor of the oscillation circuit 16 (Foot Capacitance (pF)).

[0149] The drift value is in Hertz (Hz), and the capacitance values ​​C1 and C2 are in picofarads (pF). The drift value is approximately 700ms ( Figure 2 In this example, Figure 3 The times t0 and t2 in are the same. Therefore, these values ​​are taken during the first second after the power amplifier is enabled and the transmission starts.

[0150] Figure 7 The values ​​empirically obtained by simulation or experiment are shown. The capacitance values ​​correspond to possible values ​​of the variable capacitor 38 and the variable capacitor 40 in the corresponding simulation or experiment. In other words, Figure 7 The capacitance value of corresponds to the range of possible values ​​for variable capacitor 38 and variable capacitor 40. The two variable capacitors are assumed to be equal in value. The capacitance value range is 11.3 pF to 32.92 pF.

[0151] The drift value is in the range of -4.5 Hz when the capacitance values ​​C1 and C2 are substantially equal to 11 pF to -1.5 Hz when the capacitance values ​​C1 and C2 are substantially equal to 33 pF.

[0152] These values ​​depend on the experimental conditions. However, a general trend can be observed in which the absolute value of the drift decreases as the capacitance value increases. In other words, as the capacitance value of capacitor 38 and capacitor 40 increases, the drift approaches a zero value.

[0153] Therefore, as described above, increasing the capacitance value of capacitor 38 and capacitor 40 has the benefit of reducing the absolute value of the drift. Therefore, it is useful that the capacitance value of capacitor 38 and capacitor 40 is as high as possible within the value range of variable capacitor 38 and variable capacitor 40. However, in order to maintain the possibility of slightly adjusting the capacitance value of capacitor 38 and capacitor 40 during operation of oscillation circuit 12, the capacitance value of capacitor 38 and capacitor 40 is preferably selected below the maximum value of capacitor 38 and capacitor 40, for example with a margin substantially equal to 3 pF.

[0154] Preferably, capacitors 38 and 40 are controlled so that, at least during the first seconds after the oscillator starts, the values ​​C1 and C2 are equal to at least 50% of their maximum value, preferably strictly above 50% of their maximum value, preferably between 60% and 85% of their maximum value, and for example substantially equal to 75% of their maximum value. As previously stated, the capacitance value C SERIE is selected to correspond to capacitor 38 and capacitor 40 having values ​​between 60% and 85% of the maximum values ​​of capacitor 38 and capacitor 40 .

[0155] An advantage of the described embodiments is that the drift relative to the desired frequency is reduced. The drift can be reduced enough to meet the requirements of the device.

[0156] Another advantage of the described embodiments is that relatively few components are added to the device.

[0157] Combination Figures 9 to 11 Another aspect of the specification is described.

[0158] Figure 8 An example of an electronic device 60 capable of transmitting RF signals is shown very schematically. The device 60 comprises Figure 1 Thus, the device 60 comprises a quartz crystal 14, an antenna 22, a front-end circuit 19 and a chip 24. The chip 24 comprises an oscillator 16, a circuit RF 20, a processing unit 27 and a control circuit 32.

[0159] The device 60 further includes a heater 62 (HEATER). The heater is an electrical component that dissipates heat. The heater 62 is, for example, a resistor element. The heater 62 is, for example, in the circuit 12 but not in the integrated circuit 24.

[0160] The heater 62 is located close enough to the quartz 14 so that temperature changes around the heater can affect the quartz. Preferably, the heater is as close to the quartz as possible. For example, the heater is located on the quartz. For example, the heater can be adjacent to the quartz. For example, the distance between the heater 62 and the quartz 14 is less than 10 mm, preferably less than 5 mm, preferably less than 2 mm. Preferably, the distance between the heater 62 and the quartz 14 is less than 1 mm. For example, the distance between the heater 62 and the quartz 14 is substantially equal to 1 mm. For example, the heater is in contact with the quartz.

[0161] The heater is preferably used only for heating quartz. Preferably, the heater is dedicated to the function of preheating quartz 14.

[0162] The heater is, for example, a resistor. For example, the resistance value of the resistor is in the range between 50 ohms and 150 ohms, for example substantially equal to 75 ohms.

[0163] The heater is, for example, part of an electronic circuit that also includes components configured to control the heater 62. For example, if the heater is a resistor, the resistor is part of a circuit configured to send a current through the resistor so as to increase the heat dissipated by the resistor.

[0164] The control circuit 32 generates a control signal EN3 or enable signal EN3. The control signal EN3 determines the state of the heater, in particular whether the heater generates heat. For example, if the heater is a resistor, the control circuit 28 controls the current flowing through the resistor. For example, the signal EN3 can take at least two values, a first value ensuring that a given current can flow through the resistor and a second value ensuring that no current can flow through the resistor. In this case, when the control signal EN3 takes the first value, the temperature of the heater and therefore the temperature of the quartz increases to a new temperature. When the control signal EN3 takes the second value, the temperature of the heater and therefore the temperature of the quartz decreases, for example until the heater reaches the temperature it had before the control signal EN3 took the first value.

[0165] Fig. 9 is a graph showing the effect of temperature change on quartz. Specifically, Fig. 9 shows the oscillator circuit provided by Figure 8 An example of a frequency drift (variation in Hertz (32 MHz)) or frequency variation of the clock signal of the circuit 20 according to time (time (seconds)) around a carrier frequency.

[0166] The drift value corresponds to a desired carrier frequency of 32 MHz. The drift value is expressed in Hertz. The time value is expressed in seconds.

[0167] Fig. 9The changes shown are independent of temperature changes caused by the power amplifier 21. For example, Fig. 9 The variation shown corresponds to the case where the power amplifier 21 is disabled and there is no effect on temperature.

[0168] It can be assumed that, within the time range considered in the graph, the quartz and the oscillator have been switched on for a sufficient time to be in a steady state. Therefore, the changes described below are caused only by temperature changes of the heater 62.

[0169] At time t3, the heater 62 starts heating and the first phase P1 starts. More specifically, the control circuit 32 controls the heater 62 to increase the temperature of the heater. For example, the control signal EN3 generated by the control circuit 32 takes a first value. For example, the control circuit 32 increases the current flowing through the heater.

[0170] After time t3, during the first phase P1, the temperature of the heater increases. For example, the temperature increases until a threshold value and stops increasing. The temperature of the heater is not purposefully reduced during the first phase P1.

[0171] It can be observed that the drift value decreases due to the increase in temperature. The absolute value of the drift decreases.

[0172] exist Fig. 9 In the example of FIG. 1 , during the first stage, ie, about 0.30 seconds after time t3 , the frequency drops by about 3.8 Hz.

[0173] At time t4, the first phase P1 ends and the second phase P2 begins. The control circuit 32 stops heating the heater. For example, the control signal EN3 generated by the control circuit 32 takes a first value. For example, the control circuit 32 reduces the current that preferably stops flowing through the resistor. Therefore, the temperature of the heater and the quartz decreases during the second phase.

[0174] For example, the temperature decreases until reaching the temperature at time t3.

[0175] It can be observed that the drift value increases during the second phase P2. In the second phase P2, as time passes, the drift value moves away from 0. The absolute value of the drift increases.

[0176] exist Fig. 9 In the example of , the drift reaches a value substantially equal to 3.8 Hz after approximately 0.30 seconds.

[0177] The increase in temperature in the first phase P1 leads to a decrease in the drift and thus to a decrease in the absolute value of the drift. The decrease in temperature in the second phase P2 leads to an increase in the drift and thus to an increase in the absolute value of the drift.

[0178] The change in drift is inversely proportional to the change in temperature. Figures 8 to 11 The described embodiment exploits this feature in order to compensate for the drift caused by the power amplifier 21 .

[0179] Fig.10 It is shown by Figure 8 Example of drift obtained by Example.

[0180] Specifically, Fig.10 shows the oscillator circuit provided by Figure 8 An example of a frequency drift (variation in Hertz (32 MHz)) or frequency variation of the clock signal of the circuit 20 according to time (time (seconds)) around a carrier frequency.

[0181] The drift value corresponds to a desired carrier frequency of 32 MHz. The drift value is expressed in Hertz. The time value is expressed in seconds.

[0182] Fig.10 Three curves are shown. The first curve 65 is Figure 8 The second curve 67 is the same as the curve of FIG. 67 and represents the effect of the temperature change of the heater on the carrier frequency drift of the clock signal provided to the circuit 20. Figure 2 The third curve 69 is the same as the first curve and corresponds to the effect of heating of the circuit 20 on the drift value of the carrier frequency of the clock signal provided to the circuit 20. The third curve 69 corresponds to the sum of the first curve and the second curve. Therefore, the third curve 69 represents the total actual drift of the carrier frequency of the clock signal provided to the circuit 20.

[0183] During the first phase P1, ie between the instant t3 and the instant t4, the value of the curve 67 is equal to zero. Therefore, the curve 69 follows the variation of the curve 65. Thus, the frequency decreases during the first phase.

[0184] During the first phase, as Fig. 9 As mentioned, the power amplifier is disabled. Therefore, the control signal EN1 has a second value. Since the circuit 20 is an RF transmitter, the transmitter does not send or receive signals during the first phase.

[0185] At the beginning of the second phase P2, in other words, after the time t4, the heater has stopped. In this example, the drift reaches zero and the frequency stabilizes, and, since the temperature of the quartz may take some time to decrease significantly enough to affect the frequency, the drift caused by the quartz remains substantially equal to zero for a short time, for example less than 0.03s. In another example, the drift value during this time may be different from 0.

[0186] Furthermore, at time t4, the power amplifier is still disabled.

[0187] At time t5, the power amplifier is enabled. The period between time t4 and time t5 constitutes a first part P21 of the second phase P2, and the remainder of the second phase P2 constitutes a second part P22. Alternatively, the first part P21 can be removed. In this variant, time t4 and time t5 are simultaneous.

[0188] After time t5, the absolute values ​​of the drift caused by the decrease in quartz temperature (curve 65) and the drift caused by circuit 20 (curve 67) increase. However, in relative values, the drift value caused by the decrease in quartz temperature is positive and increases, while the drift value caused by circuit 20 is negative and decreases. Therefore, these two components of the total drift tend to compensate each other. In fact, the change in the total drift (curve 69) is not as important as the change in each of the two components. The value of the total drift is closer to zero than the value of either of the two component drifts.

[0189] Figure 8 An embodiment of utilises this compensation to reduce the frequency drift due to power amplifier start-up (curve 67).

[0190] exist Fig.10 In the example of FIG. 2 , curve 69 varies between about −1.3 Hz and about 1 Hz during the second portion P22, while the value of curve 67 varies between about 0 Hz and −4 Hz. The value of curve 69 is within acceptable parameters, which is a drift with an absolute value of less than 1.4 Hz for a desired carrier frequency of 32 MHz in the first second of operation of circuit 20.

[0191] The duration of the first phase P1, in other words the difference between the instants t3 and t4, is preferably chosen so that the drift caused by the heater reaches zero before the instant t4. The duration of the first part P21 of the second phase is preferably chosen so as to optimize the compensation of the drift. In practice, the reduction of the drift represented by the curve 67 starts soon after the instant t5, whereas the drift represented by the curve 65 takes some time to start increasing depending on the temperature of the heater. Therefore, it is occasionally useful to delay the instant t5 relative to the instant t4.

[0192] To optimize the compensation, the characteristics of the heater (eg the value of the resistor), the temperature reached and the duration of the first phase, as well as the duration of the portion P21 can be selected according to the application. Specifically, the temperature of the heater and the duration of the heating can depend on several factors, for example on the size of the device.

[0193] According to an embodiment, the duration between the instants t2 and t3 is selected depending on the temperature measured by the temperature sensor.

[0194] Fig.11Shows the control Figure 8 Embodiments of the method of the device.

[0195] At the start of the method (block 70, START), the quartz and oscillator are already operating and already providing a clock signal to the circuit 20. However, the power amplifier of the circuit 20 is disabled.

[0196] The heater 62 is activated by the control circuit 32 (block 72, Activate heater). This corresponds to the instant t3. For example, the control signal EN3 takes a first value. As mentioned before, the characteristics of the heater and the temperature reached depend on the application. This corresponds to a preheating step.

[0197] In this regard, drift caused by heating of the heater, drift caused by the heater and its operation, are the main causes of drift of the carrier frequency of the clock signal provided by the oscillation circuit.

[0198] After the preheating duration, the control circuit stops heating the heater (block 74, stop heater). This corresponds to time t4. For example, the control signal EN3 takes the second value. The heater and the quartz begin to cool. The frequency drift stops decreasing.

[0199] Preferably, no heater is used after the step represented by box 74. Preferably, no heater is used during the step represented by box 72 other than heating the quartz, and in particular no heater is used during operation of the circuit 20.

[0200] Afterwards, the transmission of signals can be started (block 76, start chip). This corresponds to time t5.

[0201] An advantage of the described embodiment is that during the first seconds of operation of the transmitter 20, drift of the carrier frequency is compensated and maintained within desired parameters.

[0202] Another advantage of the described embodiment is that it is implemented with few modifications and components.

[0203] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and other variations will readily occur to those skilled in the art. Specifically, although the present invention has been described in conjunction with a half-duplex device, Figure 6 and Figure 7 Embodiments and Figures 8 to 11 2, but they can be easily adapted to be implemented on a full-duplex device. For example, a full-duplex device may include a switch or on / off relay between the output TX and the antenna to allow or stop the signal from the output TX to the antenna. The switch will be controlled by the signal EN2, just as described for switch 29 in this specification.

[0204] Furthermore, the different embodiments described may be implemented all together or two at a time. Figures 1 to 5 Examples and Figures 8 to 11 In this case, the power amplifier is Fig.10 The signal is enabled at time t5, and the channel between the output TX and the antenna is enabled after time t5 and after a delay D.

[0205] Ultimately, actual implementation of the embodiments and variations described herein is within the capabilities of a person skilled in the art based on the functional description provided above.

[0206] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a restrictive sense. By reference to the description, those skilled in the art will appreciate the various modifications and combinations of the illustrative embodiments and other embodiments of the present invention. Therefore, the appended claims include any such modifications or embodiments.

Claims

1. A method for controlling a device, the method comprising: The oscillator circuit provides a clock signal to the radio frequency RF circuit; enabling a power amplifier of the RF circuit to generate an RF signal; After enabling the power amplifier, delaying the path of the RF signal from the RF circuit to the antenna by a delay; as well as After the delay, passage of the RF signal from the RF circuit to the antenna is enabled such that a difference between an actual frequency of the RF signal and a frequency of the RF signal at the end of the delay is below a predetermined drift threshold.

2. The method of claim 1 , wherein enabling passage of the RF signal from the RF circuit to the antenna corresponds to shifting a switch from a first position to a second position, the first position being configured to enable no transmission to be sent via the antenna and the second position being configured to enable transmission to be sent via the antenna.

3. The method according to claim 1, further comprising: generating a single control signal to enable the power amplifier and the passage of the RF signal from the RF circuit to the antenna; as well as The delay is added to the single control signal before the single control signal reaches a switch coupled between the RF circuit and the antenna, the delay being related to the single control signal reaching the power amplifier. The method of claim 1 , wherein the delay has a duration of less than one second. The method of claim 1 , wherein the delay has a duration greater than 5 ms. The method of claim 1 , wherein the duration of the delay depends on a temperature measured by a temperature sensor of the device.

7. A method according to claim 6, wherein the or each temperature measured by the temperature sensor is indicative of ambient temperature.

8. The method of claim 6, wherein the device includes a plurality of duration values ​​for the delay stored in a memory, each duration value corresponding to a temperature range.

9. The method of claim 8, wherein the duration values ​​associated with some of the temperatures are zero.

10. The method of claim 8, wherein at least one duration value associated with at least one temperature is non-zero.

11. The method of claim 1, wherein the RF circuit is an RF transmitter.

12. The method of claim 1 , wherein the device comprises a first variable capacitor, a first capacitor, a quartz crystal, and a second variable capacitor coupled in series, and the method further comprises controlling the capacitance of the first variable capacitor and the second variable capacitor to be greater than 50% of the maximum capacitance of the first variable capacitor and the second variable capacitor, respectively.

13. The method according to claim 12, further comprising: preheating the quartz crystal; as well as The emission of the transmitted signal is enabled when the temperature of the quartz crystal decreases.

14. An electronic device comprising: Radio frequency RF circuit; an antenna coupled to the RF circuit; an oscillator circuit configured to provide a clock signal to the RF circuit; as well as The control circuit is configured as follows: enabling a power amplifier of the RF circuit; as well as enabling the passage of an RF signal from the RF circuit to the antenna, wherein the passage of the RF signal from the circuit to the antenna is delayed relative to the moment when the power amplifier is enabled so that the difference between an actual frequency of the RF signal and a frequency of the RF signal at the end of the delay is below a predetermined drift threshold.

15. The device of claim 14, further comprising a sensor configured to measure a temperature or a value representative of the temperature. 16 . The device of claim 14 , further comprising a memory configured to store duration values ​​of the delays corresponding to temperature ranges.

17. The apparatus of claim 14, wherein the oscillation circuit comprises a first variable capacitor, a first capacitor, a quartz crystal, and a second variable capacitor coupled in series.

18. The apparatus of claim 17, further comprising a heater configured to increase the temperature of the quartz crystal.

19. The device of claim 14, further comprising a switch coupled between the RF circuit and the antenna and controlled by the control circuit, wherein the switch has a first position and a second position, the first position being configured to enable no transmission to be sent via the antenna, and the second position being configured to enable transmission to be sent via the antenna.

20. The apparatus of claim 19, wherein the control circuit is configured to generate a single control signal to enable the power amplifier and passage of the RF signal from the RF circuit to the antenna; and The device also includes a delay circuit, which is configured to add the delay to the single control signal before the single control signal reaches the switch coupled between the RF circuit and the antenna, and the delay is related to the single control signal reaching the power amplifier.

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