Semiconductor device and method for manufacturing the same

Abstract

In a method for manufacturing a semiconductor device, a first conductive layer is formed above a substrate. A first photoresist layer is formed above the first conductive layer. The first photoresist layer is used as an etching mask to etch the first conductive layer to form an island pattern of the first conductive layer, and the island pattern is separated from the busbar pattern of the first conductive layer by an annular groove. A connection pattern is formed to connect the island pattern and the busbar pattern. A second photoresist layer is formed above the first conductive layer and the connection pattern. The second photoresist layer includes an opening above the island pattern. A second conductive layer is formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed to form a bump structure. Embodiments of the present application also relate to semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As consumer devices with better performance become smaller in response to consumer demand, the size of the individual components of these devices must also decrease. Semiconductor devices that form the main components of consumer devices such as mobile phones and tablets have become smaller and smaller. The size of semiconductor devices has continued to decrease with the advancement of semiconductor manufacturing technology, such as forming connections between semiconductor devices. Summary of the invention

[0003] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming one or more first conductive layers above a substrate; forming a first photoresist layer above the one or more first conductive layers; using the first photoresist layer as an etching mask to etch the one or more first conductive layers to form island patterns of the one or more first conductive layers, wherein the island patterns of the one or more first conductive layers are separated from busbar patterns of the one or more first conductive layers by an annular groove; forming a connecting pattern to connect the island patterns and the busbar patterns; forming a second photoresist layer above the one or more first conductive layers and the connecting pattern, wherein the second photoresist layer includes an opening above the island pattern; forming one or more second conductive layers on the island pattern in the opening; removing the second photoresist layer; and removing the connecting layer to form a bump structure.

[0004] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a pad electrode, the pad electrode being coupled to a semiconductor circuit formed above a substrate; forming a passivation layer above the pad electrode; patterning the passivation layer to expose at least a portion of the pad electrode; forming a seed layer above the passivation layer and the pad electrode; patterning the seed layer to form an island pattern of the seed layer, the island pattern of the seed layer being electrically separated from a busbar pattern of the seed layer by an annular groove; forming a connection pattern to electrically connect the island pattern with the busbar pattern; forming a photoresist layer above the seed layer and the connection pattern, the photoresist layer including an opening above the island pattern; forming one or more conductive layers on the island pattern in the opening; removing the photoresist layer; and removing the connection layer to form a bump structure.

[0005] Still other embodiments of the present application provide a semiconductor device comprising: a semiconductor circuit disposed above a substrate; a pad electrode coupled to the semiconductor circuit; a passivation layer; one or more conductive layers disposed on the pad electrode; and a bump structure disposed above the one or more conductive layers, wherein: the bump structure includes an undercut at an interface between the bump structure and the topmost layer of the one or more first conductive layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0008] Figure 2A and Figure 2B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0009] Figure 3A and Figure 3B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0010] Figure 4A and Figure 4B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0011] Figure 5A and Figure 5B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0012] Fig. 6A and Figure 6B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0013] Fig. 7A and Figure 7B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0014] Fig. 8A and Figure 8B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0015] Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E and Fig.9F One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0016] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D and Fig. 10E Various configurations of conductive connection patterns according to embodiments of the present invention are shown.

[0017] Fig.11A and Fig. 11B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0018] Fig. 11C and Fig.11D One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0019] Fig. 12A and Fig. 12B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0020] Fig.13A and Fig. 13B One stage of sequential fabrication operations of a semiconductor device according to an embodiment of the present invention is shown.

[0021] Fig.14 is a cross-sectional view of a stage in sequential fabrication operations of a semiconductor device according to an embodiment of the present invention.

[0022] Fig.15 is a cross-sectional view of a stage in sequential fabrication operations of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the size of the element is not limited to the disclosed range or value, but depends on the process conditions and / or the desired performance of the device. In addition, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. For simplicity and clarity, the various components may be arbitrarily drawn in different proportions.

[0024] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. Additionally, the term "made of" may mean "comprising" or "consisting of."

[0025] As the electronics industry develops three-dimensional integrated circuits (3D ICs) based on through-silicon via (TSV) technology, people are actively studying the process and reliability of bumps used to interconnect stacked chips. In the process of reducing the size of the bump, the diameter of the bump is reduced to about an order of magnitude smaller than the flipped chip solder joint, and the volume is reduced by about 1,000 times. The solder joint size is much smaller, which increases the possibility of bump solder joint failure.

[0026] Bumps are generally formed using electroplating. In electroplating, a seed layer and / or an underlying conductive layer, which may be collectively referred to as an under-bump metallization (UBM) layer, are formed over a substrate or wafer in which a semiconductor device (such as an integrated circuit) is formed. The UBM layer provides an electrical path for the electroplating process.

[0027] In some examples, after the bump is formed, the UBM layer is patterned (etched) to electrically separate the portion of the UBM layer bump on which the bump is formed. The etching of the UBM layer should be well controlled to not etch the bump and / or the under-bump UBM layer. When the under-bump UBM layer is over-etched, an undercut is formed around the bottom of the bump, and the bump may collapse.

[0028] In the present invention, a novel technique for forming a bump structure that can minimize undercutting in the UBM layer is provided.

[0029] Figure 1A and Figures 1B to 9A - Fig.9F 1 shows sequential fabrication operations of a bump structure above a semiconductor circuit according to an embodiment of the present invention. It should be understood that additional embodiments of the method may be Figures 1A to 9F Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchanged. Figure 1A and Figures 1B to 9A - Fig.9F , FIG. “A” shows a plan view (top view or projection view), and FIG. “B” shows a cross-sectional view taken along line AA of FIG. “A”.

[0030] like Figure 1A and Figure 1B As shown, a plurality of pad electrodes 20 on which bump structures are to be formed are arranged above the semiconductor circuit 15 formed on the substrate 10. The pad electrodes 20 are formed of suitable conductive metals including aluminum, copper, silver, gold, nickel, tungsten, titanium, alloys thereof and / or multilayers thereof. The pad electrodes 20 are formed by suitable metal deposition operations including electroplating or chemical plating, physical vapor deposition (PVD) including sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation or electron beam evaporation. In some embodiments, the pad electrodes 20 are arranged in a row-column arrangement.

[0031] In some embodiments, the semiconductor circuit 15 includes transistors (e.g., field effect transistors (FETs)), capacitors, inductors, resistors, etc. In some embodiments, the pad electrode 20 is electrically coupled to the semiconductor circuit 15 through a lower interconnect layer, which includes a wiring layer and a via formed in a dielectric layer such as an interlayer dielectric layer (ILD) and an intermetallic dielectric layer (IMD). The wiring layer and the via of the interconnect layer can be formed of copper or a copper alloy (e.g., AlCu), aluminum, tungsten, nickel, or any other suitable metal. The wiring layer and the via can be formed using an embossing process.

[0032] In some embodiments, the pad electrode 20 has a width W1 of about 10 μm to about 500 μm, as shown in a plan view. In other embodiments, the pad electrode 20 has a width W1 of about 20 μm to about 100 μm. In some embodiments, a plurality of pad electrodes 20 are arranged in a row-column arrangement with a pitch P1 of about 20 μm to about 100 μm. In some embodiments, the pitch along the X direction is the same as or different from the pitch along the Y direction.

[0033] A 2×2 arrangement of pad electrodes 20 is shown, but the present invention is not limited to a 2×2 arrangement. Other arrangements of pad electrodes 20 including fewer or more rows and columns are included within the scope of the present invention. For example, the arrangement may be a 10×10 arrangement, or more columns and rows. The arrangement of pad electrodes 20 is not limited to a rectangular arrangement. In some embodiments, other arrangements include staggered rows and columns, wherein each pad electrode 20 is next to the other 6 pad electrodes 20. In other embodiments, the pad electrodes 20 are arranged in a concentric circle arrangement. In other embodiments, the pad electrodes 20 are arranged around the periphery of the substrate or arranged in the central portion of the substrate. In other embodiments, the pad electrodes 20 are irregularly spaced apart. In some embodiments, up to about 10,000 pad electrodes 20 are formed on the substrate. As described below, a bump structure is formed above the pad electrode 20. Accordingly, in some embodiments, the bump structure has the same arrangement as the pad electrode 20.

[0034] In some embodiments, the substrate 10 is formed of at least one selected from silicon, diamond, germanium, SiGe, SiGeSn, SiGeC, GeSn, SiSn, GaAs, InGaAs, InAs, InP, InSb, GaAsP, GaInP and SiC. In some embodiments, the semiconductor substrate 10 is a silicon wafer or a silicon substrate.

[0035] In some embodiments, one or more passivation layers 25 are formed over the pad electrode 20, such as Figure 1A and Figure 1B As shown. The passivation layer 25 includes one or more layers of silicon oxide, silicon nitride, SiON, SiC, SiOCN, SiCN or any other suitable insulating layer. The passivation layer 25 is patterned using suitable photolithography and etching operations to form an opening in which a portion of the pad electrode is exposed, such as Figure 1A and Figure 1B In some embodiments, the opening has a tapered shape, such as Figure 1B shown.

[0036] Then, if Figure 2A and Figure 2B As shown, one or more conductive layers as UBM layers are formed over the passivation layer 25 and the exposed pad electrode 20. In some embodiments, the UBM layer includes a lower conductive layer 30 and a seed layer 35 formed on the lower conductive layer 30. In some embodiments, the lower conductive layer includes Ti, TiN or TiW, and the seed layer 35 includes copper or a copper alloy. In some embodiments, the copper alloy contains more than 50 mol% copper. In some embodiments, the UBM layer is formed by a suitable metal deposition operation including physical vapor deposition (PVD) (including sputtering), chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation, and electron beam evaporation. In some embodiments, each of the lower conductive layer 30 and the seed layer 35 has a thickness of about 20 nm to about 100 nm.

[0037] Next, a photoresist layer 40 is formed on the UBM layers 30 and 35. Figure 3A and Figure 3B As shown. The photoresist layer 40 can be a positive photoresist or a negative photoresist. When the photoresist is a positive photoresist, the portion of the photoresist exposed to the actinic radiation is soluble in the developer and can be removed during the development operation. When the photoresist is a negative photoresist, the portion of the photoresist exposed to the actinic radiation is insoluble in the developer and remains in the device, while the portion not exposed to the actinic radiation can be removed during the development operation. In some embodiments, the actinic radiation is ultraviolet radiation, including i-line radiation and g-line radiation, and deep ultraviolet radiation. In some embodiments, the actinic radiation is generated by a mercury arc lamp or a laser including ArF and KrF excimer lasers.

[0038] The photoresist layer 40 is then selectively exposed to actinic radiation and developed to form a plurality of first openings 45 exposing the UBM layer (seed layer 35), such as Figure 3A and Figure 3B In some embodiments, the first opening 45 has a ring or frame shape, such as Figure 3A In some embodiments, in a plan view, the first opening 45 surrounds the pad electrode 20. In other embodiments, the first opening 45 overlaps the perimeter of the pad electrode 20. In some embodiments, the perimeter of the pad electrode is located outside the first opening 45. In some embodiments, the width W2 of the first opening 45 is about 0.1 μm to about 1 μm.

[0039] Then, if Figure 4A and Figure 4B As shown, the UBM layers 30 and 35 are patterned using the photoresist layer 40 as an etching mask. The etching includes one or more of dry etching and wet etching. Figure 4A and Figure 4B As shown, a groove 38 is formed to surround the island pattern 33 of the UBM layer 30 and 35, and the pad electrode 20 is disposed below the island pattern. Each of the island patterns of the UBM layers 30 and 35 is electrically isolated from the busbar pattern 37 formed by the UBM layer by the groove 38. In some embodiments, the width W3 of the groove 38 is about 0.1 μm to about 1 μm. In some embodiments, the width W4 of the island pattern 33 is about 10 μm to about 500 μm, and in other embodiments, about 20 μm to about 100 μm. In some embodiments, the width W4 of the island pattern 33 is the same as the width W1 of the pad electrode 20, smaller than the width W1 of the pad electrode 20, or larger than the width W1 of the pad electrode 20. In some embodiments, the groove 38 has a circular shape having a diameter of about 10 μm to about 500 μm or about 20 μm to about 100 μm. The photoresist layer 40 is removed by using a suitable photoresist stripping solution or by an oxygen plasma ashing operation.

[0040] Then, if Figure 5A and Figure 5B As shown, a conductive connection pattern 40 is formed to connect the busbar pattern 37 and the island pattern 33. Figure 4A and Figure 4B One or more conductive layers are formed over the structure shown, and then one or more photolithography and etching operations are performed to form a plurality of conductive connection patterns 40 .

[0041] The conductive connection pattern 40 is formed by a suitable metal deposition operation including electroplating or chemical plating, physical vapor deposition (PVD) including sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation or electron beam evaporation. In some embodiments, the conductive connection pattern 40 is made of metal or metal material, and the conductive connection pattern 40 can be selectively removed from the UBM layer and the subsequently formed bump structure. In some embodiments, the conductive connection pattern 40 includes Al, Ni, Co, W, Au, Ag, Sn, Ta and alloys thereof.

[0042] In some embodiments, the distance H1 that the conductive connection pattern 40 extends above the surface of the seed layer 35 is about 200 nm to about 500 nm. In some embodiments, the width W5 (X direction) of the conductive connection pattern 40 is greater than the width W3 of the groove 38. In some embodiments, the width W5 of the conductive connection pattern 40 is 100 nm greater than the width W3, about 1,000 nm. Therefore, the cross-section of the conductive connection pattern 40 has a flange shape with a thick center portion and a thin peripheral portion. Through the conductive connection pattern 40, the busbar pattern 37 is electrically connected to each island pattern 33.

[0043] Next, if Fig. 6A and Figure 6B As shown, in Figure 5A and Figure 5B A second photoresist layer 50 having a second opening 55 is formed over the structure shown. The second opening 55 is then filled with one or more conductive materials to form a bump structure. In some embodiments, the second opening 55 has a width W6 of about 10 μm to about 500 μm, and in other embodiments, has a width of about 20 μm to about 100 μm.

[0044] In some embodiments, Fig. 6A and Figure 6B As shown, a portion of the conductive connection pattern 40 is exposed in the second opening 55. In some embodiments, the protrusion amount D1 of the conductive connection pattern 40 in the second opening 55 is about 0nm to 500nm, and in other embodiments, about 50nm to about 200nm. If the amount D1 is less than 0nm, the photoresist pattern completely covers the conductive connection pattern 40. If the amount D1 is too large, the undercut formed subsequently will be too large. In some embodiments, the edge of the second opening on the conductive connection pattern 40 is located above the groove 38 (above the thick central portion of the flange shape of the conductive connection pattern 40) or above the island pattern 33 (on the thin peripheral portion of the flange shape of the conductive connection pattern 40 disposed on the island pattern 33). In some embodiments, the edge of the second opening 55 is not located above the busbar pattern 37 (not located on the thin peripheral portion of the flange shape of the conductive connection pattern 40 disposed on the busbar pattern 37).

[0045] In some embodiments, the edges of the second opening 55 on the other sides except the side on which the conductive connection pattern 40 is formed are located on the island pattern 33. In some embodiments, the overlap amount D2 is about 0 nm to about 100 nm, and in other embodiments, about 20 nm to about 50 nm. If the amount D2 is less than 0 relative to the sidewall of the groove 38, a portion of the groove 38 is exposed. If the amount D2 is too large, the effective volume of the bump structure is less than the required amount. In some embodiments, the second opening 55 is substantially circular, and the circle has a diameter of about 10 μm to about 50 μm.

[0046] Next, if Fig. 7A and Figure 7B As shown, one or more conductive layers 60 are formed in the second opening 55. In some embodiments, the conductive layer 60 is a single copper or copper alloy layer. In some embodiments, the conductive layer 60 includes a first conductive layer 62, a second conductive layer 64, and a third conductive layer 66. In some embodiments, the conductive layer 60 includes gold or a gold alloy.

[0047] In some embodiments, the first conductive layer 62 is formed in the second opening 55 above the island pattern 33 of the seed layer 35. In some embodiments, the first conductive layer 62 is copper or a copper alloy (e.g., AlCu). The first conductive layer 62 may be formed by an electroplating process. In other embodiments, PVD, CVD, ALD, thermal evaporation, and / or electron beam evaporation including sputtering are used. In some embodiments, the first conductive layer 62 has a thickness of about 5 μm to about 10 μm.

[0048] Further, the second conductive layer 64 is formed in the second opening 55 over the first conductive layer 62. In some embodiments, the second conductive layer 64 includes a metal having a lower solderability or wettability to the solder alloy than copper or a copper alloy.

[0049] In some embodiments, the thickness of the second conductive layer 64 is greater than the thickness of the first conductive layer 62 above the uppermost surface of the seed layer 35. In some embodiments, the thickness of the second conductive layer 64 is in a range of about 10 μm to about 30 μm. In some embodiments, the ratio of the thickness of the second conductive layer 64 to the thickness of the first conductive layer 62 is about 6 / 1 to about 1.5 / 1.

[0050] In some embodiments, the second conductive layer 64 is mainly formed of a metal selected from aluminum, chromium, iron, manganese, magnesium, molybdenum, nickel, niobium, tantalum, titanium, tungsten, zinc and alloys thereof. In some embodiments, the second conductive layer 64 is formed of a nickel-based material. In some embodiments, the nickel-based material includes nickel and a nickel alloy containing more than 50 mol% nickel. The second conductive layer 64 is formed by an electroplating process.

[0051] In some embodiments, the third conductive layer 66 includes a solder layer. In some embodiments, the solder layer 66 includes a eutectic solder, such as an alloy selected from AgSn, SnAgCu, PbSn, and CuSn. Other suitable solders can be used as long as the solderability (wetting) of the second conductive layer 64 to the solder is lower than that of copper and copper alloys. In some embodiments, the thickness of the solder layer 66 is about 2 μm to about 10 μm. In some embodiments, excess solder is removed from above the photoresist layer 55. In some embodiments, a Ni-based second conductive layer 64 is not formed on the first conductive layer 62, but a solder layer 66 is formed. In other embodiments, a first conductive layer 62 is not formed on the seed layer 35, but a Ni-based second conductive layer 64 is formed.

[0052] Since the plurality of island patterns 33 formed of the UBM layer are electrically connected to the bus bar pattern 37 which is in turn electrically connected to the electrode of the electroplating process, the conductive layers 62 , 64 , and 66 are selectively formed in the plurality of second openings 55 .

[0053] Then, if Fig. 8A and Figure 8B As shown, the photoresist 50 is removed to expose the solder layer 66, the second conductive layer 64 and the sidewalls of the first conductive layer 62, thereby forming a bump structure 60B. In some embodiments, the photoresist layer 50 is removed using a suitable photoresist stripper.

[0054] Next, if Fig. 9A and Fig. 9B As shown, the conductive connection pattern 40 is removed by etching using a suitable etchant, and the conductive connection pattern 40 is selectively removed (etched) into the UBM layer 30, 35 and the bump structure 60B. In some embodiments, the etching operation is a wet etching operation. In some embodiments, when the conductive connection pattern 40 is an Au-based material (more than 90% Au, Au alloy), the wet etchant includes KI (potassium iodine) and I2, which can etch the Au layer selective to the Cu layer and / or Ti / Cu UBM layer.

[0055] In some embodiments, when the conductive connection pattern 40 is a Cu-based material (more than 90% Cu, Cu alloy), the wet etchant includes H2SO4 (10-30wt%) + H2O2 (5-15wt%) + <1% organic additives (0.1-1wt%), which can etch the Cu layer selective to the Au layer and / or the Ti / Au UBM layer. In some embodiments, when the conductive connection pattern 40 is an Al-based material (more than 90% Al, Al alloy), the wet etchant includes H3PO4 (10-30wt%) + H2O2 (5-15wt%) + organic additives (0.1-1wt%), which can etch the Al layer selective to the Cu layer and / or the Ti / Cu UBM layer.

[0056] In some embodiments, when the lower conductive layer 30 is a Ti-based material (more than 90% Ti, Ti alloy) and must be etched, the wet etchant includes H3PO4 (5-15wt%) + H2O2 (5-15wt%) + KOH (2-15wt%) + organic additives (0.1-1wt%), which can etch the Ti layer selective to the conductive connection pattern 40, the seed layer 35, the Au layer and / or the bump structure 60B made of Au, Cu and / or Al. By removing the conductive connection pattern 40, the bump structures 60B formed on the island pattern 33 are electrically isolated from each other. In some embodiments, after removing the photoresist layer 50, the solder layer 66 is reflowed to form a smooth hemispherical shape.

[0057] The etching operation generates an undercut 65 caused by removing the conductive connection pattern 40 , particularly removing a thin peripheral portion of the flange shape of the conductive connection pattern 40 .

[0058] like Fig. 9C As shown, the width W1 of the bump structure 60B is about 10 μm to about 500 μm, and about 20 μm to about 100 μm in other embodiments. In some embodiments, the height of the bump structure 60B from the uppermost portion of the seed layer 35 is about 17 μm to about 30 μm. Fig. 9A As shown, in some embodiments, the width along the Y direction (along the side of the bump structure 60B) is about 200 nm to about 200 μm.

[0059] In other embodiments, the lateral depth D11 of the undercut 65 from the side of the bump structure 60B is about 0 nm to about 500 nm, and in other embodiments, about 50 nm to about 200 nm. In some embodiments, the lateral depth D12 of the undercut 65 from the edge of the groove 38 is about 50 nm to about 200 nm. In some embodiments, at the portion where no conductive connection pattern 40 is formed on the island pattern 33, the bump structure 60B has an offset W12 with the edge of the groove 38. In some embodiments, the offset W12 is about 0 nm to about 100 nm, and in other embodiments, about 20 nm to about 50 nm. In some embodiments, the lateral depth D11 is greater than the lateral depth D12, such as Fig. 9C In some embodiments, the lateral depth D11 is equal to the lateral depth D12. In other embodiments, the lateral depth D11 is less than the lateral depth D12. Fig.9D In some embodiments, the height H12 of the undercut 65 is about 200 nm to about 500 nm.

[0060] In some embodiments, a portion of the UBM layer is slightly etched according to the etching selectivity between the UBM layer and the conductive connection layer 40. In such a case, the bump structure 60B has an overlapping shape at a portion where no conductive connection pattern 40 is formed on the island pattern 33, such as Fig.9E In some embodiments, the offset W15 is greater than 0 nm to about 50 nm.

[0061] Fig.9F FIG. 1 shows a schematic diagram of a structure of a bump 60B according to an embodiment of the present invention. Fig. 9A When the edge of the second opening 55 is located in the groove 38, the bump structure 60B, especially the first conductive layer 62, covers the side edges of the UBM layers 30 and 35, such as Fig.9F In some embodiments, according to the overlay error of the photoresist layer 50 (the second opening 55 ) with respect to the island pattern 33 , the thickness W21 on one side is equal to or different from the thickness W22 on the other side.

[0062] like 9A to 9F As shown, the undercut 65 is only partially formed on the side of the bump structure 60B. When the bump structure 60B has a substantially rectangular (e.g., square) shape in a plan view, the undercut 65 is only formed on one side, and the remaining side does not have an undercut. Therefore, the undercut is formed asymmetrically with respect to the center of the bump structure 60B. In the above embodiment, the position of the undercut is limited, and the amount of the undercut is uncontrollable. Further, the UBM layer is substantially not etched after the bump structure is formed. Therefore, it is possible to prevent the collapse of the bump structure due to excessive etching of the UBM layer.

[0063] In some embodiments, the second photoresist layer 50 is formed so that no portion of the conductive connection pattern 40 is exposed in the second opening 55. In other words, the photoresist pattern 50 completely covers the conductive connection pattern 40. In such a case, substantially no undercut is formed in the bump structure 60B and the UBM layer (see below). Fig.13A and Fig. 13B ).

[0064] FIG. 10A to FIG. 10E Various configurations of conductive connection patterns are shown.

[0065] In some embodiments, Fig. 10A As shown, two or more conductive connection patterns 40 are provided for one island pattern 33 having a rectangular shape (with rounded corners) at two or more sides of the rectangular shape. In such a case, undercuts 65 may be formed at symmetrical positions (at two or four sides).

[0066] In some embodiments, Fig. 10BAs shown, two or more conductive connection patterns 40 are provided for one island pattern 33 having a rectangular shape on one side of the rectangular shape.

[0067] In some embodiments, Fig. 10C As shown, a conductive connection pattern 40 is provided for two adjacent island patterns 33 .

[0068] In other embodiments, Fig. 10D As shown, a conductive connection pattern 40 is provided for four adjacent island patterns 33. In some embodiments, as Fig. 10E , the conductive connection pattern 40 has a ring or frame shape. In these cases, when the bump structure has a substantially rectangular shape (with rounded corners), an undercut 65 is formed at the corner of the bump structure.

[0069] In some embodiments, at least one of the island pattern 33 or the bump structure 60B has a circular shape in a plan view. In some embodiments, one or more undercuts 65 are formed between the bump structure of the island pattern of the UBM layer and the seed layer 45 .

[0070] Fig.11A and Figures 11B to 15 1 shows sequential fabrication operations of a bump structure over a semiconductor circuit according to an embodiment of the present invention. It should be understood that for additional embodiments of the method, FIG. 11A to FIG. 15 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or removed. The order of operations / processes may be interchangeable. In the following embodiments, materials, processes, configurations, and / or processes described relative to the previous embodiments are employed, and detailed descriptions thereof may be omitted.

[0071] In some embodiments, Fig.11A and Fig. 11B As shown, the conductive connection pattern 40 completely fills the groove 38. In some embodiments, the conductive connection pattern 40 does not have a flange shape (in Figure 5B , H1=0), the upper surface of the conductive connection pattern 40 is substantially flush with the upper surface of the seed layer 35. In some embodiments, when forming Figure 5A and Figure 5B After the structure is shown, one or more planarization operations are performed, such as an etch-back operation or a chemical mechanical polishing (CMP) operation.

[0072] Then, a photoresist pattern 55 having a second opening 55 is formed, such as Fig.11D In some embodiments, the size of the second opening 55 is smaller than the size of the island pattern 33 of the UBM layer, and the periphery of the second opening 55 is completely disposed above the island pattern 33. Therefore, the conductive connection pattern is completely covered by the photoresist pattern 50.

[0073] In some embodiments, the conductive connection pattern 40 is formed without a photolithography process. Figure 4A and Figure 4B A blanket layer of conductive material of the conductive connection pattern 40 is formed over the structure shown, and then a planarization operation, such as a CMP operation, is performed. Fig. 11C As shown, the conductive material remains not only in the groove 38 but also in the concave or convex portion of the island pattern 33. Then, a second photoresist pattern 50 having a second opening 55 is formed. Fig.11D As shown, the remaining conductive material in the recessed or protruding portions of the island pattern 33 is removed by a suitable etching operation through the second opening 55. In some embodiments, wet etching is performed to remove the conductive material selective to the seed layer 35. In some embodiments, when the volume of the remaining conductive material in the recessed or protruding portions of the island pattern 33 is small enough and the exposed seed layer in the second opening 55 is large enough, the remaining conductive material in the recessed or protruding portions of the island pattern 33 is not removed.

[0074] Next, if Fig. 12A and Fig. 12B As shown, Fig. 7A and Figure 7B Similar to the explained operation, one or more conductive layers 60 are formed in the second opening 55. Since the island pattern 33 is electrically connected to the bus bar pattern 37, the conductive layer 60 is formed by one or more electroplating processes.

[0075] Then, the second photoresist layer 50 is removed, and then the conductive connection pattern 40 is removed using a suitable etching operation, such as Fig.13A and Fig. 13B In some embodiments, the conductive connection pattern 40 is removed by wet etching selective to the UBM layer and the bump structure 60B.

[0076] like Fig.13A and Fig. 13B As shown, substantially no undercut is formed in the bump structure 60B and the UBM layer. When viewed from above, the bump structure 60B is surrounded by the seed layer 35 .

[0077] In some embodiments, the photoresist pattern 50 is formed so that the size of the second opening 55 is larger than the size of the island pattern 33 of the UBM layer, and the periphery of the second opening 55 is completely or partially disposed above the conductive connection pattern 40 having a ring or frame shape. Therefore, the conductive connection pattern is only partially covered by the photoresist pattern 50.

[0078] Next, if Fig.14 As shown, compared with Fig. 7A and Figure 7BSimilar to the operation explained above, one or more conductive layers 60 are formed in the second openings 55. The second photoresist layer 50 is then removed, and then the conductive connection pattern 40 is removed using a suitable etching operation, such as Fig.15 In some embodiments, the conductive connection pattern 40 is removed by wet etching selective to the UBM layer and the bump structure 60B.

[0079] like Fig.15 As shown, an undercut is formed in the UBM layer surrounding the bump structure 60B. However, the amount of the undercut is controlled by the overlap amount of the second opening 50 and the conductive connection pattern 40. Accordingly, it is possible to prevent unwanted collapse of the bump structure 60 due to over-etching of the UBM layer.

[0080] In some embodiments, a portion of the perimeter of the second opening 55 of the second photoresist pattern 50 is located over the island pattern 33, and a portion of the perimeter of the second opening 55 of the second photoresist pattern 50 is located over the conductive connection pattern 40. In such a case, an asymmetric undercut is formed in the UBM layer.

[0081] Bump undercuts produced by underbump metallization etching after forming the bumps can cause bump collapse. In an embodiment of the present invention, a bump structure is formed after an underbump metallization etching operation is performed. An embodiment of the present invention provides a symmetrical undercut surrounding the bump structure. An embodiment of the present invention provides high aspect ratio bumps and fine pitch structures coupled with reduced bump collapse defects.

[0082] It should be understood that not all advantages are necessarily discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0083] According to one aspect of the present invention, in a method for manufacturing a semiconductor device, one or more first conductive layers are formed over a substrate. A first photoresist layer is formed over the one or more first conductive layers. The one or more first conductive layers are etched using the first photoresist layer as an etching mask to form an island pattern of one or more first conductive layers separated from a busbar pattern of the one or more first conductive layers by an annular groove. A connection pattern is formed to connect the island pattern and the busbar pattern. A second photoresist layer is formed over the one or more first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. One or more second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed to form a bump structure. In one or more of the foregoing or following embodiments, the connection pattern is made of a conductive material different from the one or more first conductive layers and the one or more second conductive layers. In one or more of the foregoing or following embodiments, the connection pattern only partially fills the annular groove to connect the island pattern and the busbar pattern. In one or more of the foregoing or following embodiments, the connection pattern is formed in a portion of the annular groove and on a portion of the upper surface of the uppermost layer of the one or more first conductive layers. In one or more of the foregoing or following embodiments, a portion of the connection pattern is disposed in the opening. In one or more of the foregoing or following embodiments, the connection pattern is removed by wet etching. In one or more of the foregoing or following embodiments, after removing the connection pattern, the bump structure includes an undercut between the bump structure and the uppermost layer of the one or more first conductive layers. In one or more of the foregoing or following embodiments, the undercut is only partially formed, and no undercut is formed at the remaining portion between the bump structure and the uppermost layer of the one or more first conductive layers.

[0084] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a pad electrode coupled to a semiconductor circuit formed above a substrate is formed. A passivation layer is formed above the pad electrode. The passivation layer is patterned to expose at least a portion of the pad electrode. A seed layer is formed above the passivation layer and the pad electrode. The seed layer is patterned to form an island pattern of the seed layer electrically separated from the busbar pattern of the seed layer by an annular groove. A connection pattern is formed to electrically connect the island pattern and the busbar pattern. A photoresist layer is formed above the seed layer and the connection pattern. The photoresist layer includes an opening above the island pattern. One or more conductive layers are formed on the island pattern in the opening. The photoresist layer is removed, and the connection pattern is removed to form a bump structure. In one or more of the foregoing or following embodiments, at least one of the one or more conductive layers is formed by an electroplating process. In one or more of the foregoing or following embodiments, the busbar pattern is electrically connected to the potential in the electroplating process. In one or more of the foregoing or following embodiments, the seed layer includes copper or a copper alloy. In one or more of the foregoing or following embodiments, at least one of the one or more conductive layers includes copper or a copper alloy. In one or more of the foregoing or following embodiments, before forming the seed layer, a lower conductive layer is formed over the passivation layer and the pad electrode. In one or more of the foregoing or following embodiments, the lower conductive layer includes at least one selected from titanium-based metals, gold-based metals, and copper-based metals. In one or more of the foregoing or following embodiments, the connection pattern includes at least one selected from Al, Au, Cr, Fe, Mn, Mg, Mo, Ni, Nb, Ta, Ti, W, Zn, and alloys thereof.

[0085] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a plurality of pad electrodes are formed, each coupled to a semiconductor circuit formed above a substrate. A passivation layer is formed above the plurality of pad electrodes. The passivation layer is patterned to expose a portion of each of the plurality of pad electrodes. A first conductive layer is formed above the passivation layer and the plurality of pad electrodes. A seed layer is formed above the first conductive layer. The seed layer and the first conductive layer are patterned to form a plurality of island patterns of the seed layer, and the plurality of island patterns are electrically separated from each other by a plurality of annular grooves surrounding a corresponding one of the plurality of island patterns and a busbar pattern of the seed layer and the first conductive layer. A plurality of connection patterns are formed to electrically connect the plurality of island patterns and the busbar pattern, respectively. A photoresist layer is formed above the seed layer and the plurality of connection patterns. The photoresist layer includes a plurality of openings above the plurality of island patterns. One or more second conductive layers are formed on the plurality of island patterns in the plurality of openings. The photoresist layer is removed, and the plurality of connection patterns are removed, thereby forming a plurality of bump structures on the plurality of pad electrodes. In one or more of the foregoing or following embodiments, at least one of the one or more second conductive layers is formed by an electroplating process. In one or more of the foregoing or following embodiments, the plurality of connection patterns are made of a conductive material different from the seed layer, the first conductive layer, and the one or more second conductive layers. In one or more of the foregoing or following embodiments, a portion of each of the plurality of connection patterns is disposed in a corresponding one of the plurality of openings, and a lowermost layer of the one or more second conductive layers contacts that portion of each of the plurality of connection patterns.

[0086] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, an underbump metallization layer is formed over a substrate. A first photoresist layer is formed over the underbump metallization layer. The photoresist layer is patterned to form a first opening exposing a first portion of the underbump metallization layer. The underbump metallization layer is patterned to extend the first opening to expose the substrate. The first photoresist layer is removed. A first metal is deposited in the first opening to form a first metal layer. A second photoresist layer is formed over the underbump metallization layer and the first metal layer. The second photoresist layer is patterned to form a second opening layer over the underbump metallization layer. The second opening exposes a portion of the first metal layer. A second metal is deposited in the second opening to form a second metal layer. The second metal layer contacts the underbump metallization layer and the first metal layer. The second photoresist layer is removed, and the first metal layer is removed. In one or more of the foregoing or following embodiments, patterning the first photoresist layer includes forming a third opening spaced apart from the first opening exposing the second portion of the underbump metallization layer. In one or more of the foregoing or following embodiments, etching the underbump metallization layer includes extending the third opening to expose the substrate. In one or more of the foregoing or following embodiments, the second opening is disposed between the first opening and the third opening. In one or more of the foregoing or following embodiments, the first photoresist layer is removed and the second layer is removed using a stripping solution or an oxygen plasma ashing operation. In one or more of the foregoing or following embodiments, in forming under-bump metallization, a first under-bump metallization layer is formed above the substrate, and a second under-bump metallization layer is formed above the first under-bump metallization layer. In one or more of the foregoing or following embodiments, the first and second under-bump metallization layers are made of a metal selected from titanium-based metals, gold-based metals, and copper-based metals. In one or more of the foregoing or following embodiments, the first under-bump metallization layer is made of titanium-based metals, and the second under-bump metallization layer is made of gold-based metals. In one or more of the foregoing or following embodiments, the under-bump metallization surrounding the second metal layer is removed after removing the first metal layer. In one or more of the foregoing or following embodiments, the second metal layer is a bump. In one or more of the foregoing or following embodiments, the first metal and the second metal are different metals. In one or more of the foregoing or following embodiments, the first metal is selected from Ti, Cu, and combinations thereof. In one or more of the foregoing or following embodiments, the second metal is selected from Al, Au, Cr, Fe, Mn, Mg, Mo, Ni, Nb, Ta, Ti, W, Zn and alloys thereof. In one or more of the foregoing or following embodiments, a solder layer is formed over the second metal layer. In one or more of the foregoing or following embodiments, the solder is a tin alloy. In one or more of the foregoing or following embodiments, the tin alloy is selected from AgSn, SnAgCu, PbSn and CuSn.

[0087] According to another aspect of the present invention, a semiconductor device includes a semiconductor circuit disposed above a substrate, a pad electrode coupled to the semiconductor circuit, a passivation layer, one or more conductive layers disposed on the pad electrode, and a bump structure disposed on the one or more conductive layers. The bump structure includes an undercut at the interface between the bump structure and the uppermost layer of one or more first conductive layers. In one or more of the foregoing or following embodiments, the undercut is only partially formed, and no undercut is formed at the remaining portion between the bump structure and the uppermost layer of one or more first conductive layers. In one or more of the foregoing or following embodiments, one or more conductive layers on which the bump structure is formed have an island shape surrounded by an annular groove. In one or more of the foregoing or following embodiments, the bump structure has a protruding end above the annular groove. In one or more of the foregoing or following embodiments, the distance between the edge of the annular groove and the lateral end of the undercut is less than the distance between the side of the bump structure and the lateral end of the undercut. In one or more of the foregoing or following embodiments, the distance between the edge of the annular groove and the lateral end of the undercut is greater than the distance between the side of the bump structure and the lateral end of the undercut. In one or more of the foregoing or following embodiments, a portion of the bump structure is formed in the annular groove. In one or more of the foregoing or following embodiments, in a plan view, at least a portion of the uppermost layer of one or more conductive layers is exposed from the bump structure. In one or more of the foregoing or following embodiments, in a plan view, the bump structure has a rectangular shape, and the undercut is arranged on one side of the rectangular shape. In one or more of the foregoing or following embodiments, two undercuts are arranged on both sides of the rectangular shape. In one or more of the foregoing or following embodiments, the bump structure includes two or more conductive layers. In one or more of the foregoing or following embodiments, the uppermost layer of the two or more conductive layers is a solder layer. In one or more of the foregoing or following embodiments, the solder layer includes at least one selected from AgSn, SnAgCu, PbSn and CuSn. In one or more of the foregoing or following embodiments, one of the two or more conductive layers includes Ni.

[0088] According to another aspect of the present invention, a semiconductor device includes a semiconductor circuit disposed above a substrate, a plurality of pad electrodes coupled to the semiconductor circuit, a passivation layer, and a plurality of bump electrodes, each of which is disposed on a corresponding one of the plurality of pad electrodes. Each of the plurality of bump electrodes includes a first conductive layer disposed on each of the plurality of pad electrodes, a second conductive layer disposed on the first conductive layer, and a bump structure disposed on the second conductive layer. A busbar pattern formed of the same material as the first and second conductive layers is disposed between adjacent bump electrodes of the plurality of bump electrodes. The plurality of bump electrodes are separated from each other and separated from the busbar pattern by a plurality of annular grooves. In one or more of the foregoing or following embodiments, each of the plurality of bump electrodes includes an undercut at an interface between the bump structure and the second conductive layer. In one or more of the foregoing or following embodiments, in a plan view, the undercut is asymmetric relative to the center of the bump structure.

[0089] According to another aspect of the present invention, a semiconductor device includes a semiconductor circuit disposed above a substrate, a pad electrode coupled to the semiconductor circuit, a passivation layer, and a bump electrode disposed on the pad electrode. The bump electrode includes a first conductive layer disposed on the pad electrode, a second conductive layer disposed on the first conductive layer, and a bump structure disposed on the second conductive layer. The bump structure is surrounded by a busbar pattern, and the busbar pattern includes a lower layer made of the same material as the first conductive layer and an upper layer made of the same material as the second conductive layer. The bump electrode is separated from the busbar pattern by an annular groove. In one or more of the foregoing or following embodiments, in a plan view, a portion of the second conductive layer at least partially surrounds the bump structure. In one or more of the foregoing or following embodiments, in a plan view, a portion of the second conductive layer completely surrounds the bump structure.

[0090] According to another aspect of the present invention, a semiconductor device includes a substrate and at least one bump structure disposed above the substrate. At least one bump structure includes a bump disposed above an under-bump metallization layer. First and second grooves are formed in the under-bump metallization layer at the lower portion of the bump and on the opposite side of the bump structure. The distance that the first groove extends into the bump is greater than that of the second groove. In one or more of the foregoing or following embodiments, the distance that the first groove extends into the bump is 2 to 10 times that of the second groove. In one or more of the foregoing or following embodiments, the under-bump metallization layer includes a second under-bump metallization layer disposed above the first under-bump metallization layer. In one or more of the foregoing or following embodiments, the first and second under-bump metallization layers are made of a metal selected from the group consisting of titanium-based metals, gold-based metals, and copper-based metals. In one or more of the foregoing or following embodiments, the first under-bump metallization layer is made of titanium-based metals, and the second under-bump metallization layer is made of gold-based metals. In one or more of the foregoing or following embodiments, the bump is made of a metal selected from Al, Au, Cr, Fe, Mn, Mg, Mo, Ni, Nb, Ta, Ti, W, Zn, and alloys thereof. In one or more of the foregoing or following embodiments, the semiconductor device includes a plurality of bump structures disposed above a substrate. In one or more of the foregoing or following embodiments, the plurality of bump structures have a width in a range from 2 μm to 10 μm at the uppermost surface of the bump structures. In one or more of the foregoing or following embodiments, closely adjacent bump structures are spaced apart from each other by a distance in a range from 2 μm to 10 μm.

[0091] The features of several embodiments or examples are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should recognize that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming one or more first conductive layers over the substrate; forming a first photoresist layer over the one or more first conductive layers; Etching the one or more first conductive layers using the first photoresist layer as an etching mask to form island patterns of the one or more first conductive layers, wherein the island patterns of the one or more first conductive layers are separated from the busbar patterns of the one or more first conductive layers by an annular groove; forming a connection pattern to connect the island pattern and the busbar pattern; forming a second photoresist layer over the one or more first conductive layers and the connection pattern, the second photoresist layer including an opening over the island pattern; forming one or more second conductive layers on the island pattern in the opening; removing the second photoresist layer; as well as The connection pattern is removed to form a bump structure.

2. The method according to claim 1, wherein: The connection pattern is made of a conductive material different from the one or more first conductive layers and the one or more second conductive layers.

3. The method according to claim 1, wherein: The connection pattern only partially fills the annular groove to connect the island pattern and the bus bar pattern.

4. The method according to claim 3, wherein: The connection pattern is formed in a portion of the annular groove and on a portion of an upper surface of an uppermost layer of the one or more first conductive layers.

5. The method according to claim 3, wherein: A portion of the connection pattern is arranged in the opening.

6. The method according to claim 1, wherein: The connection pattern is removed by wet etching.

7. The method according to claim 1, wherein: After removing the connection pattern, the bump structure includes an undercut between the bump structure and an uppermost layer of the one or more first conductive layers.

8. The method according to claim 7, wherein: The undercut is only partially formed, and no undercut is formed at a remaining portion between the bump structure and an uppermost layer of the one or more first conductive layers.

9. A method for manufacturing a semiconductor device, comprising: forming a pad electrode coupled to a semiconductor circuit formed over a substrate; forming a passivation layer above the pad electrode; patterning the passivation layer to expose at least a portion of the pad electrode; forming a seed layer above the passivation layer and the pad electrode; Patterning the seed layer to form an island pattern of the seed layer, wherein the island pattern of the seed layer is electrically separated from the busbar pattern of the seed layer by an annular groove; forming a connection pattern to electrically connect the island pattern and the busbar pattern; forming a photoresist layer over the seed layer and the connection pattern, wherein the photoresist layer includes an opening over the island pattern; forming one or more conductive layers on the island-shaped patterns in the openings; removing the photoresist layer; as well as The connection pattern is removed to form a bump structure.

10. The method according to claim 9, wherein: At least one of the one or more conductive layers is formed by an electroplating process.

11. The method according to claim 10, wherein: During the electroplating process, the bus bar pattern is electrically connected to a potential.

12. The method according to claim 10, wherein: The seed layer includes copper or a copper alloy.

13. The method according to claim 10, wherein: At least one of the one or more conductive layers includes copper or a copper alloy. 14 . The method of claim 9 , further comprising forming a lower conductive layer over the passivation layer and the pad electrode before forming the seed layer.

15. The method according to claim 14, wherein: The lower conductive layer includes at least one selected from the group consisting of titanium-based metals, gold-based metals, and copper-based metals.

16. The method according to claim 9, wherein: The connection pattern includes at least one selected from the group consisting of Al, Au, Cr, Fe, Mn, Mg, Mo, Ni, Nb, Ta, Ti, W, Zn and alloys thereof.

17. A semiconductor device comprising: A semiconductor circuit is disposed above the substrate; a pad electrode coupled to the semiconductor circuit; A passivation layer is disposed above the pad electrode, and a portion of the pad electrode is exposed from the passivation layer; One or more conductive layers, disposed on the pad electrode; as well as A bump structure is disposed above the one or more conductive layers, wherein: The bump structure includes an undercut at an interface between the bump structure and an uppermost layer of the one or more conductive layers.

18. The semiconductor device according to claim 17, wherein: The undercut is only partially formed, and no undercut is formed at a remaining portion between the bump structure and an uppermost layer of the one or more conductive layers.

19. The semiconductor device according to claim 17, wherein: The one or more conductive layers on which the bump structure is formed have an island shape surrounded by an annular groove.

20. The semiconductor device according to claim 19, wherein The bump structure has a protruding end above the annular groove.

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