A stacked chip and preparation method thereof

Abstract

The present application discloses a stacked chip and a preparation method, wherein the stacked chip comprises: at least two mutually stacked chip units; a first support column and a first conductive column are arranged between two adjacent chip units; the first support column is used to generate supporting stress on the chip unit, and the first conductive column is used to conduct the circuits on the two connected chip units. The existing chip stacking method can improve the problem that the chip is prone to cracking and thus causing chip function failure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a stacked chip and a preparation method thereof. Background Art

[0002] In recent years, with the continuous upgrading of consumer products, the chip market has higher and higher requirements for the performance of chip components, and at the same time, the demand for the miniaturization of chip components is also increasing. At present, the use of 3D IC (three-dimensional Integrated Circuit Chip) technology can stack two chips with different functions face to face to form a functional system, which can reduce the overall area of ​​the chip, taking into account the performance while also meeting the demand for miniaturization.

[0003] However, the existing chip stacking method is prone to chip cracking, resulting in chip function failure. Summary of the invention

[0004] The embodiments of the present application provide a stacked chip and a preparation method, which can improve the existing chip stacking method, which is prone to the problem of chip cracking and chip function failure.

[0005] According to a first aspect of an embodiment of the present application, a stacked chip is provided, comprising: at least two chip units stacked on each other;

[0006] A first supporting column and a first conductive column are arranged between two adjacent chip units;

[0007] The first supporting column is used to generate supporting stress on the chip unit, and the first conductive column is used to conduct the circuits on the two connected chip units.

[0008] In a feasible implementation manner, the circuit side of the chip unit includes a circuit area and a non-circuit area, and the circuit area includes the circuit;

[0009] The contact area between the first conductive pillar and the chip unit is located in the circuit area;

[0010] The contact area between the first supporting column and the chip unit is located in the non-circuit area.

[0011] In a feasible implementation manner, the first supporting column is disposed on a virtual dividing line of the chip unit, wherein the virtual dividing line is obtained by dividing the chip unit into equal parts, and the virtual dividing line is located in the non-circuit area.

[0012] In a feasible implementation manner, the first support columns disposed on the virtual dividing line are arranged at equal intervals.

[0013] In a feasible implementation manner, it further includes a second conductive column;

[0014] The second conductive column is disposed between two non-adjacent chip units, and is used to conduct the circuits of the two connected chip units. The contact area between the second conductive column and the chip unit is located in the circuit area.

[0015] In a feasible embodiment, it further includes a second support column;

[0016] The second supporting column is disposed between two non-adjacent chip units, the second supporting column is used to generate supporting stress on the chip unit, and the contact area between the second supporting column and the chip unit is located in the non-circuit area.

[0017] In a feasible implementation manner, the method comprises: an N-th layer chip unit, an N+1-th layer chip unit and an N+2-th layer chip unit stacked in sequence, wherein N is a natural number greater than 0, the circuit side of the N-th layer chip unit is arranged opposite to the circuit side of the N+1-th layer chip unit, and the circuit side of the N-th layer chip unit is arranged opposite to the circuit side of the N+2-th layer chip unit;

[0018] The first supporting column and the first conductive column are arranged between the Nth layer chip unit and the N+1th layer chip unit;

[0019] The first supporting column is arranged between the N+1th layer chip unit and the N+2th layer chip unit;

[0020] The second conductive pillar is disposed between the Nth layer chip unit and the N+2th layer chip unit.

[0021] In a feasible implementation manner, the non-circuit area of ​​the N+1th layer chip unit is provided with a first through hole;

[0022] The second conductive column disposed between the Nth layer chip unit and the N+2th layer chip unit passes through the first through hole.

[0023] In a feasible implementation manner, it further includes a third conductive column, wherein the third conductive column is disposed between the N+1th layer chip unit and the N+2th layer chip unit;

[0024] The circuit area of ​​the N+1th layer chip unit is provided with a second through hole, and the second through hole is electrically connected to the circuit on the N+1th layer chip unit;

[0025] The third conductive column passes through the second through hole and is electrically connected to the second through hole.

[0026] In a feasible implementation manner, the material of the first supporting column and the first conductive column includes metal material.

[0027] In a feasible implementation manner, the first supporting column and the first conductive column are connected to a corresponding chip unit by metal bonding.

[0028] A second aspect of an embodiment of the present application provides a method for preparing a stacked chip, which is applied to the stacked chip as described in the first aspect, and the method comprises:

[0029] A first supporting column and a first conductive column are arranged on one side of the first layer chip unit;

[0030] The second layer chip unit is arranged opposite to the first layer chip unit, wherein the first supporting column and the first conductive column are located between the first layer chip unit connection and the second layer chip unit, the first supporting column is used to generate supporting stress on the chip unit, and the first conductive column is used to conduct the lines on the two connected chip units.

[0031] In a feasible implementation manner, before the step of providing a first supporting column and a first conductive column on one side of the first layer chip unit, the step further includes:

[0032] An integrated circuit is arranged on one side of the first layer chip unit to form a circuit side of the first layer chip unit, and an integrated circuit is arranged on one side of the second layer chip unit to form a circuit side of the second layer chip unit, wherein the circuit side of the first layer chip unit includes a first circuit area and a first non-circuit area, and the circuit side of the second layer chip unit includes a second circuit area and a second non-circuit area;

[0033] The step of providing a first supporting column and a first conductive column on one side of the first layer chip unit includes:

[0034] The first conductive column and the first supporting column are arranged on the circuit side of the first layer chip unit, wherein the contact area between the first conductive column and the first layer chip unit is located in the first circuit area, and the contact area between the first supporting column and the first layer chip unit is located in the first non-circuit area;

[0035] The step of arranging the second layer chip units relative to the first layer chip units comprises:

[0036] The second layer chip unit is arranged opposite to the first layer chip unit, wherein the contact area between the first conductive column and the second layer chip unit is located in the second circuit area, and the contact area between the first supporting column and the second layer chip unit is located in the second non-circuit area.

[0037] In a feasible implementation manner, the step of providing the first conductive column and the first supporting column on the circuit side of the first layer chip unit includes:

[0038] The first conductive column, the first supporting column, the second conductive column and / or the second supporting column are arranged on the circuit side of the first layer chip unit, wherein the contact area between the second conductive column and the first layer chip unit is located in the first circuit area, and the contact area between the second supporting column and the first layer chip unit is located in the first non-circuit area;

[0039] Before the step of arranging the second layer chip units relative to the first layer chip units, the method further includes:

[0040] An integrated circuit is arranged on one side of the third layer chip unit to form a circuit side of the third layer chip unit, wherein the circuit side of the third layer chip unit includes a third circuit area and a third non-circuit area;

[0041] Arranging a first through hole and / or a third through hole on the second layer chip unit, wherein the first through hole is arranged in the second circuit area, and the third through hole is arranged in the second non-circuit area;

[0042] After the step of arranging the second layer chip units relative to the first layer chip units, the method further includes:

[0043] The second layer chip unit and the third layer chip unit are arranged relative to each other, wherein the second conductive column is located between the first layer chip unit and the third layer chip unit, and / or the second supporting column is located between the first layer chip unit and the third layer chip unit, the second conductive column is passed through the first through hole, and / or the second supporting column is passed through the third through hole.

[0044] The stacked chips and preparation methods provided in the embodiments of the present application are as follows. During the stacking process of the stacked chips, the top chip unit will be thinned for packaging requirements. The strength of the top chip unit after thinning is reduced. The first conductive column is used to conduct the lines on the two connected chip units. The setting of the first conductive column needs to be set according to the line position on the chip unit and the electrical connection requirements. Therefore, the distribution of the first conductive column is uneven in many cases, which can easily cause the stacked chip to crack or break, resulting in functional failure of the chip. Research on the traces of cracking or the restoration of breakage has found that the crack origin or the stress concentration point of the breakage is usually at or near the position of the first conductive column. Therefore, it can be found that the uneven distribution of the first conductive column will cause different stresses at various locations on the connected chip units. In addition, the strength of the top chip unit is reduced after thinning, and it is very easy for the chip to crack or break due to uneven stress, thereby causing functional failure of the chip unit and the stacked chip. The stacked chip provided in the embodiment of the present application can generate supporting stress for the contacting chip units by setting a first supporting column, which can assist the first conductive column in supporting the chip units, and can make the overall distribution of the first conductive column and the first supporting column tend to be uniform, thereby improving the uneven stress at various locations on the connected chip units easily caused by the first conductive column, thereby solving the problem that the existing stacked chips are prone to cracking or breakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of a stacked chip structure provided in an embodiment of the present application;

[0046] Figure 2 A cross-sectional view of a stacked chip along AA′ provided in an embodiment of the present application;

[0047] Figure 3 A schematic diagram of another structure of stacked chips provided in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of the structure of another stacked chip provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of the structure of another stacked chip provided in an embodiment of the present application;

[0050] Figure 6 A schematic diagram of the position of a virtual dividing line of a stacked chip provided in an embodiment of the present application;

[0051] Figure 7 A schematic diagram of the position of another virtual dividing line of a stacked chip provided in an embodiment of the present application;

[0052] Figure 8 A side view of a stacked chip provided in an embodiment of the present application;

[0053] Fig. 9 A schematic flow chart of a method for preparing a stacked chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification are described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0055] In this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. The term "more than two" includes two or more than two situations.

[0056] In recent years, with the continuous upgrading of consumer products, the chip market has an increasingly higher demand for the performance of chip components. At the same time, the demand for the miniaturization of chip components is also increasing. At present, the use of 3D IC (which can be called stacked chip) technology can stack two chips with different functions face to face, or stack multiple chips to form a functional system, which can be called a three-dimensional chip. This functional system (three-dimensional chip) can reduce the overall area of ​​the chip, while taking into account performance, it also meets the demand for miniaturization. However, the existing chip stacking method is prone to chip cracking, resulting in chip failure.

[0057] In view of this, the present application provides a stacked chip and a preparation method, which can improve the existing chip stacking method, which is prone to the problem of chip cracking and resulting in chip function failure.

[0058] In a first aspect of an embodiment of the present application, a stacked chip is provided. Figure 1 A schematic diagram of a stacked chip structure provided in an embodiment of the present application. Figure 2A cross-sectional view of a stacked chip along AA′ provided in an embodiment of the present application. Figure 1 and Figure 2 A stacked chip provided in an embodiment of the present application includes: at least two chip units 100 stacked on each other. A first support column 300 and a first conductive column 200 are arranged between two adjacent chip units 100. The first support column 300 is used to generate supporting stress on the chip unit 100, and the first conductive column 200 is used to conduct the circuits on the two connected chip units 100. It should be noted that the chip unit 100 here can be a wafer, or a chip after the wafer is cut.

[0059] For example, Figure 2 The stacked chip shown includes two chip units, namely a bottom chip unit 101 and a top chip unit 102. The top chip unit 102 may be a chip unit that has been thinned, which is not specifically limited in this application. Figure 2 , the first supporting pillar 300 and the first conductive pillar 200 are disposed between the bottom chip unit 101 and the top chip unit 102 . Figure 2 The stacked chip shown includes two chip units, which is only for illustration purposes, and may also include more than two chip units, which is not specifically limited in this application. Figure 1 The chip unit 100 shown is rectangular, and may also be circular, elliptical or polygonal, which is not specifically limited in the present application.

[0060] The stacked chips provided in the embodiment of the present application are thinned for packaging requirements during the stacking process of the stacked chips. The strength of the thinned top chip unit 102 is reduced. The first conductive pillar 200 is used to conduct the circuits on the two connected chip units 100. The first conductive pillar 200 needs to be set according to the circuit position on the chip unit 100 and the electrical connection requirements. Therefore, the distribution of the first conductive pillar 200 is uneven in most cases, which can easily cause the stacked chip to crack or break, resulting in functional failure of the chip. Research on the traces of cracking or the restoration of breakage has found that the crack origin or the stress concentration point of the breakage is usually at or near the position of the first conductive pillar 200. Therefore, it can be found that the uneven distribution of the first conductive pillar 200 will cause different stresses at various locations on the connected chip units 100. In addition, the strength of the top chip unit 102 is reduced after thinning, which is very likely to cause the chip to crack or break due to uneven stress, thereby causing functional failure of the chip unit 100 and the stacked chip.

[0061] The stacked chip provided in the embodiment of the present application can assist the first conductive column 200 in supporting the chip unit by providing a first supporting column 300 to generate supporting stress for the contacting chip unit 100, and can make the overall distribution of the first conductive column 200 and the first supporting column 300 tend to be uniform, thereby improving the uneven stress at various locations on the connected chip unit 100 easily caused by the first conductive column 200, thereby solving the problem that the existing stacked chips are prone to cracking or breakage.

[0062] In one possible implementation, Figure 3 This is a schematic diagram of another structure of stacked chips provided in an embodiment of the present application. Figure 3 As shown, the first support column 300 can also be set at the edge of the chip unit 100. Since there is a difference in stress between the edge and the center of the chip unit 100, setting the first support column 300 at the edge of the chip unit 100 can provide more support to the edge to alleviate uneven stress.

[0063] In one possible implementation, Figure 4 This is a schematic diagram of another stacked chip structure provided in an embodiment of the present application. Figure 4 As shown, the first support column 300 disposed in the central area of ​​the chip unit 100 may include a combination of a long column and a square column, similar to a "dash-dot" shape, which can increase the supporting force and enhance the stress assist effect.

[0064] Figure 1 , Figure 3 and Figure 4 The arrangement of the first supporting pillars 300 and the first conductive pillars 200 is only for illustration and is not intended to be a specific limitation of the present application.

[0065] In one possible implementation, Figure 5 This is a schematic diagram of another stacked chip structure provided in an embodiment of the present application. Figure 5 As shown, the circuit side of the chip unit 100 includes a circuit area 110 and a non-circuit area 120, and the circuit area 110 includes circuits. The chip unit 100 can be made into circuits on one side, and the side made with circuits can be called the circuit side. The circuits on the chip unit 100 are integrated circuits integrated on the circuit side of the chip unit 100. The circuits on the chip units 100 with different functions are also different, and the circuit distribution is also different. Since the circuits are usually more complex, Figure 5 Since the first conductive pillar 200 is used to conduct the circuit on the connected chip unit 100, the contact area between the first conductive pillar 200 and the chip unit 100 is located in the circuit area 110. The contact area between the first supporting pillar 300 and the chip unit 100 is located in the non-circuit area 120. Figure 5 The circuit area 110 shown is merely an example.

[0066] In the stacked chip provided in the embodiment of the present application, since the first conductive pillars 200 are usually concentrated in the circuit area for conducting the circuits between the two chip units 100, and the non-circuit area 120 usually has no supports to provide supporting stress, the first supporting pillars 300 are arranged in the non-circuit area 120, so that the overall distribution of the first conductive pillars 200 and the first supporting pillars 300 tends to be uniform, and the first conductive pillars 200 can improve the uneven stress at various locations on the connected chip units 100, thereby solving the problem that the existing stacked chips are prone to chip cracking or breakage.

[0067] In one possible implementation, Figure 6 A schematic diagram of the position of a virtual dividing line of a stacked chip provided in an embodiment of the present application; Figure 7 A schematic diagram of the position of another virtual dividing line of a stacked chip provided in an embodiment of the present application.

[0068] like Figure 6 As shown, the chip unit 100 is divided into equal parts to obtain a virtual dividing line 400 ( Figure 6 The virtual dividing line 400 is virtual and does not need to be actually drawn on the chip unit 100. The first support column 300 is disposed on the virtual dividing line 400 of the chip unit 100. Figure 6 As shown, there is a situation where the virtual dividing line 400 may partially fall within the line area 110. In the process of determining the virtual dividing line 400, if the virtual dividing line 400 falls within the line area 110, it will cause part of the first support column 300 to be set in the line area 110. In this way, the first support column 300 may cause damage to the line in the line area 110. In order to prevent the first support column 300 from affecting the line, it is necessary to fine-tune the position of the virtual dividing line 400. Specifically, the part of the virtual dividing line 400 that falls within the line area 110 can be moved to the non-line area 120 closest to the place. At the same time, it can be evaluated as a whole whether each segmentation area is equal. By moving the position of part of the virtual dividing line 400 again, each segmentation area tends to be equal. This is to achieve the maximum degree of equal division on the basis of satisfying that the virtual dividing line 400 is located in the non-line area 120. The equal division here can be the same area.

[0069] Figure 7 The distribution position of the virtual dividing line 400 shown can be regarded as being fine-tuned to satisfy that the virtual dividing line 400 is located in the non-circuit area 120 and each dividing area tends to be equal. Figure 7 The position of the virtual dividing line 400 is only for illustration and is not intended to be a specific limitation of the present application.

[0070] The stacked chip provided in the embodiment of the present application divides the chip unit 100 into equal parts by introducing a virtual dividing line 400. If the virtual dividing line 400 falls into the circuit area 110, the virtual dividing line 400 is fine-tuned to avoid the circuit area 110, and the virtual dividing line 400 can be further adjusted to ensure that each divided area is equal. The first support column 300 is arranged on the adjusted virtual dividing line 400, so that the first support column 300 distributed on the virtual dividing line 400 can support the chip unit 100 more evenly and contribute more evenly to the support stress.

[0071] In a possible implementation, Figure 6 As shown, the virtual dividing line 400 partially falls within the circuit area 110, and the first support column 300 can be arranged on the virtual dividing line located in the non-circuit area 120. Since the first conductive column 200 is usually arranged in the circuit area 110, if the virtual dividing line 400 falls within the circuit area 110, no adjustment is made to the section of the virtual dividing line 400, and the first support column 300 is not arranged at the position where the section of the virtual dividing line 400 is located. The first support column 300 is arranged on the virtual dividing line located in the non-circuit area 120, so that the overall distribution of the first conductive column 200 and the first support column 300 tends to be uniform, and the first conductive column 200 can improve the uneven stress at various locations on the connected chip unit 100, so as to solve the problem that the existing stacked chips are prone to chip cracking or breakage.

[0072] In a feasible implementation, the first support pillars arranged on the virtual dividing line are arranged at equal intervals. The first support pillars arranged at equal intervals can provide evenly distributed stress support, so that the overall distribution of the first conductive pillars 200 and the first support pillars 300 tends to be even, which can improve the uneven stress at various locations on the connected chip unit 100 caused by the first conductive pillars 200, so as to solve the problem that the existing stacked chips are prone to chip cracking or breakage.

[0073] In one possible implementation, Figure 8 A side view of a stacked chip provided in an embodiment of the present application. Figure 8 As shown, the stacked chip may include three chip units 100, namely, a first-layer chip unit 103, a second-layer chip unit 104, and a third-layer chip unit 105. The second-layer chip unit 104 is located between the first-layer chip unit 103 and the third-layer chip unit 105, and a second conductive column 500 is further provided between the non-adjacent first-layer chip unit 103 and the third-layer chip unit 105. The second conductive column 500 is used to conduct the circuits on the connected first-layer chip unit 103 and the third-layer chip unit 105, and the contact areas of the second conductive column 500 with the first-layer chip unit 103 and the third-layer chip unit 105 are both located in the circuit area.

[0074] In a feasible embodiment, the stacked chip includes an Nth layer chip unit, an N+1th layer chip unit and an N+2th layer chip unit stacked in sequence, wherein N is a natural number greater than 0, the circuit side of the Nth layer chip unit is arranged opposite to the circuit side of the N+1th layer chip unit, and the circuit side of the Nth layer chip unit is arranged opposite to the circuit side of the N+2th layer chip unit; a first supporting column and a first conductive column are arranged between the Nth layer chip unit and the N+1th layer chip unit; a first supporting column is arranged between the N+1th layer chip unit and the N+2th layer chip unit; and a second conductive column is arranged between the Nth layer chip unit and the N+2th layer chip unit.

[0075] Continue to refer Figure 8 , for example, when N=1, the chip unit of the Nth layer, the chip unit of the N+1th layer, and the chip unit of the N+2th layer are Figure 8 The first layer chip unit 103, the second layer chip unit 104 and the third layer chip unit 105 are shown. The circuit side of the first layer chip unit 103 is arranged opposite to the circuit side of the second layer chip unit 104, which is convenient for the arrangement of the first conductive column 200. The circuit side of the first layer chip unit 103 is arranged opposite to the circuit side of the third layer chip unit 105, which is convenient for the arrangement of the second conductive column 500. The non-circuit area of ​​the second layer chip unit 104 can be provided with a first through hole 510, and the second conductive column 500 arranged between the first layer chip unit 103 and the third layer chip unit 105 is passed through the first through hole 510.

[0076] The stacked chip provided in the embodiment of the present application can electrically connect the lines of the first layer chip unit 103 and the third layer chip unit 105 together by setting the second conductive column 500 to pass through the first through hole 510, thereby realizing multi-chip unit stacking.

[0077] For example, continue to refer to Figure 8 A first support column 300 can also be set between the second-layer chip unit 104 and the third-layer chip unit 105. The position of the first support column 300 set between the second-layer chip unit 104 and the third-layer chip unit 105 can correspond to the position of the first support column 300 set between the first-layer chip unit 103 and the second-layer chip unit 104, which can play a role in stress balancing without causing additional stress unevenness.

[0078] In a feasible implementation manner, for example, continue to refer to Figure 8The stacked chip further includes a second support column 600. The second support column 600 is disposed between the non-adjacent first layer chip unit 103 and the third layer chip unit 105, and the second support column 600 is used to generate support stress on the first layer chip unit 103 and the third layer chip unit 105, and the contact area between the second support column 600 and the first layer chip unit 103 and the third layer chip unit 105 is located in the non-circuit area.

[0079] In a feasible implementation manner, for example, continue to refer to Figure 8 A third through hole 610 is disposed in the non-circuit area of ​​the second layer chip unit 104 , and the second supporting column 600 can be passed through the third through hole 610 .

[0080] The stacked chip provided in the embodiment of the present application has a second support column 600 passing through the third through hole 610 , and the second support column 600 can support the first layer chip unit 103 and the third layer chip unit 105 to balance the stress.

[0081] In a feasible implementation manner, for example, continue to refer to Figure 8 A third conductive column 700 is further provided between the second layer chip unit 104 and the third layer chip unit 105. A second through hole 710 is provided in the circuit area of ​​the second layer chip unit 104. The second through hole 710 is electrically connected to the circuit on the second layer chip unit 104. The third conductive column 700 is passed through the second through hole 710 and is electrically connected to the second through hole 710. The third conductive column 700 can be used to conduct the circuits on the second layer chip unit 104 and the third layer chip unit 105.

[0082] The stacked chip provided in the embodiment of the present application can realize stacking of multiple chip units and electrical connection of multiple chip units by setting a third conductive column 700 passing through the second through hole 710. The third conductive column 700 can electrically connect the second layer chip unit 104 with the third layer chip unit 105.

[0083] In a feasible implementation, for example, reference Figure 1 The materials of the first supporting column 300 and the first conductive column 200 include metal materials.

[0084] In a feasible implementation, for example, reference Figure 1 The first support column 300 and the first conductive column 200 can be made of the same material. The first support column 300 and the first conductive column 200 are made of the same material, and the first support column 300 and the first conductive column 200 can be prepared in the same process, which can optimize the process flow and achieve the effect of improving the uneven stress problem of the stacked chips without increasing the process cost.

[0085] In a feasible implementation manner, the first support pillar 300 and the first conductive pillar 200 are connected to a corresponding chip unit 100 by metal bonding. Figure 2 If the first support pillar 300 and the first conductive pillar 200 are both made of metal materials, the first support pillar 300 and the first conductive pillar 200 are first prepared on the bottom chip unit 101, and then the top chip unit 102 is arranged and bonded with the first support pillar 300 and the first conductive pillar 200 by metal bonding to obtain a stacked chip. It should be noted that the top chip unit 102 can be thinned on the non-circuit side (thinning the back side) before bonding.

[0086] In one possible implementation, reference Figure 1 The contact areas between the chip unit 100 and the first support column 300 and the first conductive column 200 may be provided with pads, which may be made of metal material, so as to facilitate bonding the chip unit 100 to the first support column 300 and the first conductive column 200 by metal bonding during the preparation process, which is not specifically limited in the present application.

[0087] A second aspect of the embodiments of the present application provides a method for preparing a stacked chip, which is applied to the stacked chip as described in the first aspect. Fig. 9 A schematic flow chart of a method for preparing a stacked chip provided in an embodiment of the present application. Fig. 9 As shown, the method for preparing the stacked chip provided in the embodiment of the present application includes:

[0088] S100: Arranging a first supporting column and a first conductive column on one side of a first layer chip unit;

[0089] S200: The second layer chip unit is arranged opposite to the first layer chip unit, wherein the first supporting column and the first conductive column are located between the first layer chip unit and the second layer chip unit, the first supporting column is used to generate supporting stress on the chip unit, and the first conductive column is used to conduct the circuits on the two connected chip units.

[0090] In a feasible implementation manner, before the step of providing a first supporting column and a first conductive column on one side of the first layer chip unit, the method further includes:

[0091] An integrated circuit is arranged on one side of the first layer chip unit to form a circuit side of the first layer chip unit, and an integrated circuit is arranged on one side of the second layer chip unit to form a circuit side of the second layer chip unit, wherein the circuit side of the first layer chip unit includes a first circuit area and a first non-circuit area, and the circuit side of the second layer chip unit includes a second circuit area and a second non-circuit area;

[0092] The step of providing a first supporting column and a first conductive column on one side of the first layer chip unit includes:

[0093] A first conductive column and a first supporting column are arranged on the circuit side of the first layer chip unit, wherein the contact area between the first conductive column and the first layer chip unit is located in the first circuit area, and the contact area between the first supporting column and the first layer chip unit is located in the first non-circuit area;

[0094] The step of arranging the second layer chip units relative to the first layer chip units comprises:

[0095] The second layer chip unit is arranged opposite to the first layer chip unit, wherein the contact area between the first conductive column and the second layer chip unit is located in the second circuit area, and the contact area between the first supporting column and the second layer chip unit is located in the second non-circuit area.

[0096] In a feasible implementation manner, the step of providing a first conductive column and a first supporting column on the circuit side of the first layer chip unit includes:

[0097] A first conductive column, a first supporting column, a second conductive column and / or a second supporting column are arranged on the circuit side of the first layer chip unit, wherein the contact area between the second conductive column and the first layer chip unit is located in the first circuit area, and the contact area between the second supporting column and the first layer chip unit is located in the first non-circuit area;

[0098] Before the step of arranging the second layer chip units relative to the first layer chip units, the method further includes:

[0099] An integrated circuit is arranged on one side of the third layer chip unit to form a circuit side of the third layer chip unit, wherein the circuit side of the third layer chip unit includes a third circuit area and a third non-circuit area;

[0100] Arranging a first through hole and / or a third through hole on the second layer chip unit, wherein the first through hole is arranged in the second circuit area, and the third through hole is arranged in the second non-circuit area;

[0101] After the step of arranging the second layer chip units relative to the first layer chip units, the method further includes:

[0102] The second layer chip unit and the third layer chip unit are arranged opposite to each other, wherein the second conductive column is located between the first layer chip unit and the third layer chip unit, and / or the second supporting column is located between the first layer chip unit and the third layer chip unit, the second conductive column is passed through the first through hole, and / or the second supporting column is passed through the third through hole.

[0103] By way of example, taking a stacked chip including two layers of chip units (including a bottom chip unit and a top chip unit) as an example, the method for preparing the stacked chip is briefly described as follows.

[0104] A method for preparing a stacked chip comprises the following steps:

[0105] Step 1: an integrated circuit is arranged on one side of the bottom chip unit to form the circuit side of the bottom chip unit. In this step, during the process of arranging the integrated circuit, a conductive pad can be arranged at the position where the first conductive column needs to be arranged. The conductive pad is not specifically limited in this application and can be arranged or not.

[0106] Step 2: a first conductive column and a first support column are arranged on the circuit side of the bottom chip unit, wherein the first conductive column is arranged in the circuit area, and the first support column is arranged in the non-circuit area. If the first conductive column and the first support column are made of the same material, the first conductive column and the first support column can be prepared simultaneously. The first conductive column and the first support column can be obtained by a preparation method of film formation and etching, or the first conductive column and the first support column prepared in advance can be bonded to the circuit side of the bottom chip unit by metal bonding.

[0107] Step three, an integrated circuit is set on one side of the top chip unit to form the circuit side of the top chip unit. Similarly, in the process of setting the integrated circuit in the top chip unit, a conductive pad can be set at the corresponding position where the first conductive column needs to be set. The present application does not make any specific restrictions on the conductive pad, which may or may not be set. If the first support column and the top chip unit are bonded by metal bonding, a pad can also be set in the contact area corresponding to the top chip unit and the first support column. Since the first support column is located in the non-circuit area, even if the pad is made of metal material, the circuit will not be turned on.

[0108] Step 4: Thinning the non-circuit side of the top chip unit. It should be noted that the order of step 3 and step 4 can be reversed, and the thinning process sequence can be adjusted according to the actual process flow design.

[0109] Step 5, the top chip unit is bonded to the first support column and the first conductive column respectively by metal bonding, and the circuit side of the bottom chip unit is opposite to the circuit side of the top chip unit. It should be noted that step 5 is based on the premise that the first support column and the first conductive column are both made of metal materials. In addition, the top chip unit is metal-bonded to the ends of the first support column and the first conductive column away from the bottom chip unit.

[0110] Taking a stacked chip including three layers of chip units as an example (including a first layer of chip units, a second layer of chip units and a third layer of chip units), the preparation method of the stacked chip is briefly described as follows.

[0111] When the stacked chip includes three chip units, the bottom chip unit is the first layer chip unit, the top chip unit is the third layer chip unit, and the second layer chip unit may also be thinned, which is not specifically limited in this application.

[0112] Step 2 may also include:

[0113] A second conductive column and / or a second supporting column is arranged on the circuit side of the first layer chip unit.

[0114] The following steps need to be included before step 5:

[0115] An integrated circuit is arranged on one side of the second-layer chip unit to form the circuit side of the second-layer chip. Similarly, in the process of setting the integrated circuit in the second-layer chip unit, a conductive pad can be simultaneously set at the corresponding position where the first conductive column needs to be set. The present application does not make any specific limitation on the conductive pad, which may or may not be set. If the first support column and the top chip unit are bonded by metal bonding, a pad can also be set in the contact area corresponding to the top chip unit and the first support column. Since the first support column is located in the non-circuit area, even if the pad is made of metal material, the circuit will not be turned on.

[0116] A first through hole and / or a third through hole are arranged on the second layer chip unit. The first through hole is arranged in the circuit area, and the third through hole is arranged in the non-circuit area.

[0117] The second layer chip unit is bonded to the first conductive column and the second conductive column on the first layer chip unit, and the circuit side of the first layer chip unit corresponds to the circuit side of the second layer chip unit; at the same time, the second conductive column passes through the first through hole, and / or the second supporting column passes through the third through hole.

[0118] Step five may include:

[0119] Bonding the third layer chip unit to the second support column by metal bonding; and / or,

[0120] The third layer chip unit is bonded to the second conductive column by metal bonding, and the circuit side of the third layer chip unit is opposite to the circuit side of the first layer chip unit.

[0121] If a third conductive column is provided between the second layer chip unit and the third layer chip unit, a second through hole needs to be provided in the circuit area of ​​the second layer chip unit, and the second through hole is electrically connected to the circuit of the second layer chip unit. The third conductive column can be provided on the back of the second layer chip unit and electrically connected to the second through hole, and then bonded to the third layer chip unit. Alternatively, the third conductive column can be provided on the third layer chip unit first, and then the third conductive column is inserted into the second through hole to achieve electrical connection.

[0122] The above preparation method steps are merely illustrative and are not intended to be specific limitations of the present application.

[0123] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0124] Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalents, this specification is also intended to include these modifications and variations.

Claims

1. A stacked chip, It is characterized in that include: at least two chip units stacked on top of each other; A first supporting column and a first conductive column are arranged between two adjacent chip units; The first supporting column is used to generate supporting stress on the chip unit, and the first conductive column is used to conduct the circuits on the two connected chip units, wherein the first supporting column is arranged at the edge of the chip unit, and the first supporting column includes a combination of a long strip column and a square column; a second conductive column; The second conductive column is disposed between two non-adjacent chip units; The second conductive column is used to conduct the circuits of the two connected chip units; a second support column; The second supporting column is arranged between two non-adjacent chip units; The second supporting column is used to generate supporting stress on the chip unit.

2. The stacked chip according to claim 1, characterized in that: The circuit side of the chip unit includes a circuit area and a non-circuit area, and the circuit area includes the circuit; The contact area between the first conductive pillar and the chip unit is located in the circuit area; The contact area between the first supporting column and the chip unit is located in the non-circuit area.

3. The stacked chip according to claim 2, characterized in that: The first supporting column is disposed on a virtual dividing line of the chip unit, wherein the virtual dividing line is obtained by dividing the chip unit into equal parts, and the virtual dividing line is located in the non-circuit area.

4. The stacked chip according to claim 3, characterized in that: The first support columns disposed on the virtual dividing line are arranged at equal intervals.

5. The stacked chip according to claim 2, characterized in that: The contact area between the second conductive pillar and the chip unit is located in the circuit area.

6. The stacked chip according to claim 5, characterized in that: The contact area between the second supporting column and the chip unit is located in the non-circuit area.

7. The stacked chip according to claim 6, characterized in that: include: The Nth layer chip unit, the N+1th layer chip unit and the N+2th layer chip unit are stacked in sequence, where N is a natural number greater than 0; The circuit side of the Nth layer chip unit is arranged opposite to the circuit side of the N+1th layer chip unit; The circuit side of the Nth layer chip unit is arranged opposite to the circuit side of the N+2th layer chip unit; The first supporting column and the first conductive column are arranged between the Nth layer chip unit and the N+1th layer chip unit; The first supporting column is arranged between the N+1th layer chip unit and the N+2th layer chip unit; The second conductive pillar is disposed between the Nth layer chip unit and the N+2th layer chip unit.

8. The stacked chip according to claim 7, characterized in that: The non-circuit area of ​​the N+1th layer chip unit is provided with a first through hole; The second conductive column disposed between the Nth layer chip unit and the N+2th layer chip unit passes through the first through hole.

9. The stacked chip according to claim 7, characterized in that: Also includes a third conductive column, The third conductive column is disposed between the N+1th layer chip unit and the N+2th layer chip unit; The circuit area of ​​the N+1th layer chip unit is provided with a second through hole; The second through hole is electrically connected to the circuit on the N+1th layer chip unit; The third conductive column passes through the second through hole and is electrically connected to the second through hole.

10. The stacked chip according to claim 1, characterized in that: The first supporting column and the first conductive column are made of metal.

11. The stacked chip according to claim 10, characterized in that: The first supporting column and the first conductive column are connected to a corresponding chip unit by metal bonding.

12. A method for preparing a stacked chip, characterized in that: Applied to the stacked chip according to any one of claims 1 to 11, the method comprising: A first supporting column and a first conductive column are arranged on one side of the first layer chip unit; The second layer chip unit is arranged opposite to the first layer chip unit, wherein the first supporting column and the first conductive column are located between the first layer chip unit connection and the second layer chip unit, the first supporting column is used to generate supporting stress on the chip unit, and the first conductive column is used to conduct the lines on the two connected chip units.

13. The method for preparing stacked chips according to claim 12, characterized in that: Before the step of providing a first supporting column and a first conductive column on one side of the first layer chip unit, the method further includes: An integrated circuit is arranged on one side of the first layer chip unit to form a circuit side of the first layer chip unit, and an integrated circuit is arranged on one side of the second layer chip unit to form a circuit side of the second layer chip unit, wherein the circuit side of the first layer chip unit includes a first circuit area and a first non-circuit area, and the circuit side of the second layer chip unit includes a second circuit area and a second non-circuit area; The step of providing a first supporting column and a first conductive column on one side of the first layer chip unit includes: The first conductive column and the first supporting column are arranged on the circuit side of the first layer chip unit, wherein the contact area between the first conductive column and the first layer chip unit is located in the first circuit area, and the contact area between the first supporting column and the first layer chip unit is located in the first non-circuit area; The step of arranging the second layer chip units relative to the first layer chip units comprises: The second layer chip unit is arranged opposite to the first layer chip unit, wherein the contact area between the first conductive column and the second layer chip unit is located in the second circuit area, and the contact area between the first supporting column and the second layer chip unit is located in the second non-circuit area.

14. The method for preparing stacked chips according to claim 13, characterized in that: The step of providing the first conductive column and the first supporting column on the circuit side of the first layer chip unit includes: The first conductive column, the first supporting column, the second conductive column and / or the second supporting column are arranged on the circuit side of the first layer chip unit, wherein the contact area between the second conductive column and the first layer chip unit is located in the first circuit area, and the contact area between the second supporting column and the first layer chip unit is located in the first non-circuit area; Before the step of arranging the second layer chip units relative to the first layer chip units, the method further includes: An integrated circuit is arranged on one side of the third layer chip unit to form a circuit side of the third layer chip unit, wherein the circuit side of the third layer chip unit includes a third circuit area and a third non-circuit area; Arranging a first through hole and / or a third through hole on the second layer chip unit, wherein the first through hole is arranged in the second circuit area, and the third through hole is arranged in the second non-circuit area; After the step of arranging the second layer chip units relative to the first layer chip units, the method further includes: The second layer chip unit and the third layer chip unit are arranged relative to each other, wherein the second conductive column is located between the first layer chip unit and the third layer chip unit, and / or the second supporting column is located between the first layer chip unit and the third layer chip unit, the second conductive column is passed through the first through hole, and / or the second supporting column is passed through the third through hole.

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