Solar cell and method for manufacturing the same

Abstract

The embodiments of the present disclosure provide a solar cell and a manufacturing method thereof. The solar cell comprises: a silicon substrate; at least one layer pair, arranged on the surface of the silicon substrate, wherein each layer pair in the at least one layer pair comprises: an oxide layer, arranged on a side of the layer pair close to the silicon substrate; and a doped silicon film layer, arranged on a side of the oxide layer away from the silicon substrate, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than the thickness of other oxide layers in the at least one layer pair.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a solar cell and a method for manufacturing the same. Background Art

[0002] For crystalline silicon solar cells, defects on the surface of the silicon substrate can easily lead to minority carrier recombination and affect the photoelectric conversion of the crystalline silicon solar cell. Therefore, it is usually necessary to set a passivation structure between the silicon substrate surface and the electrode to passivate the silicon substrate surface to reduce the recombination rate of minority carriers on the surface of the crystalline silicon substrate.

[0003] The stacked passivation structure of the tunneling oxide layer and the doped silicon film layer is used to passivate the surface of the silicon substrate, which can achieve an excellent passivation effect.

[0004] From the perspective of passivation effect, the higher the concentration of doping atoms in the doped silicon film layer, the better. However, if the doping concentration is too high, the doping atoms will penetrate through the oxide layer and reach the silicon substrate in the subsequent high-temperature activation process, and the passivation effect will be reduced after the doping atoms reach the silicon substrate. Summary of the invention

[0005] Embodiments of the present disclosure provide a solar cell and a method for manufacturing the same. The solar cell has reduced contact resistance between an electrode and a doped silicon film layer and improved fill factor.

[0006] On the one hand, an embodiment of the present disclosure provides a solar cell, comprising: a silicon substrate; at least one layer pair arranged on the surface of the silicon substrate, wherein each layer pair in the at least one layer pair comprises: an oxide layer arranged on a side of the layer pair close to the silicon substrate; and a doped silicon film layer arranged on a side of the oxide layer away from the silicon substrate, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than the thickness of other oxide layers in the at least one layer pair.

[0007] For example, in a direction from the surface of the silicon substrate to a direction away from the silicon substrate, the thickness of the oxide layer in the at least one layer pair decreases successively.

[0008] For example, the thicknesses of the other oxide layers in the at least one layer pair except the oxide layer closest to the silicon substrate are the same.

[0009] For example, in the at least one layer pair, the thickness of the outermost oxide layer is smaller than the thickness of other oxide layers in the at least one layer pair.

[0010] For example, the oxide layer closest to the silicon substrate in the at least one layer pair has a thickness greater than 1.8 nm and less than or equal to 2.5 nm, and the thickness of other oxide layers excluding the oxide layer closest to the silicon substrate is less than 1.8 nm.

[0011] For example, the doped silicon film layer is an n-type doped silicon film layer, and the doping concentration of the n-type dopant of the n-type doped silicon film layer in the at least one layer pair gradually increases in a direction from the surface of the silicon substrate to away from the silicon substrate.

[0012] For example, the doping concentration of the n-type dopant in the n-type doped silicon film layer closest to the silicon substrate in the at least one layer pair is greater than 1*10 20 cm -3 .

[0013] For example, the solar cell further includes: an electrode, which is arranged on a side of the at least one layer pair away from the silicon substrate.

[0014] For example, the number of the at least one layer pair is 2-50.

[0015] On the other hand, an embodiment of the present disclosure also provides a method for manufacturing a solar cell according to the first aspect, comprising: providing a silicon substrate; forming at least one layer pair on the surface of the silicon substrate, wherein forming the at least one layer pair comprises: forming an oxide layer on a side of each layer pair in the at least one layer pair close to the silicon substrate; forming a doped silicon film layer on a side of the oxide layer away from the silicon substrate, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than the thickness of other oxide layers in the at least one layer pair.

[0016] For example, the at least one layer pair includes 3 or more layer pairs, and forming the at least one layer pair includes: S1, forming an oxide layer on the surface of the silicon substrate; S2, depositing an in-situ doped silicon film layer on the oxide layer closest to the silicon substrate; S3, forming an oxide layer on the doped silicon film layer; S4, depositing an in-situ doped silicon film layer on the oxide layer; repeating the above steps S3-S4 until the second to last layer pair is formed.

[0017] For example, the manufacturing method of the solar cell also includes: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming an undoped silicon film layer on the oxide layer; performing ion implantation on the undoped silicon film to implant dopants; and performing high temperature annealing to activate the dopants in the doped silicon film layer.

[0018] For example, the manufacturing method of the solar cell also includes: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming an undoped silicon film layer on the oxide layer; and performing high-temperature diffusion of dopants on the undoped silicon film and high-temperature annealing to activate dopants in the doped silicon film layers of all layer pairs.

[0019] For example, the method for manufacturing the solar cell further includes: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; depositing the in-situ doped silicon film layer on the oxide layer; and performing high temperature annealing to activate dopants in the doped silicon film layer.

[0020] For example, forming an oxide layer on the surface of the silicon substrate includes: introducing oxygen or a mixed gas of oxygen and nitrogen into a chamber at a process temperature in the range of 400-700° C., and performing an oxidation process for 1-90 minutes.

[0021] For example, at a process temperature in the range of 400-700°C, oxygen or a mixed gas of oxygen and nitrogen is introduced into the chamber, and an oxidation process is performed for 1-90 minutes, including: at a process temperature of 630°C, oxygen with a flow rate of 3000sccm and nitrogen with a flow rate of 11000sccm are introduced into the chamber for 15 minutes to obtain an oxide layer with a thickness of 1.9nm.

[0022] For example, the silicon substrate is an n-type silicon wafer, the doped silicon film layer is an n-type doped silicon film layer, and the doping concentration of the n-type doped silicon film layer in the at least one layer pair gradually increases from the surface of the silicon substrate to the direction away from the silicon substrate.

[0023] For example, the forming of at least one layer pair is carried out in the same deposition chamber, and the forming of the doped silicon film layer and the oxide layer except the penultimate layer pair includes: in the LPCVD deposition chamber, introducing phosphine gas and silane gas with a flow ratio of 0.4:100; stopping the introduction of the phosphine gas and the silane gas and evacuating the chamber; introducing oxygen into the LPCVD deposition chamber to form an in-situ oxide layer; forming the doped silicon film layer of the penultimate layer pair includes: in the LPCVD deposition chamber, introducing phosphine gas and silane gas with a flow ratio of 0.6:100 to form an in-situ doped silicon film layer.

[0024] For example, performing high temperature annealing includes performing high temperature annealing at 880-960° C. for 25-90 minutes.

[0025] For example, the high temperature diffusion of dopants and high temperature annealing of the non-doped silicon film includes: introducing a phosphorus source with a flow rate of 1000 sccm and an oxygen gas with a flow rate of 200 sccm into the in-situ deposition chamber at 770-830°C for 30 minutes; and annealing at 820-880°C for 45 minutes.

[0026] For example, providing a silicon substrate includes: providing a single crystal N-type silicon wafer; performing texturing and boron diffusion on the silicon wafer to prepare a PN junction, leveling the back surface, and retaining a borosilicate glass layer on the front surface; cleaning the silicon wafer with a hydrofluoric acid solution; after forming at least one layer pair on the surface of the silicon substrate, the manufacturing method also includes: cleaning and removing the silicon film coated on the front side of the silicon wafer; depositing an aluminum oxide film on the front side of the silicon wafer; depositing a silicon nitride coating on the front and back sides of the silicon wafer; printing a metal slurry on the front and back sides of the silicon wafer and sintering, wherein the at least one layer pair is formed on the back side of the silicon wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0028] Figure 1 A schematic structural diagram of a solar cell according to an embodiment of the present disclosure is shown;

[0029] Figure 2 Another schematic structural diagram of a solar cell according to an embodiment of the present disclosure is shown;

[0030] Figure 3 A schematic diagram showing a method for manufacturing a solar cell according to an embodiment of the present disclosure is shown;

[0031] Figure 4 The relationship between the depth of the doped silicon film and the concentration of phosphorus atoms obtained in Comparative Example 1 is shown;

[0032] Figure 5 A graph showing the relationship between the depth of the doped silicon film obtained in Comparative Example 2 and the concentration of phosphorus atoms; and

[0033] Figure 6 A graph showing the relationship between the depth of the doped silicon film obtained in Example 1 and the phosphorus atom concentration is shown. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "one", "one" or "the" and other similar words do not indicate quantity restrictions, but indicate that there is at least one. "Including" or "including" and other similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] For N-type cells with tunneling oxide contact structure, the concentration of phosphorus in the silicon film is designed to increase from the silicon wafer surface to the electrode contact surface, and the energy level of the silicon film in the passivation contact interface gradually decreases from the silicon wafer surface to the electrode contact surface. The advantages of this design are: first, high-dose doped silicon film is conducive to forming ohmic contact between the metal electrode and the silicon film, reducing the metal-silicon contact resistance and improving the fill factor; second, the highly doped silicon film layer far away from the surface of the silicon wafer can further enhance the electron tunneling through the oxide layer to the electrode, which is conducive to reducing the contact resistance and improving the fill factor; third, under the condition of satisfying the passivation, the phosphorus atom concentration of the silicon film near the surface of the silicon wafer is appropriately reduced, so as to avoid the occurrence of phosphorus atoms penetrating through the oxide layer and reducing the passivation effect during the subsequent high-temperature activation process.

[0037] From the perspective of passivation effect, the higher the concentration of activated phosphorus atoms in the silicon film, the better. Because high concentrations of phosphorus atoms are doped into the silicon film, the degree of downward bending of the energy band of the silicon film increases. This is conducive to the entire interface extracting more electrons from the silicon matrix, repelling more minority holes, and improving the passivation effect of the silicon wafer. In actual operation, increasing the supply of phosphorus atoms (such as increasing the proportion of phosphine gas or increasing the dose of phosphorus ion implantation) can increase the concentration of phosphorus atoms in the silicon film. However, if the phosphorus supply is too high, the phosphorus atoms will penetrate the silicon wafer surface and tunnel through the oxide layer due to excessive concentration in the subsequent high-temperature activation process. After the phosphorus atoms reach the silicon matrix, the passivation effect will be reduced. Therefore, for the passivation interface of the silicon wafer surface / silicon oxide layer / doped silicon layer, it is necessary to select a suitable phosphorus atom supply, which can meet the passivation effect and not have too many phosphorus atoms penetrate.

[0038] In the process of in-situ doping of silicon film with phosphorus, the concentration of phosphorus atoms in the silicon film can be controlled by controlling the gas flow ratio of phosphine to silane. Furthermore, a silicon film with a variable doping dose can be prepared during the deposition stage. For example, the concentration of phosphorus atoms in the silicon film gradually increases from the end near the surface of the silicon wafer to the end far from the surface of the silicon wafer. Similarly, because the diffusion rate of phosphorus atoms in the silicon film is relatively fast, in the subsequent high-temperature activation process, the high-concentration phosphorus atoms in the silicon film will diffuse to the low-concentration area, and ultimately the distribution of phosphorus atom concentration in the entire silicon film will not differ too much. That is, silicon films with different phosphorus atom concentration distributions are obtained only by controlling and changing the deposition conditions, and the concentration distribution of phosphorus atoms in the entire silicon film after high-temperature activation is not much different.

[0039] An embodiment of the present disclosure provides a solar cell, comprising: a silicon substrate; at least one layer pair, arranged on the surface of the silicon substrate, wherein each layer pair in the at least one layer pair comprises: an oxide layer, arranged on the side of the layer pair close to the silicon substrate; and a doped silicon film layer, arranged on the side of the oxide layer away from the silicon substrate, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than the thickness of the other oxide layers in the at least one layer pair. By arranging an oxide layer, for example, a silicon oxide layer, between silicon films, the diffusion coefficient of phosphorus atoms in the silicon oxide film under high temperature conditions is smaller than its diffusion coefficient in the silicon film, so the silicon oxide layer in the middle of the silicon film can serve as a barrier layer for the diffusion of phosphorus atoms. After introducing different doses of phosphorus elements into the silicon film on both sides of the oxide layer and annealing at high temperature, a silicon film with different phosphorus doping concentration distributions can be obtained. Moreover, the outermost doped silicon film layer of the silicon substrate is in contact with the electrode, and the thickness of the oxide layer on the side away from the silicon substrate is made smaller than the thickness of the oxide layer close to the silicon substrate, which is more conducive to the tunneling of electrons. The electrons of the inner doped silicon film within the outermost doped silicon film can also tunnel through the oxide layer to reach the electrode, thereby further reducing the contact resistance between the electrode and the doped silicon film layer and improving the fill factor.

[0040] The solar cell and the manufacturing method thereof according to the embodiment of the present disclosure are described in detail below with reference to the accompanying drawings.

[0041] like Figure 1 As shown, the solar cell 1000 provided by the embodiment of the present disclosure includes: a silicon substrate 100; at least one layer pair 200, for example, a tunneling passivation layer, arranged on the surface of the silicon substrate, wherein each layer pair 210 in the at least one layer pair includes: an oxide layer 211, arranged on a side of the layer pair close to the silicon substrate 100; and a doped silicon film layer 212, arranged on a side of the oxide layer 211 away from the silicon substrate, wherein the thickness of the oxide layer 211 closest to the silicon substrate in the at least one layer pair is greater than the thickness of the other oxide layers 221 and 231 in the at least one layer pair.

[0042] Figure 1 At least one layer pair 200 includes three layer pairs, the layer pair close to the silicon substrate 100 is layer pair 210, including an oxide layer 211 and a doped silicon film layer 212, the layer pair 220 outwards includes an oxide layer 221 and a doped silicon film layer 222, and the layer pair 230 includes an oxide layer 231 and a doped silicon film layer 232. Figure 1 It is only a schematic diagram showing the solar cell according to the embodiment of the present disclosure. The solar cell according to the embodiment of the present disclosure does not only include three layer pairs. For example, the solar cell may include 2-50 layer pairs. Those skilled in the art may make a selection according to actual needs.

[0043] In the embodiment of the present disclosure, an electrode is disposed outside the doped silicon film layer of the outermost layer pair, for example, Figure 2 The electrode 710 shown in the figure, by setting the thickness of the oxide layer 211 on the side closest to the silicon substrate to be greater than the thickness of the oxide layers 221 and 231 in the other layer pairs, the role of the silicon oxide layer set between the doped silicon film layers is to block the diffusion of phosphorus atoms, and also to block the tunneling of electrons. By setting the oxide layer farthest from the silicon wafer to have the smallest thickness, the electrons in the inner doped silicon film layer can also tunnel through the oxide layer to reach the electrode, thereby further reducing the contact resistance between the electrode and the outermost doped silicon film layer and improving the fill factor.

[0044] For example, in the solar cell 1000, in a direction from the surface 101 of the silicon substrate to a direction away from the silicon substrate, for example, Figure 1 In the direction indicated by arrow A, the thickness of the oxide layers in the at least one layer pair decreases successively, that is, the thickness of the oxide layers 211 , 221 , and 231 decreases gradually.

[0045] For example, in the solar cell 1000 of the embodiment of the present disclosure, except for the oxide layer 211 on the surface 101 closest to the silicon substrate, the other oxide layers in the at least one layer pair, such as the oxide layer 221 and the oxide layer 231, have the same thickness, and those skilled in the art can select as needed.

[0046] For example, in the solar cell 1000 of the embodiment of the present disclosure, it may also be that: in other layer pairs except the layer pair 210 closest to the surface 101 of the silicon substrate, in the direction indicated by the arrow A, the thickness of the outermost oxide layer is less than the thickness of other oxide layers in other layer pairs, for example, the thickness of the oxide layer 231 is less than the thickness of the oxide layer 221.

[0047] For example, the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than 1.8 nm and less than or equal to 2.5 nm, and the thickness of the other oxide layers except the oxide layer closest to the silicon substrate is less than 1.8 nm. Figure 1 As shown, the thickness of the oxide layer 211 of the layer pair 210 closest to the surface 101 of the silicon substrate in at least one layer pair 200 may be greater than 1.8 nm and less than or equal to 2.5 nm, while the thickness of other oxide layers, for example, the oxide layers 221 and 231 may be less than 1.8 nm.

[0048] For example, in the solar cell 1000 of the embodiment of the present disclosure, the silicon substrate may be an n-type substrate, the at least one layer pair, for example, the tunnel passivation layer is arranged on the back side of the n-type substrate, that is, the opposite side of the sunlight absorption surface, the doped silicon film layer may be an n-type doped silicon film layer, and the doping concentration of the n-type dopant of the n-type doped silicon film layer in the at least one layer pair gradually increases from the surface of the silicon substrate to the direction away from the silicon substrate, for example, the n-type dopant may be antimony, phosphorus or arsenic. For example, in the direction from the surface 101 close to the silicon substrate to the direction away from the silicon substrate, the doping concentration of the n-type dopant, for example, phosphorus, of the n-type dopant of the n-type doped silicon film layers 212, 222, 232 gradually increases, so that the doping concentration of the doped silicon film layer of the contact electrode is higher, which is conducive to forming an ohmic contact between the metal electrode and the silicon film, reducing the metal-silicon contact resistance, and improving the fill factor. Moreover, under the condition of satisfying the passivation condition, appropriately reducing the concentration of phosphorus atoms in the silicon film near the surface of the silicon wafer can prevent phosphorus atoms from penetrating the silicon wafer surface through the oxide layer during the subsequent high-temperature activation process, thereby reducing the passivation effect, thereby widening the entire process matching window and facilitating industrial mass production. Moreover, the relatively highly doped silicon film layer far from the surface of the silicon wafer can further promote electrons from the silicon wafer end to reach the electrode after tunneling through the oxide layer, increasing the battery current and improving the fill factor.

[0049] Alternatively, in the solar cell of the embodiment of the present disclosure, the silicon substrate may also be a p-type substrate, the solar cell may be a PERC cell, the at least one layer pair, for example, the tunnel passivation layer is arranged on the front side of the p-type substrate, that is, the sunlight absorption side, the side of the n+ emitter away from the p-type substrate, the at least one layer pair may be arranged in a partial area, that is, arranged as a local structure, for example, the at least one layer pair may be arranged on the side of the front electrode of the battery facing the p-type substrate, that is, the at least one layer pair may be arranged in the area between the p-type substrate and the front electrode directly opposite to the front electrode. The doped silicon film layer may be an n-type doped silicon film layer, and the doping concentration of the n-type dopant of the n-type doped silicon film layer in the at least one layer pair gradually increases in the direction from the surface of the silicon substrate to the direction away from the silicon substrate, for example, the n-type dopant may be antimony, phosphorus or arsenic. For example, in the direction from the surface close to the silicon substrate to the direction away from the silicon substrate, the doping concentration of the n-type dopant, such as phosphorus, of the n-type doped silicon film layer gradually increases, so that the doping concentration of the doped silicon film layer contacting the electrode is relatively high, which is conducive to forming an ohmic contact between the metal electrode and the silicon film, reducing the metal-silicon contact resistance, and improving the fill factor. Moreover, under the condition of satisfying the passivation, appropriately reducing the concentration of phosphorus atoms in the silicon film near the surface of the silicon wafer can avoid the occurrence of phosphorus atoms penetrating the silicon wafer surface and tunneling through the oxide layer during the subsequent high-temperature activation process, thereby reducing the passivation effect, thereby widening the entire process matching window, and facilitating industrial mass production. Moreover, the relatively highly doped silicon film layer far from the surface end of the silicon wafer can further promote electrons from the silicon wafer end to reach the electrode after tunneling through the oxide layer, increasing the battery current and improving the fill factor.

[0050] For example, the n-type dopant concentration of the n-type doped silicon film layer closest to the silicon substrate in the at least one layer pair may be greater than 1*10 20 cm -3 .

[0051] For example, Figure 2 As shown, the solar cell 1000 according to the embodiment of the present disclosure may further include an electrode 710 , which is disposed on a side of the at least one layer pair away from the silicon substrate 100 .

[0052] For example, in the solar cell 1000 , at least one layer pair 200 is arranged on the back side of the silicon substrate to passivate the solar cell.

[0053] Alternatively, in the solar cell 1000, see Figure 2, and may also include: an aluminum oxide passivation film 400 on the front of the silicon substrate 100 and a silicon nitride coating 500 on the front and back of the battery. The nitride coating 500 on the front and back of the battery can be deposited by PECVD, the thickness of the silicon nitride coating 500 on the front can be about 80 nanometers, and the thickness of the silicon nitride coating 500 on the back can be about 70 nanometers. The aluminum oxide passivation film 400 on the front of the battery can be formed by atomic layer deposition, and its thickness can be about 4 nanometers.

[0054] Furthermore, the solar cell 1000 may also include metal electrode layers, such as silver layers, on the front and back sides of the cell, serving as electrodes on the front and back sides of the cell, respectively.

[0055] In the solar cell according to the embodiment of the present disclosure, the thickness of the oxide layer close to the silicon substrate is greater than the thickness of the oxide layer away from the silicon substrate. The thinner oxide layer is more conducive to electron tunneling, so that the electrons of at least one doped silicon film in the inner layer of the outermost doped silicon film layer can also tunnel through the oxide layer to reach the electrode, which can further reduce the contact resistance between the metal electrode layer and the outermost doped silicon film layer and improve the filling factor. Moreover, by gradually increasing the dopant concentration in the doped silicon film layer from the surface of the silicon substrate to the direction away from the silicon substrate, the doped silicon film layer close to the electrode has the largest dopant concentration, which is conducive to forming an ohmic contact between the metal electrode and the doped silicon film, reducing the metal-silicon contact resistance and improving the filling factor; and the doped silicon film close to the surface of the silicon substrate has a lower dopant concentration, so that phosphorus atoms can be prevented from penetrating and tunneling through the oxide layer during the subsequent high-temperature activation process to reduce the passivation effect. Moreover, the highly doped silicon film layer away from the surface end of the silicon wafer can further enhance the electron tunneling through the oxide layer to the electrode, which is conducive to reducing the contact resistance and improving the filling factor.

[0056] Furthermore, the embodiments of the present disclosure also provide a method for manufacturing a solar cell, such as Figure 3 As shown, the manufacturing method includes: providing a silicon substrate; and forming at least one layer pair on the surface of the silicon substrate, including: forming an oxide layer on a side of each layer pair in the at least one layer pair close to the silicon substrate; forming a doped silicon film layer on a side of the oxide layer away from the silicon substrate, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than the thickness of other oxide layers in the at least one layer pair.

[0057] The schematic diagram of the solar cell formed by this manufacturing method can be seen in Figure 1 , Figure 1 The solar cell is shown in the figure, but the solar cell does not only include three layer pairs. For example, the solar cell may include 2-50 layer pairs. Those skilled in the art may make selections according to actual needs.

[0058] For example, in an embodiment of the present disclosure, an electrode is arranged on the outside of the doped silicon film layer of the outermost layer pair, and the thickness of the oxide layer 211 on the side closest to the silicon substrate is set to be greater than the thickness of the oxide layers 221 and 231 in other layer pairs. The silicon oxide layer arranged between the doped silicon film layers serves to block the diffusion of phosphorus atoms and also to block the tunneling of electrons. By setting the oxide layer farthest from the silicon wafer to have a minimum thickness, the electrons of at least one inner doped silicon film can also tunnel through the oxide layer to reach the electrode, thereby further reducing the contact resistance between the electrode and the outermost doped silicon film layer and improving the fill factor.

[0059] Alternatively, it can be that: except for the oxide layer closest to the surface of the silicon substrate, the thickness of the other oxide layers in the at least one layer pair is the same, and those skilled in the art can select as needed. It can also be that: in the other layer pairs except the layer pair closest to the surface of the silicon substrate, in the direction indicated by arrow A, the thickness of the oxide layer in the outermost layer is less than the thickness of the other oxide layers in the other layer pairs.

[0060] For example, the oxide layer closest to the silicon substrate in the at least one layer pair may have a thickness greater than 1.8 nm and less than or equal to 2.5 nm, and the thickness of other oxide layers excluding the oxide layer closest to the silicon substrate may be less than 1.8 nm.

[0061] Alternatively, in an embodiment of the present disclosure, forming a doped silicon film layer requires performing a dopant doping operation on the silicon film. For example, the doped silicon film layer may be an n-type doped silicon film layer. Forming the n-type doped silicon film layer may be doping the silicon film layer with an n-type dopant, such as antimony, phosphorus or arsenic. For example, a high-temperature diffusion method, an ion implantation method and an in-situ doping method may be used, for example, a phosphorus high-temperature diffusion method, a phosphorus ion implantation method and a phosphorus in-situ doping method, or one or more combinations thereof may be used to dope the silicon film to form a doped silicon film layer.

[0062] For example, in the method for manufacturing a solar cell according to an embodiment of the present disclosure, the at least one layer pair includes three or more layer pairs, and forming the at least one layer pair may include:

[0063] S1, forming an oxide layer on the surface of the silicon substrate;

[0064] S2, depositing an in-situ doped silicon film layer on the oxide layer closest to the silicon substrate,

[0065] S3, forming an oxide layer on the doped silicon film layer;

[0066] S4, depositing an in-situ doped silicon film layer on the oxide layer;

[0067] Repeat the above steps S3-S4 until the second to last layer pair is formed, which is the layer pair inward of the layer pair closest to the outside, that is, Figure 1 The layer pair 220 shown in FIG. 1 is the second to last layer pair.

[0068] Alternatively, in the method for manufacturing a solar cell according to an embodiment of the present disclosure, the at least one layer pair may include two layer pairs, and forming the at least one layer pair may include:

[0069] S1, forming an oxide layer on the surface of the silicon substrate;

[0070] S2, depositing an in-situ doped silicon film layer on the oxide layer closest to the silicon substrate,

[0071] S3, forming an oxide layer on the doped silicon film layer;

[0072] S4, depositing an in-situ doped silicon film layer on the oxide layer; or forming a non-doped silicon film layer on the oxide layer; and performing ion implantation on the non-doped silicon film; and

[0073] performing high temperature annealing to activate dopants in the doped silicon film layer;

[0074] Alternatively, step S4 may be replaced by: performing high temperature diffusion of dopants on the non-doped silicon film and performing high temperature annealing to activate dopants in the doped silicon film layers of all layer pairs, thus eliminating the need for subsequent high temperature annealing.

[0075] For example, the manufacturing method of the solar cell may also include: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming an undoped silicon film layer on the oxide layer; performing ion implantation on the undoped silicon film to implant dopants; and performing high temperature annealing to activate the dopants in the doped silicon film layer.

[0076] Combination Figure 1 It is described that an oxide layer 231 is formed on the side of the in-situ doped silicon film layer 222 of the layer pair 220 away from the silicon substrate, and then a non-doped silicon film layer is formed on the oxide layer. Dopant ions are implanted into the non-doped silicon film, for example, phosphorus ions are implanted, and then high-temperature annealing is performed to activate the dopants in the silicon film layer.

[0077] Alternatively, the non-doped silicon film is implanted with dopant ions, for example, phosphorus ions, under the following process conditions: the ion beam current dose may be 4.5*10 15 atoms / cm 2 , the voltage can be 10KV, the power can be 3000W, the phosphine flow rate can be 10sccm, and the chamber pressure can be 5*10 -5 Torr.

[0078] Compared with doped silicon film, the growth rate of undoped silicon film is generally greater than 5 nanometers / minute, while the growth rate of doped silicon film is generally 1.2 nanometers / minute. Therefore, the outermost silicon film of at least one layer pair is first formed as an undoped silicon film. Compared with directly forming a doped silicon film layer, the formation time of the silicon film can be shortened and the production efficiency can be improved.

[0079] Alternatively, the method for manufacturing a solar cell may further include: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming a non-doped silicon film layer on the oxide layer; and performing high temperature diffusion of dopants on the non-doped silicon film and high temperature annealing to activate dopants in the doped silicon film layers of all layer pairs. Compared with doping the non-doped silicon film by ion implantation, the ion implantation step can be omitted.

[0080] Combination Figure 1 It is described that an oxide layer 231 is formed on the side of the in-situ doped silicon film layer 222 of the layer pair 220 away from the silicon substrate, and then a non-doped silicon film layer is formed on the oxide layer. The non-doped silicon film is subjected to high-temperature diffusion of dopants, for example, high-temperature diffusion of phosphorus, and then high-temperature annealing is performed to activate the dopants in the silicon film layer.

[0081] Alternatively, the method for manufacturing a solar cell may further include: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; depositing an in-situ doped silicon film layer on the oxide layer; and performing high temperature annealing to activate dopants in the doped silicon film layer.

[0082] Combination Figure 1 It is described that an oxide layer 231 is formed on the side of the in-situ doped silicon film layer 222 of the layer pair 220 away from the silicon substrate, and then an in-situ doped silicon film layer is deposited on the oxide layer 231. For example, the in-situ doped silicon film layer is formed by a phosphorus in-situ doping method; then, a high-temperature annealing is performed to activate the dopant in the doped silicon film layer.

[0083] For example, in the solar cell manufacturing method, forming an oxide layer on the surface of the silicon substrate may include: introducing oxygen or a mixed gas of oxygen and nitrogen into the chamber at a process temperature in the range of 400-700°C, and performing an oxidation process for 1 minute to 90 minutes.

[0084] For example, at a process temperature in the range of 400-700°C, oxygen or a mixture of oxygen and nitrogen is introduced into the chamber, and an oxidation process for 1 minute to 90 minutes may include: at a process temperature of 630°C, oxygen with a flow rate of 3000sccm and nitrogen with a flow rate of 11000sccm are introduced into the chamber for 15 minutes to obtain an oxide layer with a thickness of 1.9nm.

[0085] For example, the oxide layer may be formed on the doped silicon film layer by the same method as that for forming the oxide layer on the surface of the silicon substrate. For example, oxygen or a mixture of oxygen and nitrogen may be introduced into the chamber at a process temperature in the range of 400-700°C, and an oxidation process may be performed for 1 minute to 90 minutes. For example, at a process temperature of 630°C, oxygen with a flow rate of 3000sccm (Standard Cubic Centimeter per Minute) and nitrogen with a flow rate of 11000sccm may be introduced into the chamber for 15 minutes to obtain an oxide layer with a thickness of 1.9nm.

[0086] Alternatively, the oxide layer may be formed on the doped silicon film layer using the following process conditions: the flow rate of oxygen introduced into the chamber is 0.2-20 SLM (Standard Liter per Minute), and the oxidation time is 2 minutes to 20 minutes.

[0087] Here, the process of forming an oxide layer, that is, the silicon oxide layer, is to introduce nitrogen mainly for the nitrogen to carry oxygen and dilute the oxygen, so that a uniform oxide layer is formed on the surface of the silicon wafer, thereby improving the quality of the oxide layer and improving device performance.

[0088] For example, in the manufacturing method of a solar cell according to an embodiment of the present disclosure, the silicon substrate may be an n-type silicon wafer, and the doped silicon film layer may be an n-type doped silicon film layer. In the direction from the surface of the silicon substrate to away from the silicon substrate, the doping concentration of the n-type doped silicon film layer in the at least one layer pair gradually increases.

[0089] For example, the n-type dopant may be antimony, phosphorus or arsenic, and the phosphorus doping concentration in the n-type doped silicon film layer closest to the surface of the silicon substrate may be greater than 1*10 20 cm -3 .

[0090] For example, in the manufacturing method according to the embodiment of the present disclosure, the forming of at least one layer pair is performed in the same deposition chamber to form an in-situ silicon film layer and an oxide layer except for the penultimate layer pair, for example, Figure 1The doped silicon film layers except the doped silicon film layer 232 and the oxide layer 231 in the layer pair 230 may include: in a deposition chamber of low pressure chemical vapor deposition (LPCVD), introducing phosphine gas and silane gas with a flow ratio of 0.4:100, for example, the flow rates of the introduced phosphine gas and silane gas are 0.4sccm and 100sccm respectively, to form, for example, an in-situ deposited phosphorus-doped silicon film layer of 50nm or 100nm; stopping the introduction of the phosphine gas and the silane gas and evacuating the chamber; introducing oxygen into the LPCVD deposition chamber to form an in-situ oxide layer; wherein forming the doped silicon film layer of the penultimate layer pair includes: in the LPCVD deposition chamber, introducing phosphine gas and silane gas with a flow ratio of 0.6:100, to form, for example, an in-situ phosphorus-doped silicon film layer of 50nm or 100nm thick.

[0091] For example, in the embodiments of the present disclosure, plasma enhanced chemical vapor deposition (PECVD) may be used to form an in-situ doped silicon film layer or a non-doped silicon film layer.

[0092] Here, for the in-situ doped silicon film layer or the undoped silicon film layer formed by LPCVD, due to the use of low pressure, the chamber pressure becomes smaller and the mean free path of molecules increases, which is conducive to uniform film formation and improved film quality.

[0093] For example, in an embodiment of the present disclosure, performing high temperature annealing to activate dopants in the doped silicon film layer may include: performing high temperature annealing at 880-960° C. for 25-90 minutes; for example, performing high temperature annealing at 910° C. or 920° C. for 40 minutes.

[0094] In an embodiment of the present disclosure, the non-doped silicon film is subjected to high temperature diffusion of dopants, for example, high temperature diffusion of phosphorus, and then high temperature annealing is performed to activate the dopants in the silicon film layer, which may include: introducing a phosphorus source with a flow rate of 1000 sccm and 200 sccm of oxygen into an in-situ deposition chamber at 770-830°C for 30 minutes; and annealing at 820-880°C for 45 minutes.

[0095] In the embodiments of the present disclosure, after high-temperature annealing is performed on the doped silicon film layer, the mutual diffusion of phosphorus atoms is prevented due to the silicon oxide layer present between the doped silicon film layers, thereby achieving a concentration distribution of different phosphorus atoms in different doped silicon film layers in at least one layer pair, which can not only ensure the passivation effect on the silicon wafer surface, but also improve the FF (fill factor) of the battery device.

[0096] For example, in an embodiment of the present disclosure, providing a silicon substrate may include: providing a single crystal N-type silicon wafer; performing texturing and boron diffusion on the silicon wafer to prepare a PN junction, leveling the back surface, and retaining a front borosilicate glass layer; and cleaning the silicon wafer with a hydrofluoric acid solution.

[0097] Alternatively, in an embodiment of the present disclosure, providing a silicon substrate may include: providing a single crystal N-type silicon wafer; preparing a smooth silicon wafer surface; and cleaning the silicon wafer surface.

[0098] For example, after at least one layer pair is formed on the surface of the silicon substrate, the manufacturing method further includes: cleaning and removing the silicon film coated on the front side of the silicon wafer; depositing an aluminum oxide film on the front side of the silicon wafer; depositing a silicon nitride coating on the front and back sides of the silicon wafer; printing a metal paste on the front and back sides of the silicon wafer and sintering to form a solar cell, wherein the at least one layer pair is formed on the back side of the silicon wafer.

[0099] For example, in the step of printing the metal paste on the front and back sides of the silicon wafer and sintering, the electrode paste is printed on the surface of the silicon nitride film. After sintering, the front electrode will partially burn through the silicon nitride film and the aluminum oxide film to contact the silicon substrate, and the back electrode will partially burn through the silicon nitride film to contact the doped silicon film layer. For example, Figure 2 The back electrode 720 and the front electrode 720 in.

[0100] Illustratively, providing a single crystal N-type silicon wafer may include: providing a single crystal N-type silicon wafer with a bulk resistivity of 2.5 Ω·cm; preparing a smooth silicon wafer surface may include: selecting a potassium hydroxide alkaline solution with a mass fraction of 40% to isotropically etch the silicon wafer to obtain a polished silicon wafer surface with a reflectivity of 50%; cleaning the silicon wafer surface may include: cleaning the silicon wafer with a hydrofluoric acid solution with a mass concentration of 10%.

[0101] Exemplarily, texturing and boron diffusion of the silicon wafer to prepare a PN node, leveling the back surface, and retaining the front borosilicate glass layer may include: selecting a 5% by mass sodium hydroxide alkaline solution to anisotropically etch the silicon wafer to obtain a texturized silicon wafer surface with a reflectivity of no more than 13%; using a furnace tube boron diffusion method to prepare a PN node; using a mixed solution of hydrofluoric acid, nitric acid and sulfuric acid to etch the back surface of the silicon wafer to remove the borosilicate glass layer on the back while retaining the front borosilicate glass layer.

[0102] Illustratively, in an embodiment of the present disclosure, cleaning and removing the silicon film coated on the front side of the silicon wafer may include: using a hydrofluoric acid solution to remove the front oxide layer and retaining the back silicon oxide layer; using an alkaline solution to corrode and remove the front gradient phosphorus-doped silicon film; and then using a hydrofluoric acid solution to remove the front borosilicate glass layer.

[0103] Exemplarily, depositing an aluminum oxide film on the front side of the silicon wafer may include: depositing a 4-nanometer aluminum oxide film on the front side of the silicon wafer using an atomic layer deposition method.

[0104] For example, depositing silicon nitride coatings on the front and back sides of the silicon wafer may include: depositing a silicon nitride film in a PECVD system, depositing an 80-nanometer silicon nitride film 500 on the front side and a 70-nanometer silicon nitride film 500 on the back side, such as Figure 2 shown.

[0105] Exemplarily, printing metal paste on the front and back sides of the silicon wafer and sintering the metal paste may include: printing silver paste on the front and back sides of the silicon wafer and sintering the silver paste to form silver electrodes on the front and back sides of the silicon wafer.

[0106] Several examples of the method for manufacturing a solar cell according to the embodiment of the present disclosure are given below, and the technical effect of the technical solution of the present disclosure is described in combination with comparative examples.

[0107] Comparative Example 1

[0108] Comparative Example 1 provides a preparation method for a single-layer in-situ phosphorus-doped silicon film, and the steps are as follows:

[0109] A1. Select silicon wafer. Select single crystal N-type silicon wafer with a bulk resistivity of 2.5Ω·cm.

[0110] B1. Prepare a smooth silicon wafer surface. Use a sodium hydroxide alkaline solution with a mass fraction of 40% to isotropically etch the silicon wafer to obtain a polished silicon wafer surface with a reflectivity of 50%.

[0111] C1. Clean the silicon wafer surface. Clean the silicon wafer with a 10% mass concentration hydrofluoric acid solution.

[0112] D1. Oxidation of silicon wafer surface. The oxide layer was prepared by thermal oxidation method, the oxidation temperature was set to 630 degrees, the oxygen flow rate was 3000 sccm, the nitrogen flow rate was 11000 sccm, the oxygen flow time was 15 minutes, and the thickness of the oxide layer was about 1.9 nanometers.

[0113] E1. Double-sided deposition of in-situ phosphorus-doped silicon thin film. In the LPCVD deposition system, silane and phosphine gases are used to deposit an in-situ phosphorus-doped silicon thin film on the surface of the silicon wafer. The thickness of the doped silicon film is 130 nanometers (a single-layer phosphorus-doped silicon film, that is, the gas flow ratio remains unchanged). Three silicon films with different phosphorus contents are deposited, and the gas flow ratios of phosphine and silane are 0.4:100, 0.6:100 and 1.2:100 respectively.

[0114] F1. Perform high temperature annealing on the in-situ phosphorus-doped silicon film to activate the phosphorus atoms in the silicon film. The annealing temperature is 910 degrees and the annealing time is 40 minutes.

[0115] G1. Clean the silicon nitride film. Deposit a silicon nitride film on the surface of the doped polysilicon film. The thickness of the silicon nitride film is 79 nanometers. After high-temperature annealing, there will be a phosphorus-containing silicon oxide layer on the surface of the doped polysilicon film. This layer should be cleaned before coating. The cleaning conditions are to use a 10% HF solution for 2 minutes.

[0116] H1. Performance test. ECV (electrochemical capacitance voltage method) tests the doping concentration and the minority carrier lifetime of silicon wafers.

[0117] Figure 4 FIG. 1 shows the relationship between the depth of the doped silicon film and the concentration of phosphorus atoms obtained in Comparative Example 1. Here, the depth of the doped silicon film refers to the distance from the outermost doped silicon film surface. Figure 4 It can be seen that increasing the proportion of phosphine gas can indeed increase the content of active phosphorus atoms in the in-situ phosphorus-doped silicon film, which is beneficial to improve the contact performance of the metal-doped silicon film and improve the FF of the battery; at the same time, theoretically, the higher the active phosphorus content in the silicon film, the better its passivation effect on the silicon wafer surface. However, the sample with a phosphine flow ratio of 1.2:100 shows that the high-content phosphorus atoms in the in-situ phosphorus-doped silicon film will penetrate the tunneling oxide layer on the surface of the silicon wafer and enter the silicon wafer body after high-temperature annealing. This phosphorus atom penetration will have adverse effects on the passivation effect of the silicon wafer: first, the phosphorus atoms diffuse into the silicon wafer matrix, and the entry of phosphorus atoms destroys the integrity of the atomic lattice structure of the silicon matrix, increasing the probability of minority carrier recombination; second, the high concentration of phosphorus atoms in the matrix will further enhance the Auger recombination inside the silicon wafer.

[0118] The pseudo open circuit voltage of the sample with a gas flow ratio of phosphine to silane of 1.2:100 is 9 mV lower than that of the sample with a flow ratio of 0.4:100. Therefore, for such a single-layer in-situ phosphorus-doped silicon film, it is difficult to increase the active phosphorus content in the silicon film by simply controlling the flow rate of phosphine.

[0119] Comparative Example 2

[0120] Comparative Example 2 provides a method for preparing a multilayer silicon film (including a non-doped silicon film and an in-situ phosphorus-doped silicon film), and the steps are as follows:

[0121] A2. Select silicon wafer. Select single crystal N-type silicon wafer with a bulk resistivity of 2.5Ω·cm.

[0122] B2. Prepare a smooth silicon wafer surface. Use a potassium hydroxide alkaline solution with a mass fraction of 40% to isotropically etch the silicon wafer to obtain a polished silicon wafer surface with a reflectivity of 50%.

[0123] C2. Clean the silicon wafer surface. Clean the silicon wafer with a 10% mass concentration hydrofluoric acid solution.

[0124] D2. Oxidation of silicon wafer surface. The oxide layer was prepared by thermal oxidation method, the oxidation temperature was set to 630 degrees, the oxygen flow rate was 3000 sccm, the nitrogen flow rate was 11000 sccm, the oxygen flow time was 15 minutes, and the thickness of the oxide layer was about 1.9 nanometers.

[0125] E2. Double-sided deposition of silicon film (non-doped silicon film / in-situ phosphorus-doped silicon film / non-doped silicon film). In the LPCVD deposition system, silane is used to first deposit a 40-nanometer non-doped silicon film; then phosphine and silane gases are used to deposit an 80-nanometer in-situ phosphorus-doped silicon film on the surface of the non-doped silicon film, and the flow ratio of phosphine to silane of the doped silicon film is 0.6:100; finally, silane gas is used to deposit a 40-nanometer non-doped silicon film on the surface of the in-situ phosphorus-doped silicon film.

[0126] F2. Perform high temperature annealing on the in-situ phosphorus-doped silicon film to activate the phosphorus atoms in the silicon film. The annealing temperature is 920 degrees and the annealing time is 45 minutes.

[0127] G2, performance test. ECV test doping concentration.

[0128] Depend on Figure 5 It can be seen that after high-temperature annealing activation, phosphorus atoms diffuse from the in-situ phosphorus-doped silicon film into the non-doped silicon films on both sides, and the concentration distribution of phosphorus atoms in the three films is basically the same. In this way, the concentration gradient distribution of phosphorus atoms in the silicon film cannot be achieved by setting multiple layers of silicon films with different phosphorus doping concentrations in the silicon film, because the subsequent high-temperature activation process causes the phosphorus atoms to diffuse into all silicon films.

[0129] Example 1

[0130] Example 1 of the manufacturing method according to the embodiment of the present disclosure provides the preparation of a gradient in-situ phosphorus-doped silicon film (including a doped silicon film and an in-situ silicon oxide layer, the in-situ silicon oxide layer means that the silicon oxide layer is carried out in the same chamber as the immediately preceding process without shifting), and the steps are as follows:

[0131] A3. Select silicon wafer. Select single crystal N-type silicon wafer with a bulk resistivity of 2.5Ω·cm.

[0132] B3. Prepare a smooth silicon wafer surface. Use a potassium hydroxide alkaline solution with a mass fraction of 40% to isotropically etch the silicon wafer to obtain a polished silicon wafer surface with a reflectivity of 50%.

[0133] C3. Clean the surface of the silicon wafer. Clean the silicon wafer with a 10% mass concentration hydrofluoric acid solution.

[0134] D3. Oxidation of silicon wafer surface. The oxide layer was prepared by thermal oxidation method, the oxidation temperature was set to 630 degrees, the oxygen flow rate was 3000 sccm, the nitrogen flow rate was 11000 sccm, the oxygen flow time was 15 minutes, and the thickness of the oxide layer was about 1.9 nanometers.

[0135] E3. Double-sided deposition of in-situ phosphorus silicon film (in-situ phosphorus silicon film / oxide layer / in-situ phosphorus silicon film). In the LPCVD deposition system, phosphine and silane gases are used to deposit a 100-nanometer in-situ phosphorus-doped silicon film on the surface of the non-doped silicon film, and the flow ratio of phosphine to silane in the doped silicon film is 0.4:100; the phosphine and silane gases are turned off and vacuum is drawn, and then oxygen is introduced into the furnace to form an oxide layer on the surface of the in-situ phosphorus-doped silicon film; a 100-nanometer in-situ phosphorus-doped silicon film is deposited on the surface of the oxide layer, and the flow ratio of phosphine to silane in the doped silicon film is 0.6:100.

[0136] F3. Perform high temperature annealing on the in-situ phosphorus-doped silicon film to activate the phosphorus atoms in the silicon film. The annealing temperature is 910 degrees and the annealing time is 40 minutes.

[0137] G3, Performance test. ECV test doping concentration.

[0138] Depend on Figure 6 It can be seen that after high-temperature annealing activation, the mutual diffusion of phosphorus atoms is prevented due to the presence of an oxide layer in the film layer, achieving the concentration distribution of different phosphorus atoms in the silicon film. The effect of this design is: it can not only ensure the passivation effect of the silicon wafer surface, but also improve the FF of the battery device.

[0139] Example 2

[0140] Example 2 of the manufacturing method according to the embodiment of the present disclosure provides the preparation of a gradient in-situ phosphorus-doped silicon film (including a doped silicon film and an in-situ silicon oxide layer), and the steps are as follows:

[0141] A4. Select silicon wafer. Select single crystal N-type silicon wafer with a bulk resistivity of 2.5Ω·cm.

[0142] B4. Prepare a smooth silicon wafer surface. Use a potassium hydroxide alkaline solution with a mass fraction of 40% to isotropically etch the silicon wafer to obtain a polished silicon wafer surface with a reflectivity of 50%.

[0143] C4. Clean the surface of the silicon wafer. Clean the silicon wafer with a 10% mass concentration hydrofluoric acid solution.

[0144] D4. Oxidation of silicon wafer surface. The oxide layer was prepared by thermal oxidation method, the oxidation temperature was set to 630 degrees, the oxygen flow rate was 3000 sccm, the nitrogen flow rate was 11000 sccm, the oxygen flow time was 15 minutes, and the thickness of the oxide layer was about 1.9 nanometers.

[0145] E4. Double-sided deposition of in-situ phosphorus silicon film (in-situ phosphorus silicon film / oxide layer / non-doped silicon film). In the LPCVD deposition system, phosphine and silane gases are used to deposit a 100-nanometer in-situ phosphorus-doped silicon film on the surface of the non-doped silicon film. The flow ratio of phosphine and silane in the doped silicon film is 0.4:100. The phosphine and silane gases are turned off and vacuum is drawn. Then oxygen is introduced into the furnace to form an oxide layer on the surface of the in-situ phosphorus-doped silicon film. A 100-nanometer non-doped silicon film is deposited on the surface of the oxide layer.

[0146] F4. Perform ion implantation on the non-doped silicon film. The implantation dose is required to be greater than the concentration of phosphorus atoms in the inner doped silicon film.

[0147] G4. Perform high temperature annealing on the silicon film to activate the phosphorus atoms in the silicon film. The annealing temperature is 910 degrees and the annealing time is 40 minutes.

[0148] H4, performance test. ECV test doping concentration.

[0149] After high temperature annealing activation, due to the presence of an oxide layer in the film layer, the mutual diffusion of phosphorus atoms is prevented, and the concentration distribution of different phosphorus atoms in the silicon film is achieved. Compared with Example 1, the growth rate of the outer non-doped silicon film is faster, which can shorten the process time.

[0150] Example 3

[0151] Example 3 of the manufacturing method according to the embodiment of the present disclosure provides the preparation of a gradient in-situ phosphorus-doped silicon film (including a doped silicon film and an in-situ silicon oxide layer), and the steps are as follows:

[0152] A5. Select silicon wafer. Select single crystal N-type silicon wafer with a bulk resistivity of 2.5Ω·cm.

[0153] B5. Prepare a smooth silicon wafer surface. Use a potassium hydroxide alkaline solution with a mass fraction of 40% to isotropically etch the silicon wafer to obtain a polished silicon wafer surface with a reflectivity of 50%.

[0154] C5. Clean the surface of the silicon wafer. Clean the silicon wafer with a 10% mass concentration hydrofluoric acid solution.

[0155] D5. Oxidation of silicon wafer surface. The oxide layer was prepared by thermal oxidation method, the oxidation temperature was set to 630 degrees, the oxygen flow rate was 3000 sccm, the nitrogen flow rate was 11000 sccm, the oxygen flow time was 15 minutes, and the thickness of the oxide layer was about 1.9 nanometers.

[0156] E5. Double-sided deposition of in-situ phosphorus silicon film (in-situ phosphorus silicon film / oxide layer / non-doped silicon film). In the LPCVD deposition system, phosphine and silane gases are used to deposit a 100-nanometer in-situ phosphorus-doped silicon film on the surface of the non-doped silicon film. The flow ratio of phosphine and silane in the doped silicon film is 0.4:100. The phosphine and silane gases are turned off and vacuum is drawn. Then oxygen is introduced into the furnace to form an oxide layer on the surface of the in-situ phosphorus-doped silicon film. A 100-nanometer non-doped silicon film is deposited on the surface of the oxide layer.

[0157] F5. Perform high-temperature phosphorus diffusion and annealing on the silicon film. Phosphorus atoms are doped into the non-doped silicon layer through high-temperature diffusion, and phosphorus atoms in the inner doped silicon film are activated at the same time.

[0158] G5. Performance test. ECV test doping concentration.

[0159] After high temperature annealing and activation, due to the presence of an oxide layer in the film layer, the mutual diffusion of phosphorus atoms is prevented, and the concentration distribution of different phosphorus atoms in the silicon film is achieved. Compared with Example 2, the ion implantation step can be omitted.

[0160] Example 4

[0161] Example 4 of the manufacturing method according to the embodiment of the present disclosure provides a method for preparing a silicon-based solar cell using a gradient in-situ phosphorus-doped silicon film, the steps of which are as follows:

[0162] A6. Select silicon wafer. Select single crystal N-type silicon wafer with a bulk resistivity of 2.5Ω·cm.

[0163] B6. Texturing the silicon wafer surface: Use a sodium hydroxide alkaline solution with a mass fraction of 5% to anisotropically etch the silicon wafer to obtain a textured silicon wafer surface with a reflectivity of no more than 13%.

[0164] C6. Preparation of PN junction by boron diffusion. The PN junction was prepared by using the furnace tube boron diffusion method.

[0165] D6. Flatten the back surface. Use a mixed solution of hydrofluoric acid, nitric acid and sulfuric acid to corrode the back surface of the silicon wafer, remove the borosilicate glass layer on the back, and retain the borosilicate glass layer on the front.

[0166] E6. Oxidation of silicon wafer surface. The oxide layer was prepared by thermal oxidation method, the oxidation temperature was set to 630 degrees, the oxygen flow rate was 3000 sccm, the nitrogen flow rate was 11000 sccm, the oxygen flow time was 15 minutes, and the thickness of the oxide layer was about 1.9 nanometers.

[0167] F6. Deposition of gradient phosphorus-doped silicon film. In the LPCVD deposition system, phosphine and silane gases are used to deposit a 50-nanometer in-situ phosphorus-doped silicon film on the surface of the silicon wafer, and the flow ratio of phosphine to silane in the doped silicon film is 0.4:100; the phosphine and silane gases are turned off and vacuum is drawn, and then oxygen is introduced into the furnace to form an oxide layer on the surface of the in-situ phosphorus-doped silicon film; a 50-nanometer in-situ phosphorus-doped silicon film is deposited on the surface of the oxide layer, and the flow ratio of phosphine to silane in the doped silicon film is 0.6:100.

[0168] G6. Perform high temperature annealing on the in-situ phosphorus-doped silicon film to activate the phosphorus atoms in the silicon film. The annealing temperature is 920 degrees and the annealing time is 40 minutes.

[0169] H6. Clean and remove the silicon film on the front. Use hydrofluoric acid solution to remove the front oxide layer and keep the back oxide layer; use alkaline solution to etch and remove the front gradient phosphorus-doped silicon film; and use hydrofluoric acid solution to remove the front borosilicate glass layer.

[0170] I6. Deposit an aluminum oxide passivation film on the front surface. Use atomic layer deposition to deposit a 4-nanometer aluminum oxide film on the front surface of the silicon wafer.

[0171] J6. Double-sided silicon nitride coating. Deposit silicon nitride film in a PECVD system, deposit 80 nanometers of silicon nitride film on the front side and 70 nanometers of silicon nitride film on the back side (such as Figure 2 shown).

[0172] K6, printing and sintering. Print silver paste on both sides and then sinter.

[0173] L6, Performance test. Electrical performance test.

[0174] The battery prepared in this way can ensure the passivation effect of the silicon wafer surface and improve the FF of the battery device because the phosphorus element in the phosphorus-doped silicon film on the back surface is distributed in a gradient.

[0175] In the manufacturing method of the solar cell provided by the embodiment of the present disclosure, by making the thickness of the oxide layer close to the silicon substrate greater than the thickness of the oxide layer away from the silicon substrate, the oxide layer with a thinner thickness is more conducive to electron tunneling, so that the electrons of the inner doped silicon film within the outermost doped silicon film layer can also tunnel through the oxide layer to reach the electrode, which can further reduce the contact resistance between the metal electrode layer and the outermost doped silicon film layer, and improve the filling factor. Moreover, by gradually increasing the dopant concentration in the doped silicon film layer from the surface of the silicon substrate to the direction away from the silicon substrate, the doped silicon film layer close to the electrode has the largest dopant concentration, which is conducive to forming an ohmic contact between the metal electrode and the doped silicon film, reducing the metal-silicon contact resistance and improving the filling factor; and the doped silicon film close to the surface of the silicon substrate has a lower dopant concentration, so that phosphorus atoms can be prevented from penetrating and tunneling through the oxide layer during the subsequent high-temperature activation process to reduce the passivation effect, and the highly doped silicon film layer away from the surface end of the silicon wafer can further enhance the electron tunneling through the oxide layer to the electrode, which is conducive to reducing the contact resistance and improving the filling factor. Moreover, by providing an oxide layer between the doped silicon film layers, dopants, such as n-type dopants, such as phosphorus, can be blocked from diffusing into adjacent doped silicon film layers during high-temperature annealing, thereby forming a concentration gradient of dopants, providing a doped silicon film with a lower dopant concentration on the surface of the silicon substrate to enhance the passivation effect of the silicon substrate, and reducing the contact resistance between the electrode and the doped silicon film by increasing the dopant concentration of the doped silicon film away from the silicon substrate.

[0176] There are a few points to note:

[0177] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0178] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0179] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0180] The present disclosure also provides the following technical solutions:

[0181] Technical solution 1, a solar cell, characterized in that it comprises:

[0182] Silicon substrate;

[0183] at least one layer pair, arranged on the surface of the silicon substrate,

[0184] Each of the at least one layer pair comprises:

[0185] An oxide layer, disposed on a side of the layer pair close to the silicon substrate;

[0186] A doped silicon film layer is arranged on a side of the oxide layer away from the silicon substrate,

[0187] The thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than the thickness of other oxide layers in the at least one layer pair.

[0188] Technical Solution 2: A solar cell according to Technical Solution 1, characterized in that the thickness of the oxide layer in the at least one layer pair decreases successively in a direction from the surface of the silicon substrate to a direction away from the silicon substrate.

[0189] Technical Solution 3: A solar cell according to Technical Solution 1, characterized in that the thicknesses of the other oxide layers in the at least one layer pair except the oxide layer closest to the silicon substrate are the same.

[0190] Technical Solution 4: A solar cell according to Technical Solution 2, characterized in that, in the at least one layer pair, the thickness of the outermost oxide layer is less than the thickness of other oxide layers in the at least one layer pair.

[0191] Technical Solution 5. A solar cell according to any one of Technical Solutions 1-4, characterized in that the thickness of the oxide layer closest to the silicon substrate in at least one layer pair is greater than 1.8 nm and less than or equal to 2.5 nm, and the thickness of other oxide layers excluding the oxide layer closest to the silicon substrate is less than 1.8 nm.

[0192] Technical Solution 6. The solar cell according to Technical Solution 5 is characterized in that the silicon substrate is an n-type substrate, the doped silicon film layer is an n-type doped silicon film layer, and the doping concentration of the n-type dopant in the n-type doped silicon film layer in at least one layer pair gradually increases in a direction from the surface of the silicon substrate to away from the silicon substrate.

[0193] Technical solution 7: The solar cell according to technical solution 6 is characterized in that the doping concentration of the n-type dopant in the n-type doped silicon film layer closest to the silicon substrate in the at least one layer pair is greater than 1*10 20 cm -3 .

[0194] Technical solution 8: The solar cell according to technical solution 5 is characterized in that it also includes:

[0195] The electrode is arranged on a side of the at least one layer pair away from the silicon substrate.

[0196] Technical Solution 9: A solar cell according to Technical Solution 5, characterized in that the number of the at least one layer pair is 2-50.

[0197] Technical solution 10. A method for manufacturing a passivated solar cell according to any one of technical solutions 1-9, comprising: providing a silicon substrate; forming at least one layer pair on the surface of the silicon substrate, wherein forming the at least one layer pair comprises: forming an oxide layer on a side of each layer pair in the at least one layer pair close to the silicon substrate; forming a doped silicon film layer on a side of the oxide layer away from the silicon substrate, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than the thickness of other oxide layers in the at least one layer pair.

[0198] Technical solution 11. The method for manufacturing a solar cell according to technical solution 10, wherein the at least one layer pair includes 3 or more layer pairs, and forming the at least one layer pair includes:

[0199] S1, forming an oxide layer on the surface of the silicon substrate;

[0200] S2, depositing an in-situ doped silicon film layer on the oxide layer closest to the silicon substrate,

[0201] S3, forming an oxide layer on the doped silicon film layer;

[0202] S4, depositing an in-situ doped silicon film layer on the oxide layer;

[0203] The above steps S3-S4 are repeated until the second to last layer pair is formed.

[0204] Technical solution 12. The method for manufacturing a solar cell according to technical solution 11, further comprising:

[0205] forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair;

[0206] forming a non-doped silicon film layer on the oxide layer;

[0207] Performing ion implantation on the non-doped silicon film to implant dopants; and

[0208] A high temperature annealing is performed to activate the dopants in the doped silicon film layer.

[0209] Technical solution 13. The method for manufacturing a solar cell according to technical solution 11, further comprising:

[0210] forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair;

[0211] forming a non-doped silicon film layer on the oxide layer;

[0212] The non-doped silicon film is subjected to high temperature diffusion of dopants and high temperature annealing to activate dopants in the doped silicon film layers of all layer pairs.

[0213] Technical solution 14. The method for manufacturing a solar cell according to technical solution 11, further comprising:

[0214] forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair;

[0215] depositing an in-situ doped silicon film layer on the oxide layer;

[0216] A high temperature annealing is performed to activate the dopants in the doped silicon film layer.

[0217] Technical solution 15. The method for manufacturing a solar cell according to technical solution 11, wherein forming an oxide layer on the surface of the silicon substrate comprises:

[0218] At a process temperature ranging from 400 to 700° C., oxygen or a mixed gas of oxygen and nitrogen is introduced into the chamber to perform an oxidation process for 1 to 90 minutes.

[0219] Technical solution 16. The method for manufacturing a solar cell according to technical solution 15, wherein at a process temperature in the range of 400-700° C., oxygen or a mixed gas of oxygen and nitrogen is introduced into the chamber, and the oxidation process for 1-90 minutes comprises:

[0220] At a process temperature of 630° C., oxygen gas with a flow rate of 3000 sccm and nitrogen gas with a flow rate of 11000 sccm were introduced into the chamber for 15 minutes to obtain an oxide layer with a thickness of 1.9 nm.

[0221] Technical Solution 17. A method for manufacturing a solar cell according to any one of Technical Solutions 12-14, wherein the doped silicon film layer is an n-type doped silicon film layer, and the doping concentration of the n-type doped silicon film layer in the at least one layer pair gradually increases in a direction from the surface of the silicon substrate to away from the silicon substrate.

[0222] Technical solution 18. The method for manufacturing a solar cell according to Technical solution 17, wherein the forming of at least one layer pair is performed in the same deposition chamber.

[0223] The forming of the doped silicon film layer and the oxide layer except the penultimate layer pair includes:

[0224] In the LPCVD deposition chamber, phosphine gas and silane gas were introduced at a flow ratio of 0.4:100;

[0225] Stopping the introduction of the phosphine gas and the silane gas and evacuating the gas;

[0226] introducing oxygen into the LPCVD deposition chamber to form an in-situ oxide layer;

[0227] The doped silicon film layer forming the penultimate layer pair includes:

[0228] In the LPCVD deposition chamber, phosphine gas and silane gas with a flow ratio of 0.6:100 are introduced to form an in-situ doped silicon film layer.

[0229] Technical solution 19. The method for manufacturing a solar cell according to technical solution 12 or 14, wherein the high temperature annealing comprises:

[0230] High temperature annealing is performed at 880-960°C for 25-90 minutes.

[0231] Technical solution 20. The method for manufacturing a solar cell according to technical solution 13, wherein the step of performing high-temperature diffusion of dopants and high-temperature annealing on the non-doped silicon film comprises:

[0232] At 770-830° C., a phosphorus source with a flow rate of 1000 sccm and an oxygen gas with a flow rate of 200 sccm were introduced into the in-situ deposition chamber for 30 minutes;

[0233] Annealing was performed at 820-880°C for 45 minutes.

[0234] Technical solution 21. The method for manufacturing a solar cell according to technical solution 10, wherein providing a silicon substrate comprises:

[0235] Provide single crystal N-type silicon wafers;

[0236] The silicon wafer is textured and boron diffused to prepare a PN junction, the back surface is leveled, and the front borosilicate glass layer is retained;

[0237] Clean the silicon wafer with a hydrofluoric acid solution;

[0238] After forming at least one layer pair on the surface of the silicon substrate, the manufacturing method further comprises:

[0239] Cleaning and removing the silicon film coated on the front side of the silicon wafer;

[0240] Depositing an aluminum oxide film on the front side of the silicon wafer;

[0241] Depositing silicon nitride coatings on the front and back sides of the silicon wafer;

[0242] Printing metal paste on the front and back sides of the silicon wafer and sintering them,

[0243] The at least one layer pair is formed on the back side of the silicon wafer.

[0244] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A solar cell comprising: Silicon substrate; at least one layer pair, arranged on the surface of the silicon substrate, Each of the at least one layer pair comprises: An oxide layer, disposed on a side of the layer pair close to the silicon substrate; A doped silicon film layer is arranged on a side of the oxide layer away from the silicon substrate, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than the thickness of the other oxide layers in the at least one layer pair, The doped silicon film layer is an n-type doped silicon film layer, and the doping concentration of the n-type dopant in the n-type doped silicon film layer closest to the silicon substrate in the at least one layer pair is greater than 1*10 20 cm -3 . 2 . The solar cell according to claim 1 , wherein the thickness of the oxide layer in the at least one layer pair decreases in sequence in a direction from the surface of the silicon substrate to a direction away from the silicon substrate. 3 . The solar cell according to claim 1 , wherein the oxide layers in the at least one layer pair, except for the oxide layer closest to the silicon substrate, have the same thickness. 4 . The solar cell according to claim 2 , wherein in the at least one layer pair, the outermost oxide layer has a thickness smaller than thicknesses of other oxide layers in the at least one layer pair.

5. The solar cell according to any one of claims 1 to 4, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than 1.8 nm and less than or equal to 2.5 nm, and the thickness of other oxide layers excluding the oxide layer closest to the silicon substrate is less than 1.8 nm.

6. The solar cell according to claim 5, wherein the silicon substrate is an n-type substrate, and the doping concentration of the n-type dopant of the n-type doped silicon film layer in the at least one layer pair gradually increases in a direction from the surface of the silicon substrate to away from the silicon substrate.

7. The solar cell according to claim 5, further comprising: The electrode is arranged on a side of the at least one layer pair away from the silicon substrate. 8 . The solar cell according to claim 5 , wherein the number of the at least one layer pair is 2-50.

9. A method for manufacturing a solar cell according to any one of claims 1 to 8, comprising: providing a silicon substrate; Forming at least one layer pair on the surface of the silicon substrate, wherein forming the at least one layer pair comprises: forming an oxide layer on a side of each layer pair in the at least one layer pair close to the silicon substrate; A doped silicon film layer is formed on a side of the oxide layer away from the silicon substrate, wherein the oxide layer closest to the silicon substrate in the at least one layer pair has a thickness greater than that of other oxide layers in the at least one layer pair.

10. The method for manufacturing a solar cell according to claim 9, wherein the at least one layer pair comprises three or more layer pairs, and forming the at least one layer pair comprises: S1, forming an oxide layer on the surface of the silicon substrate; S2, depositing an in-situ doped silicon film layer on the oxide layer closest to the silicon substrate, S3, forming an oxide layer on the doped silicon film layer; S4, depositing an in-situ doped silicon film layer on the oxide layer; The above steps S3-S4 are repeated until the second to last layer pair is formed.

11. The method for manufacturing a solar cell according to claim 10, further comprising: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming a non-doped silicon film layer on the oxide layer; Performing ion implantation on the non-doped silicon film to implant dopants; as well as A high temperature annealing is performed to activate the dopants in the doped silicon film layer.

12. The method for manufacturing a solar cell according to claim 10, further comprising: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming a non-doped silicon film layer on the oxide layer; The non-doped silicon film is subjected to high temperature diffusion of dopants and high temperature annealing to activate dopants in the doped silicon film layers of all layer pairs.

13. The method for manufacturing a solar cell according to claim 10, further comprising: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; depositing an in-situ doped silicon film layer on the oxide layer; A high temperature annealing is performed to activate the dopants in the doped silicon film layer.

14. The method for manufacturing a solar cell according to claim 10, wherein forming an oxide layer on the surface of the silicon substrate comprises: At a process temperature ranging from 400 to 700° C., oxygen or a mixed gas of oxygen and nitrogen is introduced into the chamber to perform an oxidation process for 1 to 90 minutes.

15. The method for manufacturing a solar cell according to claim 14, wherein the oxidation process of introducing oxygen or a mixed gas of oxygen and nitrogen into the chamber for 1-90 minutes at a process temperature in the range of 400-700° C. comprises: At a process temperature of 630° C., oxygen gas with a flow rate of 3000 sccm and nitrogen gas with a flow rate of 11000 sccm were introduced into the chamber for 15 minutes to obtain an oxide layer with a thickness of 1.9 nm.

16. The method for manufacturing a solar cell according to any one of claims 11 to 13, wherein the doped silicon film layer is an n-type doped silicon film layer, and the doping concentration of the n-type doped silicon film layer in the at least one layer pair gradually increases in a direction from the surface of the silicon substrate to away from the silicon substrate.

17. The method for manufacturing a solar cell according to claim 16, wherein the forming of at least one layer pair is performed in the same deposition chamber, The forming of the doped silicon film layer and the oxide layer except the penultimate layer pair includes: In the LPCVD deposition chamber, phosphine gas and silane gas were introduced at a flow ratio of 0.4:100; Stopping the introduction of the phosphine gas and the silane gas and evacuating the gas; introducing oxygen into the LPCVD deposition chamber to form an in-situ oxide layer; The doped silicon film layer forming the penultimate layer pair includes: In the LPCVD deposition chamber, phosphine gas and silane gas with a flow ratio of 0.6:100 are introduced to form an in-situ doped silicon film layer.

18. The method for manufacturing a solar cell according to claim 11 or 13, wherein performing high temperature annealing comprises: High temperature annealing is performed at 880-960°C for 25-90 minutes.

19. The method for manufacturing a solar cell according to claim 12, wherein the step of performing high temperature diffusion of dopants and high temperature annealing on the non-doped silicon film comprises: At 770-830° C., a phosphorus source with a flow rate of 1000 sccm and an oxygen gas with a flow rate of 200 sccm were introduced into the in-situ deposition chamber for 30 minutes; Annealing was performed at 820-880°C for 45 minutes.

20. The method for manufacturing a solar cell according to claim 9, wherein providing a silicon substrate comprises: Provide single crystal N-type silicon wafers; The silicon wafer is textured and boron diffused to prepare a PN junction, the back surface is leveled, and the front borosilicate glass layer is retained; Clean the silicon wafer with a hydrofluoric acid solution; After forming at least one layer pair on the surface of the silicon substrate, the manufacturing method further comprises: Cleaning and removing the silicon film coated on the front side of the silicon wafer; Depositing an aluminum oxide film on the front side of the silicon wafer; Depositing silicon nitride coatings on the front and back sides of the silicon wafer; Printing metal paste on the front and back sides of the silicon wafer and sintering them, The at least one layer pair is formed on the back side of the silicon wafer.

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