Semiconductor memory device and manufacturing method thereof

Abstract

A semiconductor memory device includes: a first impurity region and a second impurity region spaced apart in a substrate; a device isolation pattern located between the first impurity region and the second impurity region; a bit line contact located on the first impurity region; a storage node contact located on the second impurity region; and a dielectric pattern located between the bit line contact and the storage node contact. An upper portion of a sidewall of the device isolation pattern has a first tilt angle, and a lower portion of the sidewall of the device isolation pattern has a second tilt angle different from the first tilt angle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0024309 filed on February 27, 2020, in the Korean Intellectual Property Office, the subject matter of which is incorporated herein by reference. Technical Field

[0003] The present inventive concept generally relates to a semiconductor memory device and a method of manufacturing the same. Background Art

[0004] Semiconductor devices have become an important factor in the electronics industry due to their small size, advanced functions and low manufacturing costs. The integration level of semiconductor devices is getting higher and higher to meet the demand for enhanced functionality and smaller physical size. As a result, the line width of various patterns in contemporary semiconductor devices has been reduced. However, new and expensive exposure techniques are required to achieve the desired fineness of certain patterns, and this trend makes the manufacture of densely integrated semiconductor devices more difficult. Recently, various research has been conducted on new integration technologies. Summary of the Invention

[0005] Some embodiments of the present inventive concept provide a semiconductor memory device having improved reliability. Some embodiments of the present inventive concept provide a method of manufacturing a semiconductor memory device that provides improved reliability by reducing process defects.

[0006] According to an embodiment of the present invention, a semiconductor memory device may include: a first impurity region and a second impurity region spaced apart from each other in a substrate; a device isolation pattern located between the first impurity region and the second impurity region; a bit line contact located on the first impurity region; a storage node contact located on the second impurity region; and a dielectric pattern located between the bit line contact and the storage node contact, wherein an upper portion of a sidewall of the device isolation pattern has a first inclination angle, and a lower portion of the sidewall of the device isolation pattern has a second inclination angle different from the first inclination angle.

[0007] According to an embodiment of the present invention, a semiconductor memory device may include: a substrate including a first impurity region spaced apart from a second impurity region; a device isolation pattern disposed between the first impurity region and the second impurity region; a bit line contact located on the first impurity region; a storage node contact located on the second impurity region; and a dielectric pattern disposed between the bit line contact and the storage node contact, wherein the dielectric pattern includes lower portions each having a constant width and upper portions each having a variable width.

[0008] According to an embodiment of the present invention, a semiconductor memory device may include: a first impurity region located in a substrate; a pair of second impurity regions located in the substrate, spaced apart from each other, and located on both sides of the first impurity region; a device isolation pattern located between the first impurity region and the second impurity region, respectively; a bit line contact located on the first impurity region; a storage node contact located on the second impurity region, respectively; and a dielectric pattern located between the bit line contact and the storage node contact, respectively, wherein sidewalls and an upper surface of the device isolation pattern define a recess having a first inner sidewall and an opposite second inner sidewall, the first inner sidewall including an upper portion, a lower portion, and a first inflection point disposed above the upper surface of the first impurity region, the inclination angle of the first inner sidewall changes at the first inflection point, the second inner sidewall including an upper portion, a lower portion, and a second inflection point disposed above the upper surface of the first impurity region, the inclination angle of the second inner sidewall changes at the second inflection point.

[0009] According to an embodiment of the present invention, a method for manufacturing a semiconductor memory device may include: forming a device isolation pattern in a substrate to define an active portion; forming a first impurity region in the active portion; forming a second impurity region in the active portion spaced apart from the first impurity region; forming a buffer layer on the substrate; etching the buffer layer to expose an upper surface of the first impurity region; selectively etching the exposed first impurity region; isotropically etching the buffer layer and the device isolation pattern; forming a bit line contact on the first impurity region; and forming a storage node contact on the second impurity region.

[0010] According to an embodiment of the present invention, a method for manufacturing a semiconductor memory device may include: isotropically etching a buffer layer to form a buffer pattern, the buffer pattern including a recess exposing a first impurity region in a substrate, wherein the first recess is disposed away from the first impurity region; selectively etching the first impurity region exposed by the buffer pattern so that the depth of the recess increases; isotropically etching the exposed sidewalls of the buffer pattern and the sidewalls of the device isolation pattern to expand the recess; conformally forming a linear oxide layer above the recess to cover the first impurity region and the second impurity region; etching the oxide layer to form an oxide spacer exposing an upper surface of the first impurity region and a lower surface of the recess, so that a lower portion of a first inner sidewall of the recess and a lower portion of a second inner sidewall of the recess are spaced apart from the first impurity region by the same interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a plan view illustrating a semiconductor memory device according to an embodiment of the inventive concept; Figure 1B It is along Figure 1A A cross-sectional view taken along line AA' and line BB'; Figure 1C It further shows Figure 1B an enlarged cross-sectional view of portion "aa"; Figure 1D It further shows Figure 1CAn enlarged cross-sectional view of portion "bb" of FIG.

[0012] Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10A They are floor plans; Figure 2B 、 Figure 2C 、 Figure 3B 、 Figure 3C 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 10C 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 14 are cross-sectional views collectively illustrating one example of a method of manufacturing a semiconductor memory device according to an embodiment of the inventive concept.

[0013] Figure 15A It is along Figure 1A A cross-sectional view taken along line AA'.

[0014] Figure 15B It shows Figure 15A An enlarged cross-sectional view of portion "cc" of FIG.

[0015] Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 16E 、 Figure 16F 、 Figure 16G and Figure 16H are related cross-sectional views illustrating, by way of example, a method of manufacturing a semiconductor memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0016] Embodiments of the inventive concept will now be described in some additional detail with reference to the accompanying drawings.

[0017] Throughout the written description and the accompanying drawings, like reference numerals and designations are used to denote like or similar elements and / or features. Throughout the written description, certain geometric terms may be used to emphasize the relative relationships between elements, components, and / or features of certain embodiments of the present invention. Those skilled in the art will recognize that such geometric terms are relative in nature and are arbitrary in describing relationships and / or relate to aspects of the embodiments shown. For example, geometric terms may include: end / center; inside / outside; height / width; vertical / horizontal; up / down; higher / lower; closer / further; thicker / thinner; near / far; above / below; below / above; up / down; center / side; around; covering / bottom layer, etc.

[0018] Figure 1A is a plan view (or top view) illustrating a semiconductor memory device according to an embodiment of the inventive concept. Figure 1B It is along Figure 1A A cross-sectional view taken along line AA' and line BB'; Figure 1C It further shows Figure 1B an enlarged cross-sectional view of portion "aa"; Figure 1D It further shows Figure 1C An enlarged cross-sectional view of portion "bb" of FIG.

[0019] Reference Figure 1A 、 Figure 1B 、 Figure 1C and Figure 1D , an active portion ACT can be defined by forming a device isolation pattern 302 in a substrate 301. Each of the active portions ACT may have an isolated shape. When viewed in a plane, each of the active portions ACT may have a strip shape elongated along the first direction X1. When viewed in a plane, the active portion ACT may correspond to a portion of the substrate 301 surrounded by the device isolation pattern 302. The substrate 301 may include one or more semiconductor materials, such as silicon, a germanium substrate, silicon germanium, etc. The device isolation pattern 302 may include one or more oxides (e.g., silicon oxide). The active portions ACT may be arranged parallel to each other in the first direction X1, and the end portion of one active portion ACT may be adjacent to the center portion of an adjacent active portion ACT.

[0020] The word lines WL may extend above the active portion ACT and may be disposed in trenches formed in the device isolation pattern 302 and the active portion ACT. The word lines WL may extend parallel to each other in a second direction X2 that intersects the first direction X1. The word lines WL may be formed of one or more conductive materials. A gate dielectric layer 107 may be disposed between each of the word lines WL and the inner surface of each trench. Although not shown, the lower surface of the trench may be relatively deep in the device isolation pattern 302 and relatively shallow in the active portion ACT. The gate dielectric layer 107 may include silicon oxide. Each of the word lines WL may have a curved lower surface.

[0021] The first impurity region 312a may be disposed in the active portion ACT between a corresponding pair of word lines WL, and a pair of second impurity regions 312b may be disposed in opposite edges of each of the active portions ACT. The first impurity region 312a and the second impurity region 312b may be doped with, for example, N-type impurities. The first impurity region 312a may correspond to a common drain region, and the second impurity region 312b may correspond to a source region.

[0022] When along Figure 1B or Figure 1C When viewed in a cross section taken along line AA', the first recess R1 may be defined by the sidewalls and upper surface of the device isolation pattern 302. The first recess R1 may have a first inner sidewall SN1 and an opposing second inner sidewall SN2. The first inner sidewall SN1 and the second inner sidewall SN2 may correspond to the sidewalls of the device isolation pattern 302. Therefore, the first inner sidewall SN1 and the second inner sidewall SN2 may be referred to as "sidewalls" of the device isolation pattern 302.

[0023] The first inner sidewall SN1 of the first recess R1 may have an upper portion SN1U and a lower portion SN1L. The second inner sidewall SN2 of the first recess R1 may have an upper portion SN2U and a lower portion SN2L.

[0024] The lower portion SN1L of the first inner sidewall SN1 and the lower portion SN2L of the second inner sidewall SN2 may be symmetrically disposed with respect to the first impurity region 312a.

[0025] In some embodiments, the upper portion SN1U of the first inner sidewall SN1 and the upper portion SN2U of the second inner sidewall SN2 may be symmetrically disposed with respect to the first impurity region 312 a .

[0026] like Figure 1DAs shown in , the upper portion SN1U of the first inner sidewall SN1 may have a first inclination angle θ1 relative to the upper surface 301U of the substrate 301, and the lower portion SN1L of the first inner sidewall SN1 may have a second inclination angle θ2 relative to the upper surface 301U of the substrate 301. The first inclination angle θ1 and the second inclination angle θ2 may be different from each other. The second inclination angle θ2 may be closer to 90 degrees than the first inclination angle θ1. That is, the second inclination angle θ2 may be less sharp than the first inclination angle θ1. The first inner sidewall SN1 may have an inflection point N1, and the inclination angle changes at the inflection point N1. The inflection point N1 may be located above the upper surface U1 of the first impurity region 312a.

[0027] The inclination angle relationship between the upper portion SN2U and the lower portion SN2L of the second inner sidewall SN2 may also be the same as the inclination angle relationship between the upper portion SN1U and the lower portion SN1L of the first inner sidewall SN1. In some embodiments, at least one of the first inner sidewall SN1 and the second inner sidewall SN2 may have a step difference.

[0028] The first recess R1 may have a lower surface including a lowermost portion L1 disposed below the upper surface U1 of the first impurity region 312 a .

[0029] Each word line WL and the corresponding adjacent first and second impurity regions 312a and 312b can form a transistor. When the word lines WL are disposed in the trenches, each word line WL defines a corresponding channel region thereunder, with the length of the channel region extending within a limited planar area. Therefore, short channel effects, etc., can be reduced or minimized.

[0030] The word lines WL may have corresponding upper surfaces located below the active portions ACT. A word line cover pattern 31 may be provided on each of the word lines WL. The word line cover pattern 31 may have a linear shape extending longitudinally along the word lines WL and may cover the corresponding upper surfaces of the word lines WL. Each of the trenches may include an unoccupied inner space not occupied by the word lines WL, and the word line cover pattern 31 may fill the unoccupied inner space of the trench. The word line cover pattern 31 may be formed, for example, of a silicon nitride layer.

[0031] When along Figure 1B When viewed in a cross section taken along line BB' of FIG, an upper surface of the gate dielectric layer 107 between the first impurity region 312a and the word line capping pattern 31 may be below an upper surface U1 of the first impurity region 312a. An upper surface of the gate dielectric layer 107 between the word line capping pattern 31 and the device isolation pattern 302 may be coplanar with the word line capping pattern 31.

[0032] The buffer pattern 305 may be provided on the substrate 301. The buffer pattern 305 may include the same material as that of the device isolation pattern 302. For example, the buffer pattern 305 may be a single layer including silicon oxide.

[0033] When viewed in a plane, the buffer pattern 305 may be formed in an island shape spaced apart from each other. The buffer pattern 305 may be formed to cover end portions of two adjacent active portions ACT.

[0034] The substrate 301 , the device isolation pattern 302 , and the buffer pattern 305 may be partially recessed to form a first recess R1 .

[0035] The bit line BL may be disposed on the buffer pattern 305. The bit line BL may extend over the word line capping pattern 31 and the word line WL. Figure 1A As shown in FIG, the bit lines BL may extend in parallel in a third direction X3 intersecting the first direction X1 and the second direction X2. Each of the bit lines BL may include a bit line polysilicon pattern 330, a bit line ohmic pattern 331, and a bit line metal-containing pattern 332 stacked sequentially. The bit line polysilicon pattern 330 may include polysilicon doped with impurities and / or polysilicon undoped with impurities. The bit line ohmic pattern 331 may include a metal silicide layer. The bit line metal-containing pattern 332 may include at least one selected from a metal (e.g., tungsten, titanium, and tantalum) and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and tungsten nitride). A bit line capping pattern 337 may be provided on each of the bit lines BL. The bit line capping pattern 337 may be formed of one or more dielectric materials. For example, the bit line capping pattern 337 may include one or more nitrides (e.g., silicon nitride) and / or oxynitrides (e.g., silicon oxynitride).

[0036] The bit line contact DC may be provided in the first recess R1. The bit line contact DC may include polysilicon doped with impurities and / or polysilicon not doped with impurities. Figure 1B When viewed in a cross section taken along line BB' of FIG. 1 , the bit line contact DC may have a sidewall in contact with a side surface of the buffer pattern 305. Figure 1A When viewed in the plane shown in , the bit line contact DC may have a convex side surface that contacts the buffer pattern 305. The bit line contact DC may electrically connect the first impurity region 312a and the bit line BL to each other.

[0037] When along Figure 1B When viewed in the line BB' cross section of FIG. , the bit line contact DC may be at least partially interposed between the first impurity region 312a and the word line capping pattern 31. The bit line contact DC may contact upper and side surfaces of the first impurity region 312a.

[0038] The first recess R1 may include an unoccupied space not occupied by the bitline contact DC, and a lower buried dielectric pattern 341 may fill the unoccupied space of the first recess R1. The first recess R1 may include a pair of lower buried dielectric patterns 341 disposed therein, located on opposite sides of the bitline contact DC. The lower buried dielectric patterns 341 may include, for example, a silicon nitride layer. Each of the lower buried dielectric patterns 341 may have a lower width and an upper width greater than the lower width. One of the lower buried dielectric patterns 341 may have a sidewall whose shape is transferred from the first inner sidewall SN1 of the first recess R1. The other of the lower buried dielectric patterns 341 may have a sidewall whose shape is transferred from the second inner sidewall SN2 of the first recess R1. The sidewalls of each of the lower buried dielectric patterns 341 may have an inflection point 341P at which the inclination angle changes, and the inflection point 341P may be located above the upper surface U1 of the first impurity region 312a.

[0039] Storage node contacts BC may be provided between each pair of adjacent bit lines BL. The storage node contacts BC may be spaced apart from each other. The storage node contacts BC may include polysilicon doped with impurities and / or polysilicon undoped with impurities. Between the bit lines BL, a dielectric pattern (not shown) may be provided between the storage node contacts BC.

[0040] A bit line spacer SP may be interposed between the bit line BL and the storage node contact BC. The bit line spacer SP may include a first subspacer 321 and a second subspacer 325 spaced apart from each other via a gap region GP. Here, the gap region GP may be referred to as an "air gap." The first subspacer 321 may cover the sidewalls of the bit line BL and the sidewalls of the bit line capping pattern 337. The second subspacer 325 may be adjacent to the storage node contact BC. The first subspacer 321 and the second subspacer 325 may include the same material. For example, the first subspacer 321 and the second subspacer 325 may include a silicon nitride layer.

[0041] The lower surface of the second sub-spacer 325 may be located below the lower surface of the first sub-spacer 321. The upper end of the second sub-spacer 325 may be located below the upper end of the first sub-spacer 321. This configuration may increase the formation margin of the landing pad LP to be described below. As a result, disconnection between the landing pad LP and the storage node contact BC may be prevented. The first sub-spacer 321 may extend to cover the sidewalls of the bit line contact DC and also cover the sidewalls and lower surface of the first recess R1. For example, the first sub-spacer 321 may be inserted between the bit line contact DC and the lower buried dielectric pattern 341, between the word line covering pattern 31 and the lower buried dielectric pattern 341, between the substrate 301 and the lower buried dielectric pattern 341, and between the device isolation pattern 302 and the lower buried dielectric pattern 341.

[0042] The storage node ohmic layer 309 may be disposed on the storage node contact BC. The storage node ohmic layer 309 may include a metal silicide. The storage node ohmic layer 309, the first subspacer 321, the second subspacer 325, and the bit line cover pattern 337 may be conformally covered by the anti-diffusion pattern 311a. The anti-diffusion pattern 311a may include a metal nitride (e.g., a titanium nitride layer, a tantalum nitride layer, etc.). The landing pad LP may be disposed on the anti-diffusion pattern 311a. The landing pad LP may include one or more metals (e.g., tungsten). The landing pad LP may have an upper portion that covers the upper surface of the bit line cover pattern 337 and has a width greater than the width of the storage node contact BC. The center of the landing pad LP may be shifted relative to the center of the storage node contact BC in the second direction X2. A portion of the bit line BL may vertically overlap with the landing pad LP. The upper sidewall of the bit line cover pattern 337 may overlap with the landing pad LP and may be covered by the third subspacer 327. The second recess R2 may be formed on other upper sidewalls of the bit line capping pattern 337 .

[0043] The landing pad LP may include a first landing pad LP1 and an adjacent second landing pad LP2. The first landing pad LP1 may have a first upper sidewall sw1 adjacent to the second landing pad LP2. The second landing pad LP2 may have a second upper sidewall sw2 adjacent to the first upper sidewall sw1. The first covering pattern 358a may connect the first upper sidewall sw1 and the second upper sidewall sw2 to each other while covering the first upper sidewall sw1 and the second upper sidewall sw2. The first covering pattern 358a may have a uniform thickness regardless of position. The first covering pattern 358a may have a third recess R3 located between the first landing pad LP1 and the second landing pad LP2. The third recess R3 may be filled with a second covering pattern 360a. The first covering pattern 358a and the second covering pattern 360a may independently include a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a porous layer. The porosity of the first covering pattern 358a may be greater than the porosity of the second covering pattern 360a. Upper surfaces of the first and second capping patterns 358 a and 360 a may be coplanar with an upper surface of the landing pad LP.

[0044] The gap region GP between the first subspacer 321 and the second subspacer 325 may extend into the space between the landing pads LP. The gap region GP may expose the lower surface of the first capping pattern 358a. The gap region GP may extend toward the anti-diffusion pattern 311a. For example, the anti-diffusion pattern 311a may have sidewalls that are recessed between the second landing pad LP2 and the bit line capping pattern 337. The gap region GP may partially expose the upper surface of the bit line capping pattern 337 and the lower surface of the second landing pad LP2.

[0045] The data storage pattern DS may be disposed on the landing pad LP. The data storage pattern DS may include a capacitor lower electrode, a phase change material pattern, a variable resistance material pattern, and / or a magnetic tunnel junction pattern.

[0046] Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10A Each of them is a planar graph, Figure 2B 、 Figure 2C 、 Figure 3B 、 Figure 3C 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 10C 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 14 Each of them is a cross-sectional view collectively illustrating, in one example, a method of manufacturing a semiconductor memory device according to an embodiment of the inventive concept.

[0047] Reference Figure 2A and Figure 2B , a device isolation pattern 302 may be formed in the substrate 301 to define an active portion ACT. A device isolation trench may be formed in the substrate 301, and the device isolation pattern 302 may fill the device isolation trench. The active portion ACT and the device isolation pattern 302 may be patterned to form a trench. Here, the etching conditions of the substrate 301 and the device isolation pattern 302 may be appropriately controlled so that the device isolation pattern 302 can be etched more easily than the substrate 301. As a result, the trench may have a curved lower surface.

[0048] Word lines WL may be formed in the corresponding trenches. A pair of word lines WL may extend over each of the active portions ACT. The pair of word lines WL may divide each of the active portions ACT into a first source / drain region SDR1 and a pair of second source / drain regions SDR2. The first source / drain region SDR1 may be defined between the pair of word lines WL, and the pair of second source / drain regions SDR2 may be defined on opposite edges of each of the active portions ACT.

[0049] Before forming the word lines WL, a gate dielectric layer 107 may be formed on the inner surface of each of the trenches. The gate dielectric layer 107 may be formed by one or more of thermal oxidation, chemical vapor deposition, and atomic layer deposition. A gate conductive layer may be formed to fill the trenches, and then the gate conductive layer may be etched back to form the word lines WL. The word lines WL may be recessed so that their upper surfaces are lower than the upper surface of the active portion ACT. A dielectric layer, such as a silicon nitride layer, may be formed on the substrate 301 to fill the trenches, and then the dielectric layer may be etched to form word line capping patterns 31 on the corresponding word lines WL.

[0050] Reference Figure 2A and Figure 2C The word line capping pattern 31 and the device isolation pattern 302 may be used as masks to dope the active portion ACT with impurities to form a first impurity region 312a and a second impurity region 312b. Figure 2B A first impurity region 312 a and a second impurity region 312 b are formed in the first source / drain region SDR1 and the second source / drain region SDR2 shown in FIG.

[0051] Then, a buffer layer 305 a (eg, silicon oxide) may be formed on the entire surface of the substrate 301 .

[0052] Reference Figure 3A and Figure 3B A separate etching mask (not shown) may be used to isotropically etch the buffer layer 305 a to form a buffer pattern 305 including a first recess R1 exposing the first impurity region 312 a .

[0053] The etching mask (not shown) may have an opening slightly larger than the size required to expose the first impurity region 312a. For example, the opening size of the etching mask (not shown) may be the sum of the width of the active portion ACT in the second direction X2 and an additional width margin provided for misalignment.

[0054] The buffer layer 305a, the device isolation pattern 302, the substrate 301, and the first impurity region 312a may be etched to form a first recess R1, and simultaneously form the buffer pattern 305. Since the horizontal width of the first recess R1 is sufficient to expose the first impurity region 312a, the first recess R1 may be formed such that its sidewalls are closer to the first impurity region 312a than to the second impurity region 312b on other active portions ACT.

[0055] Reference Figure 3A and Figure 3C, the first impurity region 312a exposed by the buffer pattern 305 can be selectively etched. Because the first impurity region 312a includes silicon, and the device isolation pattern 302, the buffer pattern 305, and the gate dielectric layer 107 include silicon oxide, the first impurity region 312a can be selectively etched due to the etching selectivity of the first impurity region 312a relative to the device isolation pattern 302, the buffer pattern 305, and the gate dielectric layer 107. The first impurity region 312a can be etched so that the first recess R1 can be expanded to include a first portion R1a and a second portion R1b, wherein the first portion R1a has a first inclination angle on the sidewall of the buffer pattern 305 and the second portion R1b has a second inclination angle on the sidewall of the device isolation pattern 302. For example, the first recess R1 can have an increased depth. The first inclination angle and the second inclination angle can be different. For example, the second inclination angle can be less sharp than the first inclination angle (i.e., closer to 90 degrees). Thereafter, the etching mask (not shown) is removed. In some embodiments, the etch mask may be removed before selectively etching the first impurity region 312 a .

[0056] Reference Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B , an isotropic etching process may be performed to expand the first recess R1. A wet etching process may be used as the isotropic etching process. In this case, the first recess R1 may have an increased width in both the vertical and horizontal directions. The isotropic etching process may etch the exposed sidewalls of each of the buffer pattern 305 and the device isolation pattern 302. Since the buffer pattern 305 and the device isolation pattern 302 may include the same material, the exposed portions of both the buffer pattern 305 and the device isolation pattern 302 may be similarly etched during the isotropic etching process. Therefore, as Figure 4B As shown in , the profile of the exposed sidewall of the buffer pattern 305 may be transferred, and similarly, the profile of the exposed sidewall of the device isolation pattern 302 may be transferred. According to some embodiments, a straight line may be provided between the exposed sidewall of the buffer pattern 305 and the exposed sidewall of the device isolation pattern 302.

[0057] The first recess R1 may have a first inner sidewall SN1 and an opposite second inner sidewall SN2. Here, the first inner sidewall SN1 and the second inner sidewall SN2 may be formed to have respective lower portions spaced apart from the first impurity region 312a by the same interval "W".

[0058] When the first recess R1 is expanded, the first impurity region 312a may be connected to the first impurity region 312a on opposite sides thereof. Figure 3CThe second portion R1b of the first recess R1 shown in FIG is etched by the same amount as the adjacent device isolation pattern 302, and therefore, the first recess R1 may be formed to have the same interval "W" at portions spaced apart from each other via the first impurity region 312a. Figure 5B As shown in , first recess R1 may include a first inner sidewall SN1 and an opposing second inner sidewall SN2, and lower portions of the first inner sidewall SN1 and the second inner sidewall SN2 may be formed symmetrically with respect to the first impurity region 312 a. In addition, first recess R1 may be formed such that the lowest portion of its lower surface is lower than the upper surface of the first impurity region 312 a.

[0059] The first impurity region 312a may have a fin shape including an exposed upper surface and partially exposed sidewalls. Figure 5B As shown in the cross-sectional view of , the gate dielectric layer 107 may be partially etched to expose the sidewalls of the first impurity region 312a.

[0060] Reference Figure 6A and Figure 6B A first polysilicon layer 329 may be formed on the entire surface of the substrate 301 to fill the first recess R1. The first polysilicon layer 329 may undergo a planarization etching process to expose the buffer pattern 305. The first polysilicon layer 329 and the buffer pattern 305 may constitute a substantially flat surface.

[0061] Reference Figure 7A and Figure 7B , a second polysilicon layer 330a may be formed on the buffer pattern 305 and the first polysilicon layer 329. A bit line ohmic layer 331a, a bit line metal-containing layer 332a, and a bit line capping layer 337a may be sequentially formed on the second polysilicon layer 330a. The bit line ohmic layer 331a may be formed of a metal silicide (e.g., cobalt silicide). The bit line ohmic layer 331a may be formed by the following steps: depositing a metal layer on the second polysilicon layer 330a; performing an annealing process in which the metal layer and the polysilicon of the second polysilicon layer 330a react with each other to form a metal silicide; and subsequently removing an unreacted portion of the metal layer.

[0062] A first mask pattern 339 may be formed on the bit line capping layer 337a to define a planar shape of a bit line BL to be described below. The first mask pattern 339 may extend in the third direction X3.

[0063] Reference Figure 8A and Figure 8BThe first mask pattern 339 can be used as an etching mask during an etching process in which the bit line capping layer 337a, the bit line metal-containing layer 332a, the bit line ohmic layer 331a, the second polysilicon layer 330a, and the first polysilicon layer 329 are sequentially etched to form a bit line capping pattern 337, a bit line contact DC, and a bit line BL including a bit line polysilicon pattern 330, a bit line ohmic pattern 331, and a bit line metal-containing pattern 332. The etching process can partially expose the upper surface of the buffer pattern 305, the inner sidewalls of the first recess R1, and a portion of the lower surface of the first recess R1. The first mask pattern 339 can then be removed.

[0064] When forming the bit line contact DC, the first polysilicon layer 329 exposed by the first mask pattern 339 can be removed to expose the inner sidewalls of the first recess R1. In the event of misalignment when forming the first mask pattern 339, a reduced horizontal distance can be set between the sidewalls of the first mask pattern 339 and the inner sidewalls of the first recess R1. In this case, when forming the bit line contact DC, it may be difficult to introduce an etchant between the first polysilicon layer 329 and the inner sidewalls of the first recess R1, and therefore, the first polysilicon layer 329 may not be sufficiently etched to form the bit line contact DC having a bridge shape covering the inner sidewalls of the first recess R1. This may increase the distance between the bit line contact DC and the storage node contact (e.g., see Figure 1B possibility of a short circuit between components "BC").

[0065] According to an embodiment of the inventive concept, since the etching process for achieving the shallow etching depth required to expose the first impurity region 312a (eg, Figure 3B As described above), due to the selective etching process in which the first impurity region 312a is selectively etched (as described with respect to Figure 3C ), and due to the isotropic etching process performed around the first impurity region 312a (as described with respect to Figure 4B As described above, the space around the first impurity region 312a into which the etchant is introduced can be expanded. For example, because a space large enough to facilitate the introduction of the etchant is formed around the first impurity region 312a, and because the first recess R1 has enough space to receive the etchant, the lower portion of the first polysilicon layer 329 can be sufficiently etched when forming the bit line contact DC. Therefore, certain process defects such as short circuits can be significantly reduced.

[0066] Reference Figure 9A and Figure 9BA first sub-spacer layer may be conformally formed over the entire surface of the substrate 301. The first sub-spacer layer may conformally cover the lower surface and inner sidewalls of the third recess R3. The first sub-spacer layer may be, for example, a silicon nitride layer. A dielectric layer, such as a silicon nitride layer, may be formed over the entire surface of the substrate 301 to fill the first recess R1. Then, an anisotropic etching process may be performed in which the dielectric layer is anisotropically etched to leave the lower buried dielectric pattern 341 in the first recess R1.

[0067] When the anisotropic etching process is performed, the first sub-spacer layer may also be etched to form a first sub-spacer 321. In addition, the anisotropic etching process may expose the upper surface of the buffer pattern 305. A sacrificial spacer layer may be conformally formed on the entire surface of the substrate 301, and then an anisotropic etching process may be performed to form a sacrificial spacer 323 covering the sidewalls of the first sub-spacer 321. The sacrificial spacer 323 may be formed of a material having an etching selectivity relative to the first sub-spacer 321. A second sub-spacer 325 may be formed to cover the sidewalls of the sacrificial spacer 323. The second sub-spacer 325 may be formed of, for example, silicon nitride. After the second sub-spacer 325 is formed, the upper surface of the buffer pattern 305 may be exposed.

[0068] Reference Figure 10A and Figure 10B A polysilicon layer may be formed on the entire surface of the substrate 301 to fill the space between the bit lines BL, and then the polysilicon layer may be etched to form the initial storage node contact 350, exposing the upper sidewalls of each of the first sub-spacer 321, the sacrificial spacer 323, and the second sub-spacer 325. The upper portions of the sacrificial spacer 323 and the second sub-spacer 325 may be removed so that the height (or horizontal height) of the upper ends of the sacrificial spacer 323 and the second sub-spacer 325 is similar to the height (or horizontal height) of the upper surface of the initial storage node contact 350. Thus, the upper sidewalls of the first sub-spacer 321 may be exposed. This process may provide a large process margin for forming the landing pad LP to be discussed below. When removing the upper portions of the sacrificial spacer 323 and the second sub-spacer 325, the upper portion of the first sub-spacer 321 may also be partially removed, so that the width of the first sub-spacer 321 may be reduced.

[0069] Reference Figure 10A and Figure 10CA third sub-spacer layer may be conformally formed over the entire surface of the substrate 301. The third sub-spacer layer may then be anisotropically etched to form a third sub-spacer 327 covering the exposed upper sidewalls of the first sub-spacer 321. The third sub-spacer 327 may have a lower portion covering the exposed upper end of the sacrificial spacer 323. The initial storage node contact 350 may be etched to expose the upper sidewalls of the second sub-spacer 325, while simultaneously forming the storage node contact BC. The third sub-spacer 327 may complement the damaged upper portion of the first sub-spacer 321 and cover the sacrificial spacer 323, thereby protecting the bit line BL from the etchant used to etch the storage node contact BC and / or the cleaning solution used in a subsequent cleaning process. As a result, damage to the bit line BL may be prevented. A cleaning process may be performed to clean the upper surface of the storage node contact BC. The upper surface of the storage node contact BC may undergo a metal silicide process to form the storage node ohmic layer 309. An anti-diffusion layer 311 may be conformally formed over the entire surface of the substrate 301. A landing pad layer 352 may be formed over the entire surface of the substrate 301 and may fill the spaces between the bit line capping patterns 337. The landing pad layer 352 may include, for example, tungsten. A second mask pattern 340 may be formed over the landing pad layer 352. The second mask pattern 340 may define the position of a landing pad LP, which will be discussed below. The second mask pattern 340 may be formed to vertically overlap the storage node contact BC. The second mask pattern 340 may be formed to have island shapes spaced apart from each other.

[0070] Reference Figure 1A and Figure 11 In the embodiment shown in , an anisotropic etching process may be performed such that the second mask pattern 340 may be used as an etching mask to partially remove the landing pad layer 352 to form the landing pad LP, while simultaneously forming an opening 354 that exposes the anti-diffusion layer 311. Thereafter, an isotropic etching process may be performed such that the anti-diffusion layer 311 exposed in the opening 354 may be removed to form anti-diffusion patterns 311 a separated from each other, while simultaneously exposing a portion of the upper surface of the third sub-spacer 327 and the bit line capping pattern 337. Depending on the extent of the isotropic etching process, the anti-diffusion pattern 311 a may be excessively etched to partially expose the lower surface of the landing pad LP.

[0071] Reference Figure 1A and Figure 12 An anisotropic etching process may be performed to remove portions of the third sub-spacer 327 and the bit line capping pattern 337 exposed to the opening 354 to expose the sacrificial spacer 323. In this case, a second recess R2 may be formed on the bit line capping pattern 337.

[0072] Reference Figure 1A and Figure 13 , the sacrificial spacer 323 may be removed to form an air gap AG between the first sub-spacer 321 and the second sub-spacer 325. Thereafter, a thermal decomposition layer 356 may be formed to fill the opening 354 and the second recess R2. The thermal decomposition layer 356 may also be formed on the landing pad LP. The thermal decomposition layer 356 may close the upper portion of the air gap AG.

[0073] Reference Figure 1A and Figure 14 A first annealing process may be performed to thermally decompose and remove the upper portion of the thermal decomposition layer 356. Partially removing the thermal decomposition layer 356 may expose the upper surface and upper sidewalls of the landing pad LP and form thermal decomposition patterns 356a spaced apart from each other. A first capping layer 358 may be conformally formed on the thermal decomposition patterns 356a and the landing pad LP.

[0074] Reference Figure 1A and Figure 1B A second annealing process may be performed to remove both the thermally decomposed pattern 356a and the sacrificial spacer 323 to form a gap region GP. A second capping layer (not shown) may be formed on the first capping layer 358. An etch-back or chemical mechanical polishing (CMP) process may then be performed to remove the first capping layer 358 and the second capping layer (not shown) on the landing pad LP to expose the landing pad LP. A data storage pattern DS may be formed contacting the landing pad LP.

[0075] Figure 15A It is along Figure 1A A cross-sectional view of a semiconductor memory device according to an embodiment of the inventive concept is taken along line AA′ and illustrates the cross-sectional view. Figure 15A A case is shown in which neither the first recess R1 nor the bit line contact DC is accurately aligned with the first impurity region 312 a . Figure 15B It further shows Figure 15A An enlarged cross-sectional view of portion "cc" of FIG.

[0076] Reference Figure 15A and Figure 15B , the first recess R1 is displaced away from the first impurity region 312a in the second direction X2. Conversely, the bit line contact DC may be displaced in the second direction X2 toward the first impurity region 312a. The first recess R1 may have a first inner sidewall SN1 and an opposing second inner sidewall SN2. The first inner sidewall SN1 may be relatively closer to the bit line contact DC, while the second inner sidewall SN2 may be relatively farther away from the bit line contact DC. The first inner sidewall SN1 may correspond to a relatively less etched sidewall of the device isolation pattern 302, while the second inner sidewall SN2 may correspond to a relatively more etched sidewall of the device isolation pattern 302.

[0077] Lower portions of the first and second inner sidewalls SN1 and SN2 may be symmetrically disposed with respect to the first impurity region 312a. In addition, lower portions of the first and second inner sidewalls SN1 and SN2 may be spaced apart from the first impurity region 312a by the same interval W.

[0078] The bit line contact DC may divide the first recess R1 into a first compartment Ra having a relatively large space and a second compartment Rb having a relatively small space. A lowermost portion L2 of a lower surface of the first compartment Ra of the first recess R1 may be located at a level lower than that of the upper surface U1 of the first impurity region 312 a. Similarly, a lowermost portion L3 of a lower surface of the second compartment Rb of the first recess R1 may be located at a level lower than that of the upper surface U1 of the first impurity region 312 a.

[0079] The first compartment Ra of the first recess R1 may be filled with a first lower buried dielectric pattern 341 a having an upper width smaller than an upper width of the second lower buried dielectric pattern 341 b filling the second compartment Rb of the first recess R1 .

[0080] Each of the first lower buried dielectric pattern 341a and the second lower buried dielectric pattern 341b may include a lower portion having a constant width and an upper portion having a variable width. The lower portion of the first lower buried dielectric pattern 341a and the lower portion of the second lower buried dielectric pattern 341b may be symmetrically disposed with respect to the first impurity region 312a. The upper surface of the first sub-spacer 321 covering the first inner sidewall SN1 of the first recess R1 may be in contact with the lower surface of the second sub-spacer 325. Other configurations may be similar to those previously described with reference to Figure 1A 、 Figure 1B and Figure 1C The configuration described is similar.

[0081] Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 16E 、 Figure 16F 、 Figure 16G and Figure 16H 2 is a related cross-sectional view illustrating one example of a method of manufacturing a semiconductor memory device according to an embodiment of the inventive concept.

[0082] Reference Figure 2C and Figure 16A A separate etching mask (not shown) may be used to anisotropically etch the buffer layer 305a to form a buffer pattern 305 including a first recess R1 exposing the first impurity region 312a. The first recess R1 may be displaced away from the first impurity region 312a in the second direction X2.

[0083] This displacement may correspond to a misalignment between the first impurity region 312 a and an opening of an etching mask (not shown). The size of the opening of the etching mask may be the sum of the width of the first impurity region 312 a and an additional width provided for the misalignment. Even if misalignment occurs, the upper surface of the first impurity region 312 a can be exposed.

[0084] Reference Figure 16B , it is possible to selectively etch the first impurity region 312a exposed by the buffer pattern 305. Therefore, the first recess R1 may have an increased depth, which may result in expansion of the first recess R1.

[0085] Thereafter, the etching mask (not shown) is removed. In some embodiments, the etching mask may be removed before selectively etching the first impurity region 312a.

[0086] Reference Figure 16C , an isotropic etching process may be performed to expand the first recess R1. The isotropic etching process may etch exposed sidewalls of each of the buffer pattern 305 and the device isolation pattern 302. Since the buffer pattern 305 and the device isolation pattern 302 include the same material, the buffer pattern 305 and the device isolation pattern 302 may be similarly etched.

[0087] The expansion of first recess R1 may allow the lower portions of first inner sidewall SN1 and second inner sidewall SN2 to be symmetrically disposed relative to first impurity region 312a and spaced the same distance W from first impurity region 312a. First impurity region 312a may have a fin-like shape including an exposed upper surface and partially exposed sidewalls. The sidewalls and / or upper surface of the adjacent second impurity region 312b may be exposed during the isotropic etching process. In some embodiments, the sidewalls and / or upper surface of the adjacent second impurity region 312b may not be exposed.

[0088] Reference Figure 16D , a linear oxide layer 306a may be formed. The oxide layer 306a may include the same material as the buffer pattern 305 and the device isolation pattern 302. The oxide layer 306a may be, for example, a silicon oxide layer. The oxide layer 306a may be formed on the exposed top surface and sidewalls of the buffer pattern 305, the exposed top surface and sidewalls of the device isolation pattern 302, the exposed top surface and sidewalls of the first impurity region 312a, and the exposed top surface and / or sidewalls of the second impurity region 312b.

[0089] Reference Figure 16EThe oxide layer 306a may be etched to form oxide spacers 306. For example, an anisotropic etching process may be used to etch the oxide layer 306a. The anisotropic etching process may again expose the upper surface of the first impurity region 312a and the lower surface of the first recess R1. The oxide spacers 306 may again cover the sidewalls of the first recess R1 and the exposed portion of the second impurity region 312b.

[0090] Since the oxide spacer 306 protects Figure 16C The second impurity region 312b is exposed due to the isotropic etching process, so the second impurity region 312b may not be allowed to contact the etchant during the subsequent etching process. For example, additional etching of the second impurity region 312b may be prevented during the formation of the bit line BL as described below. When the oxide spacer 306 is not formed, the exposed second impurity region 312b may be etched to cause the second impurity region 312b to contact the storage node (e.g., see Figure 15A According to an embodiment of the inventive concept, such contact failure can be prevented.

[0091] The formation of oxide spacers 306 can also be applied to Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B The second impurity region 312b is exposed by the isotropic etching process discussed in the above.

[0092] Reference Figure 16F , a bit line BL, a bit line contact DC and a bit line capping pattern 337 may be formed on the substrate 301. Figure 7B The bit line BL, the bit line contact DC, and the bit line capping pattern 337 are formed by an etching process using the first mask pattern 339 as an etching mask. As an example of performing the etching process in a state where the first mask pattern 339 is not aligned with the first impurity region 312a, the bit line contact DC can be formed closer to the first inner sidewall SN1 than to the second inner sidewall SN2. A first width d1 between the bit line contact DC and the first inner sidewall SN1 of the first recess R1 can be smaller than a second width d2 between the bit line contact DC and the second inner sidewall SN2 of the first recess R1.

[0093] According to an embodiment of the inventive concept, since the isotropic etching process of the device isolation pattern 302 is performed around the first impurity region 312 a , a space into which an etchant can be introduced may be expanded.

[0094] The lower portion of first inner sidewall SN1 and the lower portion of second inner sidewall SN2 may be spaced apart from first impurity region 312a by the same interval W. Therefore, even if first recess R1 is formed so as to be displaced in one direction away from first impurity region 312a, and even if bit line BL is formed so as to be displaced in another direction away from first impurity region 312a, a space for introducing an etchant can be uniformly and sufficiently provided in first recess R1. As a result, even if misalignment occurs, insufficient etching of the conductive layer (e.g., the polysilicon layer) can be prevented when forming bit line contact DC, resulting in reduced process defects.

[0095] Reference Figure 16G , a first sub-spacer 321 and a lower buried dielectric pattern 341 may be formed. Thereafter, a second sub-spacer 325 and a sacrificial spacer 323 may be formed.

[0096] Reference Figure 16H , an initial storage node contact 350 may be formed. In some embodiments, initial storage node contacts 350 having different sizes may be formed across the bit line contact DC.

[0097] Afterwards, in order to complete Figure 15A The fabrication of the semiconductor memory device shown in FIG. 1 may be performed by performing the aforementioned Figure 10C 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 14 Describe the process.

[0098] For a semiconductor memory device and a manufacturing method thereof according to an embodiment of the present invention, the recess can be arranged so that the inner sidewall facing it is spaced apart from the impurity region on which the bit line contact is formed by the same interval. According to an embodiment of the present invention, even in the case of misalignment when forming the recess and / or the bit line, it is possible to ensure that space is obtained around the impurity region for introducing an etchant during and / or after forming the bit line contact. Therefore, it is possible to prevent the conductive layer (e.g., polysilicon) from being insufficiently etched when forming the bit line contact, and therefore, when the storage node contact is subsequently formed, defects such as a short circuit between the bit line contact and the storage node contact can be prevented. Therefore, the semiconductor memory device according to the present invention can have improved reliability.

[0099] The foregoing description is directed to specific embodiments of the present invention. However, the present invention is not limited to the foregoing embodiments. Those skilled in the art will recognize that various modifications may be made to the foregoing without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device comprising: a first impurity region and a second impurity region spaced apart in the substrate; a device isolation pattern located between the first impurity region and the second impurity region; a bit line contact located on the first impurity region; a storage node contact located on the second impurity region; a dielectric pattern located between the bit line contact and the storage node contact; as well as a spacer located between the dielectric pattern and the device isolation pattern, The upper portion of the sidewall of the device isolation pattern has a first inclination angle, and the lower portion of the sidewall of the device isolation pattern has a second inclination angle different from the first inclination angle. Each dielectric pattern is disposed between the first impurity region and the second impurity region, and has a lower surface located below an upper surface of the first impurity region, and The lowermost surface of the spacer is below the upper surface of the first impurity region.

2. The semiconductor memory device according to claim 1, wherein The second inclination angle is less acute than the first inclination angle.

3. The semiconductor memory device according to claim 1, wherein The sidewall of the device isolation pattern includes an inflection point, and the inclination angle of the sidewall changes from the first inclination angle to the second inclination angle at the inflection point, and The inflection point is disposed above an upper surface of the first impurity region.

4. The semiconductor memory device according to claim 1, wherein A sidewall of the dielectric pattern has a shape transferred from a sidewall of the device isolation pattern. 5 . The semiconductor memory device according to claim 1 , further comprising a single-layer buffer pattern on the substrate.

6. The semiconductor memory device according to claim 5, wherein The buffer pattern and the device isolation pattern include the same material.

7. The semiconductor memory device according to claim 6, wherein The buffer pattern includes a silicon oxide layer, and the buffer pattern does not include a silicon nitride layer.

8. The semiconductor memory device according to claim 1, wherein The second impurity region is provided as a pair of second impurity regions, and the pair of second impurity regions is provided across the first impurity region, and Widths of the dielectric patterns are the same at a level of an upper surface of the first impurity region.

9. The semiconductor memory device according to claim 8, wherein The width of the dielectric pattern changes at a level above an upper surface of the first impurity region and makes one of the dielectric patterns different from another.

10. The semiconductor memory device according to claim 1, wherein The device isolation pattern includes a sidewall having a step difference.

11. A semiconductor memory device comprising: a substrate comprising a first impurity region, the first impurity region being spaced apart from a second impurity region; a device isolation pattern disposed between the first impurity region and the second impurity region; a bit line contact located on the first impurity region; a storage node contact located on the second impurity region; a dielectric pattern disposed between the bit line contact and the storage node contact; and a spacer located between the dielectric pattern and the device isolation pattern, wherein the dielectric pattern includes lower portions each having a constant width and upper portions each having a variable width, Each dielectric pattern is disposed between the first impurity region and the second impurity region, and has a lower surface located below an upper surface of the first impurity region, and The lowermost surface of the spacer is below the upper surface of the first impurity region.

12. The semiconductor memory device according to claim 11, wherein A lower surface of the dielectric pattern is located below an upper surface of the first impurity region.

13. The semiconductor memory device according to claim 11, further comprising: A buffer pattern is provided on the substrate, wherein the buffer pattern includes a material different from a material of the dielectric pattern.

14. The semiconductor memory device according to claim 11, wherein The second impurity region is provided as a pair of second impurity regions, and the pair of second impurity regions is provided across the first impurity region, and A lower portion of the dielectric pattern between the first impurity region and the second impurity region is symmetrically disposed with respect to the first impurity region.

15. A semiconductor memory device comprising: a first impurity region located in the substrate; a pair of second impurity regions located in the substrate, spaced apart from each other, and separated from the first impurity region; device isolation patterns, each located between the first impurity region and the second impurity region; a bit line contact located on the first impurity region; storage node contacts, each located on the second impurity region; dielectric patterns, each located between the bit line contact and the storage node contact; as well as a spacer located between the dielectric pattern and the device isolation pattern, wherein the sidewall and the upper surface of the device isolation pattern define a recess having a first inner sidewall and an opposite second inner sidewall, The first inner sidewall includes an upper portion, a lower portion, and a first inflection point, the first inflection point is disposed above the upper surface of the first impurity region, and the inclination angle of the first inner sidewall changes at the first inflection point. The second inner sidewall includes an upper portion, a lower portion, and a second inflection point, the second inflection point is disposed above the upper surface of the first impurity region, and the inclination angle of the second inner sidewall changes at the second inflection point. Each dielectric pattern is disposed between the first impurity region and the second impurity region, and has a lower surface located below an upper surface of the first impurity region, and A lowermost surface of the spacer is below an upper surface of the first impurity region.

16. The semiconductor memory device according to claim 15, wherein A lower portion of the first inner sidewall and a lower portion of the second inner sidewall are spaced apart from the first impurity region by the same interval.

17. The semiconductor memory device according to claim 16, wherein The lower portion of the first inner sidewall and the lower portion of the second inner sidewall have the same inclination angle.

18. The semiconductor memory device according to claim 16, wherein At the same level, a distance between the bit line contact and the first inner sidewall is different from a distance between the bit line contact and the second inner sidewall.

19. The semiconductor memory device according to claim 16, wherein At least one of the first inner sidewall and the second inner sidewall has a step difference.

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