Light emitting device, optical device and measuring device

Abstract

The present invention provides a light-emitting device, an optical device and a measuring device, wherein the light-emitting device includes: a wiring substrate having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer; a laser unit having a cathode electrode and an anode electrode, which is mounted on the wiring substrate and driven by a low side; and a capacitor element, which is mounted on the wiring substrate and supplies a driving current to the laser unit, wherein a cathode wiring connected to the cathode electrode and an anode wiring connected to the anode electrode are arranged in the first wiring layer, a reference potential wiring connected to a reference potential is arranged in the second wiring layer, the reference potential wiring of the second wiring layer is arranged in an area overlapping with the anode wiring, and the anode wiring is arranged in a manner surrounding the capacitor element.

Description

Technical Field

[0001] The present disclosure relates to a light emitting device, an optical device and a measuring device. Background Art

[0002] Japanese Patent Publication No. 2008-252129 describes a light-emitting device comprising: a light-transmitting ceramic substrate; a light-emitting element mounted on a surface of the ceramic substrate; a wiring pattern for supplying power to the light-emitting element; and a metallization layer including a light-reflecting metal, the metallization layer being formed inside the ceramic substrate in a manner that reflects light emitted from the light-emitting element. Summary of the invention

[0003] When measuring the three-dimensional shape of an object using the so-called time of flight (ToF) method utilizing the flight time of light, it is required to reduce the inductance of a drive circuit that supplies a drive current to a laser unit and shorten the rise time of light emitted from the laser unit.

[0004] The purpose of the present disclosure is to, in a light-emitting device including a wiring substrate having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer, and a laser unit mounted on the wiring substrate and driven from the low side, make it possible to utilize more capacitance components between wirings as a driving current for driving the laser unit, compared with a case where the anode wiring of the first wiring layer is arranged in a manner not to surround a capacitor element.

[0005] According to a first scheme of the present disclosure, a light-emitting device is provided, comprising: a wiring substrate having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer; a laser unit having a cathode electrode and an anode electrode, which is mounted on the wiring substrate and driven from the low side; and a capacitor element, which is mounted on the wiring substrate and supplies a driving current to the laser unit, wherein a cathode wiring connected to the cathode electrode and an anode wiring connected to the anode electrode are arranged in the first wiring layer, a reference potential wiring connected to a reference potential is arranged in the second wiring layer, the reference potential wiring of the second wiring layer is arranged in an area overlapping with the anode wiring, and the anode wiring is arranged in a manner surrounding the capacitor element.

[0006] According to a second aspect of the present disclosure, the light emitting device includes a plurality of the capacitor elements, and the anode wiring is provided so as to surround the plurality of the capacitor elements.

[0007] According to a third aspect of the present disclosure, the anode wiring has an area that is 50% or more of the area of ​​the wiring substrate.

[0008] According to a fourth aspect of the present disclosure, the anode wiring has an area that is 75% or more of the area of ​​the wiring substrate.

[0009] According to a fifth aspect of the present disclosure, the thickness of the insulating layer is 100 μm or less.

[0010] According to a sixth aspect of the present disclosure, the laser unit is a surface emitting laser element array in which a plurality of surface emitting laser elements are formed on a common semiconductor substrate.

[0011] According to a seventh aspect of the present disclosure, the light emitting device includes an optical member that changes at least one of a direction and a spread angle of light emitted from the laser unit.

[0012] According to the eighth scheme of the present disclosure, there is provided an optical device, comprising: the light-emitting device; and a light-receiving unit, receiving reflected light emitted from a laser unit included in the light-emitting device and reflected by an object to be measured, wherein the light-receiving unit outputs a signal, and the signal is equivalent to the time from the light being emitted from the laser unit to being received by the light-receiving unit.

[0013] According to the ninth scheme of the present disclosure, a measuring device is provided, comprising: the optical device; and a three-dimensional shape determination unit, which determines the three-dimensional shape of the object to be measured based on reflected light from the object to be measured emitted from a laser unit included in the optical device and received by a light receiving unit included in the optical device, and the measuring device measures the three-dimensional shape of the object to be measured.

[0014] (Effect)

[0015] According to the first aspect, compared with the case where the anode wiring of the first wiring layer is provided so as not to surround the capacitor, a larger amount of capacitance components between the wirings can be utilized as a driving current for driving the laser unit.

[0016] According to the second aspect, compared with the case where the reference potential wiring of the second wiring layer is provided so as to surround only one capacitor, it is easy to increase the overlapping area of ​​the reference potential wiring and the anode wiring.

[0017] According to the third aspect, it is easy to increase the overlapping area of ​​the reference potential wiring and the anode wiring of the second wiring layer, compared with a case where the area is less than 50%.

[0018] According to the fourth aspect, it is easy to increase the overlapping area of ​​the reference potential wiring and the anode wiring of the second wiring layer, compared with a case where the area is less than 75%.

[0019] According to the fifth aspect, compared with the case where the thickness of the insulating layer exceeds 100 μm, the capacitance between the wirings increases.

[0020] According to the sixth aspect, compared with the case of using an end emission laser, it is easier to arrange the laser elements two-dimensionally.

[0021] According to the seventh aspect, compared with a case where no optical member is provided, it is possible to irradiate light emitted from the light source while changing at least one of the direction and the spread angle.

[0022] According to the eighth aspect, an optical device capable of acquiring a signal corresponding to a three-dimensional shape can be provided.

[0023] According to the ninth aspect, a measuring device capable of measuring a three-dimensional shape can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a block diagram illustrating an example of the structure of a measuring device that measures a three-dimensional shape.

[0025] Figure 2 is the plan view of the light source.

[0026] Figure 3 The figure is a diagram for explaining the cross-sectional structure of a vertical cavity surface emitting laser (VCSEL) which is one of the light sources.

[0027] Figure 4 (a) and Figure 4 (b) is a diagram illustrating an example of a light diffusion member. Figure 4 (a) is a plane diagram, Figure 4 (b) is Figure 4 (a) is a cross-sectional view taken along line IVB-IVB.

[0028] Figure 5 This is a diagram showing an example of an equivalent circuit when a light source is driven by low-side driving.

[0029] Figure 6 (a) and Figure 6 (b) is a diagram illustrating a capacitor. Figure 6 (a) is the equivalent circuit of a capacitor, Figure 6 (b) is the frequency characteristic of the impedance of the capacitor.

[0030] Figure 7 (a) and Figure 7 (b) is a diagram illustrating an example of a low ESL capacitor and a non-low ESL capacitor. Figure 7 (a) is a low ESL capacitor, Figure 7 (b) is a non-low ESL capacitor.

[0031] Figure 8It is a diagram for explaining a driving current pulse supplied to a light source.

[0032] Fig. 9 (a) to Fig. 9 (c) is a diagram illustrating a light-emitting device to which this embodiment is applicable. Fig. 9 (a) is a plane diagram, Fig. 9 (b) is Fig. 9 (a) is a cross-sectional view of the IXB-IXB line. Fig. 9 (c) is Fig. 9 (a) Cross-sectional view at line IXC-IXC.

[0033] Fig.10 (a) to Fig.10 (c) is a diagram for explaining a light-emitting device to which this embodiment is not applied, and is shown for comparison. Fig.10 (a) is a plane diagram, Fig.10 (b) is Fig.10 (a) is a cross-sectional view of the XB-XB line. Fig.10 (c) is Fig.10 (a) Cross-sectional view at line XC-XC. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Among the measuring devices for measuring the three-dimensional shape of the object to be measured, there are devices that measure the three-dimensional shape based on the so-called time of flight (ToF) method using the flight time of light. In the ToF method, the time from the time when light is emitted from the light source of the self-measuring device to the time when the irradiated light is reflected by the object to be measured and received by the three-dimensional sensor of the measuring device (hereinafter referred to as 3D sensor) is measured to determine the three-dimensional shape of the object to be measured. In addition, the object whose three-dimensional shape is measured is called the object to be measured. Moreover, measuring the three-dimensional shape is sometimes referred to as three-dimensional measurement, 3D measurement, or 3D perception.

[0036] This type of measuring device is installed in a mobile information processing device and is used for facial authentication of a user who wants to access. In the past, a method of authenticating a user using a password, fingerprint, iris, etc. was used in a mobile information processing device. In recent years, a more secure authentication method is being sought. Therefore, a measuring device for measuring a three-dimensional shape is installed in a mobile information processing device. That is, a three-dimensional image of the face of the user to be accessed is obtained to identify whether access is allowed, and only when the user is authenticated as a user who is allowed to access, the user is allowed to use the device (mobile information processing device).

[0037] Moreover, this type of measuring device is also suitable for situations such as augmented reality (AR) where the three-dimensional shape of the object being measured is continuously measured.

[0038] In a measuring device for measuring a three-dimensional shape by means of the ToF method, the rise time of the light emitted from the laser unit (hereinafter referred to as the light source) is required to be short. The shorter the rise time of the light emitted from the light source, the higher the accuracy of the measurement. The smaller the inductance of the driving circuit that supplies the driving current for driving the light source, the shorter the rise time of the light emitted from the light source. That is, the greater the inductance of the driving circuit that supplies the driving current, the more difficult it is for the high-frequency (hereinafter referred to as high frequency) driving current to flow, and the longer the rise time of the light emitted from the light source will become.

[0039] The configuration, function, method, and the like described in the present embodiment described below can be applied to measurement of the three-dimensional shape of an object to be measured other than face authentication or augmented reality.

[0040] (Measurement device 1)

[0041] Figure 1 This is a block diagram for explaining an example of the configuration of a measuring device 1 that measures a three-dimensional shape.

[0042] The measuring device 1 includes an optical device 3 and a control unit 8. The control unit 8 controls the optical device 3. In addition, the control unit 8 includes a three-dimensional shape determination unit 81 for determining the three-dimensional shape of the object to be measured. The control unit 8 is configured as a computer including a central processing unit (CPU), a read only memory (ROM), a random access memory (RAM), etc. In addition, the ROM includes a non-volatile rewritable memory, such as a flash memory. In addition, by expanding the program or constant stored in the ROM in the RAM and executing the program by the CPU, the three-dimensional shape determination unit 81 is formed to determine the three-dimensional shape of the object to be measured.

[0043] The following is an explanation in order.

[0044] The optical device 3 includes a light emitting device 4 and a 3D sensor 5 .

[0045] The light emitting device 4 includes a wiring substrate 10, a light source 20, a light diffusion member 30, a driving unit 50, a holding unit 60, and a capacitor 70A and a capacitor 70B. The capacitor 70A is a capacitor that reduces the equivalent series inductance ESL (hereinafter referred to as a low ESL capacitor), and the capacitor 70B is a capacitor with an equivalent series inductance ESL greater than that of the capacitor 70A (hereinafter referred to as a non-low ESL capacitor). As described later, the wiring substrate 10 includes the capacitor (hereinafter referred to as Figure 5 , Fig. 9 (a) to Fig. 9 (c) of the capacitor 70C), the capacitor (described later Figure 5 , Fig. 9 (a) to Fig. 9 The capacitor 70C) described in (c) includes a parasitic capacitance generated by the structure of the wiring substrate 10. In addition, Figure 1 In the figure, capacitor 70A and capacitor 70B are recorded as one each, but either or both may be multiple. In addition, the light emitting device 4 may also include other circuit parts such as capacitors or resistor elements in order to operate the driving unit 50. In the case where capacitor 70A, capacitor 70B, and capacitor 70C are not distinguished, they are referred to as capacitor 70 or capacitor. Capacitors (low ESL capacitors and non-low ESL capacitors) will be described later. A capacitor is sometimes referred to as a capacitor element or a capacitor. In addition, capacitor 70A and capacitor 70B are examples of capacitor elements. A capacitor including parasitic capacitance (capacitor 70C) is an example of a capacitance component.

[0046] The light source 20, the driving unit 50, the capacitor 70A, the capacitor 70B, and the holding unit 60 are provided on the surface of the wiring substrate 10. Figure 1 In the embodiment, the 3D sensor 5 is not provided on the surface of the wiring substrate 10, but may be provided on the surface of the wiring substrate 10. Furthermore, the light diffusion member 30 is provided on the holding portion 60. Here, the so-called surface refers to Figure 1 More specifically, in the wiring substrate 10, the place where the light source 20 and the like are provided is referred to as the surface, the surface side, or the surface side.

[0047] The light source 20 is constituted as a surface emitting laser element array in which a plurality of surface emitting laser elements are arranged two-dimensionally (see the following description). Figure 2). As an example, the surface emitting laser element is a vertical cavity surface emitting laser VCSEL (Vertical Cavity Surface Emitting Laser). In the following, the surface emitting laser element is assumed to be a vertical cavity surface emitting laser VCSEL for explanation. And, the vertical cavity surface emitting laser VCSEL is referred to as VCSEL. The light source 20 is provided on the surface of the wiring substrate 10, so that the light source 20 emits light toward the outside in a direction perpendicular to the surface of the wiring substrate 10. The light source 20 is an example of a laser unit.

[0048] The light diffusion component 30 allows the light emitted by the light source 20 to enter, and diffuses the incident light and emits it. The light diffusion component 30 is provided in a manner to cover the light source 20. That is, the light diffusion component 30 is provided at a predetermined distance from the light source 20 provided on the wiring substrate 10 by the holding portion 60 provided on the surface of the wiring substrate 10. Therefore, the light emitted by the light source 20 is diffused by the light diffusion component 30 and irradiated to the object to be measured. That is, compared with the case where the light diffusion component 30 is not included, the light emitted by the light source 20 is diffused by the light diffusion component 30 and irradiated to a wider range.

[0049] In the case of three-dimensional measurement by ToF method, the light source 20 is required to emit pulse light (hereinafter referred to as the emitted light pulse) of, for example, 100 MHz or more and a rise time of less than 1 ns through the driving unit 50. That is, the light source 20 is driven by supplying a driving current pulse to the driving circuit driving the light source 20 so as to emit the emitted light pulse. In addition, in the case of facial recognition as an example, the distance of the irradiated light is about 10 cm to about 1 m. And, the range of the irradiated light is about 1 m square. In addition, the distance of the irradiated light is referred to as the measurement distance, and the range of the irradiated light is referred to as the irradiation range or the measurement range. And, the surface hypothetically set in the irradiation range or the measurement range is referred to as the irradiation surface. In addition, in cases other than facial recognition, the measurement distance up to the object to be measured and the irradiation range for the object to be measured may also be other than those described above.

[0050] The 3D sensor 5 includes a plurality of light receiving cells and outputs a signal corresponding to the time from when the light source 20 emits light to when the light is received by the 3D sensor 5. For example, each light receiving cell of the 3D sensor 5 receives a pulsed reflected light (hereinafter referred to as a light receiving pulse) from the object to be measured relative to the outgoing light pulse from the light source 20, and stores a charge corresponding to the time until the light is received in each light receiving cell. The 3D sensor 5 is configured as an element of a complementary metal oxide semiconductor (CMOS) structure in which each light receiving cell includes two gates and a charge storage unit corresponding to them. In addition, by alternately applying pulses to the two gates, the generated photoelectrons are transmitted to either of the two charge storage units at a high speed. In the two charge storage units, charges corresponding to the phase difference between the outgoing light pulse and the light receiving pulse are stored. Furthermore, the 3D sensor 5 outputs a digital value corresponding to the phase difference between the outgoing light pulse and the received light pulse as a signal corresponding to each light receiving cell via an analog digital (AD) converter. That is, the 3D sensor 5 outputs a signal corresponding to the time from the time when the light is emitted from the light source 20 to the time when it is received by the 3D sensor 5. That is, a signal corresponding to the three-dimensional shape of the object to be measured is obtained from the 3D sensor 5. Therefore, the rise time of the outgoing light pulse is required to be short, and the rise time of the received light pulse is required to be short. That is, the rise time of the driving current pulse supplied to drive the light source 20 is required to be short. In addition, the AD converter can be included in the 3D sensor 5 or provided outside the 3D sensor 5. The 3D sensor 5 is an example of a light receiving unit.

[0051] Furthermore, when the 3D sensor 5 is, for example, an element of the aforementioned CMOS structure, the three-dimensional shape determination unit 81 of the control unit 8 acquires the digital value obtained for each light-receiving cell, and calculates the distance to the object to be measured for each light-receiving cell. Furthermore, the three-dimensional shape of the object to be measured is determined based on the calculated distance, and the determination result is output.

[0052] As described above, the control unit 8 is configured as a computer, and the three-dimensional shape determination unit 81 is implemented by a program. However, they may also include an integrated circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Furthermore, they may also include software such as a program and an integrated circuit such as an ASIC.

[0053] As described above, the measuring device 1 diffuses the light emitted by the light source 20 and irradiates the object to be measured, and receives the reflected light from the object to be measured by the 3D sensor 5. In this way, the measuring device 1 measures the three-dimensional shape of the object to be measured.

[0054] Figure 1 In FIG. 1 , the optical device 3 and the control unit 8 are shown separately, but they may be integrally configured.

[0055] First, the light source 20 , the light diffusion member 30 , the drive unit 50 , and the capacitors (capacitor 70A, capacitor 70B, capacitor 70C) constituting the light emitting device 4 will be described.

[0056] (Structure of Light Source 20)

[0057] Figure 2 2 is a plan view of the light source 20. The light source 20 is composed of a plurality of VCSELs arranged in a two-dimensional array. Figure 2 In the figure, the VCSELs are arranged at the lattice points of a square lattice, but they may also be arranged in other arrangement methods. As described above, the light source 20 is configured as a surface emitting laser element array in which the VCSELs are set as surface emitting laser elements. Here, the right direction of the paper is set as the x direction, and the upper direction of the paper is set as the y direction. The direction orthogonal to the x direction and the y direction around the counterclockwise direction is set as the z direction. In addition, the so-called surface of the light source 20 refers to the surface side of the paper, that is, the surface on the +z direction side, and the so-called back side of the light source 20 refers to the back side of the paper, that is, the surface on the -z direction side. The so-called plan view of the light source 20 is a view of the light source 20 observed from the surface side. To further explain, in the light source 20, the place where the epitaxial layer that functions as a light-emitting layer (active region 206 described later) is formed is referred to as the surface, surface side or surface side of the light source 20.

[0058] VCSEL is a surface emitting laser element as described below, that is, a semiconductor substrate 200 (see below) is stacked on the semiconductor substrate 200. Figure 3 ) is provided between the lower multilayer film reflector and the upper multilayer film reflector on the surface, so that the laser light is emitted in a direction perpendicular to the surface. Therefore, VCSEL is easier to be arrayed in two dimensions than when an end-emitting laser element is used. As an example, the number of VCSELs included in the light source 20 is 100 to 1000. In addition, a plurality of VCSELs are connected in parallel to each other and are driven in parallel. The number of VCSELs is an example and can be set according to the measurement distance or the irradiation range.

[0059] On the surface of the light source 20, an anode electrode 218 common to a plurality of VCSELs is provided. On the back of the light source 20, a cathode electrode 214 (see below) is provided. Figure 3). That is, a plurality of VCSELs are connected in parallel. By connecting a plurality of VCSELs in parallel and driving them, strong light can be emitted compared to the case where the VCSELs are driven independently.

[0060] Here, the shape of the light source 20 observed from the surface side (referred to as a plane shape, the same below) is a rectangle. Also, the side surface on the -y direction side is referred to as the side surface 21A, the side surface on the +y direction side is referred to as the side surface 21B, the side surface on the -x direction side is referred to as the side surface 22A, and the side surface on the +x direction side is referred to as the side surface 22B. The side surface 21A and the side surface 21B face each other. The side surface 22A and the side surface 22B are connected to the side surface 21A and the side surface 21B, respectively, and face each other.

[0061] (VCSEL structure)

[0062] Figure 3 1 is a diagram for explaining the cross-sectional structure of one VCSEL in the light source 20. The VCSEL is a VCSEL of a λ resonance structure. The upper direction of the paper is defined as the z direction, the +z direction is referred to as the upper side, and the -z direction is referred to as the lower side.

[0063] The VCSEL is composed of an n-type lower distributed Bragg reflector (DBR) 202, an active region 206, and a p-type upper distributed Bragg reflector 208 stacked in sequence on an n-type GaAs or other semiconductor substrate 200. The n-type lower distributed Bragg reflector 202 is formed by alternately stacking AlGaAs layers with different Al components, the active region 206 includes a quantum well layer sandwiched by an upper diaphragm layer and a lower diaphragm layer, and the p-type upper distributed Bragg reflector 208 is formed by alternately stacking AlGaAs layers with different Al components. Hereinafter, the distributed Bragg reflector is referred to as DBR.

[0064] The n-type lower DBR 202 is configured so that Al 0.9 Ga 0.1 The thickness of each layer of the lower DBR 202 is λ / 4n. r (where λ is the oscillation wavelength, n r is the refractive index of the medium), and 40 periods are alternately stacked. As a carrier, silicon (Si) is doped as an n-type impurity. The carrier concentration is, for example, 3×10 18 cm -3 .

[0065] The active region 206 is composed of a lower diaphragm layer, a quantum well active layer, and an upper diaphragm layer stacked together. For example, the lower diaphragm layer is undoped Al 0.6 Ga0.4 As layer, the quantum well active layer is a non-doped InGaAs quantum well layer and a non-doped GaAs barrier layer, and the upper diaphragm layer is a non-doped Al 0.6 Ga 0.4 As layer.

[0066] The p-type upper DBR 208 is configured so that the p-type Al 0.9 Ga 0.1 The thickness of each layer of the upper DBR 208 is λ / 4n. r , and 29 cycles are alternately stacked. As a carrier, carbon (C) is doped as a p-type impurity. The carrier concentration is, for example, 3×10 18 cm -3 Preferably, a contact layer including p-type GaAs is formed at the uppermost layer of the upper DBR 208 , and a current constriction layer 210 including p-type AlAs is formed at the lowermost layer of the upper DBR 208 or inside thereof.

[0067] By etching the semiconductor layers stacked from the upper DBR 208 to the lower DBR 202, a cylindrical mesa M is formed on the semiconductor substrate 200. As a result, the current constriction layer 210 is exposed on the side of the mesa M. Through the oxidation process, an oxidized region 210A oxidized from the side of the mesa M and a conductive region 210B surrounded by the oxidized region 210A are formed in the current constriction layer 210. In addition, in the oxidation process, the oxidation rate of the AlAs layer is faster than that of the AlGaAs layer, and the oxidized region 210A is oxidized at a substantially constant rate from the side of the mesa M toward the inside, so the cross-sectional shape of the conductive region 210B becomes a shape reflecting the outer shape of the mesa M, that is, a circular shape, and its center is substantially consistent with the axis of the mesa M shown by a dotted chain line. In this embodiment, the mesa M has a columnar structure.

[0068] On the uppermost layer of the mesa M, a metal annular p-side electrode 212 formed by stacking Ti / Au and the like is formed. The p-side electrode 212 is in ohmic contact with a contact layer provided in the upper DBR 208. The inner side of the annular p-side electrode 212 becomes a light exit port 212A from which laser light is emitted to the outside. That is, the VCSEL emits light in the +z direction perpendicular to the surface (the surface on the +z direction side) of the semiconductor substrate 200. And, the axis of the mesa M becomes the optical axis. Furthermore, on the back side of the semiconductor substrate 200, a cathode electrode 214 is formed as an n-side electrode. In addition, the surface (the surface on the +z direction side) of the upper DBR 208 on the inner side of the p-side electrode 212 is a light emitting surface.

[0069] In addition, an insulating film 216 is provided so as to cover the surface of the mesa M except for the portion of the p-side electrode 212 connected to the anode electrode 218 and the light exit port 212A. In addition, the anode electrode 218 is provided so as to be in ohmic contact with the p-side electrode 212 except for the light exit port 212A. In addition, the anode electrode 218 is provided in common to a plurality of VCSELs. That is, the p-side electrodes 212 of the plurality of VCSELs constituting the light source 20 are connected in parallel through the anode electrode 218.

[0070] Figure 3 In the figure, the portion of the anode electrode 218 is marked as [A] indicating that it is an anode, and the portion of the cathode electrode 214 is marked as [K] indicating that it is a cathode.

[0071] VCSEL can oscillate in either a single transverse mode or multiple transverse modes. For example, the light output of one VCSEL is 4 mW to 8 mW. Therefore, when the light source 20 includes 500 VCSELs, the light output of the light source 20 is 2 W to 4 W.

[0072] (Structure of the Light Diffusing Member 30)

[0073] Figure 4 (a) and Figure 4 (b) is a diagram illustrating an example of the light diffusion member 30 . Figure 4 (a) is a plane diagram, Figure 4 (b) is Figure 4 (a) is a cross-sectional view taken along line IVB-IVB. Figure 4 In (a), the right direction of the paper is set as the x direction, and the upward direction of the paper is set as the y direction. The direction orthogonal to the x direction and the y direction in the counterclockwise direction is set as the z direction. In addition, in the light diffusion member 30, the +z direction side is called the surface or the surface side, and the -z direction side is called the back side or the back side. Therefore, Figure 4 In (b), the right direction of the paper is the x direction, the back direction of the paper is the y direction, and the upper direction of the paper is the z direction.

[0074] like Figure 4 As shown in (b), the light diffusion member 30 includes, for example, a resin layer 32, and the resin layer 32 has a concave-convex shape for diffusing light on the back side (-z direction) of the glass substrate 31 whose two sides are parallel and flat. The light diffusion member 30 expands the spread angle of the light incident from the VCSEL of the light source 20 and emits it. That is, the concave-convex shape formed on the resin layer 32 of the light diffusion member 30 refracts or scatters the light, so that the incident light becomes light with a wider spread angle and is emitted. That is, as Figure 4 (a) and Figure 4As shown in (b), the light diffusion member 30 causes the light with a spread angle θ incident from the back side (-z direction side) and emitted from the VCSEL to be emitted from the surface (+z direction side) as light with a spread angle φ larger than the spread angle θ (θ<φ). Therefore, when the light diffusion member 30 is used, the area of ​​the irradiated surface irradiated by the light emitted by the light source 20 is expanded compared to the case where the light diffusion member 30 is not used. The spread angle θ and the spread angle φ are the full width half maximum (FWHM).

[0075] Here, the planar shape of the light diffusion member 30 is a rectangle. Also, the thickness (thickness in the z direction) t of the light diffusion member 30 is d The plane shape of the light diffusion member 30 may be other shapes such as a polygon or a circle.

[0076] (Driver 50 and Capacitor 70A, Capacitor 70B)

[0077] When the light source 20 is to be driven at a higher speed, low-side driving can be performed. The so-called low-side driving refers to a structure in which a driving element such as a MOS transistor is located on the downstream side of a path for current flow (hereinafter referred to as a current path) relative to a driving object such as a VCSEL. On the contrary, a structure in which a driving element is located on the upstream side is called a high-side driving.

[0078] Figure 5 1 is a diagram showing an example of an equivalent circuit when the light source 20 is driven by low-side driving. Figure 5 , the VCSEL of the light source 20, the driving unit 50, the capacitor 70A, the capacitor 70B, the capacitor 70C and the power supply 82 are shown. As mentioned above, the capacitor 70C is a parasitic capacitance generated by the structure of the wiring substrate 10. Therefore, the capacitor 70C is represented by a dotted line. In addition, Figure 5 In Figure 1 The control unit 8 shown in FIG. 8 is provided with a power supply 82. The power supply 82 generates a DC voltage with the + side being the power supply potential and the - side being the reference potential. The power supply potential is supplied to the power supply line 83, and the reference potential is supplied to the reference line 84. In addition, the reference potential may be a ground potential (sometimes referred to as GND, Figure 5 marked as [G] in the figure).

[0079] As described above, the light source 20 is composed of a plurality of VCSELs connected in parallel. Figure 3 , Figure 5 Marked as [A] in the figure) is connected to the power line 83.

[0080] The driving unit 50 includes an n-channel MOS transistor 51 and a signal generating circuit 52 for turning the MOS transistor 51 on and off. Figure 5 The cathode electrode 214 (see Figure 3 , Figure 5 The source of MOS transistor 51 ( Figure 5 The gate of the MOS transistor 51 is connected to the signal generating circuit 52. That is, the MOS transistor 51 of the VCSEL and driving unit 50 is connected in series between the power supply line 83 and the reference line 84. The signal generating circuit 52 generates an "H level" signal for turning on the MOS transistor 51 and an "L level" signal for turning off the MOS transistor 51 under the control of the control unit 8.

[0081] One terminal of each of capacitor 70A, capacitor 70B, and capacitor 70C is connected to power line 83 ( Figure 5 The other terminal is connected to the reference line 84 ( Figure 5 [G]).

[0082] Next, a method of driving the light source 20 by low-side driving will be described.

[0083] First, assume that the signal generated by the signal generating circuit 52 in the driving unit 50 is at an "L level". At this time, the MOS transistor 51 is in an off state. That is, at the source ( Figure 5 [S])-Drain( Figure 5 Therefore, no current flows in the VCSEL connected in series with the MOS transistor 51. That is, the VCSEL does not emit light.

[0084] At this time, capacitor 70A, capacitor 70B, and capacitor 70C are connected to power source 82, and capacitor 70A, capacitor 70B, and capacitor 70C are connected to one terminal of power line 83 ( Figure 5 The terminal on the [A] side of the VCSEL) becomes the power supply potential, and the other terminal ( Figure 5 The terminal on the [G] side of the capacitor 70A) becomes the reference potential. Therefore, a current flows from the power supply 82 to the capacitor 70A, the capacitor 70B, and the capacitor 70C (charge is supplied) and they are charged.

[0085] Next, when the signal generated by the signal generating circuit 52 in the driving unit 50 becomes "H level", the MOS transistor 51 changes from the off state to the on state. Thus, a closed loop is formed between the capacitor 70A, the capacitor 70B, the capacitor 70C and the MOS transistor 51 and VCSEL connected in series, and the charge stored in the capacitor 70A, the capacitor 70B, and the capacitor 70C is supplied to the MOS transistor 51 and VCSEL connected in series. That is, the current flows through the VCSEL and the VCSEL emits light. The closed loop is a driving circuit for supplying a driving current for causing the light source 20 to emit light. In addition, since the driving current for causing the light source 20 to emit light is supplied to each capacitor 70A, the capacitor 70B, and the capacitor 70C, the driving circuit is constructed for each capacitor 70A, the capacitor 70B, and the capacitor 70C. In addition, the operation of supplying a driving current for causing the light source 20 to emit light is sometimes referred to as driving the light source 20.

[0086] Furthermore, when the signal generated by the signal generating circuit 52 in the driving unit 50 changes to the "L level" again, the MOS transistor 51 changes from the on state to the off state. As a result, the closed loop of the capacitor 70A, the capacitor 70B, the capacitor 70C, the MOS transistor 51 connected in series, and the VCSEL becomes an open loop, and no current flows to the VCSEL. As a result, the VCSEL stops emitting light. Then, the capacitor 70A, the capacitor 70B, and the capacitor 70C are charged by the current flowing from the power supply 82 (charge is supplied).

[0087] As described above, every time the signal outputted from the signal generating circuit 52 changes to "H level" and "L level", the MOS transistor 51 repeatedly turns on and off, and the VCSEL repeatedly emits light and does not emit light. The on and off repetition of the MOS transistor 51 is sometimes called switching.

[0088] As described above, when the MOS transistor 51 is switched from the off state to the on state, the charges stored in the capacitors 70A, 70B, and 70C are discharged at once, and a driving current is supplied to the VCSEL.

[0089] Here, capacitors (low ESL capacitors and non-low ESL capacitors) are described.

[0090] Figure 6 (a) and Figure 6 (b) is a diagram illustrating a capacitor. Figure 6 (a) is the equivalent circuit of a capacitor, Figure 6 (b) is the frequency characteristic of the capacitor's impedance. In addition, Figure 6 In (b), the horizontal axis is frequency and the vertical axis is impedance.

[0091] like Figure 6 As shown in (a), a capacitor is represented by an equivalent circuit in which a capacitor C, an equivalent series inductance ESL, and an equivalent series resistance ESR (Equivalent Series Resistance) are connected in series.

[0092] like Figure 6 As shown in (b), when the frequency is low, the impedance of the capacitor is determined by the capacitance C. That is, the capacitor is capacitive, and its impedance decreases with the frequency. On the other hand, when the frequency is high, the impedance of the capacitor is determined by the equivalent series inductance ESL. That is, the capacitor is inductive, and its impedance increases with the frequency. In addition, the frequency at which the capacitance C and the equivalent series inductance ESL have the same impedance is called the resonant frequency.

[0093] In order to shorten the rise time of the driving current pulse supplied to the light source 20, it is better to have a small impedance at high frequency, that is, a small equivalent series inductance ESL. That is, in order to shorten the rise time of the driving current pulse supplied to the light source 20, it is better to use a capacitor configured to reduce the equivalent series inductance ESL, that is, a low ESL capacitor. Figure 6 As shown in (b), the low ESL capacitor has a smaller impedance at high frequencies than the non-low ESL capacitor having a structure in which the equivalent series inductance ESL is larger than that of the low ESL capacitor.

[0094] Figure 7 (a) and Figure 7 (b) is a diagram illustrating an example of a low ESL capacitor (capacitor 70A) and a non-low ESL capacitor (capacitor 70B). Figure 7 (a) is a low ESL capacitor (capacitor 70A), Figure 7 (b) is a non-low ESL capacitor (capacitor 70B). They are two-terminal multilayer ceramic capacitors. Multilayer ceramic capacitors such as Figure 7 (a) Figure 7 As shown in (b), it has a structure in which a ceramic sheet 71 made of titanium oxide, barium titanate or the like having a rectangular planar shape and a plurality of internal wirings 72 provided on the surface of the ceramic sheet 71 are stacked.

[0095] Figure 7The low ESL capacitor shown in (a), i.e., capacitor 70A, is constructed such that current flows along the short side direction in a ceramic sheet 71 having a rectangular planar shape. That is, the low ESL capacitor is provided with electrodes at both ends in the short side direction to form a two-terminal stacked ceramic capacitor. When the direction in which the current flows in the ceramic sheet 71 (short side direction) is set to the length L1, and the direction orthogonal to the direction in which the current flows (long side direction) is set to the width W1, the length L1 is smaller than the width W1 (L1<W1). In this way, by shortening the current path, the equivalent series inductance ESL becomes smaller compared to the non-low ESL capacitor described next. This low ESL capacitor in which the width W1 is larger than the length L1 is sometimes referred to as an LW reverse type.

[0096] Figure 7 The non-low ESL capacitor shown in (b), that is, the capacitor 70B, is configured such that the current flows along the long side direction in the ceramic sheet 71 having a rectangular planar shape. That is, the non-low ESL capacitor is provided with electrodes at both ends in the long side direction to form a two-terminal laminated ceramic capacitor. When the direction in which the current flows in the ceramic sheet 71 (the long side direction) is set to the length L2, and the direction orthogonal to the direction of the current flow (the short side direction) is set to the width W2, the length L2 is greater than the width W2 (L2>W2). Therefore, the current path becomes longer, and therefore the equivalent series inductance ESL becomes larger than that of the low ESL capacitor.

[0097] If a low-ESL capacitor with a small equivalent series inductance ESL is used, the impedance at high frequency becomes smaller, and the rise time of the driving current pulse supplied to the light source 20 becomes shorter. However, most low-ESL capacitors have a small rated capacity despite the large mounting area occupied on the wiring substrate 10. Therefore, when only capacitor 70A as a low-ESL capacitor is used instead of capacitor 70B as a non-low-ESL capacitor, for example, to drive a light source 20 of about 2W, a plurality of capacitors 70A will be used. At this time, for each capacitor 70A, the current path to the VCSEL will become different. If the current path becomes longer, the wiring inductance will increase, making it difficult to obtain the effect of using a low-ESL capacitor. That is, since the mounting area occupied on the wiring substrate 10 is increased by using a plurality of capacitors 70A as low-ESL capacitors, it is difficult to obtain the effect of a small equivalent series inductance ESL.

[0098] On the other hand, non-low ESL capacitors use ceramic sheets 71 with high dielectric constants, and most of them have large rated capacitance despite a small mounting area on the wiring substrate 10. For example, to drive a light source 20 of about 2W, only one non-low ESL capacitor is needed. However, compared with low ESL capacitors, the equivalent series inductance ESL is large, so it is difficult to shorten the rise time of the driving current pulse supplied to the light source 20.

[0099] Therefore, in this embodiment, capacitor 70A as a low ESL capacitor and capacitor 70B as a non-ESL capacitor are used together. In addition, capacitor 70A as a low ESL capacitor and capacitor 70B as a non-low ESL capacitor are connected in parallel. That is, the rise time of the driving current pulse supplied to the light source 20 is shortened by capacitor 70A as a low ESL capacitor, and the current for driving the light source 20 is supplied by capacitor 70B as a non-ESL capacitor.

[0100] Furthermore, in the present embodiment, by using a capacitor 70C including parasitic capacitance generated by the structure of the wiring substrate 10, the rise time of the driving current pulse supplied to the light source 20 is further shortened. As described later, the capacitor including parasitic capacitance generated by the structure of the wiring substrate 10 has a smaller equivalent series inductance ESL than the low ESL capacitor. Therefore, by using the capacitor 70C including parasitic capacitance, the rise time of the current pulse supplied to the light source 20 is further shortened. Therefore, as described below, in the present embodiment, the parasitic capacitance generated by the structure of the wiring substrate 10 becomes larger.

[0101] Figure 8 It is a diagram for explaining a driving current pulse supplied to the light source 20 . Figure 8 In the figure, the horizontal axis is time and the vertical axis is current.

[0102] like Figure 8 As shown, the portion α where the driving current pulse starts to rise is supplied by the capacitor 70C including parasitic capacitance. Also, the rising portion β of the driving current pulse is supplied by the capacitor 70A which is a low ESL capacitor. Furthermore, the portion γ supplying the driving current is supplied by the capacitor 70B which is a non-low ESL capacitor.

[0103] (Light emitting device 4)

[0104] Next, the light emitting device 4 will be described in detail.

[0105] Fig. 9 (a) to Fig. 9 (c) is a diagram for explaining a light emitting device 4 to which this embodiment is applied. Fig. 9 (a) is a plane diagram, Fig. 9 (b) is Fig. 9 (a) is a cross-sectional view of the IXB-IXB line. Fig. 9 (c) is Fig. 9 (a) is a cross-sectional view at the IXC-IXC line. In addition, Fig. 9 (a) is a view obtained by looking through the light diffusion member 30. Fig. 9In (a), the right direction of the paper is set as the x direction, and the upper direction of the paper is set as the y direction. The direction perpendicular to the x direction and the y direction around the counterclockwise direction (the surface direction of the paper) is set as the z direction. In addition, with respect to each component described below (wiring substrate 10, light diffusion component 30, etc.), the surface direction of the paper (+z direction) is referred to as the surface or the surface side, and the back direction of the paper (-z direction) is referred to as the back side or the back side. In the following, the situation of observing each component through the surface side is referred to as a top view. In addition, Fig. 9 (b) and Fig. 9 In (c), the right direction of the paper is the x direction, the back direction of the paper is the y direction, and the upper direction of the paper is the z direction.

[0106] like Fig. 9 (a) and Fig. 9 As shown in (b) of FIG. 1 , the light source 20 , the driving unit 50 , the capacitor 70A, the capacitor 70B, and the holding unit 60 are provided on the surface of the wiring substrate 10 . Furthermore, the light diffusion member 30 is provided on the holding unit 60 .

[0107] The wiring substrate 10 is formed by providing a wiring layer on an insulating substrate (sometimes referred to as an insulating layer) such as glass epoxy resin, and the wiring layer forms wiring including metal such as copper (Cu) foil. In addition, the so-called wiring refers to a conductor pattern for connecting an electrical circuit, and the shape is not limited. Here, the wiring substrate 10 is described as a printed circuit board having four wiring layers. As an example, the substrate of glass epoxy resin is a glass composite substrate (CEM-3) or a glass epoxy substrate (FR-4).

[0108] like Fig. 9 As shown in FIG. 2( a ), in the light emitting device 4 , the light source 20 and the driving unit 50 are arranged on the wiring substrate 10 so as to be aligned in the x direction.

[0109] like Fig. 9 As shown in (a), the holding portion 60 includes a wall ( Fig. 9 In (a), the light source 20 side is indicated by a dotted line). Fig. 9 As shown in (b), the holding portion 60 holds the light diffusion member 30 through the wall. That is, the light diffusion member 30 is provided at a predetermined distance from the light source 20 provided on the wiring substrate 10 through the holding portion 60. And, the light diffusion member 30 is provided in a manner of covering the light source 20. Here, the so-called light diffusion member 30 covering the light source 20 means that the light diffusion member 30 is provided on the emission path of the light emitted by the light source 20, and the light emitted by the light source 20 is transmitted through the light diffusion member 30. That is, it refers to a state in which the light source 20 and the light diffusion member 30 overlap when viewed from the surface side of the light diffusion member 30.

[0110] The holding portion 60 is, for example, a molded member of resin or the like. Furthermore, the holding portion 60 may be colored, for example, black to absorb the light emitted by the light source 20. Thus, the light emitted by the light source 20 and irradiated to the holding portion 60 is absorbed by the holding portion 60. Therefore, the light irradiated to the holding portion 60 is prevented from being transmitted through the holding portion 60 or reflected by the holding portion 60 and irradiated to the object to be measured.

[0111] The wiring substrate 10 is as follows Fig. 9 (b) and Fig. 9 As shown in (c), the wiring substrate 10 includes a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer from the surface side (+z direction side). The first wiring layer and the second wiring layer are insulated by an insulating layer 11A, the second wiring layer and the third wiring layer are insulated by an insulating layer 11B, and the third wiring layer and the fourth wiring layer are insulated by an insulating layer 11C. In addition, when the insulating layer 11A, the insulating layer 11B, and the insulating layer 11C are not distinguished, they are referred to as the insulating layer 11.

[0112] The first wiring layer includes a cathode wiring 12, an anode wiring 13F, a reference potential wiring 14-1F, a reference potential wiring 14-2F, and a reference potential wiring 14-3F that are electrically isolated from each other. Fig. 9 In (a) of FIG. 1 , the cathode wiring 12 , the anode wiring 13F, and the reference potential wiring 14 - 3F portions hidden by the drive unit 50 are indicated by a dotted chain line.

[0113] In the second wiring layer, a reference potential wiring 14M is provided. Fig. 9 As shown by the dotted line in (a), the reference potential wiring 14M is provided on the entire surface of the wiring substrate 10, that is, the so-called whole surface. In addition, the cathode wiring 12, the anode wiring 13F, the reference potential wiring 14-1F, the reference potential wiring 14-2F, and the reference potential wiring 14-3F are provided so as to overlap with the reference potential wiring 14M when viewed from above. Fig. 9 In (a), the edge of the reference potential wiring 14M is set to be wide so as to protrude from the edge of any one of the cathode wiring 12, the anode wiring 13F, the reference potential wiring 14-1F, the reference potential wiring 14-2F, and the reference potential wiring 14-3F. However, the edge of the reference potential wiring 14M does not need to protrude from the edge of any one of the cathode wiring 12, the anode wiring 13F, the reference potential wiring 14-1F, the reference potential wiring 14-2F, and the reference potential wiring 14-3F.

[0114] The third wiring layer is provided with power supply potential wiring 13M. The power supply potential wiring 13M may be provided over the entire surface of the wiring substrate 10, similarly to the reference potential wiring 14M, or may be provided in a manner connected to the anode wiring 13F to supply a power supply potential to the anode wiring 13F.

[0115] The fourth wiring layer is provided with signal wiring for transmitting a signal for controlling the signal generating circuit 52 from the control section 8 to the driving section 50 . Fig. 9 (a) and Fig. 9 In (b), the signal wiring 15 - 1 and the signal wiring 15 - 2 are shown as an example.

[0116] like Fig. 9 (a) and Fig. 9 As shown in (b), the cathode wiring 12 in the first wiring layer has a rectangular planar shape and is provided in a manner to connect the light source 20 and the drive unit 50. In addition, the light source 20 is provided at one end of the cathode wiring 12. That is, the light source 20 (VCSEL) is mounted on the cathode wiring 12 in a manner that the cathode wiring 12 is in contact with the cathode electrode 214 of the VCSEL constituting the light source 20. In addition, the other end of the cathode wiring 12 is connected to the drain of the MOS transistor 51 of the drive unit 50 (see Figure 5 [D]) method and is connected to the driving unit 50.

[0117] The anode wiring 13F in the first wiring layer is provided close to the three sides of the cathode wiring 12, namely, the -x direction side and the ±y direction side. Figure 2 , Figure 3 ) is connected to the anode wiring 13F using a bonding wire 23.

[0118] Furthermore, two openings are provided in the anode wiring 13F, and reference potential wiring 14-1F and reference potential wiring 14-2F are provided inside the respective openings. Furthermore, reference potential wiring 14-3F is provided at the end portion on the x-direction side of the wiring substrate 10. The reference potential wiring 14-3F is connected to the driving unit 50 to be connected to the source of the MOS transistor 51 of the driving unit 50 (see Figure 5 [S]).

[0119] like Fig. 9 (b) and Fig. 9 As shown in (c), the reference potential wiring 14-1F and the reference potential wiring 14-3F in the first wiring layer are connected to the reference potential wiring 14M in the second wiring layer by means of through conductors 14-1V and 14-3V provided in the insulating layer 11A. In addition, although not shown in the figure, the reference potential wiring 14-2F and the reference potential wiring 14M are connected by means of through conductors provided in the insulating layer 11A. In addition, the through conductor is a member in which a conductive material such as copper (Cu) is provided in a through hole provided in the insulating layer 11, and electrically connects the wiring on the surface side of the insulating layer 11 with the wiring on the back side. The through conductor is sometimes referred to as a through hole.

[0120] Anode wiring 13F in the first wiring layer and power supply potential wiring 13M in the third wiring layer are connected by through conductor 13V provided in insulating layer 11A and insulating layer 11B. Through conductor 13V is electrically isolated from reference potential wiring 14M in the second wiring layer.

[0121] And, if Fig. 9 As shown in (a), in the first wiring layer of the wiring substrate 10, a capacitor 70A is provided between the anode wiring 13F and the reference potential wiring 14-1F, and a capacitor 70B is provided between the anode wiring 13F and the reference potential wiring 14-2F. As described above, the reference potential wiring 14-1F and the reference potential wiring 14-2F are provided inside the two openings provided in the anode wiring 13F. Therefore, the capacitor 70A and the capacitor 70B are surrounded by the anode wiring 13F. That is, the anode wiring 13F is provided in a manner surrounding the capacitor 70A and the capacitor 70B. In addition, the anode wiring 13F may be provided in a manner surrounding only one of them, for example, only surrounding the capacitor 70A.

[0122] Here, the anode wiring 13F is provided with two openings, and the reference potential wiring 14-1F and the reference potential wiring 14-2F are provided inside each opening. However, the anode wiring 13F may be provided with one opening, and a reference potential wiring that connects the reference potential wiring 14-1F and the reference potential wiring 14-2F into one may be provided inside the opening.

[0123] like Fig. 9 As shown in (c), the parasitic capacitance generated between the anode wiring 13F in the first wiring layer of the wiring substrate 10 and the reference potential wiring 14M in the second wiring layer is a capacitor 70C. The anode wiring 13F in the first wiring layer and the reference potential wiring 14M in the second wiring layer are insulated by the insulating layer 11A. Here, in order to increase the capacity of the capacitor 70C, the area of ​​the anode wiring 13F is set large. For example, the area where the reference potential wiring 14M in the second wiring layer overlaps with the anode wiring 13F in the first wiring layer is set to be larger than the area where the reference potential wiring 14M in the second wiring layer overlaps with the reference potential wiring 14-3F in the first wiring layer.

[0124] Furthermore, in the first wiring layer, the area of ​​the anode wiring 13F is set larger than the areas of the reference potential wiring 14 - 1F, the reference potential wiring 14 - 2F, and the reference potential wiring 14 - 3F.

[0125] Anode wiring 13F in the first wiring layer of wiring substrate 10 is provided to occupy 50% or more of the surface area of ​​wiring substrate 10. Preferably, anode wiring 13F in the first wiring layer of wiring substrate 10 occupies 75% or more of the surface area of ​​wiring substrate 10.

[0126] Furthermore, the thickness t of the insulating layer 11A is c It is preferred that the thickness of the insulating layer 11A is t 100 μm or less, so that the capacitance of the capacitor 70C including the parasitic capacitance becomes larger. More preferably, the thickness t c Preferably, the thickness is 80 μm or less.

[0127] Fig.10 (a) to Fig.10 (c) is a diagram for explaining a light emitting device 4' to which the present embodiment is not applied for comparison. Fig.10 (a) is a plane diagram, Fig.10 (b) is Fig.10 (a) is a cross-sectional view of the XB-XB line. Fig.10 (c) is Fig.10 (a) is a cross-sectional view at the XC-XC line. In addition, Fig.10 (a) is a view obtained by looking through the light diffusion member 30. Fig. 9 (a) Fig. 9 (b) and Fig. 9 The same reference numerals are used to denote components having the same functions as the light emitting device 4 shown in (c) of the present embodiment. Hereinafter, description of the same components as those of the light emitting device 4 will be omitted, and different components will be described.

[0128] In the light emitting device 4', the anode wiring 13F and the reference potential wiring 14F in the first wiring layer of the wiring substrate 10 are different from those in the light emitting device 4. That is, the anode wiring 13F has a rectangular planar shape and is provided on the side surface 21A (-y direction) of the light source 20. That is, the anode wiring 13F is provided in the following manner, that is, it is connected to the anode electrode 218 of the light source 20 by the bonding wire 23, and is connected to one of the terminals of the capacitor 70A and the capacitor 70B. In addition, the reference potential wiring 14F is provided in a manner surrounding the cathode wiring 12 and the anode wiring 13F. In addition, the reference potential wiring 14F is connected to the reference potential wiring 14M of the second wiring layer through the through conductor 14V.

[0129] That is, in the light emitting device 4', similarly to the light emitting device 4, the cathode wiring 12, the anode wiring 13F, and the reference potential wiring 14F in the first wiring layer of the wiring substrate 10 overlap with the reference potential wiring 14M in the second wiring layer of the wiring substrate 10 in a plan view. However, in the first wiring layer of the wiring substrate 10, the reference potential wiring 14F is provided except for the portion where the cathode wiring 12 and the anode wiring 13F are provided. Here, the area where the reference potential wiring 14M in the second wiring layer overlaps with the anode wiring 13F in the first wiring layer is set to be smaller than the area where the reference potential wiring 14M in the second wiring layer overlaps with the reference potential wiring 14-3F in the first wiring layer.

[0130] Furthermore, in the first wiring layer, the area of ​​the anode wiring 13F is set smaller than the area of ​​the reference potential wiring 14F.

[0131] Furthermore, anode wiring 13F in the first wiring layer of wiring substrate 10 is provided so as to occupy less than 50% of the surface area of ​​wiring substrate 10 .

[0132] In the conventional design of the wiring substrate 10, the cathode wiring 12 and the anode wiring 13F are generally provided in the first wiring layer at the portion required for electrical connection, and the reference potential wiring 14F is provided in the other portion. Thus, the area facing the anode wiring 13F in the first wiring layer of the wiring substrate 10 and the reference potential wiring 14M in the second wiring layer is smaller than that of the light emitting device 4. Therefore, the capacitor 70C (see FIG. 1 ) including the parasitic capacitance is Figure 5 ) is small. Therefore, in the light emitting device 4', the capacitor 70C including the parasitic capacitance is difficult to supply the portion ( Figure 8 That is, in the light emitting device 4', it is difficult to shorten the rise time of the driving current pulse supplied to the light source 20.

[0133] As described above, in the light emitting device 4 to which the present embodiment is applied, the area of ​​the anode wiring 13F is set large so that the area where the anode wiring 13F in the first wiring layer of the wiring substrate 10 and the reference potential wiring 14M in the second wiring layer face each other with the insulating layer 11A sandwiched therebetween becomes larger. In this way, the capacity of the capacitor 70C included in the parasitic capacitance formed between the anode wiring 13F and the reference potential wiring 14M is increased, and the rise time of the driving current pulse supplied to the light source 20 is shortened. That is, in the light emitting device 4, the parasitic capacitance (capacitance component) between the wirings sandwiched with the insulating layer 11 is used more.

[0134] The light output of the light source 20 in the light emitting device 4 is 2W to 4W. Such a high-output light source 20 generates a lot of heat. Therefore, it is required to dissipate heat efficiently from the light source 20. Therefore, the light source 20 may be disposed on an insulating heat dissipation substrate having a higher thermal conductivity than the wiring substrate 10, and the heat dissipation substrate may be disposed on the wiring substrate 10. In addition, the thermal conductivity of the insulating layer called FR-4 used for the wiring substrate 10 is about 0.4W / m·K. Therefore, as a heat dissipation substrate, a substrate having a thermal conductivity of 10W / m·K or more is preferred, and a substrate having a thermal conductivity of 50W / m·K or more is further preferred. Furthermore, a substrate having a thermal conductivity of 100W / m·K or more is more preferred. As a substrate having a thermal conductivity of 10W / m·K or more, aluminum oxide (Al2O3) having a thermal conductivity of 20W / m·K to 30W / m·K can be cited. 2 O 3 ). In addition, as a substrate having a thermal conductivity of 50 W / m·K or more, silicon nitride (Si 2+) having a thermal conductivity of about 85 W / m·K can be cited. 3 N 4 ). Furthermore, as a substrate having a thermal conductivity of 100 W / m·K or more, aluminum nitride (AlN) having a thermal conductivity of 150 W / m·K to 250 W / m·K can be cited. They are sometimes referred to as ceramic materials. Moreover, it is preferred that the heat dissipation substrate as a whole comprises a ceramic material. Moreover, the heat dissipation substrate may also be other insulating materials having a high thermal conductivity, such as silicon (Si) not doped with impurities.

[0135] Furthermore, in the light emitting device 4 to which this embodiment is applied, the capacitor 70A as a low ESL capacitor and the capacitor 70B as a non-ESL capacitor are used. However, if the capacitance of the capacitor 70C including the parasitic capacitance is large, the capacitor 70A as a low ESL capacitor may not be used.

[0136] Furthermore, in the light emitting device 4 to which this embodiment is applied, the parasitic capacitance generated between the anode wiring 13F in the first wiring layer of the wiring substrate 10 and the reference potential wiring 14M in the second wiring layer is used as the capacitor 70C. Alternatively, a wiring layer (herein referred to as a capacitor layer) for supplying a reference potential may be provided at a position facing the anode wiring 13F in the insulating layer 11A, and a capacitance including the anode wiring 13F and the capacitor layer may be used as the capacitor 70C. The capacitance including the anode wiring 13F and the capacitor layer is another example of a capacitance component.

[0137] In addition, in the light-emitting device 4 applicable to the present embodiment, a light source 20 and a driving unit 50 are provided on the surface of the wiring substrate 10, but the circuit substrate provided with the light source 20 and the circuit substrate provided with the driving unit 50 can also be independently constructed, and they are connected using a flexible flat cable (Flexible Flat Cable, FFC) or a flexible printed circuit (Flexible Printed Circuit, FPC) and the like.

[0138] In addition, in the light emitting device 4 to which this embodiment is applied, a light diffusion member 30 is used as an example of an optical member, and the light diffusion member 30 changes the spread angle of the incident light in an expanded manner by diffusion and emits it. The optical member may also be a diffractive optical element (DOE) that changes the light in a direction different from the incident direction and emits it. In addition, the optical member may also be a transparent member such as a focusing lens, a microlens, or a protective cover.

Claims

1. A light emitting device, comprising: A wiring substrate having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer; A laser unit having a cathode electrode and an anode electrode, mounted on the wiring substrate and driven by a low side; as well as A capacitor element is mounted on the wiring substrate and supplies a driving current to the laser unit, wherein: A cathode wiring connected to the cathode electrode and an anode wiring connected to the anode electrode are provided in the first wiring layer. A reference potential wiring connected to a reference potential is provided in the second wiring layer, The reference potential wiring of the second wiring layer is provided in a region overlapping with the anode wiring, The anode wiring is provided so as to surround the capacitor element.

2. The light emitting device according to claim 1, wherein having a plurality of said capacitive elements, The anode wiring is provided so as to surround the plurality of capacitor elements.

3. The light emitting device according to claim 1 or 2, wherein The anode wiring has an area that is 50% or more of an area of ​​the wiring substrate.

4. The light emitting device according to claim 1 or 2, wherein The anode wiring has an area that is 75% or more of an area of ​​the wiring substrate.

5. The light emitting device according to claim 1 or 2, wherein The thickness of the insulating layer is less than 100 μm.

6. The light emitting device according to claim 1 or 2, wherein The laser unit is a surface emitting laser element array in which a plurality of surface emitting laser elements are formed on a common semiconductor substrate.

7. The light emitting device according to claim 1 or 2, wherein An optical member is provided for changing at least one of the direction and the spread angle of the light emitted from the laser unit.

8. An optical device comprising: The light emitting device according to any one of claims 1 to 7; as well as a light receiving unit for receiving reflected light emitted from the laser unit included in the light emitting device and reflected by the object to be measured, The light receiving unit outputs a signal corresponding to the time from when the light is emitted from the laser unit to when the light is received by the light receiving unit.

9. A measuring device comprising: The optical device as claimed in claim 8; as well as a three-dimensional shape determination unit that determines the three-dimensional shape of the object to be measured based on reflected light from the object to be measured, which is emitted from the laser unit included in the optical device and received by the light receiving unit included in the optical device; The measuring device measures the three-dimensional shape of the object to be measured.

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