Memory Module Controller

Abstract

The present disclosure includes devices and methods related to memory module controllers. An example device, such as a memory module, may include a first interface coupled to a host, a second interface coupled to another memory module. The memory module may include a controller configured to communicate with the host via the first interface and to communicate with the other memory module via the second interface. The first and second interfaces may be configured according to different standards or protocols. The controller may control access to memory on the memory module. In some examples, the other memory module connected via the second interface may include a local controller and different types of memory. The memory module may be heterogeneous and may support various operations or functions within a wider system managed by the host. In some examples, the memory module may include non-volatile or volatile memory, or both.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices, and more particularly, to apparatus and methods for a memory module controller. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory may provide persistent data by retaining stored data when not powered and may include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memories are also used as volatile and nonvolatile data storage devices for a wide range of electronic applications. Nonvolatile memories can be used, for example, in personal computers, portable memory sticks, digital cameras, cellular phones, portable music players (such as MP3 players), movie players, and other electronic devices. Memory cells can be arranged in an array, where the array is used in a memory device.

[0004] The memory may be part of a memory module, such as a dual in-line memory module (DIMM), used in a computing device. The memory module may include volatile memory, such as DRAM, for example, and / or non-volatile memory, such as flash memory or RRAM, for example. A DIMM may use main memory in a computing system. Summary of the invention

[0005] In one aspect, the present disclosure relates to an apparatus for a memory module controller, comprising: a first plurality of memory devices; a second plurality of memory devices, which are configured as cache memories; a controller, which is coupled to the first plurality and the second plurality of memory devices and is configured to control access operations to the first plurality and the second plurality of memory devices; a non-volatile dual in-line memory module (NVDIMM) interface, which is coupled to the controller and can be coupled to a host, the controller being configured to communicate with the host via the NVDIMM interface; and a second interface of a different type from the NVDIMM interface, which is coupled to the controller and can be coupled to a remote memory module, the controller being configured to communicate with the remote memory module via the second interface. a remote memory module for communicating with the remote memory module; wherein the controller is configured to: receive a command from the host requesting data from the first plurality of memory devices; determine whether data associated with the command is located in the second plurality of memory devices; in response to determining that the data is located in the second plurality of memory devices, transfer the data from the second plurality of memory devices to the host; determine whether data associated with the command is located in the first plurality of memory devices; in response to determining that the data is located in the first plurality of memory devices, transfer the data from the first plurality of memory devices to the host; and in response to determining that the data is not located in the first plurality of memory devices or the second plurality of memory devices, transfer the command to the remote memory module.

[0006] In another aspect, the present disclosure relates to an apparatus for a memory module controller, comprising: a non-volatile dual in-line memory module (NVDIMM) interface that can be coupled to a host; a second interface of a different type than the NVDIMM interface that can be coupled to a memory module; a first number of memory devices; a second number of memory devices that are configured as cache memory; and a controller that is coupled to the NVDIMM interface, the second interface, the first number of memory devices, and the second number of memory devices, wherein the controller is configured to: execute a number of first commands to transfer data between the host and the first number of memory devices; and transfer a number of second commands and data from the host to the memory module for execution on the memory module; determine and request a number of first commands to transfer data between the host and the first number of memory devices; and determine and request a number of second commands to transfer data to the memory module. determining whether data associated with a command for the data from the first number of memory devices is located in the second number of memory devices; transferring the data from the second number of memory devices to the host in response to a determination by the cache controller that the data is located in the second number of memory devices; determining whether data associated with the command is located in the first number of memory devices; transferring the data from the first number of memory devices to the host in response to a determination that the data is located in the first number of memory devices; and generating a plurality of third commands to be executed by the memory module to transfer data between the memory module and the plurality of memory devices in response to a determination that the data is not located in the first number of memory devices or the second number of memory devices.

[0007] On the other hand, the present disclosure relates to an apparatus for a memory module controller, comprising: a non-volatile dual in-line memory module (NVDIMM) interface that can be coupled to a host; a second interface of a different type than the NVDIMM interface that can be coupled to a memory module; a first number of memory devices; a second number of memory devices that are configured as cache memory; and a controller that is coupled to the NVDIMM interface, the second interface, the first number of memory devices, and the second number of memory devices, wherein the controller includes a cache controller and a dynamic random access memory (DRAM) controller and wherein the controller is configured to: receive a request from the host for a request from the first number of memory devices; The invention relates to a method for transmitting data associated with a memory device of the present invention; determining, using the cache controller, whether the data associated with the command is located in the second number of memory devices; transferring the data from the second number of memory devices to the host in response to the cache controller determining that the data is located in the second number of memory devices; determining whether the data associated with the command is located in the first number of memory devices; transferring the data from the first number of memory devices to the host in response to determining that the data is located in the first number of memory devices; and transferring the command to the memory module in response to determining that the data is not located in the first number of memory devices or the second number of memory devices.

[0008] In another aspect, the present disclosure relates to a method for a memory controller module, comprising: receiving a plurality of first commands, a plurality of second commands, and a plurality of third commands from a host via a non-volatile dual in-line memory module (NVDIMM) interface, the plurality of first commands, the plurality of second commands, and the plurality of third commands each requesting data from a first number of memory devices of a dual in-line memory module; using a cache controller to determine whether the data associated with the plurality of first commands and the data associated with the plurality of second commands are located in a plurality of second memory devices of the dual in-line memory module configured as cache memory; In response to the cache controller determining that the data associated with the first commands are located in the second memory devices, the first commands are executed; in response to the cache controller determining that the data associated with the second commands are located in the first memory devices, the second commands are executed; and in response to the cache controller determining that the data associated with the third commands are not located in the first memory devices or the second memory devices, the third commands are transmitted to the second memory module via an interface different from the NVDIMM interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a device in the form of a computing system including a memory system according to several embodiments of the present disclosure.

[0010] Figure 2A and 2B is a block diagram of a device in the form of a computing system including at least a portion of a memory system on a printed circuit board (PCB) in accordance with several embodiments of the present disclosure.

[0011] Figure 3A and 3B is a block diagram of a device in the form of a computing system including a memory system having a memory module with a memory system controller in accordance with several embodiments of the present disclosure.

[0012] Figure 4A and 4B is a block diagram of an apparatus in the form of a computing system including a memory module with a memory system controller and a direct memory access (DMA) module according to several embodiments of the present disclosure.

[0013] Figure 5 is a block diagram of a device in the form of a computing system including a memory system having a memory module with a memory system controller, a cache controller, and a DRAM controller in accordance with several embodiments of the present disclosure.

[0014] Figure 6 is a flow chart illustrating an example method of using a memory module controller according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] The present disclosure includes apparatus and methods related to memory module controllers. An example apparatus may include a first interface coupled to a host, a second interface coupled to a memory module, and a controller, wherein the controller is configured to communicate with the host via the first interface and with the memory module via the second interface.

[0016] In several embodiments, a first DIMM may be coupled to a host via a first interface. The first interface may be formed on a printed circuit board. The first DIMM may be coupled to a plurality of other DIMMs via a second interface. The host may communicate with the plurality of other DIMMs through the first DIMM via the first interface. The first DIMM may include a controller to execute commands from the host and / or send commands and / or data to the plurality of other DIMMs coupled to the first DIMM via the second interface.

[0017] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure and in which several embodiments of the present disclosure are shown by way of illustration how they may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designator "N" indicates that a number of specific features so specified may be included in several embodiments of the present disclosure.

[0018] As used herein, "a number" of something may refer to one or more such things. For example, a number of memory devices may refer to one or more memory devices. Additionally, designators such as "N" as used herein, particularly with respect to reference numerals in the accompanying drawings, indicate that a number of particular features so designated may be included in several embodiments of the present disclosure.

[0019] The figures herein follow a numbering convention in which the first or first few digits correspond to the figure number of the accompanying drawing and the remaining digits identify the element or assembly in the accompanying drawing. Similar elements or assemblies between different figures can be identified by using similar numbers. It will be appreciated that the elements shown in the various embodiments herein can be added, exchanged and / or eliminated in order to provide several additional embodiments of the present disclosure. In addition, the proportions and relative dimensions of the elements provided in the figures are intended to illustrate the various embodiments of the present disclosure and are not used in a limiting sense.

[0020] Figure 1 is a block diagram of an apparatus in the form of a computing system including a memory system according to several embodiments of the present disclosure. As used herein, "apparatus" may refer to, but is not limited to, any of a variety of structures or combinations of structures, such as, for example, a circuit or circuit system, a die or several dies, a module or several modules, a device or several devices, or a system or several systems. Figure 1 In the embodiments described in, the memory system may include one or more memory modules, such as memory modules 110-1, ..., 110-X, 110-Y, for example. Memory modules 110-1, ..., 110-X, 110-Y may be dual in-line memory modules (DIMMs) and may include volatile memory (such as DRAM), and / or non-volatile memory (such as storage class memory and / or 3D X-Point memory), as well as other types of memory. The memory system may include any type of memory device, such as a DIMM with memory. In several embodiments, the memory system may include a multi-chip device. The multi-chip device may include several different memory types and / or memory modules. For example, the memory system may include non-volatile or volatile memory on any type of module. The following is combined with Figures 1 to 5The described examples use DIMMs as memory modules, but the disclosed protocols can be used on any memory system.

[0021] exist Figure 1 In the embodiment, the memory system includes a host 102 coupled to a DIMM 110-1 via a channel including a bus 113-1, an interface A 112-1, and an interface A 112-2. The DIMM 110-1 is coupled to DIMMs 110-2 and 110-X and the DIMM 110-1 may be coupled to Figure 1 DIMMs 110-1, 110-2, and 110-X are coupled together and configured to transfer commands and / or data between each other. Figure 1 1, DIMM 110-1 is coupled to DIMM 110-2 via bus 116-1, interface B 114-1, and interface B 114-2. DIMM 110-2 is coupled to DIMM 110-X via bus 116-2, interface B 114-3, and interface B 114-4. Interfaces A 112-1, 112-2, 112-3, and 112-4 may be used to couple host 102 to DIMMs (e.g., Figure 1 , 110-X, 110-Y). Interface A 114-1, ..., 114-8 may be used to couple DIMMs 110-1, ..., 110-X, 110-Y to each other. Interface A may be an interface of the same type as interface B; and interface A may be an interface of a different type than interface B. Interface A may be an NVDIMM interface that allows non-deterministic execution of commands. For example, interface B may be a parallel, serial, and / or multi-serial interface. The interface type of interface A and / or interface B may depend on the type of memory module and / or the type of memory device on the memory module. For example, DIMM 110-1 may include interface A 112-2 as an NVDIMM interface to communicate with host 102, wherein host 102 includes interface A 112-1 that is also in an NVDIMM interface. DIMM 110-1 may include Interface B 114-1 as a DDR5 interface to communicate with DIMM 110-2, where DIMM 110-2 is a DDR DIMM and includes Interface B 114-2 as a DDR5 interface. DIMM 110-2 may include Interface B 114-3 as a storage class memory interface to communicate with DIMM 110-X, where DIMM 110-X is a DIMM including storage class memory and Interface B 114-4 is a storage class memory interface.

[0022] DIMMs 110-1 and 110-2 may be configured to receive commands from host 102 via interface A 112-2 and interface A 112-4, respectively. DIMMs 110-1 and 110-2 may be configured to execute commands by transferring data between DIMMs 110-1, ..., 110-X, 110-Y via interface B 114-1, ..., 114-8, and between host 102 and DIMMs 110-1 and 110-2 via interface A 112-2 and interface A 112-4, respectively. DIMMs may be configured to transfer data between DIMMs 110-1, ..., 110-X, 110-Y via interfaces B 114-1, ..., 114-8, respectively, while transferring data between host 102 and DIMMs 110-1 and 110-2 via interfaces A 112-2 and A 112-4.

[0023] exist Figure 1 , the memory system includes a host 102 coupled to a DIMM 110-3 via a channel including a bus 113-2, an interface A 112-3, and an interface A 112-4. DIMM 110-3 is coupled to DIMMs 110-4 and 110-Y and DIMM 110-1 may be coupled to Figure 1 DIMMs 110-3, 110-4, and 110-Y are coupled together and configured to transfer commands and / or data between each other. Figure 1 In FIG. 1 , DIMM 110-3 is coupled to DIMM 110-4 via bus 116-3, interface B 114-5, and interface B 114-6. DIMM 110-4 is coupled to DIMM 110-Y via bus 116-4, interface B 114-7, and interface B 114-8.

[0024] In some embodiments, each of the DIMMs 110-1, ..., 110-X, 110-Y may include a controller, such as a memory system controller. In some embodiments, at least one of the coupled DIMMs 110-1, ..., 110-X may include a controller, such as a memory system controller; and at least one of the coupled DIMMs 110-3, ..., 110-Y may include a controller, such as a memory system controller. Figures 3A to 5A memory system controller is described. The controller on DIMMs 110-1, ..., 110-X, 110-Y can receive commands from host 102 and control the execution of commands on the DIMMs. Moreover, in several embodiments, the disclosed protocol can be implemented by memory devices on DIMMs (e.g., DIMMs 110-1, ..., 110-X, 110-Y) that do not have a controller and the execution of commands using the disclosed protocol can be built into the memory devices.

[0025] The host 102 may send commands to the DIMMs 110-1, ..., 110-X, 110-Y using a protocol that depends on the type of memory in the DIMMs. For example, the host may use the NVDIMM protocol to communicate with NVDIMM DIMMs on the same channel and use the DDR5 protocol to communicate with DRAM DIMMs coupled together.

[0026] like Figure 1 , the host 102 may be coupled to the DIMMs 110-1, ..., 110-X, 110-Y. In several embodiments, the DIMMs 110-1, ..., 110-X may be coupled to the host 102 via a channel including interfaces A 112-1 and 112-2, a bus 113-1, an interface B 114-1, ..., 114-4, and buses 116-1 and 116-2. The DIMMs 110-3, ..., 110-Y may be coupled to the host 102 via a channel including interfaces A 112-3 and 112-4, a bus 113-2, an interface B 114-5, ..., 114-8, and buses 116-3 and 116-4. Host 102 may be a laptop computer, a personal computer, a digital camera, a digital recording and playback device, a mobile phone, a PDA, a memory card reader, an interface hub, and other host systems, and may include a memory access device, such as a processor. A person skilled in the art will appreciate that "processor" may mean one or more processors, such as a parallel processing system, a plurality of coprocessors, a processing resource, etc.

[0027] The host 102 includes a host controller 104 to communicate with the memory system. The host controller 104 may send commands to the DIMMs 110-1, ..., 110-X, 110-Y. The host controller 104 may communicate with the DIMMs 110-1, ..., 110-X, 110-Y and / or the controllers on each of the DIMMs 110-1, ..., 110-X, 110-Y to read, write, and erase data, as well as other operations. An interface (e.g., interface A 112) may provide an interface for transferring control, address, data, and other signals between a DIMM (e.g., DIMM 110-1, ..., 110-X, 110-Y) having a compatible interface receiver and the host 102. Signals may be communicated between the host 102 and the DIMMs 110-1, ..., 110-X, 110-Y via a plurality of buses (e.g., buses 113-1 and 113-2), such as data buses and / or address buses, such as via a plurality of channels. An interface (e.g., interface B 114) may provide an interface for passing control, address, data, and other signals between DIMMs (e.g., DIMMs 110-1, ..., 110-X, 110-Y) having compatible interface receptacles. Signals may be communicated between the DIMMs 110-1, ..., 110-X, 110-Y via a plurality of buses (e.g., buses 116-1, ..., 116-4), such as data buses and / or address buses, such as via a plurality of channels.

[0028] The host controller 104 and / or the controller on the DIMM may include control circuitry, such as hardware, firmware, and / or software. In one or more embodiments, the host controller 108 and / or the controller on the DIMM may be an application specific integrated circuit (ASIC) coupled to a printed circuit board that includes a physical interface. In addition, each DIMM 110-1, ..., 110-X, 110-Y may include buffers and registers of volatile and / or non-volatile memory. The buffers may be used to buffer data used during the execution of a read command and / or a write command.

[0029] DIMMs 110-1, ..., 110-X, 110-Y may provide main memory for a memory system or may be used as additional memory or storage devices throughout the memory system. Each DIMM 110-1, ..., 110-X, 110-Y may include a number of memory devices, each memory device having one or more arrays of memory cells (e.g., volatile and / or non-volatile memory cells). For example, the arrays may be flash memory arrays with a NAND architecture. Embodiments are not limited to a particular type of memory device. For example, the memory devices may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, 3D X-Point, and flash memory, among others.

[0030] Figure 1 Embodiments of the present disclosure may include additional circuitry not described so as not to obscure the embodiments of the present disclosure. For example, the memory system may include address circuitry to latch address signals provided on the I / O connections by the I / O circuitry. The address signals may be received and decoded by row decoders and column decoders to access the DIMMs 110-1, ..., 110-X, 110-Y. Those skilled in the art will appreciate that the number of address input connections may depend on the density and architecture of the DIMMs 110-1, ..., 110-X, 110-Y.

[0031] Figure 2A and 2B is a block diagram of a device in the form of a computing system including at least a portion of a memory system on a printed circuit board (PCB) according to several embodiments of the present disclosure. Figure 2A 2, a host 202, a DIMM 210-1, and a DIMM 210-2 are formed on a PCB 207. The host 202 is coupled to the DIMM 210-1 via an interface A 212-1, an interface A 212-2, and a bus 213. The bus 213 is formed in the PCB 207. The host 202 can send commands and / or data to the DIMM 210-1 and the DIMM 210-2 through the bus 213. The DIMM 210-1 is coupled to the DIMM 210-2 via an interface B 214-1, an interface B 214-2, and a bus 216. Commands and / or data from the host 202, the DIMM 210-1, and / or the DIMM 210-2 can be transmitted between the DIMMs 210-1 and 210-2 via the interface B 214-1, the interface B 214-2, and the bus 216.

[0032] DIMMs 210-1 and 210-2 may receive power and ground signals via connection points on PCB 207. DIMM 210-2 may receive commands and / or data via bus 216, which is external to PCB 207. Several DIMMs may be coupled together via a bus (e.g., bus 216) and an interface (e.g., interface B 214) that is not on PCB 207 (e.g., external to PCB 207). This allows several DIMMs to be coupled together and not be constrained by the physical limitations of using connection points on PCB 207. In several embodiments, bus 216 that couples DIMM 210-1 to DIMM 210-2 may be located on PCB 207.

[0033] Commands and / or data may be transferred between the host 202 and DIMM 210-1 via bus 213, while commands and / or data may be transferred between DIMM 210-1 and DIMM 210-2 via bus 216. Bus 213 and bus 216 may be controlled independently of one another. Moreover, DIMM 210-1 may be configured to transfer commands and / or data intended for DIMM 210-2 from the host 202 to DIMM 210-2, and DIMM 210-1 may be configured to transfer commands and / or data intended for the host 202 from DIMM 210-2 to the host 202.

[0034] exist Figure 2B 2, a host 202, a DIMM 210-1, and a DIMM 210-2 are formed on a PCB 207, and a solid state drive (SSD) 211 is coupled to the DIMM 210-2. The SSD 211 is not formed on the PCB 207. The host 202 is coupled to the DIMM 210-1 via an interface A 212-1, an interface A 212-2, and a bus 213. The bus 213 is formed in the PCB 207. The host 202 can send commands and / or data to the DIMM 210-1 and the DIMM 210-2 through the bus 213. The DIMM 210-1 is coupled to the DIMM 210-2 via an interface B 214-1, an interface B 214-2, and a bus 216. The SSD 211 is coupled to the DIMM 210-2 via an interface C 215 and a bus 217. Commands and / or data from host 202 , DIMM 210 - 1 , DIMM 210 - 2 , and / or SSD 211 may be transferred between DIMMs 210 - 1 and 210 - 2 via interface B 214 - 1 , interface B 214 - 2 , and bus 216 , and / or between DIMM 210 - 1 and SSD 211 via interface C 215 and bus 217 .

[0035] DIMMs 210-1 and 210-2 may receive power and ground signals via connection points on PCB 207. DIMM 210-2 may receive commands and / or data via bus 216, which is external to PCB 207. Several DIMMs may be coupled together via buses (e.g., bus 216) and interfaces (e.g., interface B 214) that are not on PCB 207. DIMMs may be coupled to other memory devices (e.g., SSD 211) that are also not on PCB 207. This allows several DIMMs and memory devices to be coupled together and not be constrained by the physical limitations of using connection points on PCB 207. In several embodiments, bus 217 and SSD 211 may be located on PCB 207.

[0036] Figure 3A and3B is a block diagram of a device in the form of a computing system including a memory system having a memory module with a memory system controller according to several embodiments of the present disclosure. Figure 3A , a host 302 is coupled to a DIMM 310-1 via an interface A 312-1, an interface A 312-2, and a bus 313. The DIMM 310-1 includes a controller 320 coupled to the interface A 312-2. The DIMM 310-1 includes a memory device 330-1, ..., 330-4 coupled to the controller 320. The memory devices 330-1, ..., 330-4 may include a non-volatile memory array and / or a volatile memory array. The memory devices 330-1, ..., 330-4 may include a control circuit system 332 (e.g., hardware, firmware, and / or software) that can be used to execute commands on the memory devices 330-1, ..., 330-4. The control circuit system 332 may receive commands from the controller 320. The control circuit system 332 may be configured to execute commands to read and / or write data in the memory devices 330-1, ..., 330-4. For example, DIMM 310-1 may be an NVDIMM with memory devices 330-1 and 330-2 including DRAM and memory devices 330-3 and 330-4 including 3D X-Point memory.

[0037] DIMM 310-1 is coupled to DIMM 310-2 via interface B 314-1, interface B 314-2, and bus 316. DIMM 310-2 includes a controller 322 coupled to interface B 314-2. DIMM 310-2 includes memory devices 330-5, ..., 330-8 coupled to controller 322. Memory devices 330-5, ..., 330-8 may include non-volatile memory arrays and / or volatile memory arrays. Memory devices 330-5, ..., 330-8 may include control circuit systems 332 (e.g., hardware, firmware, and / or software) that can be used to execute commands on memory devices 330-5, ..., 330-8. Control circuit systems 332 may receive commands from controller 320. Control circuit systems 332 may be configured to execute commands to read and / or write data in memory devices 330-5, ..., 330-8. For example, the memory devices 330-5, ..., 330-8 may include storage class memory.

[0038] The controller 320 on DIMM 310-1 may be a memory system controller. The memory system controller may receive commands and / or data and determine where to send the commands and / or data. The controller 320 may receive commands from the host 302 and / or DIMM 310-2 and determine that the commands are to be executed by DIMM 310-1. The controller 320 may control the execution of the commands in response to determining that the commands are to be executed by DIMM 310-1. The controller 320 may receive commands from the host 302 and determine that the commands are to be executed by DIMM 310-2. The controller 320 may transmit the commands to DIMM 310-2 in response to determining that the commands are to be executed by DIMM 310-2. The controller 320 may receive data from DIMM 310-2 from the host 302 and determine that the data is to be stored on DIMM 310-2. The controller 320 may cause the data to be written on DIMM 310-2 in response to determining that the data is to be stored on DIMM 310-1. The controller 320 may receive data from the DIMM 310-2 from the host 302 and determine that the data is to be sent to the host 302. The controller 320 may send the data to the host 302 in response to determining that the data is to be sent to the host 302.

[0039] exist Figure 3B , a host 302 is coupled to a DIMM 310-1 via an interface A 312-1, an interface A 312-2, and a bus 313. The DIMM 310-1 includes a controller 320 coupled to the interface A 312-2. The DIMM 310-1 includes memory devices 330-1, ..., 330-4 coupled to the controller 320. The memory devices 330-1, ..., 330-4 may include a non-volatile memory array and / or a volatile memory array. The memory devices 330-1, ..., 330-4 may include a control circuit system 332 (e.g., hardware, firmware, and / or software) that can be used to execute commands on the memory devices 330-1, ..., 330-4. The control circuit system 332 may receive commands from the controller 320. The control circuit system 332 may be configured to execute commands to read and / or write data in the memory devices 330-1, ..., 330-4. For example, DIMM 310-1 may be an NVDIMM with memory devices 330-1 and 330-2 including DRAM and memory devices 330-3 and 330-4 including 3D X-Point memory.

[0040] DIMM 310-1 is coupled to DIMM 310-2 via bus 319. DIMM 310-2 includes memory devices 330-5, ..., 330-8. Memory devices 330-5, ..., 330-8 may include non-volatile memory arrays and / or volatile memory arrays. Memory devices 330-5, ..., 330-8 may include control circuit systems 332 (e.g., hardware, firmware, and / or software) that can be used to execute commands on memory devices 330-5, ..., 330-8. Control circuit systems 332 may receive commands from controller 320. Control circuit systems 332 may be configured to execute commands to read and / or write data in memory devices 330-5, ..., 330-8. For example, memory devices 330-5, ..., 330-8 may include storage class memory.

[0041] The controller 320 on DIMM 310-1 may be a memory system controller. The memory system controller may receive commands and / or data and determine where to send the commands and / or data. The controller 320 may receive commands from the host 302 and / or DIMM 310-2 and determine that the commands are to be executed by DIMM 310-1 and / or DIMM 310-2. The controller 320 may control the execution of the commands in response to determining the location of the commands to be executed. The controller 320 may receive commands from the host 302 and determine that the commands are to be executed using DIMM 310-2. The controller 320 may execute the commands in response to determining that the commands are to be executed using DIMM 310-2 to transfer data between DIMM 310-1 and DIMM 310-2 via bus 319. The controller 320 may receive data from DIMM 310-2 from the host 302 and determine that the data is to be stored on DIMM 310-2. The controller 320 may execute the command in response to determining that data is to be stored on the DIMM 310-2 so as to write the data on the DIMM 310-2 via the bus 319. The controller 320 may receive data from the DIMM 310-2 via the bus 319 and determine that the data is to be sent to the host 302. The controller 320 may send the data to the host 302 in response to determining that the data is to be sent to the host 302.

[0042] Figure 4A and 4B is a block diagram of an apparatus in the form of a computing system including a memory system having a memory module with a memory system controller and a direct memory access (DMA) module according to several embodiments of the present disclosure. Figure 4A, a host 402 is coupled to a DIMM 410-1 via an interface A 412-1, an interface A 412-2, and a bus 413. The DIMM 410-1 includes a controller 420 coupled to the interface A 412-2. The DIMM 410-1 includes a memory device 430-1, ..., 430-4 coupled to the controller 420. The memory devices 430-1, ..., 430-4 may include a non-volatile memory array and / or a volatile memory array. The memory devices 430-1, ..., 430-4 may include a control circuit system 432 (e.g., hardware, firmware, and / or software) that can be used to execute commands on the memory devices 430-1, ..., 430-4. The control circuit system 432 may receive commands from the controller 420. The control circuit system 432 may be configured to execute commands to read and / or write data in the memory devices 430-1, ..., 430-4. For example, DIMM 410-1 may be an NVDIMM with memory devices 430-1 and 430-2 including DRAM and memory devices 430-3 and 430-4 including 3D X-Point memory.

[0043] DIMM 410-1 is coupled to DIMM 410-2 via interface B 414-1, interface B 414-2, and bus 416. DIMM 410-2 includes a controller 422 coupled to interface B 414-2. DIMM 410-2 includes memory devices 430-5, ..., 430-8 coupled to controller 422. Memory devices 430-5, ..., 430-8 may include non-volatile memory arrays and / or volatile memory arrays. Memory devices 430-5, ..., 430-8 may include control circuitry 432 (e.g., hardware, firmware, and / or software) that may be used to execute commands on memory devices 430-5, ..., 430-8. Control circuitry 432 may receive commands from controller 420. Control circuitry 432 may be configured to execute commands to read and / or write data in memory devices 430-5, ..., 430-8. For example, memory devices 430-5, ..., 430-8 may include storage class memory.

[0044] The controller 420 on the DIMM 410-1 may be a memory system controller. The memory system controller may receive commands and / or data and determine where to send the commands and / or data. The controller 420 may receive commands from the host 402 and / or the DIMM 410-2 and determine the commands to be executed by the DIMM 410-1. The controller 420 may include a direct memory access (DMA) module 424. The controller 420 may generate commands via the DMA module 424 to perform a DMA transfer of data from the DIMM 410-2 to the DIMM 410-1.

[0045] exist Figure 4B , a host 402 is coupled to a DIMM 410-1 via an interface A 412-1, an interface A 412-2, and a bus 413. The DIMM 410-1 includes a controller 420 coupled to the interface A 412-2. The DIMM 410-1 includes a memory device 430-1, ..., 430-4 coupled to the controller 420. The memory devices 430-1, ..., 430-4 may include a non-volatile memory array and / or a volatile memory array. The memory devices 430-1, ..., 430-4 may include a control circuit system 432 (e.g., hardware, firmware, and / or software) that can be used to execute commands on the memory devices 430-1, ..., 430-4. The control circuit system 432 may receive commands from the controller 420. The control circuit system 432 may be configured to execute commands to read and / or write data in the memory devices 430-1, ..., 430-4. For example, DIMM 410-1 may be an NVDIMM with memory devices 430-1 and 430-2 including DRAM and memory devices 430-3 and 430-4 including 3D X-Point memory.

[0046] DIMM 410-1 is coupled to DIMM 410-2 via bus 419. DIMM 410-2 includes memory devices 430-5, ..., 430-8. Memory devices 430-5, ..., 430-8 may include non-volatile memory arrays and / or volatile memory arrays. Memory devices 430-5, ..., 430-8 may include control circuit systems 432 (e.g., hardware, firmware, and / or software) that can be used to execute commands on memory devices 430-5, ..., 430-8. Control circuit systems 432 may receive commands from controller 420. Control circuit systems 432 may be configured to execute commands to read and / or write data in memory devices 430-5, ..., 430-8. For example, memory devices 430-5, ..., 430-8 may include storage class memory.

[0047] The controller 420 on the DIMM 410-1 may be a memory system controller. The memory system controller may receive commands and / or data and determine where to send the commands and / or data. The controller 420 may receive commands from the host 402 and / or the DIMM 410-2 and determine the commands to be executed by the DIMM 410-1. The DIMM 410-2 may include a direct memory access (DMA) module 424. The controller 420 may generate commands via the DMA module 424 to perform a DMA transfer of data from the DIMM 410-2 to the DIMM 410-1.

[0048] Figure 5is a block diagram of a device in the form of a computing system including a memory system having a memory module with a memory system controller, a cache controller, and a DRAM controller according to several embodiments of the present disclosure. Figure 5 , a host 502 is coupled to a DIMM 510-1 via an interface A 512-1, an interface A 512-2, and a bus 513. The DIMM 510-1 includes a controller 520 coupled to the interface A 512-2. The DIMM 510-1 includes a memory device 530-1, ..., 530-4 coupled to the controller 520. The memory devices 530-1, ..., 530-4 may include a non-volatile memory array and / or a volatile memory array. The memory devices 530-1, ..., 530-4 may include a control circuit system 532 (e.g., hardware, firmware, and / or software) that can be used to execute commands on the memory devices 530-1, ..., 530-4. The control circuit system 532 may receive commands from the controller 520. The control circuit system 532 may be configured to execute commands to read and / or write data in the memory devices 530-1, ..., 530-4. For example, DIMM 510-1 may be a DDR5 DIMM with memory devices 530-1, ..., 530-4 including DRAM.

[0049] DIMM 510-1 is coupled to DIMM 510-2 via interface B 514-1, interface B 514-2, and bus 516. DIMM 510-1 includes a controller 522 coupled to interface B 514-2. DIMM 510-2 includes memory devices 530-5, ..., 530-8 coupled to controller 522. Memory devices 530-5, ..., 530-8 may include non-volatile memory arrays and / or volatile memory arrays. Memory devices 530-5, ..., 530-8 may include control circuit systems 532 (e.g., hardware, firmware, and / or software) that can be used to execute commands on memory devices 530-5, ..., 530-8. Control circuit systems 532 may receive commands from controller 520. Control circuit systems 532 may be configured to execute commands to read and / or write data in memory devices 530-5, ..., 530-8. For example, the memory devices 530-5, ..., 530-8 may include storage class memory.

[0050] Controller 520 on DIMM 510-1 may be a memory system controller. The memory system controller may receive commands and / or data and determine where to send the commands and / or data. Controller 520 may include cache controller 526 and DRAM controller 528. DIMM 510-1 may be configured as a cache for a memory system. Cache tags and data may be stored in memory devices 530-1, ..., 530-4 and / or in a memory such as SRAM on memory devices 530-1, ..., 530-4 and / or controller 520. Controller 520 may receive a command from host 502, using cache controller 526 to determine whether data associated with the command is located in cache (e.g., in memory devices 530-1, ..., 530-4) based on cache tag data. The controller 520 may use the DRAM controller 528 to send data from the devices 530-1, ..., 530-4 to the host 502 in response to the cache controller 526 determining that the data associated with the command is a hit (e.g., the cache tag data in the devices 530-1, ..., 530-4 matches the tag data of the command). The controller 520 may send the command to the DIMM 510-2 in response to determining that the data associated with the command is a miss (e.g., the cache tag data in the devices 530-1, ..., 530-4 does not match the tag data of the command). The DIMM 510-2 may send the data to the host 502 via the DIMM 510-2 in response to receiving the command from the controller 520.

[0051] Figure 6 is a flow chart illustrating an example method of using a memory module controller according to several embodiments of the present disclosure. Figure 6 The process described in may be performed by, for example, a memory system including a memory module such as DIMM 310 shown in FIG. 3 .

[0052] At block 650, the method may include receiving a first number of commands and a second number of commands from a host.

[0053] At block 652, the method may include executing the first number of commands in response to determining that the first number of commands include instructions to transfer data between the first memory module and the host.

[0054] At block 654, the method may include transferring the second number of commands to the second memory module in response to determining that the second number of commands includes instructions to transfer data between the second memory module and the host.

[0055] Although specific embodiments have been illustrated and described herein, it will be understood by those of ordinary skill in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or changes of various embodiments of the present disclosure. It should be understood that the above description has been made in an illustrative manner and not in a restrictive manner. Upon reviewing the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those of skill in the art. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims together with the full scope of equivalents enjoyed by such claims.

[0056] In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This disclosure method should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than those explicitly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment.

Claims

1. A device for a memory module controller, comprising: a first plurality of memory devices (330, 330-1, 330-2, 330-3, 330-4, 430, 430-1 to 430-8, 530); a second plurality of memory devices (330, 330-1, 330-2, 330-3, 330-4, 430, 430-1 to 430-8, 530) configured as cache memory; a controller (320, 322, 420, 422, 520, 522) coupled to the first and second pluralities of memory devices and configured to control access operations to the first and second pluralities of memory devices; a non-volatile dual in-line memory module NVDIMM interface (112-1, 112-2, 312-2, 412-2, 512-2) coupled to the controller and coupleable to a host (102, 202, 302, 402, 502) and located on a printed circuit board PCB, the controller being configured to communicate with the host via the NVDIMM interface; and a second interface (114-1, 114-2, 314-1, 414-1, 514-1) of a different type than the NVDIMM interface, not located on the PCB and coupled to the controller and coupleable to a remote memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2), the controller being configured to communicate with the remote memory module via the second interface; The controller is configured to: receiving a command from the host requesting data from the first plurality of memory devices; determining whether data associated with the command is located in the second plurality of memory devices; transferring the data from the second plurality of memory devices to the host in response to determining that the data is located in the second plurality of memory devices; determining whether data associated with the command is located in the first plurality of memory devices; transferring the data from the first plurality of memory devices to the host in response to determining that the data is located in the first plurality of memory devices; transmitting the command to the remote memory module in response to determining that the data is not located in the first plurality of memory devices or the second plurality of memory devices; and The data is received from the remote memory module, transferred to the host, and stored in the second plurality of memory devices.

2. The apparatus of claim 1, wherein the apparatus is a dual in-line memory module, the first plurality of memory devices comprises dynamic random access memory (DRAM) memory devices, and the remote memory module comprises memory devices of a different type.

3. The apparatus of claim 2, wherein the memory devices of the remote memory modules (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2) include at least one of 3D X-Point, NAND flash memory, or NOR flash memory, or any combination thereof.

4. The apparatus of claim 1, wherein the controller (320, 322, 420, 422, 520, 522) is configured to cause data to be transferred from the remote memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2) to the apparatus via the second interface (114-1, 114-2, 314-1, 414-1, 514-1) and to transfer data from the apparatus to the host (102, 202, 302, 402, 502) via the NVDIMM interface (112-1, 112-2, 312-2, 412-2, 512-2).

5. The apparatus of claim 1 , wherein the controller ( 320, 322, 420, 422, 520, 522) is configured to simultaneously cause a first data transfer between the host ( 102, 202, 302, 402, 502) and the apparatus via the NVDIMM interface ( 112-1, 112-2, 312-2, 412-2, 512-2) and a second data transfer between the apparatus and the remote memory module ( 110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2) via the second interface (114-1, 114-2, 314-1, 414-1, 514-1).

6. The apparatus of claim 1, wherein the NVDIMM interface (112-1, 112-2, 312-2, 412-2, 512-2) is configured according to a first protocol and the second interface (114-1, 114-2, 314-1, 414-1, 514-1) is configured according to a second protocol different from the first protocol.

7. A device for a memory module controller, comprising: A non-volatile dual in-line memory module NVDIMM interface (112-1, 112-2, 312-2, 412-2, 512-2) that can be coupled to a host (102, 202, 302, 402, 502) and is located on a printed circuit board PCB; a second interface (114-1, 114-2, 314-1, 414-1, 514-1) of a different type than the NVDIMM interface that can be coupled to a remote memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2) and is not located on the PCB; a first number of memory devices (330, 330-1, 330-2, 330-3, 330-4, 430, 430-1 to 430-8, 530); a second number of memory devices configured as cache memory; and a controller (320, 322, 420, 422, 520, 522) coupled to the NVDIMM interface, the second interface, the first number of memory devices, and the second number of memory devices, wherein the controller is configured to: executing a plurality of first commands to transfer data between a host and the first number of memory devices; transmitting a plurality of second commands and data from the host to the remote memory module for execution on the remote memory module; determining whether data associated with a command requesting the data from the first number of memory devices is located in the second number of memory devices; transferring the data from the second number of memory devices to the host in response to a determination by the cache controller that the data is located in the second number of memory devices; determining whether data associated with the command is located in the first number of memory devices; transferring the data from the first number of memory devices to the host in response to determining that the data is located in the first number of memory devices; generating a number of third commands to be executed by the remote memory module to transfer data between the remote memory module and the second number of memory devices in response to determining that the data is not located in the first number of memory devices or the second number of memory devices; and The data is received from the remote memory module, transferred to the host, and stored in the second number of memory devices.

8. The apparatus of claim 7, wherein the controller (320, 322, 420, 422, 520, 522) is configured to determine that the plurality of first commands are for execution on the apparatus and to determine that the plurality of second commands are for execution on the remote memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2).

9. The apparatus of claim 7, wherein the plurality of second commands are transmitted to a controller (320, 322, 420, 422, 520, 522) on the remote memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2); and The controller receives the first commands and the second commands from the host (102, 202, 302, 402, 502).

10. The apparatus of claim 7, wherein: the controller being configured to execute the plurality of second commands by sending data from the host (102, 202, 302, 402, 502) to the remote memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2) on a bus; The host generates the plurality of second commands, and The second plurality of commands are executed by reading data from the remote memory module and sending the data read from the remote memory module to the host on a bus.

11. The apparatus of claim 7, wherein the controller (320, 322, 420, 422, 520, 522) is configured to generate the third number of commands via a direct memory access (DMA) module and to execute the third number of commands by transferring data between the second number of memory devices of the apparatus and the remote memory module.

12. The apparatus of claim 7, wherein the controller (320, 322, 420, 422, 520, 522) is configured to receive the plurality of third commands from a direct memory access (DMA) module and to execute the plurality of third commands by transferring data between the remote memory module and the second number of memory devices (330, 330-1, 330-2, 330-3, 330-4, 430, 430-1 to 430-8, 530) of the apparatus.

13. An apparatus for a memory module controller, comprising: A non-volatile dual in-line memory module NVDIMM interface (112-1, 112-2, 312-2, 412-2, 512-2) that can be coupled to a host (102, 202, 302, 402, 502) and is located on a printed circuit board PCB; a second interface (114-1, 114-2, 314-1, 414-1, 514-1) of a different type than the NVDIMM interface that can be coupled to a remote memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2) and is not located on the PCB; a first number of memory devices (330, 330-1, 330-2, 330-3, 330-4, 430, 430-1 to 430-8, 530); a second number of memory devices configured as cache memory; and a controller (320, 322, 420, 422, 520, 522) coupled to the NVDIMM interface, the second interface, the first number of memory devices, and the second number of memory devices, wherein the controller includes a cache controller and a dynamic random access memory (DRAM) controller and wherein the controller is configured to: receiving a command from the host requesting data from the first number of memory devices; determining, using the cache controller, whether data associated with the command is located in the second number of memory devices; transferring the data from the second number of memory devices to the host in response to a determination by the cache controller that the data is located in the second number of memory devices; determining whether data associated with the command is located in the first number of memory devices; transferring the data from the first number of memory devices to the host in response to determining that the data is located in the first number of memory devices; transmitting the command to the remote memory module in response to a determination by the cache controller that the data is not located in the first number of memory devices or the second number of memory devices; and The data is received from the remote memory module, transferred to the host, and stored in the second number of memory devices.

14. The apparatus of claim 13, wherein the controller (320, 322, 420, 422, 520, 522) is configured to receive the data from the remote memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2) and to transmit the data to the host (102, 202, 302, 402, 502) in response to transmitting the command to the remote memory module.

15. The apparatus of claim 14, wherein the controller (320, 322, 420, 422, 520, 522) is configured to store the data in the first number of memory devices (330, 330-1, 330-2, 330-3, 330-4, 430, 430-1 to 430-8, 530) in response to receiving the data from the remote memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2).

16. The apparatus of claim 13, wherein the second number of memory devices (330, 330-1, 330-2, 330-3, 330-4, 430, 430-1 to 430-8, 530) are configured to store a cache tag table and cache data; and wherein the cache controller (320, 322, 420, 422, 520, 522) is configured to manage the cache tag table and the cache data in the second number of memory devices.

17. The apparatus of claim 13, wherein the command is received by the controller from the host, and wherein the command comprises instructions to transfer data between the host and the remote memory module.

18. A method for a memory controller module, comprising: Receiving a plurality of first commands, a plurality of second commands, and a plurality of third commands from a host (102, 202, 302, 402, 502) via a non-volatile dual in-line memory module (NVDIMM) interface located on a printed circuit board (PCB), the plurality of first commands, the plurality of second commands, and the plurality of third commands each requesting data from a plurality of first memory devices of a remote dual in-line memory module; determining, using a cache controller, whether data associated with the plurality of first commands and data associated with the plurality of second commands are located in a plurality of second memory devices of the remote dual in-line memory module configured as cache memory; executing the plurality of first commands in response to a determination by the cache controller that the data associated with the plurality of first commands is located in the plurality of second memory devices; executing the plurality of second commands in response to a determination by the cache controller that the data associated with the plurality of second commands is located in the plurality of first memory devices; transmitting the third commands to the remote dual in-line memory module via an interface that is a different type than the NVDIMM interface in response to a determination by the cache controller that the data associated with the third commands is not located in the first memory devices or the second memory devices, wherein the interface of a different type from the NVDIMM interface is not located on the PCB; and The data is received from the remote dual in-line memory module, transmitted to the host, and stored in the plurality of second memory devices.

19. The method of claim 18, wherein executing the first commands comprises reading data associated with the first commands from the second memory devices on the remote dual in-line memory module and sending the data associated with the first commands to the host.

20. The method of claim 18, further comprising: receiving data from the remote dual in-line memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2) at the remote dual in-line memory module (110-1, 110-2, 110-X, 110-3, 110-4, 110-Y, 210-1, 210-2, 310-1, 310-2, 410-1, 410-2, 510-1, 510-2) in response to executing the plurality of third commands; and The data received from the remote dual in-line memory module is sent to the host (102, 202, 302, 402, 502) in response to executing the third commands.

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