Semiconductor package

Abstract

A semiconductor package includes an upper substrate having a first surface and a second surface opposite each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0025383, filed on February 28, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor package, and more specifically, to a semiconductor package in which a plurality of semiconductor chips are mounted. Background Technology

[0004] Integrated circuit chips can be implemented in the form of semiconductor packages for suitable application in electronic products. In a typical semiconductor package, the semiconductor chip can be mounted on a printed circuit board (PCB) and electrically connected to the PCB via bonding wires or bumps. Given the increasing demand for small, lightweight, and multifunctional electronic devices, there has recently been increased interest in multi-chip packages and / or system-in-packages. A multi-chip package can be characterized as a single semiconductor package in which chips are stacked, while a system-in-package can be characterized as a single semiconductor package in which different types of chips are mounted for system operation. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor package in which multiple semiconductor chips can be easily mounted and where integration density can be easily increased.

[0006] An embodiment of the present invention provides a semiconductor package comprising: an upper substrate having a first surface and a second surface opposite to each other; a lower semiconductor chip disposed on the first surface of the upper substrate; a plurality of conductive pillars disposed on at least one side of the lower semiconductor chip on the first surface of the upper substrate; and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.

[0007] Embodiments of the inventive concept also provide a semiconductor package including an upper substrate having first and second surfaces opposite each other, a plurality of lower semiconductor chips on the first surface of the upper substrate and laterally spaced apart from each other, a plurality of conductive pillars on the first surface of the upper substrate and laterally spaced apart from the plurality of lower semiconductor chips, and a plurality of upper semiconductor chips on the second surface of the upper substrate and laterally spaced apart from each other. The upper substrate includes first upper substrate pads adjacent to the first surface and second upper substrate pads adjacent to the second surface. Each of the plurality of lower semiconductor chips can include lower chip pads connected to corresponding respective first upper substrate pads, and the plurality of conductive pillars can be connected to corresponding respective first upper substrate pads. Each of the plurality of upper semiconductor chips includes upper chip pads connected to corresponding respective second upper substrate pads.

[0008] Embodiments of the inventive concept also provide a semiconductor package including an upper substrate having first and second surfaces opposite each other, a lower semiconductor chip disposed on the first surface of the upper substrate, an intermediate substrate disposed on the first surface of the upper substrate at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the intermediate substrate are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate. The intermediate substrate can be a semiconductor chip, a printed circuit board, an interposer, or a redistribution substrate. The intermediate substrate includes a through electrode penetrating therethrough.

[0009] Embodiments of the inventive concept also provide a semiconductor package including a first substrate having first and second surfaces opposite each other, a second substrate having a first surface facing the first surface of the first substrate, a plurality of first semiconductor chips and a plurality of conductive pillars disposed between the first and second substrates, the plurality of first semiconductor chips mounted on the first surface of the first substrate, at least one of the plurality of first semiconductor chips including a plurality of through electrodes electrically connected to the first substrate, the plurality of conductive pillars laterally spaced apart from the plurality of first semiconductor chips and electrically connected to the first and second substrates, and a plurality of second semiconductor chips disposed on the second surface of the first substrate and electrically connected to the first substrate. BRIEF DESCRIPTION OF DRAWINGS

[0010] Embodiments of the inventive concept will become more apparent in view of the following detailed description, taken in conjunction with the attached drawings.

[0011] Figure 1 A plan view of a semiconductor package according to embodiments of the inventive concept is shown.

[0012] Figure 2 A cross-sectional view taken along lineFigure 1 a cross-sectional view taken along line I-I' of

[0013] Figure 3 shows a cross-sectional view taken along line I-I' of Figure 1 semiconductor package 1100 according to embodiments of inventive concepts.

[0014] Figure 4 shows a cross-sectional view taken along line I-I' of Figure 1 semiconductor package 1200 according to embodiments of inventive concepts.

[0015] Figure 5 shows a cross-sectional view taken along line I-I' of Figure 1 semiconductor package 1300 according to embodiments of inventive concepts.

[0016] Figure 6 shows a cross-sectional view taken along line I-I' of Figure 1 semiconductor package 1400 according to embodiments of inventive concepts.

[0017] Figure 7 shows a cross-sectional view taken along line I-I' of Figure 1 semiconductor package 1500 according to embodiments of inventive concepts.

[0018] Figure 8 , Figure 9 , Figure 10 and Figure 11 shows a cross-sectional view taken along line I-I' of Figure 1 describing a method of manufacturing a semiconductor package according to embodiments of inventive concepts.

[0019] Figure 12 shows a cross-sectional view taken along line I-I' of Figure 1 semiconductor package 1600 according to embodiments of inventive concepts.

[0020] Figure 13 shows a cross-sectional view taken along line I-I' of Figure 1 describing a method of manufacturing a semiconductor package according to embodiments of inventive concepts.

[0021] Figure 14 shows a cross-sectional view taken along line I-I' of Figure 1 semiconductor package 1700 according to embodiments of inventive concepts.

[0022] Figure 15 shows a cross-sectional view taken along line I-I' of Figure 1 describing a method of manufacturing a semiconductor package according to embodiments of inventive concepts.

[0023] Figure 16 An embodiment of the concept of the present invention is shown along Figure 1 A cross-sectional view of the semiconductor package 1800 taken by line I-I'.

[0024] Figure 17 An embodiment of the concept of the present invention is shown along Figure 1 A cross-sectional view of the semiconductor package 1900 taken from line I-I'.

[0025] Figure 18 An embodiment of the concept of the present invention is shown along Figure 1 A cross-sectional view of semiconductor package 2000 taken from line I-I'.

[0026] Figure 19 An embodiment of the concept of the present invention is shown along Figure 1 A cross-sectional view of semiconductor package 2100 taken by line I-I'.

[0027] Figure 20 An embodiment of the concept of the present invention is shown along Figure 1 A cross-sectional view of semiconductor package 2200 taken by line I-I'. Detailed Implementation

[0028] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 A plan view of a semiconductor package according to an embodiment of the present invention is shown. Figure 2 It shows along Figure 1 The cross-sectional view taken from line I-I'.

[0030] Reference Figure 1 and Figure 2 The semiconductor package 1000 may include: a lower substrate 100; an upper substrate 300 located on the lower substrate 100; a lower semiconductor chip 200 disposed between the lower substrate 100 and the upper substrate 300; a plurality of conductive pillars 280 disposed between the lower substrate 100 and the upper substrate 300 on at least one side of the lower semiconductor chip 200; and an upper semiconductor chip 400 disposed on the upper substrate 300.

[0031] The upper substrate 300 can have a first surface 300S1 and a second surface 300S2 opposite to each other. The upper substrate 300 can be disposed on the lower substrate 100 in such a way that the first surface 300S1 faces the top surface 100U of the lower substrate 100. The upper substrate 300 can include a first upper substrate pad 314 adjacent to the first surface 300S1 and a second upper substrate pad 324 adjacent to the second surface 300S2. The first upper substrate pad 314 and the second upper substrate pad 324 can include an electrically conductive material.

[0032] In some embodiments, the upper substrate 300 can be a silicon interposer. In this case, the upper substrate 300 can include a via layer 310 and a metal interconnect layer 320 on the via layer 310. The metal interconnect layer 320 can be disposed adjacent to the second surface 300S2 of the upper substrate 300, the via layer 310 can be spaced apart from the second surface 300S2 of the upper substrate 300, and the metal interconnect layer 320 can be interposed between the via layer 310 and the second surface 300S2 of the upper substrate 300. The metal interconnect layer 320 can include a metal interconnect line 322 disposed adjacent to the second surface 300S2 of the upper substrate 300. The metal interconnect line 322 can be connected to the second upper substrate pad 324. The via layer 310 can include a via 312 connected to the metal interconnect line 322. The via 312 can extend (e.g., vertically extend) from the metal interconnect line 322 toward the first surface 300S1 of the upper substrate 300. The via 312 can be connected to the first upper substrate pad 314. The via 312 can include an electrically conductive material. The first upper substrate pad 314 can be electrically connected to the second upper substrate pad 324 through the via 312 and the metal interconnect line 322.

[0033] The first upper substrate pad 314 and the second upper substrate pad 324 can have a width (or pitch) in a first direction D1 parallel to the first surface 300S1. For example, the width (or pitch) of the first upper substrate pad 314 and the second upper substrate pad 324 can be greater than about 1 pm and less than about 30 pm. The upper substrate 300 can have a thickness in a second direction D2 perpendicular to the first surface 300S1. For example, the upper substrate 300 can have a thickness of about 30 pm to about 150 pm.

[0034] The lower semiconductor chip 200 can be disposed on and can be connected to the first surface 300S1 of the upper substrate 300. In some embodiments, a plurality of lower semiconductor chips 200 can be disposed between the upper substrate 300 and the lower substrate 100. The plurality of lower semiconductor chips 200 can be disposed on the first surface 300S1 of the upper substrate 300 and can be laterally spaced apart from each other in a first direction D1 parallel to the first surface 300S1. Each of the plurality of lower semiconductor chips 200 can be connected to the first surface 300S1 of the upper substrate 300. The plurality of lower semiconductor chips 200 can be, for example, semiconductor chips of the same kind. In other words, the plurality of lower semiconductor chips 200 can be, for example, memory chips, logic chips, application processor (AP) chips, or system on chips (SOCs). As other examples, the plurality of lower semiconductor chips 200 can include semiconductor chips of different kinds. In other words, the plurality of lower semiconductor chips 200 can include different semiconductor chips selected from a group consisting of memory chips, logic chips, application processor (AP) chips, and system on chips (SOCs).

[0035] One surface 200S of the lower semiconductor chip 200 can face the first surface 300S1 of the upper substrate 300. For example, the lower semiconductor chip 200 can include a lower circuit layer 210 adjacent to one surface 200S of the lower semiconductor chip 200. The lower circuit layer 210 can include an integrated circuit. Alternatively, the lower circuit layer 210 can be disposed adjacent to another surface 200SO of the lower semiconductor chip 200. Figure 2 Differently, the lower circuit layer 210 can be disposed adjacent to another surface 200SO of the lower semiconductor chip 200.

[0036] The lower semiconductor chip 200 can include a lower chip pad 220 adjacent to one surface 200S of the lower semiconductor chip 200. The lower chip pad 220 can include a conductive material. The lower chip pad 220 can be connected to a corresponding one of the first upper substrate pads 314. In some embodiments, a lower bump 240 can be disposed between the lower chip pad 220 and the corresponding first upper substrate pad 314. Each of the lower chip pads 220 can be connected to a corresponding one of the first upper substrate pads 314 through a corresponding one of the lower bumps 240. Each of the lower bumps 240 can include a conductive material and can have at least one of a solder ball shape, a bump shape, and a pillar shape. In some embodiments, a lower underfill layer 245 can be disposed between the one surface 200S of the lower semiconductor chip 200 and the first surface 300S1 of the upper substrate 300 and can cover the lower bumps 240. The lower underfill layer 245 can be disposed locally on the one surface 200S of the lower semiconductor chip 200 and can fill spaces between the lower bumps 240. For example, the lower underfill layer 245 can include an insulating polymer material such as an epoxy resin.

[0037] Another surface 200SO of the lower semiconductor chip 200 can face the top surface 100U of the lower substrate 100. Conductive pads 230 can be disposed on the another surface 200SO of the lower semiconductor chip 200. In some embodiments, at least one of the plurality of lower semiconductor chips 200 can include a lower through via 250 therethrough. In other words, the lower through via 250 can be disposed in at least one of the plurality of lower semiconductor chips 200. Each of the lower through vias 250 can be connected to a corresponding one of the lower chip pads 220 and a corresponding one of the conductive pads 230. The lower through vias 250 can include a conductive material.

[0038] The plurality of conductive pillars 280 can be disposed on the first surface 300S1 of the upper substrate 300 at at least one side of the lower semiconductor chip 200. In some embodiments, the plurality of conductive pillars 280 can be disposed between the plurality of lower semiconductor chips 200. The conductive pillars 280 can be laterally spaced apart from each other on the first surface 300S1 of the upper substrate 300 in the first direction D1, and each of the conductive pillars 280 can be connected to the first surface 300S1 of the upper substrate 300. For example, the conductive pillars 280 can be connected to corresponding respective first upper substrate pads 314, respectively. The conductive pillars 280 can include a metal (e.g., copper). The conductive pillars 280 can have a length in the second direction D2. For example, the length of the conductive pillars 280 can be in a range from about 20 pm to about 30 pm.

[0039] The lower semiconductor chip 200 can be electrically connected to the upper substrate 300 through the lower chip pads 220, the corresponding lower bumps 240, and the corresponding first upper substrate pads 314. The conductive pillars 280 can be electrically connected to the upper substrate 300 through the first upper substrate pads 314 corresponding to the conductive pillars 280. In some embodiments, a width (or pitch) of the first upper substrate pads 314 connected to the lower semiconductor chip 200 can be different from a width (or pitch) of the first upper substrate pads 314 connected to the conductive pillars 280. For example, the width (or pitch) of the first upper substrate pads 314 connected to the conductive pillars 280 can be greater than the width (or pitch) of the first upper substrate pads 314 connected to the lower semiconductor chip 200.

[0040] The lower substrate 100 can include first lower substrate pads 110 adjacent to a top surface 100U of the lower substrate 100 and second lower substrate pads 120 adjacent to a bottom surface 100L of the lower substrate 100. The first lower substrate pads 110 and the second lower substrate pads 120 can include a conductive material. In some embodiments, the lower substrate 100 can be a printed circuit board (PCB). External terminals 130 can be disposed on the bottom surface 100L of the lower substrate 100 and can be connected to the second lower substrate pads 120, respectively. The first lower substrate pads 110 can be electrically connected to the second lower substrate pads 120 by internal interconnection lines (not shown) disposed in the lower substrate 100. In this specification, the lower substrate 100 can also be referred to as a lower structure.

[0041] The conductive pads 230 and the conductive pillars 280 can be connected to the first lower substrate pads 110. In some embodiments, connection bumps 260 can be disposed between the conductive pads 230 and the respective first lower substrate pads 110 and between the conductive pillars 280 and the respective first lower substrate pads 110. Each of the conductive pads 230 and the conductive pillars 280 can be connected to a corresponding one of the first lower substrate pads 110 by a corresponding one of the connection bumps 260. Each of the connection bumps 260 can include a conductive material and can have at least one of a solder ball shape, a bump shape, and a pillar shape.

[0042] The lower semiconductor chips 200 can be electrically connected to the lower substrate 100 by the corresponding conductive pads 230, the corresponding connection bumps 260, and the corresponding first lower substrate pads 110. In some embodiments, at least one of the plurality of lower semiconductor chips 200 can include the lower through electrode 250, and at least one of the plurality of lower semiconductor chips 200 can be electrically connected to the lower substrate 100 by the lower through electrode 250, the corresponding conductive pad 230, the corresponding connection bump 260, and the corresponding first lower substrate pad 110. The conductive pillars 280 can be electrically connected to the lower substrate 100 by the corresponding connection bumps 260 and the corresponding first lower substrate pads 110.

[0043] The lower molding layer 290 can be disposed between the lower substrate 100 and the upper substrate 300 and can fill a space between the lower semiconductor chips 200 and the conductive pillars 280. The lower molding layer 290 can extend onto the other surface 200SO of the lower semiconductor chip 200 to cover sidewalls of the conductive pads 230. The lower molding layer 290 can include an insulating material (e.g., an epoxy molding compound).

[0044] The underfill layer 150 can be disposed between the lower substrate 100 and the lower molding layer 290 and can fill a space between the connection bumps 260. The underfill layer 150 can include an insulating polymer material such as an epoxy resin.

[0045] The upper semiconductor chip 400 can be disposed on and can be connected to the second surface 300S2 of the upper substrate 300. The upper semiconductor chip 400 can be vertically overlapped with at least a portion of the lower semiconductor chip 200 and / or at least a portion of the conductive pillar 280.

[0046] In some embodiments, a plurality of upper semiconductor chips 400 can be disposed on the second surface 300S2 of the upper substrate 300 and can be laterally spaced apart from each other in the first direction D1. Each of the plurality of upper semiconductor chips 400 can be connected to the second surface 300S2 of the upper substrate 300. For example, the plurality of upper semiconductor chips 400 can be semiconductor chips of the same kind. In other words, for example, the plurality of upper semiconductor chips 400 can be memory chips, logic chips, application processor (AP) chips, or system on chips (SOCs). As other examples, the plurality of upper semiconductor chips 400 can include semiconductor chips of different kinds. In other words, the plurality of upper semiconductor chips 400 can include different semiconductor chips selected from a group consisting of memory chips, logic chips, application processor (AP) chips, and system on chips (SOCs). In some embodiments, at least one of the plurality of upper semiconductor chips 400 can be a high bandwidth memory (HBM) chip including a plurality of memory chips stacked in a second direction D2 perpendicular to the second surface 300S2 of the upper substrate 300.

[0047] One surface 400S of the upper semiconductor chip 400 can face the second surface 300S2 of the upper substrate 300. The upper semiconductor chip 400 can include an upper circuit layer 410 adjacent to the one surface 400S of the upper semiconductor chip 400. The upper circuit layer 410 can include an integrated circuit.

[0048] The upper semiconductor chip 400 can include upper chip pads 420 adjacent to one surface 400S of the upper semiconductor chip 400. The upper chip pads 420 can include a conductive material. The upper chip pads 420 can be connected to the second upper substrate pads 324. In some embodiments, upper bumps 440 can be disposed between the upper chip pads 420 and the second upper substrate pads 324. Each of the upper chip pads 420 can be connected to a corresponding one of the second upper substrate pads 324 through a corresponding one of the upper bumps 440. Each of the upper bumps 440 can include a conductive material, and can have at least one of a solder ball shape, a bump shape, and a pillar shape. In some embodiments, an upper underfill layer 445 can be disposed between the one surface 400S of the upper semiconductor chip 400 and the second surface 300S2 of the upper substrate 300, and can cover the upper bumps 440. The upper underfill layer 445 can be disposed locally on the one surface 400S of the upper semiconductor chip 400, and can fill spaces between the upper bumps 440. The upper underfill layer 445 can include an insulating polymer material such as an epoxy resin.

[0049] The upper semiconductor chip 400 can be electrically connected to the upper substrate 300 through the upper chip pads 420, the corresponding upper bumps 440, and the corresponding second upper substrate pads 324. In some embodiments, the upper semiconductor chip 400 can be connected to the metal interconnection lines 322 in the upper substrate 300. The upper semiconductor chip 400 can be electrically connected to the lower semiconductor chip 200 and / or the corresponding conductive pillars 280 through the metal interconnection lines 322 and the vias 312 in the upper substrate 300, and can be electrically connected to the lower substrate 100 through the lower semiconductor chip 200 and / or the corresponding conductive pillars 280. In some embodiments, a plurality of upper semiconductor chips 400 can be electrically connected to each other through the metal interconnection lines 322.

[0050] According to embodiments of the inventive concepts, the upper semiconductor chip 400 can be vertically stacked with at least a portion of the lower semiconductor chip 200 and / or at least a portion of the plurality of conductive pillars 280, and can be connected to the lower semiconductor chip 200 and / or the corresponding conductive pillars 280 through the upper substrate 300. In addition, a plurality of upper semiconductor chips 400 can be horizontally stacked on the upper substrate 300, and can be connected to each other through the upper substrate 300. In other words, the vertically and horizontally stacked plurality of semiconductor chips 200 and 400 can be easily connected to each other through the upper substrate 300, and can be easily connected to the lower substrate 100 through the plurality of conductive pillars 280. As a result, the plurality of semiconductor chips 200 and 400 can be easily mounted on the lower substrate 100, and thus the integration density of the semiconductor package 1000 can be easily improved or increased.

[0051] Figure 3 FIG. 1 illustrates a cross-sectional view of a semiconductor package 1000 according to embodiments of the inventive concepts. Figure 1FIG. 1 is a cross-sectional view of a semiconductor package 100 taken along a line I-I’ thereof. In the following, for the sake of convenience and for the sake of brevity, differences between the semiconductor package 100 and the semiconductor package 1000 described with reference to Figure 3 FIG. 1 will mainly be described. Figure 1 and Figure 2 described with reference to

[0052] With reference to Figure 1 and Figure 3 , the upper substrate 300 can include a first upper substrate pad 314 adjacent to the first surface 300S1 and a second upper substrate pad 324 adjacent to the second surface 300S2. In the present embodiment, the upper substrate 300 can be a printed circuit board (PCB). The first upper substrate pad 314 can be electrically connected to the second upper substrate pad 324 by internal interconnects (not shown) disposed in the upper substrate 300.

[0053] The upper semiconductor chip 400 can be electrically connected to the upper substrate 300 by the upper chip pad 420, the corresponding upper bump 440, and the corresponding second upper substrate pad 324. In the present embodiment, the upper semiconductor chip 400 can be electrically connected to the lower semiconductor chip 200 and / or the corresponding conductive pillar 280 by the corresponding second upper substrate pad 324 and the first upper substrate pad 314 connected thereto. In some embodiments, a plurality of upper semiconductor chips 400 can be electrically connected to each other by the corresponding second upper substrate pad 324.

[0054] Figure 4 FIG. 12 is a cross-sectional view of a semiconductor package 1200 taken along a line I-I’ thereof according to an embodiment of the present inventive concept. In the following, for the sake of convenience and for the sake of brevity, differences between the semiconductor package 1200 and the semiconductor package 1000 described with reference to Figure 1 FIG. 12 will mainly be described. Figure 4 described with reference to Figure 1 and Figure 2 described with reference to

[0055] With reference to Figure 1 and Figure 4 , the upper substrate 300 can include a first upper substrate pad 314 adjacent to the first surface 300S1 and a second upper substrate pad 324 adjacent to the second surface 300S2. In the present embodiment, the upper substrate 300 can be a redistribution substrate. The upper substrate 300 can include redistribution patterns 342 and 344. The redistribution patterns 342 and 344 can include redistribution lines 342 and redistribution contacts 344 disposed between the redistribution lines 342. The redistribution patterns 342 and 344 can include a conductive material. The first upper substrate pad 314 can be electrically connected to the second upper substrate pad 324 by the redistribution patterns 342 and 344.

[0056] The upper semiconductor chip 400 can be electrically connected to the upper substrate 300 through the upper chip pad 420, the corresponding upper bump 440, and the corresponding second upper substrate pad 324. In the present embodiment, the upper semiconductor chip 400 can be electrically connected to the lower semiconductor chip 200 and / or the corresponding conductive pillar 280 through the first upper substrate pad 314 and the redistribution patterns 342 and 344 connected to the corresponding second upper substrate pad 324. In some embodiments, a plurality of upper semiconductor chips 400 can be electrically connected to each other through the corresponding second upper substrate pads 324 and the redistribution patterns 342 and 344 connected thereto.

[0057] Figure 5 A cross-sectional view of the semiconductor package 1300 taken along the line I-I’ of Figure 1 is shown according to an embodiment of the inventive concept. In the following, for the sake of ease of explanation and for brevity, the differences between the semiconductor package 1300 and the semiconductor package 1000 described with reference to Figure 5 and Figure 1 will mainly be described. Figure 2

[0058] With reference to Figure 1 and Figure 5 , the upper substrate 300 can include a first upper substrate pad 314 adjacent to the first surface 300S1 and a second upper substrate pad 324 adjacent to the second surface 300S2. In the present embodiment, the upper substrate 300 can be a semiconductor chip. The upper substrate 300 can include an upper through electrode 352 penetrating the upper substrate 300, which can include an electrically conductive material. The first upper substrate pad 314 can be electrically connected to the second upper substrate pad 324 through the upper through electrode 352.

[0059] The upper semiconductor chip 400 can be electrically connected to the upper substrate 300 through the upper chip pad 420, the corresponding upper bump 440, and the corresponding second upper substrate pad 324. In the present embodiment, the upper semiconductor chip 400 can be electrically connected to the lower semiconductor chip 200 and / or the corresponding conductive pillar 280 through the first upper substrate pad 314 and the upper through electrode 352 connected to the corresponding second upper substrate pad 324. In some embodiments, a plurality of upper semiconductor chips 400 can be electrically connected to each other through the corresponding second upper substrate pads 324 and the upper through electrodes 352 connected thereto.

[0060] Figure 6 A cross-sectional view of the semiconductor package 1400 taken along the line I-I’ of Figure 1 is shown according to an embodiment of the inventive concept. In the following, for the sake of ease of explanation and for brevity, the differences between the semiconductor package 1400 and the semiconductor package 1000 described with reference to Figure 6 and Figure 1 will mainly be described. Figure 2 ​Differences between the semiconductor packages 1000 described.

[0061] Referring to Figure 1 and Figure 6 , the upper substrate 300 can include a first upper substrate pad 314 adjacent to the first surface 300S1 and a second upper substrate pad 324 adjacent to the second surface 300S2. In the present embodiment, the upper substrate 300 can include an upper redistribution layer 360 disposed adjacent to the first surface 300S1 of the upper substrate 300. The upper redistribution layer 360 can include upper redistribution lines 362 and upper redistribution contacts 364 connected thereto. The upper redistribution lines 362 and the upper redistribution contacts 364 can include an electrically conductive material. The upper redistribution lines 362 and the upper redistribution contacts 364 can be connected to the first upper substrate pad 314.

[0062] In some embodiments, the upper substrate 300 can be a silicon interposer as described with reference to Figure 2 , and can further include the via layer 310 and the metal interconnect layer 320. In this case, the via layer 310 can be disposed between the metal interconnect layer 320 and the upper redistribution layer 360. The upper redistribution lines 362 and the upper redistribution contacts 364 can be connected to the vias 312 in the via layer 310. The first upper substrate pad 314 can be electrically connected to the second upper substrate pad 324 through the upper redistribution lines 362, the upper redistribution contacts 364, the vias 312, and the metal interconnect lines 322.

[0063] In certain embodiments, the upper substrate 300 can include a printed circuit board as described with reference to Figure 3 or a semiconductor chip as described with reference to Figure 5 . In this case, unlike Figure 6 , the first upper substrate pad 314 can be electrically connected to the second upper substrate pad 324 through the upper redistribution lines 362, the upper redistribution contacts 364, and internal interconnect lines (e.g., the metal interconnect lines 322 and the vias 312 of Figure 3 , the internal interconnect lines (not shown) of Figure 5 , or the upper through electrodes 352 disposed in the upper substrate 300.

[0064] The upper semiconductor chip 400 can be electrically connected to the upper substrate 300 through the upper chip pads 420, the corresponding upper bumps 440, and the corresponding second upper substrate pads 324. In the present embodiment, the upper semiconductor chip 400 can be electrically connected to the upper substrate 300 through internal interconnect lines (e.g., the metal interconnect lines 322 and the vias 312 of Figure 2 , the internal interconnect lines (not shown) of Figure 3 , or the upper through electrodes 352 disposed in the upper substrate 300. Figure 5The upper through electrode 352, the upper redistribution line 362, and the upper redistribution contact 364 of the upper semiconductor chip 400 are electrically connected to the lower semiconductor chip 200 and / or the corresponding conductive pillar 280. In addition, the upper semiconductor chip 400 can be electrically connected to the lower substrate 100 through the lower semiconductor chip 200 and / or the corresponding conductive pillar 280. In some embodiments, a plurality of lower semiconductor chips 200 can be electrically connected to each other through the corresponding first lower substrate pads 314, the upper redistribution line 362, and the upper redistribution contact 364 connected to each other.

[0065] Figure 7 A cross-sectional view of the semiconductor package 1500 taken along a line I-I’ according to an embodiment of the inventive concept is shown. Figure 1 In the following, for the sake of explanation and for brevity, the differences between the semiconductor package 1500 and the semiconductor package 1000 described with reference to Figure 7 will mainly be described. Figure 1 and Figure 2 will mainly be described.

[0066] With reference to Figure 1 and Figure 7 , the semiconductor package 1500 can further comprise a lower redistribution layer 370 disposed between the lower substrate 100 and the lower semiconductor chip 200 and between the lower substrate 100 and the plurality of conductive pillars 280. The lower redistribution layer 370 can comprise lower redistribution lines 372 and lower redistribution contacts 374 connected thereto. The lower redistribution lines 372 and the lower redistribution contacts 374 can comprise an electrically conductive material. One surface 370S of the lower redistribution layer 370 can face the top surface 100U of the lower substrate 100. The lower redistribution layer 370 can further comprise redistribution pads 376 adjacent to the one surface 370S of the lower redistribution layer 370. The lower redistribution lines 372 and the lower redistribution contacts 374 can be connected to the redistribution pads 376.

[0067] The lower semiconductor chip 200 and the conductive pillars 280 can be electrically connected to the lower substrate 100 through the lower redistribution layer 370. For example, the conductive pads 230 and the conductive pillars 280 can be connected to the lower redistribution lines 372 and the lower redistribution contacts 374 in the lower redistribution layer 370, the redistribution pads 376 can be connected to the first lower substrate pads 110 of the lower substrate 100. The connection bumps 260 can be disposed between the redistribution pads 376 and the first lower substrate pads 110, and each of the redistribution pads 376 can be connected to a corresponding one of the first lower substrate pads 110 through a corresponding one of the connection bumps 260. The underfill layer 150 can be disposed between the lower substrate 100 and the lower redistribution layer 370, and can fill the space between the connection bumps 260. The lower molding layer 290 can be disposed between the lower redistribution layer 370 and the upper substrate 300, and can fill the space between the lower semiconductor chip 200 and the conductive pillars 280.

[0068] Figure 8 to Figure 11 FIG. 6 shows a cross-sectional view taken along line I-I’ of a method of manufacturing a semiconductor package according to an embodiment of the inventive concepts. For convenience and brevity, descriptions of features that are identical to those described with reference to the semiconductor packages 1000, 1100, 1200, 1300, 1400, and 1500 will be omitted below. Figure 1 Figure 1 to Figure 7

[0069] Figure 1 Figure 8 The upper substrate 300 can be disposed on the first carrier substrate CA1. The upper substrate 300 can have a first surface 300S1 and a second surface 300S2 opposite each other. The upper substrate 300 can be disposed on the first carrier substrate CA1 in such a way that the second surface 300S2 faces the first carrier substrate CA1. The upper substrate 300 can include a first upper substrate pad 314 adjacent to the first surface 300S1 and a second upper substrate pad 324 adjacent to the second surface 300S2. Hereinafter, a case where the upper substrate 300 is a silicon interposer will be described as an example for ease and convenience of explanation. However, embodiments of the inventive concepts are not limited thereto, and in some embodiments, the upper substrate 300 can be a printed circuit board, a redistribution substrate, or a semiconductor chip. Figure 2 Figure 3 Figure 4 Figure 5

[0070] The upper substrate 300 can include a via layer 310 and a metal interconnection layer 320. The metal interconnection layer 320 can include a metal interconnection line 322 disposed adjacent to the second surface 300S2 of the upper substrate 300, and the via layer 310 can include a via 312 connected to the metal interconnection line 322. The via 312 can extend (e.g., vertically extend) from the metal interconnection line 322 toward the first surface 300S1 of the upper substrate 300. In some embodiments, as described with reference to FIG. 5, the upper substrate 300 can further include an upper redistribution layer 360 disposed adjacent to the first surface 300S1 of the upper substrate 300. Figure 6

[0071] ​​​​​​​​​A plurality of conductive pillars 280 can be formed on the first surface 300S1 of the upper substrate 300. A chip mounting region 200R can be defined on the first surface 300S1 of the upper substrate 300 in advance, and the conductive pillars 280 can be formed on the first surface 300S1 of the upper substrate 300 except for the chip mounting region 200R. The conductive pillars 280 can be connected to corresponding respective first upper substrate pads 314, respectively. The conductive pillars 280 can be formed using, for example, an electroplating process. For example, the formation of the conductive pillars 280 can include forming a photoresist pattern having openings that expose regions on the first surface 300S1 of the upper substrate 300 where the conductive pillars 280 are to be formed, forming a seed layer on the photoresist pattern, and forming the conductive pillars 280 by performing an electroplating process on the seed layer. The photoresist pattern can be removed after the conductive pillars 280 are formed.

[0072] Referring to Figure 1 and Figure 9 A lower bump 240 can be formed on the first surface 300S1 of the upper substrate 300 in the chip mounting region 200R. The lower bump 240 can be formed on corresponding respective first upper substrate pads 314, respectively, and can be connected to the corresponding first upper substrate pads 314, respectively.

[0073] A lower semiconductor chip 200 can be mounted in the chip mounting region 200R. The lower semiconductor chip 200 can include lower chip pads 220, and the lower chip pads 220 can be disposed adjacent to one surface 200S of the lower semiconductor chip 200. The lower semiconductor chip 200 can be disposed on the first surface 300S1 of the upper substrate 300 in such a manner that the lower chip pads 220 are in contact with the lower bumps 240, respectively. For example, the lower semiconductor chip 200 can include a lower circuit layer 210 adjacent to one surface 200S of the lower semiconductor chip 200. Alternatively, the lower circuit layer 210 can be disposed adjacent to another surface 200SO of the lower semiconductor chip 200. Conductive pads 230 can be formed on the another surface 200SO of the lower semiconductor chip 200. Figure 9

[0074] In some embodiments, a plurality of lower semiconductor chips 200 can be mounted on the first surface 300S1 of the upper substrate 300, and the plurality of lower semiconductor chips 200 can be spaced apart horizontally from each other. At least one of the plurality of lower semiconductor chips 200 can include a lower through electrode 250 that penetrates therethrough. Each of the lower through electrodes 250 can be connected to a corresponding one of the lower chip pads 220 and a corresponding one of the conductive pads 230.

[0075] ​A lower underfill layer 245 can be formed between one surface 200S of the lower semiconductor chip 200 and the first surface 300S1 of the upper substrate 300, and the lower underfill layer 245 can be formed to fill spaces between the lower bumps 240. A lower molding layer 290 can be formed on the first surface 300S1 of the upper substrate 300, and the lower molding layer 290 can cover the lower semiconductor chip 200, the conductive pillars 280, and the conductive pads 230.

[0076] Referring to Figure 1 and Figure 10 A portion of the lower molding layer 290 can be removed by performing a grinding process on the lower molding layer 290. One surface of each of the conductive pillars 280 and one surface of each of the conductive pads 230 can be exposed by the grinding process. Connection bumps 260 can be formed on the lower molding layer 290. The connection bumps 260 can be formed on and can be connected to the conductive pillars 280 and the conductive pads 230, respectively. In some embodiments, before the connection bumps 260 are formed, a reference Figure 7 The lower redistribution layer 370 described above can be formed on the lower molding layer 290. In this case, the connection bumps 260 can be formed on and can be connected to the redistribution pads 376 of the lower redistribution layer 370.

[0077] Referring to Figure 1 and Figure 11 The aforementioned stack structure formed on the first carrier substrate CA1 can be mounted on the lower substrate 100. For example, the lower substrate 100 can be a printed circuit board (PCB). The lower substrate 100 can include first lower substrate pads 110 adjacent to a top surface 100U of the lower substrate 100 and second lower substrate pads 120 adjacent to a bottom surface 100L of the lower substrate 100. The aforementioned stack structure can be disposed on the top surface 100U of the lower substrate 100 in such a manner that the connection bumps 260 are in contact with the respective first lower substrate pads 110.

[0078] An underfill layer 150 can be formed between the lower substrate 100 and the lower molding layer 290, and the underfill layer 150 can be formed to fill spaces between the connection bumps 260. External terminals 130 can be disposed on the bottom surface 100L of the lower substrate 100, and the external terminals 130 can be connected to the second lower substrate pads 120, respectively. The first carrier substrate CA1 can be removed after the aforementioned stack structure is mounted on the lower substrate 100.

[0079] Referring again to Figure 1 and Figure 2Upper bumps 440 can be formed on the second surface 300S2 of the upper substrate 300. The upper bumps 440 can be formed on the corresponding second upper substrate pads 324 respectively, and can be connected to the corresponding second upper substrate pads 324 respectively.

[0080] A semiconductor chip 400 can be mounted on the second surface 300S2 of the upper substrate 300. The upper semiconductor chip 400 may include upper chip pads 420, and the upper chip pads 420 may be disposed adjacent to one surface 400S of the upper semiconductor chip 400. The upper semiconductor chip 400 can be disposed on the second surface 300S2 of the upper substrate 300 in such a manner that the upper chip pads 420 respectively contact the upper bumps 440. For example, the upper semiconductor chip 400 may include an upper circuit layer 410 adjacent to one surface 400S of the upper semiconductor chip 400.

[0081] The upper semiconductor chip 400 may be vertically stacked with at least a portion of the lower semiconductor chip 200 and / or at least a portion of the multiple conductive pillars 280. In some embodiments, multiple upper semiconductor chips 400 may be mounted on the second surface 300S2 of the upper substrate 300, and the multiple upper semiconductor chips 400 may be horizontally spaced apart from each other.

[0082] An upper bottom filler layer 445 can be formed between a surface 400S of the upper semiconductor chip 400 and a second surface 300S2 of the upper substrate 300, and the upper bottom filler layer 445 can be formed to fill the space between the upper bumps 440.

[0083] Figure 12 An embodiment of the concept of the present invention is shown along Figure 1 The image shows a cross-sectional view of the semiconductor package 1600 taken along line I-I'. In the following text, for ease of explanation and for brevity, the main focus will be on describing... Figure 12 Semiconductor package 1600 and reference Figure 1 and Figure 2 The differences between the described semiconductor packages 1000.

[0084] Reference Figure 1 and Figure 12 The lower chip pad 220 of the lower semiconductor chip 200 can be directly bonded to the corresponding first upper substrate pad 314 of the upper substrate 300. The lower chip pad 220 can contact the corresponding first upper substrate pad 314. In this embodiment, references can be omitted. Figure 1 and Figure 2The lower bumps 240 and the lower underfill layer 245 are described. In addition, the upper chip pads 420 of the upper semiconductor chip 400 can be directly bonded to the corresponding second upper substrate pads 324 of the upper substrate 300. The upper chip pads 420 can be in contact with the corresponding second upper substrate pads 324. In the present embodiment, the upper bumps 440 and the upper underfill layer 445 described with reference to Figure 1 and Figure 2 may be omitted.

[0085] Figure 13 A cross-sectional view taken along line I-I' of a method of manufacturing a semiconductor package according to an embodiment of the present inventive concept is shown. Figure 1 In the following, for the sake of convenience and brevity, the differences between the present embodiment and the embodiments described above with reference to Figure 12 and Figure 13 will mainly be described. Figure 8 to Figure 11

[0086] First, the upper substrate 300 can be provided on the first carrier substrate CA1, and a plurality of conductive pillars 280 can be formed on the first surface 300S1 of the upper substrate 300 except for the chip mounting region 200R, as described with reference to Figure 1 and Figure 8 The lower semiconductor chip 200 can be mounted in the chip mounting region 200R, with reference to

[0087] The lower semiconductor chip 200 can be mounted in the chip mounting region 200R, with reference to Figure 1 and Figure 13 In the present embodiment, the lower semiconductor chip 200 can be provided on the first surface 300S1 of the upper substrate 300 in such a way that the lower chip pads 220 are in direct contact with the corresponding first upper substrate pads 314 of the upper substrate 300. The lower chip pads 220 of the lower semiconductor chip 200 can be directly bonded to the corresponding first upper substrate pads 314 by a thermal treatment process. A lower molding layer 290 can be formed on the first surface 300S1 of the upper substrate 300, and the lower molding layer 290 can cover the lower semiconductor chip 200, the conductive pillars 280, and the conductive pads 230. Thereafter, a portion of the lower molding layer 290 can be removed by performing a grinding process on the lower molding layer 290, as described with reference to Figure 1 and Figure 10 A surface of each of the conductive pillars 280 and a surface of each of the conductive pads 230 can be exposed by the grinding process. Connection bumps 260 can be formed on the conductive pillars 280 and the conductive pads 230, respectively.

[0088] Again with reference to Figure 1 and Figure 12 ​The aforementioned stack structure formed on the first carrier substrate CA1 can be mounted on the lower substrate 100. The first carrier substrate CA1 can be removed after the aforementioned stack structure is mounted on the lower substrate 100.

[0089] The upper semiconductor chip 400 can be mounted on the second surface 300S2 of the upper substrate 300. In the present embodiment, the upper semiconductor chip 400 can be disposed on the second surface 300S2 of the upper substrate 300 in such a way that the upper chip pads 420 are in direct contact with the corresponding second upper substrate pads 324 of the upper substrate 300. The upper chip pads 420 of the upper semiconductor chip 400 can be directly bonded to the corresponding second upper substrate pads 324 by a thermal treatment process.

[0090] Figure 14 A cross-sectional view of the semiconductor package 1700 taken along the line I-I’ is shown according to an embodiment of the inventive concept. In the following, for the sake of convenience and for brevity, the differences between the semiconductor package 1700 and the semiconductor package 1000 described with reference to Figure 1 and Figure 14 will mainly be described. Figure 1 and Figure 2 will mainly be described.

[0091] With reference to Figure 1 and Figure 14 , the semiconductor package 1700 can further comprise an upper molding layer 490 disposed on the second surface 300S2 of the upper substrate 300. The upper molding layer 490 can cover the upper semiconductor chip 400. The upper molding layer 490 can comprise an insulating material (e.g. an epoxy molding compound).

[0092] Figure 15 A cross-sectional view of the method of manufacturing a semiconductor package taken along the line I-I’ is shown according to an embodiment of the inventive concept. In the following, for the sake of convenience and for brevity, the differences between the present embodiment and the embodiments described above with reference to Figure 1 and Figure 14 will mainly be described. Figure 15 Figure 8 to Figure 11 With reference to and

[0093] , the stack structure of Figure 1 can be disposed on the second carrier substrate CA2. The first carrier substrate CA1 can be removed after the stack structure is disposed on the second carrier substrate CA2. Figure 15 Figure 10

[0094] ​​Subsequently, upper bumps 440 can be formed on the respective second upper substrate pads 324, respectively, and the upper semiconductor chip 400 can be mounted on the second surface 300S2 of the upper substrate 300. The upper semiconductor chip 400 can be disposed on the second surface 300S2 of the upper substrate 300 in such a manner that the upper chip pads 420 are in contact with the upper bumps 440, respectively. An upper underfill layer 445 can be formed between one surface 400S of the upper semiconductor chip 400 and the second surface 300S2 of the upper substrate 300, and the upper underfill layer 445 can be formed to fill spaces between the upper bumps 440. In the present embodiment, an upper molding layer 490 can be formed on the second surface 300S2 of the upper substrate 300 to cover the upper semiconductor chip 400.

[0095] Referring again to Figure 1 and Figure 14 , the stack structure formed on the second carrier substrate CA2 can be mounted on the lower substrate 100. The second carrier substrate CA2 can be removed first. Subsequently, the stack structure can be disposed on the top surface 100U of the lower substrate 100 in such a manner that the connection bumps 260 are in contact with the respective first lower substrate pads 110, respectively. An underfill layer 150 can be formed between the lower substrate 100 and the lower molding layer 290, and the underfill layer 150 can be formed to fill spaces between the connection bumps 260.

[0096] Figure 16 A cross-sectional view of a semiconductor package 1800 taken along a line I-I' of an embodiment according to the inventive concept is illustrated. Hereinafter, for ease of explanation and for the sake of brevity, differences between the semiconductor package 1800 and the semiconductor package 1000 described with reference to Figure 1 will mainly be described. Figure 16 Figure 1 and Figure 2 described with reference to

[0097] Referring to Figure 1 and Figure 16 , the semiconductor package 1800 can include a lower substrate 100, an upper substrate 300 on the lower substrate 100, a lower semiconductor chip 200 disposed between the lower substrate 100 and the upper substrate 300, an intermediate substrate 500 disposed between the lower substrate 100 and the upper substrate 300 at at least one side of the lower semiconductor chip 200, and an upper semiconductor chip 400 disposed on the upper substrate 300.

[0098] ​The middle substrate 500 can be disposed on and can be connected to the first surface 300S1 of the upper substrate 300. One surface 500S of the middle substrate 500 can face the first surface 300S1 of the upper substrate 300. The middle substrate 500 can include middle substrate pads 520 adjacent to the one surface 500S of the middle substrate 500. The middle substrate pads 520 can include a conductive material. The middle substrate pads 520 can be connected to corresponding individual first upper substrate pads 314. In some embodiments, the lower bumps 240 can be disposed between the middle substrate pads 520 and the corresponding first upper substrate pads 314. Each of the middle substrate pads 520 can be connected to a corresponding one of the first upper substrate pads 314 through a corresponding one of the lower bumps 240. The underfill layer 245 can be disposed between the one surface 500S of the middle substrate 500 and the first surface 300S1 of the upper substrate 300 and can cover the lower bumps 240. The underfill layer 245 can be disposed locally on the one surface 500S of the middle substrate 500 and can fill spaces between the lower bumps 240.

[0099] Another surface 500SO of the middle substrate 500 can face the top surface 100U of the lower substrate 100. The conductive pads 230 can also be disposed on the other surface 500SO of the middle substrate 500.

[0100] In some embodiments, the middle substrate 500 can be a semiconductor chip. In this case, the middle substrate 500 can include a middle circuit layer 510 adjacent to the one surface 500S of the middle substrate 500. The middle circuit layer 510 can include an integrated circuit. Alternatively, the middle circuit layer 510 can be disposed adjacent to the other surface 500SO of the middle substrate 500. The middle substrate 500 can include middle through electrodes 550 that penetrate the middle substrate 500, and the middle through electrodes 550 can include a conductive material. Each of the middle through electrodes 550 can be connected to a corresponding one of the middle substrate pads 520 and a corresponding one of the conductive pads 230. The conductive pads 230 can be connected to corresponding first lower substrate pads 110 of the lower substrate 100. In some embodiments, each of the conductive pads 230 can be connected to a corresponding one of the first lower substrate pads 110 through a corresponding one of the connection bumps 260. Figure 16 Alternatively, the middle circuit layer 510 can be disposed adjacent to the other surface 500SO of the middle substrate 500. The middle substrate 500 can include middle through electrodes 550 that penetrate the middle substrate 500, and the middle through electrodes 550 can include a conductive material. Each of the middle through electrodes 550 can be connected to a corresponding one of the middle substrate pads 520 and a corresponding one of the conductive pads 230. The conductive pads 230 can be connected to corresponding first lower substrate pads 110 of the lower substrate 100. In some embodiments, each of the conductive pads 230 can be connected to a corresponding one of the first lower substrate pads 110 through a corresponding one of the connection bumps 260.

[0101] The middle substrate 500 can be electrically connected to the upper substrate 300 through the middle substrate pads 520, the corresponding lower bumps 240, and the corresponding first upper substrate pads 314. The middle substrate 500 can be electrically connected to the lower substrate 100 through the middle through electrodes 550, the corresponding conductive pads 230, the corresponding connection bumps 260, and the corresponding first lower substrate pads 110.

[0102] A lower molding layer 290 can be disposed between the lower substrate 100 and the upper substrate 300, and can fill a space between the lower semiconductor chip 200 and the middle substrate 500. The lower molding layer 290 can extend onto another surface 200SO of the lower semiconductor chip 200 and another surface 500SO of the middle substrate 500 to cover sidewalls of the conductive pads 230.

[0103] According to the present embodiment, the upper semiconductor chip 400 can be electrically connected to the lower semiconductor chip 200 and / or the middle substrate 500 through the upper substrate 300, and can be electrically connected to the lower substrate 100 through the lower semiconductor chip 200 and / or the middle substrate 500.

[0104] Figure 17 A cross-sectional view of a semiconductor package 1900 taken along a line I-I' of FIG. 19A according to an embodiment of the present inventive concept is illustrated. Hereinafter, for convenience of explanation and for brevity, differences between the semiconductor package 1900 of FIG. 19A and the semiconductor package 1000 described with reference to FIGS. 1A to 1C will be mainly described. Figure 1 Figure 17 Figure 1 Figure 2

[0105] Referring to FIGS. 19A and 19B, the semiconductor package 1900 can include a lower substrate 100, an upper substrate 300 on the lower substrate 100, a lower semiconductor chip 200 disposed between the lower substrate 100 and the upper substrate 300, a middle substrate 500 disposed between the lower substrate 100 and the upper substrate 300 at at least one side of the lower semiconductor chip 200, and an upper semiconductor chip 400 disposed on the upper substrate 300. Figure 1 Figure 17 The middle substrate 500 can be disposed on and connected to a first surface 300S1 of the upper substrate 300. One surface 500S of the middle substrate 500 can face the first surface 300S1 of the upper substrate 300. The middle substrate 500 can include a middle substrate pad 520 adjacent to the one surface 500S of the middle substrate 500. Another surface 500SO of the middle substrate 500 can face a top surface 100U of the lower substrate 100. The conductive pads 230 can also be disposed on the another surface 500SO of the middle substrate 500.

[0106] The middle substrate 500 can be disposed on and connected to a first surface 300S1 of the upper substrate 300. One surface 500S of the middle substrate 500 can face the first surface 300S1 of the upper substrate 300. The middle substrate 500 can include a middle substrate pad 520 adjacent to the one surface 500S of the middle substrate 500. Another surface 500SO of the middle substrate 500 can face a top surface 100U of the lower substrate 100. The conductive pads 230 can also be disposed on the another surface 500SO of the middle substrate 500.

[0107] ​​​​​In some embodiments, the middle substrate 500 can be an interposer, a printed circuit board, or a redistribution substrate. In this case, the middle substrate pads 520 can be electrically connected to the corresponding individual conductive pads 230 by internal interconnection lines (shown by dashed lines) in the middle substrate 500. Except for the above-mentioned differences, other components and features of the semiconductor package 1900 according to the present embodiments can be substantially the same as those of the semiconductor package 1800 described with reference to Figure 1 and Figure 16 .

[0108] Figure 18 A cross-sectional view of a semiconductor package 2000 taken along line I-I’ of FIG. 20 is shown according to an embodiment of the present inventive concept. Hereinafter, for ease of explanation and for the sake of brevity, differences between the semiconductor package 2000 of FIG. 20 and the semiconductor package 1000 described with reference to Figure 1 and Figure 18 will mainly be described. Figure 1 Figure 2 Referring to and

[0109] , the semiconductor package 2000 can include a lower structure LS, an upper substrate 300 on the lower structure LS, a lower semiconductor chip 200 disposed between the lower structure LS and the upper substrate 300, a plurality of conductive pillars 280 disposed between the lower structure LS and the upper substrate 300 at at least one side of the lower semiconductor chip 200, and an upper semiconductor chip 400 disposed on the upper substrate 300. Figure 1 Figure 18 The lower structure LS can include a lower substrate 100 and a semiconductor chip 700 on the lower substrate 100. The semiconductor chip 700 can be disposed between the lower substrate 100 and the upper substrate 300. The lower semiconductor chip 200 and the plurality of conductive pillars 280 can be disposed between the semiconductor chip 700 and the upper substrate 300.

[0110] One surface 700S of the semiconductor chip 700 can face a first surface 300S1 of the upper substrate 300, and another surface 700SO of the semiconductor chip 700 can face a top surface 100U of the lower substrate 100. The semiconductor chip 700 can include a chip pad 720 adjacent to the one surface 700S of the semiconductor chip 700, and the chip pad 720 can include a conductive material. The semiconductor chip 700 can include a through electrode 750 penetrating the semiconductor chip 700, and the through electrode 750 can include a conductive material. The through electrode 750 can be connected to the chip pad 720.

[0111] One surface 700S of the semiconductor chip 700 can face a first surface 300S1 of the upper substrate 300, and another surface 700SO of the semiconductor chip 700 can face a top surface 100U of the lower substrate 100. The semiconductor chip 700 can include a chip pad 720 adjacent to the one surface 700S of the semiconductor chip 700, and the chip pad 720 can include a conductive material. The semiconductor chip 700 can include a through electrode 750 penetrating the semiconductor chip 700, and the through electrode 750 can include a conductive material. The through electrode 750 can be connected to the chip pad 720.

[0112] ​The connection bumps 260 can be disposed between the conductive pads 230 and the corresponding chip pads 720 and between the conductive pillars 280 and the corresponding chip pads 720. Each of the conductive pads 230 and the conductive pillars 280 can be connected to the corresponding chip pad 720 through the corresponding connection bump 260. The lower semiconductor chip 200 can be electrically connected to the semiconductor chip 700 through the corresponding conductive pad 230, the corresponding connection bump 260, and the corresponding chip pad 720. The conductive pillars 280 can be electrically connected to the semiconductor chip 700 through the corresponding connection bump 260 and the corresponding chip pad 720.

[0113] The lower molding layer 290 can be disposed between the semiconductor chip 700 and the upper substrate 300, and can fill a space between the lower semiconductor chip 200 and the conductive pillars 280. The underfill layer 150 can be disposed between the semiconductor chip 700 and the lower molding layer 290, and can fill a space between the connection bumps 260.

[0114] The additional connection bumps 760 can be disposed between the semiconductor chip 700 and the lower substrate 100. The additional connection bumps 760 can be disposed between the through electrodes 750 of the semiconductor chip 700 and the first lower substrate pads 110 of the lower substrate 100. Each of the through electrodes 750 of the semiconductor chip 700 can be connected to a corresponding one of the first lower substrate pads 110 through a corresponding one of the additional connection bumps 760. The semiconductor chip 700 can be electrically connected to the lower substrate 100 through the through electrodes 750, the additional connection bumps 760, and the first lower substrate pads 110. Each of the additional connection bumps 760 can include a conductive material, and can have at least one of a solder ball shape, a bump shape, and a pillar shape.

[0115] The additional underfill layer 770 can be disposed between the semiconductor chip 700 and the lower substrate 100, and can fill a space between the additional connection bumps 760. The additional underfill layer 770 can include an insulating polymer material such as an epoxy resin.

[0116] Figure 19 A cross-sectional view of a semiconductor package 2100 taken along a line I-I' of an embodiment according to the inventive concept is illustrated. Hereinafter, for ease of explanation and for the sake of brevity, differences between the semiconductor package 2100 of Figure 1 and the semiconductor package 1000 described with reference to Figure 19 and Figure 1 will mainly be described. Figure 2

[0117] Figure 1 Figure 19 ​​​The semiconductor package 2100 can include a lower structure LS, an upper substrate 300 on the lower structure LS, a lower semiconductor chip 200 disposed between the lower structure LS and the upper substrate 300, a plurality of conductive pillars 280 disposed between the lower structure LS and the upper substrate 300 at at least one side of the lower semiconductor chip 200, and an upper semiconductor chip 400 disposed on the upper substrate 300.

[0118] The lower structure LS can include a lower semiconductor package. The lower structure LS can include a first substrate 800 and a semiconductor chip 820 on the first substrate 800. The first substrate 800 can be a printed circuit board or a redistribution layer. The first substrate 800 can include first substrate pads 810. The first substrate pads 810 can include a conductive material. The semiconductor chip 820 can include chip pads 822 disposed on a bottom surface thereof. Connection portions 824 can be disposed between the first substrate 800 and the semiconductor chip 820 and can be connected to the chip pads 822, respectively. The connection portions 824 can be connected to corresponding individual first substrate pads 810. The chip pads 822 and the connection portions 824 can include a conductive material. Each of the connection portions 824 can have at least one of a solder ball shape, a bump shape, and a pillar shape. The semiconductor chip 820 can include an integrated circuit (not shown) and the integrated circuit can be adjacent to the bottom surface of the semiconductor chip 820. The semiconductor chip 820 can be a logic chip or a memory chip.

[0119] The lower structure LS can include a solder structure 830 on the first substrate 800. The solder structure 830 can be laterally spaced apart from the semiconductor chip 820. The solder structure 830 can be connected to corresponding individual first substrate pads 810. The solder structure 830 can include a conductive material such as, for example, tin, lead, silver, or alloys thereof. Each of the solder structures 830 can be electrically connected to an external terminal or the semiconductor chip 820 through internal interconnection lines (not shown) in the first substrate 800.

[0120] The lower structure LS can include a second substrate 850 disposed on the semiconductor chip 820. For example, the second substrate 850 can be an interposer substrate. The second substrate 850 can include first pads 852 disposed on a bottom surface of the second substrate 850 and second pads 854 disposed on a top surface of the second substrate 850. Interconnection lines (not shown) can be disposed in the second substrate 850 to electrically connect the first pads 852 to the second pads 854. The first pads 852 and the second pads 854 can include a conductive material (for example, a metal such as copper or aluminum). The solder structure 830 can be connected to the first pads 852. The second substrate 850 can be electrically connected to the first substrate 800 and the semiconductor chip 820 through the solder structure 830.

[0121] The lower structure LS can include a molding layer 840 between the first substrate 800 and the second substrate 850. The molding layer 840 can cover the semiconductor chip 820 and the solder structure 830. In some embodiments, the molding layer 840 can extend between the first substrate 800 and the semiconductor chip 820 to seal the connection portion 824. The molding layer 840 can include an insulating material (e.g., an epoxy molding compound).

[0122] The connection bumps 260 can be disposed between the conductive pads 230 and the second substrate 850 and between the conductive pillars 280 and the second substrate 850. Each of the conductive pads 230 and the conductive pillars 280 can be connected to a corresponding second pad 854 of the second substrate 850 through a corresponding connection bump 260. The lower semiconductor chip 200 can be electrically connected to the lower structure LS (e.g., a lower semiconductor package) through a corresponding conductive pad 230, a corresponding connection bump 260, and a corresponding second pad 854. The conductive pillars 280 can be electrically connected to the lower structure LS (e.g., a lower semiconductor package) through a corresponding connection bump 260 and a corresponding second pad 854.

[0123] The lower molding layer 290 can be disposed between the lower structure LS and the upper substrate 300, and can fill a space between the lower semiconductor chip 200 and the conductive pillars 280. The underfill layer 150 can be disposed between the lower structure LS and the lower molding layer 290, and can fill a space between the connection bumps 260.

[0124] Figure 20 A cross-sectional view of a semiconductor package 2200 taken along a line I-I’ of FIG. 22A is illustrated according to an embodiment of the present disclosure. Hereinafter, for convenience of explanation and for brevity, differences between the semiconductor package 2200 of FIG. 22A and the semiconductor package 1000 described with reference to FIGS. 1A to 1C will be mainly described. Figure 1 Figure 20 Hereinafter, for convenience of explanation and for brevity, differences between the semiconductor package 2200 of FIG. 22A and the semiconductor package 1000 described with reference to FIGS. 1A to 1C will be mainly described. Figure 1 Figure 2

[0125] Figure 1 Figure 20 ​​​​​The semiconductor package 2200 can further include a heat dissipation structure 920 disposed on the lower substrate 100. The heat dissipation structure 920 can be disposed on the top surface 100U of the lower substrate 100, and can cover the upper substrate 300, the lower semiconductor chip 200, the plurality of conductive pillars 280, and the upper semiconductor chip 400. The heat dissipation structure 920 can include a thermally conductive material. The thermally conductive material can include a metal (e.g., copper and / or aluminum) or a carbon-containing material (e.g., graphene, graphite, and / or carbon nanotube). For example, the heat dissipation structure 920 can include a single metal layer or a plurality of stacked metal layers. As other examples, the heat dissipation structure 920 can include a heat sink or a heat pipe. As still other examples, the heat dissipation structure 920 can include a water cooling configuration.

[0126] The semiconductor package 2200 can further include a thermally conductive layer 910 disposed on the upper semiconductor chip 400. The thermally conductive layer 910 can be disposed between the upper semiconductor chip 400 and the heat dissipation structure 920. The thermally conductive layer 910 can include a thermal interface material (TIM). For example, the thermal interface material (TIM) can include a polymer and thermally conductive particles. The thermally conductive particles can be dispersed in the polymer. Heat generated from the upper semiconductor chip 400 can be transferred through the thermally conductive layer 910 to the heat dissipation structure 920.

[0127] According to embodiments of the inventive concept, the vertically and horizontally stacked plurality of semiconductor chips 200 and 400 can be easily connected to each other by the upper substrate 300, and can be easily connected to the lower substrate 100 or the lower structure LS by the plurality of conductive pillars 280 or the intermediate substrate 500. As a result, the plurality of semiconductor chips 200 and 400 can be easily mounted on the lower substrate 100 or the lower structure LS, and thus, the integration density of the semiconductor package can be easily improved and increased.

[0128] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those having ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept. Therefore, it is to be understood that the foregoing embodiments are by way of example only, and are not intended to be limiting. Accordingly, the scope of the inventive concept is to be interpreted only in accordance with the broadest permissible interpretation of the following claims and equivalents thereto, and should not be limited or restricted to the foregoing description and accompanying drawings.

Claims

1. A semiconductor package comprising: an upper substrate having a first surface and a second surface opposite to each other; a lower semiconductor die disposed on the first surface of the upper substrate; a plurality of conductive pillars disposed on the first surface of the upper substrate at least on one side of the lower semiconductor die; and an upper semiconductor die disposed on the second surface of the upper substrate, wherein the lower semiconductor die and the plurality of conductive pillars are connected to the first surface of the upper substrate, wherein the upper semiconductor die is connected to the second surface of the upper substrate, wherein the upper substrate is a silicon interposer substrate, and comprises: a via layer spaced apart from the second surface of the upper substrate, a metal interconnect layer disposed adjacent to the second surface of the upper substrate and interposed between the via layer and the second surface of the upper substrate, and a first upper substrate pad adjacent to the first surface and a second upper substrate pad adjacent to the second surface, the first upper substrate pad electrically connected to the second upper substrate pad through a via in the via layer and a metal interconnect line in the metal interconnect layer, and wherein the semiconductor package further comprises: a lower substrate spaced apart from the first surface of the upper substrate, wherein the lower semiconductor die and the plurality of conductive pillars are interposed between the lower substrate and the upper substrate; and a lower redistribution layer between the lower substrate and the lower semiconductor die and between the lower substrate and the plurality of conductive pillars, wherein the lower semiconductor die and the plurality of conductive pillars are connected to the lower redistribution layer. the upper semiconductor die is one of a plurality of upper semiconductor dies laterally spaced apart from each other on the second surface of the upper substrate, and 2. The semiconductor package of claim 1, wherein, wherein each of the plurality of upper semiconductor dies is connected to the second surface of the upper substrate. the lower semiconductor die is one of a plurality of lower semiconductor dies laterally spaced apart from each other on the first surface of the upper substrate, and 3. The semiconductor package of claim 1, wherein, wherein each of the plurality of lower semiconductor dies is connected to the first surface of the upper substrate. at least one of the plurality of lower semiconductor dies comprises at least one lower through via electrode penetrating the at least one lower semiconductor die.

4. The semiconductor package of claim 3, wherein, the first surface of the upper substrate faces a top surface of the lower substrate, and 5. The semiconductor package of claim 1, wherein, wherein the lower semiconductor die and the plurality of conductive pillars are between the first surface of the upper substrate and the top surface of the lower substrate. the upper semiconductor die is connected to the metal interconnect line.

6. The semiconductor package of claim 1, wherein, the via is connected to the metal interconnect line, and 7. The semiconductor package of claim 6, wherein, wherein the via extends vertically from the metal interconnect line towards the first surface of the upper substrate.

8. The semiconductor package of claim 1, further comprising a lower molding layer on the first surface of the upper substrate, the lower molding layer covering the lower semiconductor die and the plurality of conductive pillars.

9. The semiconductor package of claim 8, further comprising an upper molding layer on the second surface of the upper substrate, the upper molding layer covering the upper semiconductor die. the upper substrate comprises an upper redistribution layer disposed adjacent to the first surface, and 10. The semiconductor package of claim 1, wherein, wherein the upper semiconductor die is connected to the upper redistribution layer. wherein the lower semiconductor chips and the plurality of conductive pillars are connected to the upper redistribution layer.

11. The semiconductor package of claim 1, further comprising: a lower structure spaced apart from the first surface of the upper substrate, wherein the lower semiconductor chips and the plurality of conductive pillars are interposed between the lower structure and the upper substrate, wherein the plurality of conductive pillars are connected to the lower structure, and wherein the lower structure comprises a printed circuit board, a semiconductor chip, or a lower semiconductor package.

12. The semiconductor package of claim 11, further comprising a heat dissipation structure on the lower structure, the heat dissipation structure covering the upper semiconductor chips, the upper substrate, the lower semiconductor chips, and the plurality of conductive pillars.

13. A semiconductor package, comprising: an upper substrate having a first surface and a second surface opposite to each other; a plurality of lower semiconductor chips on the first surface of the upper substrate and laterally spaced apart from each other; a plurality of conductive pillars on the first surface of the upper substrate and laterally spaced apart from the plurality of lower semiconductor chips; and a plurality of upper semiconductor chips on the second surface of the upper substrate and laterally spaced apart from each other, wherein the upper substrate is a silicon interposer substrate and comprises: a via layer spaced apart from the second surface of the upper substrate, a metal interconnect layer disposed adjacent to the second surface of the upper substrate and interposed between the via layer and the second surface of the upper substrate, and a first upper substrate pad adjacent to the first surface and a second upper substrate pad adjacent to the second surface, the first upper substrate pad electrically connected to the second upper substrate pad through a via in the via layer and a metal interconnect line in the metal interconnect layer, wherein the semiconductor package further comprises: a lower substrate spaced apart from the first surface of the upper substrate, wherein the lower semiconductor chips and the plurality of conductive pillars are interposed between the lower substrate and the upper substrate; and a lower redistribution layer between the lower substrate and the lower semiconductor chips and between the lower substrate and the plurality of conductive pillars, wherein the lower semiconductor chips and the plurality of conductive pillars are connected to the lower redistribution layer, wherein each of the plurality of lower semiconductor chips comprises respective lower chip pads connected to respective ones of the first upper substrate pads, and the plurality of conductive pillars are connected to respective ones of the first upper substrate pads, and 14. The semiconductor package of claim 13, wherein, wherein each of the plurality of upper semiconductor chips comprises respective upper chip pads connected to respective ones of the second upper substrate pads. each of the plurality of upper semiconductor chips comprises a first surface facing the second surface of the upper substrate, and the upper chip pads are adjacent to the first surfaces of the plurality of upper semiconductor chips, wherein each of the plurality of upper semiconductor chips comprises an upper circuit layer adjacent to the first surfaces of the plurality of upper semiconductor chips.

15. The semiconductor package of claim 14, wherein, each of the plurality of lower semiconductor chips includes a first surface facing the first surface of the upper substrate, and the lower chip pads are adjacent to the first surface of the plurality of lower semiconductor chips, wherein at least one of the plurality of lower semiconductor chips includes a lower circuit layer adjacent to the first surface of the at least one of the plurality of lower semiconductor chips.

16. The semiconductor package of claim 13, further comprising: a lower structure spaced apart from the first surface of the upper substrate and including pads, wherein the plurality of lower semiconductor chips and the plurality of conductive pillars are interposed between the lower structure and the upper substrate, wherein the plurality of conductive pillars are connected to respective ones of the pads of the lower structure, and wherein the lower structure includes a printed circuit board, a semiconductor chip, or a lower semiconductor package.

17. The semiconductor package of claim 16, further comprising a heat spreading structure on the lower structure, the heat spreading structure covering the plurality of upper semiconductor chips, the upper substrate, the plurality of lower semiconductor chips, and the plurality of conductive pillars.

18. The semiconductor package of claim 13, wherein, the via is connected to the metal interconnect line and extends from the metal interconnect line toward the first surface of the upper substrate, wherein the upper semiconductor chip is connected to the metal interconnect line through the upper chip pad and the second upper substrate pad.

19. A semiconductor package, comprising: an upper substrate having a first surface and a second surface opposite to each other; a lower semiconductor chip disposed on the first surface of the upper substrate; an intermediate substrate disposed on the first surface of the upper substrate at least on one side of the lower semiconductor chip; and an upper semiconductor chip disposed on the second surface of the upper substrate, wherein the lower semiconductor chip and the intermediate substrate are connected to the first surface of the upper substrate, wherein the upper semiconductor chip is connected to the second surface of the upper substrate, wherein the intermediate substrate is a semiconductor chip, a printed circuit board, an interposer substrate, or a redistribution substrate, and the intermediate substrate includes a through electrode penetrating the intermediate substrate, and wherein the upper substrate is a silicon interposer substrate and includes: a via layer spaced apart from the second surface of the upper substrate, a metal interconnect layer disposed adjacent to the second surface of the upper substrate and interposed between the via layer and the second surface of the upper substrate, and a first upper substrate pad adjacent to the first surface and a second upper substrate pad adjacent to the second surface, the first upper substrate pad being electrically connected to the second upper substrate pad through a via in the via layer and a metal interconnect line in the metal interconnect layer. ​

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