A charge pump output node discharge circuit and method of implementation

Abstract

The application discloses a charge pump output node discharging circuit and a realization method, and belongs to the technical field of integrated circuits. The charge pump output node discharging circuit comprises a first NMOS tube connected with a high-voltage node of a charge pump, a second NMOS tube connected with the first NMOS tube, a first PMOS tube connected with the second NMOS tube, and a third NMOS tube connected with the first PMOS tube and used for controlling a gate voltage of the first NMOS tube. The third NMOS tube determines the highest gate voltage of the first NMOS tube. The gate electrode of the third NMOS tube is connected with the drain electrode, and the gate electrode and the drain electrode are connected with one end of a resistor and a capacitor. The device parameters of the first NMOS tube, the second NMOS tube, the resistor and the capacitor determine the discharging speed and the maximum voltage difference borne by the drain-source, the gate-drain and the gate-source of the first NMOS tube and the second NMOS tube during discharging. The charge pump output node discharging circuit has the advantages of simple structure and low production cost.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a technology of discharging a high-voltage node of a charge pump by a low-voltage device inside an integrated circuit. BACKGROUND

[0002] If a level higher than an input power supply voltage is needed inside an integrated circuit, a charge pump is usually used for bootstrap, such as driving of a gate of an upper tube of an H-bridge output structure. However, when the power supply needs to be turned off or the gate drive needs to be exited, the output node of the charge pump needs to be discharged to the ground. An NMOS tube is usually used to discharge the output node of the charge pump to the ground. However, the voltage of the output node of the charge pump is higher than the voltage resistance of other devices in the integrated circuit, and thus an extra high-voltage device needs to be used. However, in most standard low-voltage processes, there is no high-voltage device, or an extra photolithography needs to be added to manufacture the high-voltage device, which increases the production cost. Therefore, a new charge pump output node discharge circuit needs to be developed to solve the existing problems. SUMMARY

[0003] The present application aims to provide a charge pump output node discharge circuit to solve the problem of high production cost of the charge pump output node discharge circuit.

[0004] To achieve the above-mentioned purpose, the present application provides the following technical scheme: a charge pump output node discharge circuit, comprising a first NMOS tube connected with a high-voltage node of a charge pump, a second NMOS tube connected with the first NMOS tube, a first PMOS tube connected with the second NMOS tube, and a third NMOS tube connected with the first PMOS tube and controlling a gate voltage of the first NMOS tube; the parameter of the third NMOS tube determines the highest gate voltage of the first NMOS tube.

[0005] The gate and the drain of the third NMOS tube are connected, and are connected with one end of a resistor and a capacitor, the device parameters of the first NMOS tube, the second NMOS tube, the resistor and the capacitor determine the discharging speed and the maximum voltage difference borne by the first NMOS tube, the second NMOS tube, the resistor and the capacitor when discharging.

[0006] Preferably, the source of the first NMOS tube is connected with an end of a substrate, and is connected with the drain of the second NMOS tube and the drain of the first PMOS tube, and the drain of the first NMOS tube is connected with the high-voltage node of the charge pump.

[0007] Preferably, the gate of the first NMOS tube is connected with the gate and the drain of the third NMOS tube, and is connected with the upper plate of the capacitor and one end of the resistor to form a first node, and the other end of the resistor is connected with a system power supply voltage.

[0008] Preferably, the second NMOS gate is connected with the first PMOS gate and the capacitor lower plate, and is connected to the control signal.

[0009] Preferably, the second NMOS source is connected with the substrate end and the system power ground.

[0010] Preferably, the first PMOS source is connected with the substrate end and the third NMOS source, and the third NMOS source is connected with the substrate end and the system power voltage.

[0011] Preferably, the device withstand voltage of the first NMOS, the second NMOS, the third NMOS and the first PMOS is matched with the system power voltage, and the first NMOS, the second NMOS, the third NMOS and the first PMOS are low-voltage devices matched with the system power voltage.

[0012] Preferably, the first NMOS and the third NMOS are isolation NMOS, and the sources of the first NMOS and the third NMOS are connected with the substrate end.

[0013] Preferably, the first NMOS source is connected with the second NMOS drain and the first PMOS drain to form a second node and is connected to the first NMOS substrate end.

[0014] An implementation method of discharging the charge pump output node, comprising the following steps:

[0015] S1, if the control signal is low, the charge pump output high voltage node is not discharged, the first NMOS drain end potential is the charge pump output voltage; the second NMOS gate, the first PMOS gate and the capacitor lower plate connection signal are low, the second NMOS is cut off; the first PMOS is turned on, so that the first NMOS source potential is the system power voltage; the first NMOS gate is charged to the system power voltage by the resistor, so that the first NMOS is cut off, at this time, the voltage between each port of the first NMOS, the second NMOS and the first PMOS does not exceed the system power voltage, and the voltage difference between the two ends of the capacitor is the value of the system power voltage;

[0016] S2. When the control signal is high, the high-voltage node of the charge pump is discharged. The connection signal between the gate of the second NMOS transistor, the gate of the first PMOS transistor, and the lower plate of the capacitor is switched to the power supply voltage. At this time, the level of the upper plate of the capacitor begins to rise synchronously. When the level of the upper plate of the capacitor rises to the point where the third NMOS transistor is turned on, the voltage is clamped by the third NMOS transistor. At the same time, both the first and second NMOS transistors are turned on, discharging the output node of the charge pump. The potential of the output node of the charge pump and the source potential of the first NMOS transistor both decrease. The gate of the first NMOS transistor discharges to the system power supply voltage through the resistor. Since the source potential of the first NMOS transistor has decreased, the first NMOS transistor is still turned on.

[0017] The technical effects and advantages of this invention are as follows: The discharge circuit and implementation method of the charge pump output node are simple in structure and low in production cost. They use low-voltage devices that match the system power supply voltage for discharge, and ensure that all devices operate within a safe operating range. This solves the problem that high production costs are incurred in standard low-voltage processes due to the lack of high-voltage devices or the need for additional photolithography to fabricate high-voltage devices. Attached Figure Description

[0018] Figure 1 This is a circuit structure diagram of the present invention;

[0019] Figure 2 V in the two states of the present invention CK Signal and charge pump node V CP The voltage waveform;

[0020] Figure 3 The control signal V of this invention CK During the switching from low to high, the drain-source voltage V of the first NMOS transistor M1... DS,M1 The gate-source voltage V of the first NMOS transistor M1 GS,M1 The drain-source voltage V of the second NMOS transistor M2 DS，M2 The waveform diagram. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention provides a charge pump output node discharge circuit, such as... Figure 1As shown, including the first NMOS tube M1, the second NMOS tube M2, the first PMOS tube M4, the third NMOS tube M3; capacitor C1 and resistor R1, wherein the first NMOS tube M1 drain and system charge pump output high voltage node V CP Connection, the first NMOS tube M1 gate is connected with the third NMOS tube M3 gate and drain, and is connected with the capacitor C1 upper plate and the resistor R1 one end to form the first node V G , the resistor R1 other end is connected with the system power supply voltage V CC , the first NMOS tube M1 source is connected with the substrate end, and is connected to the second NMOS tube M2 drain and the first PMOS tube M4 drain to constitute the second node V MID ; the second NMOS tube M2 gate is connected with the first PMOS tube M4 gate and the capacitor C1 lower plate, and is connected with the control signal V CK ; the second NMOS tube M2 source is connected with the substrate end and is connected with the system power supply ground GND; the first PMOS tube M4 source is connected with the substrate end and the system power supply voltage V CC ; the third NMOS tube M3 source is connected with the substrate end and the system power supply voltage V CC When the system charge pump works normally, the high voltage node V CP The voltage is at most twice the system power supply voltage, the control signal V CK It is low, so that the second NMOS tube M2 tube is cut off, the first PMOS tube M4 tube is turned on, and the first NMOS tube M1 tube source end potential is pulled to the system power supply voltage V CC , the first NMOS tube M1 gate is charged to the system power supply voltage V CC by the resistor R1, at this time, the voltage difference between each two ports of the first NMOS tube M1 does not exceed the system power supply voltage V CC The voltage between each node of the first NMOS tube M1, the second NMOS tube M2, the third NMOS tube M3 and the first PMOS tube M4 tube does not exceed the system power supply voltage V CC , the voltage difference between the two plates of the capacitor C1 is V CC When it is needed to discharge the charge pump node, the control signal V CK It is flipped to high level, the first PMOS tube M4 tube is cut off, and the second NMOS tube M2 tube is turned on; at the same time, the capacitor C1 upper plate voltage is self-boosted, so that the first NMOS tube M1 tube is also turned on, and since there is the third NMOS tube M3 tube clamping, the first node V G The voltage is at most the system power supply voltage V CC + the third NMOS tube M3 gate-source voltage V GS，M3 Since the first NMOS tube M1 and the second NMOS tube M2 tube are turned on, the high voltage node V CP Starts discharging, and the high voltage node V CP, the second node V MID The node voltage starts to drop, the first node V G Discharge through the resistor R1, and the final voltage stabilizes at the system power supply voltage V CC , the second node V MID The potential has dropped, the first NMOS transistor M1 is still on, and by designing the parameters of the first NMOS transistor M1, the second NMOS transistor M2, and the capacitor C1 and the resistor R1, it can be ensured that the potentials between the various ports are not greater than the system power supply voltage V CC When the charge pump is started next time, the control signal V CK Turns low, the discharge path is closed, and the initial state is returned.

[0023] As shown in Figure 2 , the voltage waveforms of the control signal V CK and the high voltage node V CP of the charge pump during switching between the two states can be seen, when the control signal V CK Turns from high to low, the output of the charge pump is high, and when the control signal V CK Turns from low to high, the output voltage of the charge pump is discharged to low.

[0024] As shown in Figure 3 , when the system power supply voltage V CC = 5V, the output voltage of the charge pump in the system is 2*system power supply voltage V CC , the device process platform is 5V CMOS standard process, the drain-source voltage V DS , the gate-source voltage V GS of the MOS transistor cannot exceed 6V, and when the control signal V CK Turns from low to high, the drain-source voltage V DS,M1 of the first NMOS transistor M1, the gate-source voltage V GS,M1 of the first NMOS transistor M1, and the drain-source voltage V DS，M2 of the second NMOS transistor M2 can be seen, and the maximum voltage difference of the drain-source voltage V DS,M2 of the second NMOS transistor M2 is 5.3V, which is less than the device limit, and other voltages are less than the system power supply voltage V CC ;

[0025] A method for discharging the output node of a charge pump, comprising the following steps:

[0026] S1, if the control signal V CKWhen the control signal V is low, the drain potential of the first NMOS transistor M1 is the output voltage of the charge pump; the signal connected to the gate of the second NMOS transistor M2, the gate of the first PMOS transistor (M4) and the lower plate of the capacitor C1 is low, the second NMOS transistor M2 is cut off; the first PMOS transistor M4 is turned on, so that the source potential of the first NMOS transistor M1 is the system power supply voltage V CC ; the gate of the first NMOS transistor M1 is charged to the system power supply voltage V CC by the resistor R1, so that the first NMOS transistor M1 is cut off, at this time, the voltage carried between each port of the first NMOS transistor M1, the second NMOS transistor M2 and the first PMOS transistor M4 does not exceed the system power supply voltage V CC , and the voltage difference between the two ends of the capacitor C1 is the value of the system power supply voltage V CC .

[0027] S2, if the control signal V CK is high, the gate of the second NMOS transistor M2, the gate of the first PMOS transistor M4 and the lower plate of the capacitor C1 are switched to the power supply voltage, at this time, the upper plate level of the capacitor C1 starts to rise synchronously, the upper plate level of the capacitor C1 rises to the voltage at which the third NMOS transistor M3 is turned on and is clamped by the third NMOS transistor M3, at the same time, the first NMOS transistor M1 and the second NMOS transistor M2 are both turned on, the output node of the charge pump is discharged, the output node of the charge pump and the source potential of the first NMOS transistor M1 are both lowered, and the gate of the first NMOS transistor M1 is discharged to the system power supply voltage V CC through the resistor R1. CP Since the source potential of the first NMOS transistor M1 has been lowered, the first NMOS transistor M1 is still turned on, and the high voltage node V of the output of the charge pump is discharged.

[0028] Finally, it should be noted that: the above only describes the preferred embodiments of the present application and is not used to limit the present application, although the present application has been described in detail with reference to the foregoing embodiments, for those skilled in the art, the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents, any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A charge pump output node discharge circuit, characterized by: The first NMOS transistor (M1) is connected with a high voltage node (V CP ) of a charge pump output, the second NMOS transistor (M2) is connected with the first NMOS transistor (M1), the first PMOS transistor (M4) is connected with the second NMOS transistor (M2), and the third NMOS transistor (M3) is connected with the first PMOS transistor (M4) and controls the gate voltage of the first NMOS transistor (M1). The third NMOS transistor (M3) is connected with the resistor (R1) and the capacitor (C1); the source electrode of the first NMOS transistor (M1) is connected with the substrate end and the drain electrode of the second NMOS transistor (M2) and the drain electrode of the first PMOS transistor (M4), and the drain electrode of the first NMOS transistor (M1) is connected with the high voltage node (V CP ) of the charge pump output; the gate electrode of the first NMOS transistor (M1) is connected with the gate electrode and the drain electrode of the third NMOS transistor (M3), and is connected with the upper plate of the capacitor (C1) and one end of the resistor (R1) to form the first node (V G ), and the other end of the resistor (R1) is connected with the system power voltage (V CC ); the gate electrode of the second NMOS transistor (M2) is connected with the gate electrode of the first PMOS transistor (M4) and the lower plate of the capacitor (C1), and is connected with the control signal (V CK ); the source electrode of the second NMOS transistor (M2) is connected with the substrate end and the system power ground (GND); the source electrode of the first PMOS transistor (M4) is connected with the substrate end and the source electrode of the third NMOS transistor (M3), and the source electrode of the third NMOS transistor (M3) is connected with the substrate end and the system power voltage (V CC ).

2. A charge pump output node discharge circuit according to claim 1, characterized in that: The device withstand voltage of the first NMOS transistor (M1), the second NMOS transistor (M2), the third NMOS transistor (M3) and the first PMOS transistor (M4) are matched with the system power voltage (V CC ).

3. A charge pump output node discharge circuit according to claim 1, wherein: The first NMOS transistor (M1) and the third NMOS transistor (M3) are both isolation NMOS transistors, and the source of the first NMOS transistor (M1) and the third NMOS transistor (M3) is connected to the substrate end.

4. The charge pump output node discharge circuit of claim 1, wherein: The first NMOS transistor (M1) source is connected with the second NMOS transistor (M2) drain and the first PMOS transistor (M4) drain to form a second node (V MID ) and is connected to the first NMOS transistor (M1) substrate end.

5. A method of controlling a charge pump output node discharge circuit according to any one of claims 1 to 4, characterized in that: comprising the steps of: S1, if the control signal (V CK ) is low, the drain potential of the first NMOS transistor (M1) is the output voltage of the charge pump; the gate of the second NMOS transistor (M2), the gate of the first PMOS transistor (M4) and the lower plate of the capacitor (C1) are connected to the low-level signal, the second NMOS transistor (M2) is cut off; the first PMOS transistor (M4) is turned on, so that the source potential of the first NMOS transistor (M1) is the system power supply voltage (V CC ); the gate of the first NMOS transistor (M1) is charged to the system power supply voltage (V CC ) by the resistor (R1), so that the first NMOS transistor (M1) is cut off, at this time, the voltage carried between each port of the first NMOS transistor (M1), the second NMOS transistor (M2) and the first PMOS transistor (M4) does not exceed the system power supply voltage (V CC ), and the voltage difference between the two ends of the capacitor (C1) is the value of the system power supply voltage (V CC ). S2, if the control signal (V CK ) is high, the second NMOS tube (M2) gate, the first PMOS tube (M4) gate and the capacitor (C1) lower plate connection signal (V CK ) switch to power voltage, at this time the capacitor (C1) upper plate level starts to rise synchronously, the capacitor (C1) upper plate level rises to the third NMOS tube (M3) conduction voltage is clamped by the third NMOS tube (M3), at the same time the first NMOS tube (M1) and the second NMOS tube (M2) are all turned on, the charge pump output node is discharged, the charge pump output node and the first NMOS tube (M1) source potential are all decreased, the first NMOS tube (M1) gate is discharged to the system power voltage (V CC ) through the resistor (R1), because the first NMOS tube (M1) source potential has been decreased, the first NMOS tube (M1) is still turned on, realizing the discharge of the charge pump output high voltage node (V CP ).

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