ADC Circuit

Abstract

The present application relates to an ADC circuit. The ADC circuit (200) has a first conversion path (201a) and a second conversion path (201b) for converting an analog signal into a digital signal, and can be operated in a first mode and a second mode. In the first mode, the first conversion path and the second conversion path are connected to the corresponding first input node (202a) and the second input node (202b) to receive a full-scale first analog input signal (Ain1) and a second analog input signal (Ain2) and convert them into separate digital outputs (Dout1, Dout2). In the second mode, the first conversion path and the second conversion path are both connected to the first input node (202a) to convert the first analog input signal (Ain1) into corresponding first digital signals and second digital signals, and the first conversion path and the second conversion path are configured to process different signal levels of the first analog input signal. The selector (207) selects the first digital signal or the second digital signal to be output as an output signal based on an indication of the amplitude of the first analog input signal.

Description

Technical Field

[0001] The field of representative embodiments of the present disclosure relates to methods, apparatus and / or implementations relating to or involving ADC (Analog-to-Digital Converter) circuits. Background Art

[0002] There are many applications that implement analog-to-digital conversion, for example, for converting analog audio signals generated by an input transducer (such as a microphone) into digital signals for processing, transmission and / or storage. Typically, an ADC circuit with an analog front end (AFE) is used to receive an analog input signal and convert it into a digital signal. Preferably, the ADC circuit should be able to convert the received input signal at the maximum expected signal amplitude without distortion or limiting in normal operation, which may require the ADC circuit to have a relatively high dynamic range. In at least some applications, it may also be desirable that the ADC circuit can also convert relatively low amplitude input signals with a relatively good SNR (signal-to-noise ratio), which requires the ADC circuit to be able to operate with relatively low noise.

[0003] One way to implement an ADC circuit that provides good performance with a high dynamic range is to provide the ADC circuit with multiple conversion paths, where each conversion path is coupled to the ADC input and optimized for a specific input signal range. For example, a dual-path ADC circuit may include one conversion path optimized for lower amplitude input signals to provide good SNR for low signal levels and another conversion path optimized for converting higher amplitude signals without significant distortion, so that the ADC circuit can provide a relatively high dynamic range. Depending on the level of the input signal, the appropriate path can be used to provide a digital output. Summary of the invention

[0004] Embodiments of the present disclosure relate to ADC circuits capable of multipath operation.

[0005] According to one aspect of the present disclosure, an analog-to-digital conversion circuit is provided, the analog-to-digital conversion circuit comprising: a first input node, the first input node is used to receive a first analog input signal; a second input node, the second input node is used to receive a second analog input signal; a first conversion path, the first conversion path is used to convert the analog signal into a digital signal; and a second conversion path, the second conversion path is used to convert the analog signal into a digital signal. The analog-to-digital conversion circuit can selectively operate in a first mode or a second mode. In the first mode, the first conversion path is connected to the first input node to convert the first analog input signal into a first digital signal, and the second conversion path is connected to the second input node to convert the second analog input signal into a second digital signal. In the first mode, each of the first conversion path and the second conversion path is configured to process the full range of the corresponding first analog input signal and the second analog input signal, and the first digital signal and the second digital signal are output as a first output signal and a second output signal, respectively. In the second mode, the first conversion path and the second conversion path are both connected to the first input node to convert the first analog input signal into the corresponding first digital signal and the second digital signal. In a second mode, the first conversion path and the second conversion path are configured to process different signal levels of the first analog input signal, and the selector is configured to select the first digital signal or the second digital signal to be output as the output signal based on an indication of the amplitude of the first analog input signal.

[0006] In some examples, in the second mode, the first conversion path can be configured to process a full scale of the first analog input signal and the second conversion path can be configured to process a lower amplitude signal level of the first analog input signal.

[0007] The first conversion path and the second conversion path may each include a corresponding analog front end. In the second operating mode, the corresponding analog front end of the second conversion path may be configured to apply a greater gain to the first analog input signal than the analog front end of the first conversion path. In some embodiments, the analog front end of the second conversion path may include a programmable gain amplifier. The mode controller may control the gain of the programmable gain amplifier of the analog front end of the second conversion path to be different in the first mode and the second mode. The analog front end of the first conversion path may additionally or alternatively include a programmable gain amplifier.

[0008] At least one of the first conversion path and the second conversion path may include a digital gain element for applying a gain to the associated first digital signal or second digital signal in the second mode to provide gain matching of the first conversion path and the second conversion path.

[0009] In some embodiments, the analog-to-digital circuit is operable to dynamically switch between a first mode and a second mode in use.

[0010] The circuit may include at least one switch for selectively connecting the second conversion path to the first input node or the second input node. The second conversion path may be configured to be switchably connected to the first input node via a first input resistor and to be switchably connected to the second input node via a different second input resistor.

[0011] In some examples, the selector may include an attenuator configured to transition between outputting one of the first digital signal and the second digital signal as the selector output signal and outputting the other of the first digital signal and the second digital signal by cross-fading between the first digital signal and the second digital signal.

[0012] In some examples, the controller can be configured to, when operating in the second mode, suspend or disable at least some components of the first conversion path in response to a low signal condition. The low signal condition can include the amplitude of the second digital signal remaining below a defined threshold for a defined period of time.

[0013] In some examples, there may be at least one additional conversion path operable in one mode to connect to an associated additional input node to convert an additional analog input signal received at the additional input node to a digital signal. The at least one additional conversion path may further be operable in another mode to connect to one of the first input node, the second input node, or a further additional input node to convert an analog input signal received at the associated input node to a digital signal.

[0014] In some examples, the clipping controller can be configured to, when operating in the second mode, control the second conversion path to reduce or prevent nonlinear current from being drawn from the first input node due to clipping of the second conversion path. The clipping controller can be configured to control a gain of the second conversion path to prevent clipping of the second conversion path, and / or the clipping controller can be configured to reconfigure the second conversion path to provide regulation of a virtual ground node of the second conversion path.

[0015] In some examples, the circuit may be configured to output an indication of transient noise and / or dynamic range. The analog-to-digital conversion circuit may include a module for determining an indication of transient noise and / or dynamic range based on a setting of a selector that determines a contribution of the first digital signal and the second digital signal to the output signal.

[0016] The analog-to-digital conversion may be implemented as an integrated circuit.In some cases, the first microphone may be coupled to a first input node of the integrated circuit, and the second microphone may be coupled to a second input node of the integrated circuit.

[0017] Aspects also relate to an electronic device comprising an analog-to-digital conversion circuit according to any of the embodiments discussed herein.

[0018] In another aspect, an analog-to-digital conversion circuit is provided, the analog-to-digital conversion circuit comprising: a first analog-to-digital conversion path and a second analog-to-digital conversion path. The analog-to-digital conversion circuit can operate in the following modes: a first mode in which the first analog-to-digital conversion path and the second analog-to-digital conversion path are connected to different input nodes to process separate input signals from separate sources; and a second mode in which the first analog-to-digital conversion path and the second analog-to-digital conversion path are connected to the same input node to process different signal levels of the same input signal.

[0019] In another aspect, an ADC circuit is provided, the ADC circuit comprising: a first ADC path, and

[0020] and a second ADC path, wherein the ADC circuit is operable to connect the first ADC path and the second ADC path to different inputs to process separate analog input signals from separate sources, and is also operable to connect the first ADC path and the second ADC path to the same input to process the same input signal with different analog gains applied.

[0021] Any of the various features of the various embodiments discussed herein may be implemented with any or more of the other described features in any and all suitable combinations, unless explicitly indicated to the contrary. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to better understand the examples of the present disclosure, and to more clearly show how these examples may work, reference is now made, by way of example only, to the following drawings, in which:

[0023] Figure 1 A conventional dual-path ADC circuit is shown;

[0024] Figure 2 An ADC circuit according to one embodiment is shown;

[0025] Figure 3 An example ADC circuit with a suitable AFE is shown;

[0026] Figure 4 Another example of an ADC circuit is shown; and

[0027] Figure 5 An example of an ADC circuit having a differential conversion path with differential inputs is shown according to one embodiment. DETAILED DESCRIPTION

[0028] The following description sets forth exemplary embodiments according to the present disclosure. For those of ordinary skill in the art, other exemplary embodiments and implementations will be apparent. In addition, those of ordinary skill in the art will recognize that various equivalent technologies may be applied to replace or be combined with the embodiments discussed below, and all such equivalents are considered to be encompassed by the present disclosure.

[0029] As described above, ADC circuits having a plurality of parallel conversion paths optimized for different signal levels of an input analog signal have been previously proposed.

[0030] Figure 1 An example of a conventional ADC circuit 100 is shown, which has two conversion paths 101a and 101b optimized for different signal levels. The ADC circuit 100 has an input node 102, which is used to receive an analog input signal Ain from a source 103 such as a transducer, which is a microphone in this example. In such examples, the ADC circuit 100 can be formed as an integrated circuit and configured to receive an input signal from a microphone 103 outside the integrated circuit (i.e., from an off-chip microphone) in a host device. The microphone can be a microphone of a host device or a microphone of a removable accessory device, which can be removably connected to the host device via some wired connection during use. The input node 102 may therefore include an input terminal of the ADC circuit (or a node of a signal path connected to such an input terminal). Conversion paths 101a and 101b are both coupled to the input node 102 so as to be able to receive the analog input signal Ain and convert it into a digital signal.

[0031] Each of the conversion paths 101a and 101b includes a corresponding AFE 104a and 104b and ADC 105a and 105b. The AFE of each conversion path includes a circuit for adjusting the input analog signal Ain to be converted by the corresponding ADC, and may generally include an amplifier. As described above, the conversion paths 101a and 101b are optimized for different input signal levels. For example, the first conversion path 101a may be optimized for a higher amplitude signal, and the second conversion path 101b may be optimized for a lower amplitude signal. The AFE 104b and ADC 105b of the second conversion path 101b may therefore be configured with a higher conversion gain than the AFE 104a and ADC 105a of the first conversion path 101a.

[0032] The AFE 104a of the first conversion path 101a may be configured with a gain such that for an input signal expected to have a maximum signal amplitude in normal operation, the output of the AFE 104a is within the input range of the ADC 105a, and preferably uses substantially the entire input range of the ADC 105a. Such a high amplitude input signal will be well above the noise floor of the ADC 105b and may be converted to a digital signal with a good SNR.

[0033] The first conversion path 101a can therefore be configured to convert any received input signal within the normal operating range without significant distortion due to limiting or overload, etc. However, for low amplitude input signals, the lower input signal level will be closer to the noise floor of the ADC, which will result in a lower SNR. The AFE 104b of the second conversion path 101b therefore includes an amplifier with a relatively high gain so that the low amplitude input signal is amplified to use the wider input range of the ADC 105b. The second conversion path in this example also includes a digital gain element 106, which is used to apply digital gain to the output of the ADC 105b in order to match the overall conversion gain of the second conversion path 101b. The digital gain element 106 can therefore apply gain to the digital signal in the second conversion path 101b to compensate for the increased gain of the AFE 104b compared to the AFE 104a. For example, this can be an attenuation that has the effect of attenuating the noise of the ADC 105b. It should be understood that, Figure 1 Only the digital gain element 106 in the second conversion path 101 b is shown, but in some embodiments, there may additionally or alternatively be a digital gain element in the first conversion path 101 a for providing gain matching of the two paths.

[0034] The second conversion path 101b thus provides a better SNR for lower amplitude input signals. However, for higher amplitude input signals, the relatively higher gain of the AFE 104b will result in clipping in the second conversion path 101b, i.e., the AFE 104b may experience clipping (and if not, the output of the AFE 104b will exceed the input range of the ADC 105b). The ADC circuit 100 therefore includes a selector 107 for selecting the output of the first conversion path 101a or the second conversion path 101b to be output as the digital output signal Dout. The controller 108 may control the selector 107 to select the output of the appropriate path based on the characteristics of the signal being converted (e.g., the signal amplitude). The controller 108 may monitor one or both of the conversion paths 101a and 101b, and as Figure 1 As shown, the digital signals in the conversion paths may be monitored to determine which conversion path should contribute to the digital output signal and generate an appropriate output path selection control signal OP.

[0035] In some embodiments, the selector 107 may include a selection switch or a multiplexer or the like to select the output of one conversion path or the other conversion path. However, for the digital output Dout, the abrupt change from using the output of one conversion path to using the output of the other conversion path may cause some undesirable artifacts in the signal content. Therefore, in some embodiments, it may be preferred to use the contributions from the two conversion paths during the transition from the output of one conversion path to the output of the other conversion path by cross-fading, so the selector 107 may include a suitable cross-fader or mixer, etc.

[0036] Additionally, there may be at least some processing or conditioning of the digital signals in one or both of the signal paths by respective signal processing modules 109a and 109b, such as to apply filtering to remove offsets and / or provide phase and / or delay matching between the two conversion paths.

[0037] like Figure 1 The multipath ADC circuit shown may thus provide a relatively high dynamic range, but may also provide a relatively good SNR for converting lower amplitude input signals. However, the circuit does require two separate conversion paths, conversion paths 101a and 101b, coupled to input node 102, each with a dedicated AFE and ADC optimized for that conversion path, which may increase the circuit area required for the ADC circuit. A larger circuit area may increase the cost of the integrated circuit. Furthermore, in some applications, circuit size is important, and generally speaking, a smaller circuit area may be preferred.

[0038] In addition, the separate AFE 104b and ADC 105b in the second conversion path increases power consumption in use, and power consumption is an important consideration, especially for portable devices. In some applications, the higher performance provided by the multi-path approach may only be required for certain use cases, while in other use cases, the performance of the first conversion path 101a may be sufficient. In this case, when not needed, components of the second conversion path 101b (e.g., AFE 104b and / or ADC 105b) may be disabled to save power, and the selector 107 may be controlled to provide only the digital output from the first conversion path 101a.

[0039] In certain applications, it may be desirable for an integrated circuit to be able to receive and convert multiple analog input signals from different sources. For example, some electronic devices may include multiple microphones, and in such devices, it may be desirable for audio processing circuitry such as an audio codec to be able to receive analog input signals from each of the multiple microphones and convert them to digital signals. Such processing circuitry will have a separate ADC arrangement for processing input signals from each input, and the ADC arrangement for a given input may be implemented as a multipath ADC if desired, but providing a multipath ADC arrangement for each input may significantly increase circuit area.

[0040] Embodiments of the present disclosure relate to an ADC circuit having at least two conversion paths, wherein the ADC circuit is operable such that the two conversion paths are coupleable to separate input nodes so as to independently convert different analog input signals, and wherein the ADC circuit is further operable such that the two conversion paths are alternatively coupleable to the same input node so as to convert the same analog input signal, wherein each conversion path is configured to process different input signal levels so as to provide the benefits of multipath operation.

[0041] Figure 2 An example of an ADC circuit 200 is generally shown according to one embodiment. Figure 2 The ADC circuit is shown to include a first conversion path 201a and a second conversion path 201b. The ADC circuit system 200 also includes a first input node 202a capable of receiving a first analog input signal Ain1 from a first source and a second input node capable of receiving a second analog input signal Ain2 from a different second source. Figure 2 It is shown that a first input node may be coupled to receive a first analog input signal from a first transducer (microphone 203a in this example), and a second input node may be coupled to a different second transducer (microphone 203b in this example). The first source and the second source (e.g., microphones 203a and 203b) may be external to ADC circuit 200 (i.e., off-chip), and first input node 202a and second input node 202b may include terminals of ADC circuit 200 for connecting to such external sources (or nodes of a signal path of ADC circuit 200 to which such terminals are coupled).

[0042] The analog input signal Ain1 or Ain2 can be a single-ended signal or a differential input signal, and for a differential input signal, each input node can be an input node of a differential signal path, and thus can include two input terminals for differential signal components. Similarly, the first conversion path 201a and the second conversion path 201b are paths for processing signals, which can be single-ended or differential (including pseudo-differential) signals. For differential signals, each conversion path can therefore have a separate component signal path for differential components. It should be noted that the first input node 202a and the second input node 202b are separate inputs for receiving separate signals from different sources (e.g., different microphones). For the avoidance of doubt, the first input node 202a and the second input node 202b are therefore not part of a differential pair for receiving a differential signal from one source, but are separate inputs for receiving signals that are independent of each other.

[0043] In the ADC circuit 200, the first conversion path 201a is coupled to the first input node 202a to receive the first input signal Ain1 from the first microphone 203a in this example. Figure 1 The similar approach includes AFE 204a, ADC 205a and possibly digital signal processing module 209a. The AFE 204a of the first conversion path 201a can be configured with a gain so that for the maximum expected amplitude of the input signal Ain1 in normal operation, the output of the AFE 204a is within the input range of the ADC 205a, and preferably substantially the entire input range of the ADC 205a is used. The first conversion path 201a is therefore configured to process the full range of the first analog input signal Ain1, that is, the analog input signal Ain1 can be received and converted at any amplitude within the normal operating range without significant distortion due to limiting, etc. The first conversion path can therefore be regarded as a standard performance conversion path capable of processing the full range of the input signal Ain1.

[0044] exist Figure 2 In the example of , the second conversion path 201b can be selectively coupled to the first input node 202a or to the second input node 202b. The ADC circuit 200 in this example therefore includes a switch 210 for selectively connecting the second conversion path 201b to the second input node 202b or disconnecting it from the second input node, and a switch 211 for selectively connecting the second conversion path 201b to the first input node 202a or disconnecting it from the first input node. However, it should be understood that other switch arrangements or input selection components may be used in other embodiments.

[0045] The second conversion path 201b includes an AFE 204b, an ADC 205, a digital gain element 206, and a digital signal processing module 209b, as shown in FIG. Figure 1 As discussed, however, for ADC circuit 200, the gain of AFE 204b is variable, and the gain of digital gain element 206 is correspondingly controllably variable. In some embodiments, AFE 204b may include a programmable gain amplifier (PGA), as will be appreciated by those skilled in the art. Digital gain element 206 may be any suitable variable digital gain element, such as a multiplier.

[0046] ADC circuit 200 is operable in at least two operating modes.

[0047] In the first operating mode, the second conversion path 201b can be connected to the second input node 202b and disconnected from the first input node 202a, wherein the switch 210 is closed and the switch 211 is open. The second conversion path 201b is thus connected to receive the second analog input signal Ain2. In this mode, the first conversion path and the second conversion path are connected to receive and convert separate input signals Ain1 and Ain2, respectively. The first operating mode can therefore be regarded as an independent single-path conversion mode, in which the two conversion paths operate independently.

[0048] In this mode, the second conversion path 201b is configured so that the gain of the AFE 204b of the input signal Ain2 is such that: for the maximum expected amplitude in normal operation, the output of the AFE 204b is within the input range of the ADC 205b, and preferably, preferably substantially the entire input range of the ADC 205a is used, i.e., the second conversion path is configured to process the full scale of the second analog input signal. In this mode, the second conversion path 201b can therefore convert the full scale or range of the input signal Ain2 without significant distortion due to limiting or overload, etc. In this first mode, the second conversion path can also be regarded as operating as a standard performance conversion path capable of processing the full range of the input signal Ain2. In this mode, the gain of the digital gain element 206 can be controlled to provide the desired total conversion gain for the second conversion path.

[0049] In this first mode, the first conversion path 201a and the second conversion path 201b are thus capable of converting separate input signals Ain1 and Ain2 received from different sources (e.g., microphones 203a and 203b) into separate output signals Dout1 and Dout2. In this first mode of operation, the ADC circuit 200 may thus be capable of outputting the output from each of the conversion paths 201a and 201b as separate independent outputs.

[0050] In the second operating mode, the second conversion path 201b is connected to the first input node 202a and disconnected from the second input node 202b, wherein the switch 210 is open and the switch 211 is closed. The second conversion path 201b is thus connected to receive the first analog input signal Ain1. In this second mode, the first conversion path and the second conversion path are therefore both connected to receive the same input signal Ain1, and the conversion paths can be configured to process different signal levels of the input signals. This second operating mode can therefore be regarded as a multipath (in this case, dual path) operating mode for the first input signal Ain1.

[0051] In this mode, the AFE 204b of the second conversion path 201b is configured to provide a greater gain to the input signal Ain1 than the AFE 204a. The second conversion path can therefore be configured to provide better performance than the first conversion path, for example in terms of SNR, for lower amplitude input signals. In this mode, the AFE 204b can therefore be configured with a relatively high gain so that low amplitude input signals are amplified to use a wider range of the input range of the associated ADC than is the case with the first conversion path 201a. The gain of the digital gain element 206 can be controlled so that the overall conversion gain of the second conversion path 201b matches the overall conversion gain of the first conversion path 201a. As shown in FIG. Figure 1 As discussed, the gain applied by the digital gain element 206 may actually be an attenuation having the effect of attenuating the noise of the ADC 205b. It should be appreciated that Figure 2 Only the digital gain element 206 in the second conversion path 201b is shown, but in some embodiments, in the second mode of operation, there may additionally or alternatively be a digital gain element in the first conversion path 201a for providing gain matching of the two paths.

[0052] In the second operation mode, the output of the ADC is selected from the first conversion path 201a and / or the second conversion path 201b according to the signal level of the input signal Ain1. The ADC circuit thus includes an output path selector 207 that receives the outputs of the two conversion paths and provides a dual-path mode output DoutD, and a controller 208 that is used to generate a reference signal. Figure 1 The selector 207 is controlled in a similar manner as described above. Figure 1As discussed, the selector 207 may include a switching selector or multiplexer or the like for selecting the output of one conversion path or the other conversion path, but preferably the selector includes a mixer or attenuator or the like operable to cross-fade between the outputs of the two conversion paths. The controller 208 controls the selector based on an indication of the signal level of an input signal, which in this example is a digital output of at least one of the conversion paths, but it should be understood that the indication of the input signal level may be provided in other ways.

[0053] This second operating mode thus provides the benefit of dual path operation for the input signal Ain1, wherein the two conversion paths are configured to process input signals of different levels. The first conversion path 201a is configured to process higher amplitude input signals to allow the ADC circuit to operate with a desired dynamic range, wherein the second conversion path 201b is configured to convert lower amplitude signals with a better SNR.

[0054] The operation mode of the ADC circuit 200 may be controlled by a controller 208, which may generate a path selection control signal PS for selecting the relevant input of the second conversion path 201b, i.e., for controlling switches 210 and 211. The controller 208 may also generate a gain control signal GA2 for controlling the analog gain of the AFE 204b and / or a gain control signal GD2 for controlling the digital gain of the digital gain element 206 of the second conversion path. In some embodiments, the controller may control the operation mode in response to receiving a mode selection signal MS, which may be received from some other circuit that may be off-chip. It should be noted that although Figure 2 The controller 208 is shown as being operable to control the operating mode of the ADC circuit 200 and also control output path selection when operating in the second dual path operating mode, but in some embodiments these functions may be implemented by different control modules.

[0055] In the second dual-path operation mode, the second conversion path 201b may therefore be configured for a lower amplitude input signal, and therefore the gain of the AFE 204b may be relatively high. When operating in this mode, if the input signal Ain1 has a relatively high amplitude, the relatively high gain of the AFE 204b may result in signal clipping in the second conversion path, and therefore, at such a signal level, the selector 207 is controlled to output the first digital signal Dout1 from the first conversion path as the dual-path output DoutD. However, in some embodiments, the clipping of the second conversion path 201b may have an undesirable effect on the first conversion path. If the signal level of the input signal Ain1 results in clipping in the second conversion path 201b, then for the AFE 204b, the virtual ground may stop being correctly adjusted by the amplifier of the AFE 204b. This may result in a nonlinear current being drawn from the first input node 202a, which may result in distortion in the first conversion path when the AFE 204a supplies a correction current.

[0056] Thus, in some embodiments, the ADC circuit 200 may be configured to limit or prevent such nonlinear current when operating in the second mode. In some implementations, the controller 208 may be configured to control the gain GA2 of the AFE 204b so as to reduce the gain based on an indication of the signal amplitude of the input signal Ain1 to limit or prevent clipping of the second conversion path. At such a signal amplitude, the controller 208 will control the selector 207 to select the digital signal output from the first conversion path 201a, and thus the change in gain in the second signal path will not have a negative impact on the digital output, but may help reduce or eliminate distortion in the first conversion path 201a. Additionally or alternatively, the controller 208 may generate a clipping control signal CC to reconfigure at least a portion of the second conversion path 201b to reduce or prevent nonlinear current from being drawn from the first input node due to clipping of the second conversion path 201b. For example, the virtual ground of the AFE 204b may be switched to be coupled to a buffered reference when necessary to maintain regulation, or for a differential signal path, the differential virtual ground nodes may be connected together to prevent the amplifier from seeing differential input swings.

[0057] Compared with Figure 1 Compared to the conventional dual-path ADC shown, the ADC circuit 200 allows for increased flexibility. Figure 1In the ADC circuit 100 shown, two conversion paths are coupled to the same input to receive the same signal. In addition, the components of the two conversion paths are dedicated components for appropriate signal levels. That is, the second conversion path 101b of the ADC circuit 100 can only be used for low amplitude signals, and will be overloaded if used for higher amplitude input signals. In the ADC circuit 200, the second conversion path 201b can be configured to process low amplitude signals with good SNR, or can be configured to process full-scale input signals.

[0058] An advantage of the ADC circuit 200 is that it allows the same circuit to be used for different applications. For applications where high performance is required for analog input, the circuit may be configured with an analog source coupled to the first input node 202a, and the ADC circuit may operate in a second dual path mode. In this case, there may be no source connected to the second input node. Alternatively, for applications where two separate conversion paths are required and the standard performance from each conversion path is sufficient, the first input node and the second input node may be connected to separate sources, and the ADC circuit may operate in a first independent conversion mode. The ability to allow the same circuit to be used for different applications may be advantageous because a circuit manufacturer that can supply components to a device manufacturer may be able to supply the same parts for different devices. In these exemplary applications, the operating mode of the ADC circuit may be set when the device is manufactured.

[0059] However, in at least some applications, for example, based on the operating state of the host device, the operating mode of the ADC circuit 200 can be controllably changed during use. As described above, for some applications, some analog inputs may only require the high performance provided by the first dual-path operating mode at certain times or in certain use cases, which may mean that for the conventional dual-path approach, the dual paths are only used at certain times. In such use cases, when the analog input signal from one of the sources requires high performance, it may not be necessary to process the analog input from another of the sources, and / or it may be acceptable to stop processing the input from such other sound sources.

[0060] For example, the host device may include at least two microphones, and in one operating state, it may be desirable that more than one microphone is active at the same time. For example, some electronic devices may be operable to be voice controlled by a user, i.e., in response to at least some verbal commands, and it may be desirable to make two microphones that may be located at different locations on the device active so as to allow monitoring of any verbal commands. Using more than one microphone may allow for better reliability in detecting relevant verbal commands. In particular, if the device can be operated with an always-on voice function, i.e., so that the user can speak a command at any time without physically interacting with the host device, power consumption is important, and monitoring is generally expected to be relatively low power. Therefore, it may be beneficial to use a single conversion path to provide conversion for each microphone input signal to avoid the power consumption of the dual-path method at least before detecting some signal activity of interest. In some cases, if a signal activity corresponding to speech is detected in the input signal from one or both of the microphones, the device may switch to a higher performance mode if necessary, and provide dual-path processing for one of the microphone input signals, which may be a signal in which speech is detected or a signal that is considered to have better quality, and at this time, it may no longer be necessary to repeat processing of other microphone inputs. Additionally or alternatively, such a device may also operate in other states where high quality conversion is only required for one of the microphones. For example, a device may be operable for audio / video recording, and if the recording function is operating, it may be desirable to provide high quality digital output from a particular microphone of the device.

[0061] Thus, in some applications, the ADC circuit may be implemented in a host device, wherein both the first input node 202a and the second input node 202b are coupled so as to be able to receive analog inputs from separate analog sources (e.g., microphones 203a and 203b) in use. In one operating state of the host device, the ADC circuit 200 may operate in a first independent conversion operating mode, such that either or both analog sources may be active as required and provide corresponding analog input signals Ain1 or Ain2, which are converted into digital outputs Dout1 or Dout2 by the associated conversion paths 201a or 201b. However, the host device may transition to a different operating state, and the ADC circuit 200 may be changed to operate in a second dual-path operating mode. In this case, the switch 210 may be opened and the switch 211 may be closed to disconnect the second conversion path from the second input node 202b and connect it to the first input node 202a instead. In some embodiments, the gain of the programmable gain amplifier of AFE 204b can be changed to a suitable value for the second operating mode, which value may be predefined, but in some embodiments, at least some changes in gain may be caused by the switching of inputs and different components in different input paths. In this operating state, the output of ADC circuit 200 will be the dual path output DoutD, which thus provides high performance for the first analog input Ain1.

[0062] This operation may be advantageous when it is desired for the analog input Ain1 because it allows dual mode operation, which can provide an output DoutD with a better SNR for low amplitude input signals than when the first conversion path is used alone. However, if such dual mode operation is only required relatively infrequently, the need for a dedicated high gain conversion path connected to the first input node with associated circuit area is avoided, which is only used infrequently. Conversely, when the input signal Ain1 is not operated in the high performance mode, the second conversion path can be used to process signals from different analog sources.

[0063] AFEs 204a and 204b may be configured to apply different gains when connected to different input nodes 202a and 202b in any convenient manner. Figure 3 An example of an ADC circuit 300 is shown, showing AFEs 204a and 204b in greater detail. Figure 3 The AFE 204a is shown to include a programmable gain amplifier (PGA) 301. The PGA 301 is coupled to the first input node 202a via an input resistor 302. The gain G1 of the PGA 301 and the input resistor 302 together are configured to provide appropriate gain to the input signal Ain1 to convert a full range signal.

[0064] AFE 204b includes PGA 303. When connected to the second input node, PGA 303 is coupled to receive input signal Ain2 via input resistor 304. In this mode, the gain G2 of PGA 303 is set to provide appropriate gain to input signal Ain2 to convert a full range signal. However, when connected to the first input node, PGA 303 is coupled to receive input signal Ain1 via input resistor 305, and the gain G2 of PGA 303 is set to provide appropriate gain to the low amplitude of input signal Ain2.

[0065] Figure 3 It is shown that, in this example, in addition to the digital gain element 206 b in the second conversion path, the first conversion path also includes a digital gain element 206 a , which may have a gain controlled by a gain control signal GD1 from the controller 208 .

[0066] In some embodiments, the gains G1 and G2 of both PGAs 301 and 303 may be configurable in use and may be changed, for example by controller 208, when switching between operating modes to provide appropriate gains for the AFEs of both conversion paths.

[0067] It should be noted that in the above discussion, the first conversion path 201a is used as a low gain path for full-scale signals in the second dual-path operating mode, where the second conversion path is used as a high gain path for lower amplitude signals. This arrangement may be advantageous because it avoids reconfiguration of the first conversion path when switching between modes. However, in some embodiments, it is possible to use the first conversion path as a high gain path in the second dual-path operating mode, where the second conversion path provides a low gain path for full-scale signals. In this case, when switching between modes, the effective gain of the AFE 204a of the first conversion path 201a can be changed, for example, by connecting the first conversion path 201a to the first input node via different input resistors and / or changing the gain of the PGA 301.

[0068] It should also be noted that Figure 2 and Figure 3 The first conversion path 201a is shown coupled to the first input node 202a, while the second conversion path 201b can be selectively coupled to either the first input node 202a or the second input node 202b. However, the first conversion path can be selectively coupled to either the input node 202a or 202b, which can allow independent conversion of separate inputs at both input nodes 202a and 202b, or dual path operation of inputs from one of the input nodes, which can be selected as the first input node 202a or the second input node 202b.

[0069] Figure 2 and Figure 3 An example of an ADC circuit having two conversion paths is shown, which conversion paths can be used independently to convert separate signals from separate analog sources, or can be configured to provide dual path operation for an analog input signal from a given analog source. However, it should be understood that the principles apply to ADC circuits having more than two conversion paths. In some applications, there may be multiple pairs of conversion paths, each pair of conversion paths being operable to independently convert input analog signals from corresponding inputs, but also being operable in dual path mode for one of the inputs of the pair. For example, Figure 4 An example of an ADC circuit 400 having four separate input nodes 202a, 202b, 202c, and 202d and four conversion paths 201a, 201b, 201c, and 201d is shown. The first conversion path and the second conversion path may be as described above with respect to Figure 2 and Figure 3 The third conversion path 201c and the fourth conversion path 201d can also operate in a similar manner and can operate in a mode to independently convert signals from input nodes 202c and 202d to provide outputs Dout3 and Dout4, respectively, or operate in a dual path operation mode for input node 202c, thereby providing a dual path output DoutD2. It should be understood that the operation modes of the first conversion path and the second conversion path can be controlled independently of the operation modes of the third conversion path and the fourth conversion path.

[0070] The ADC circuit 400 thus provides a significant degree of flexibility in how the various conversion paths may be used. In one mode of operation, the ADC circuit 400 may be used to allow independent conversion of four separate analog signals Ain1, Ain2, Ain3, and Ain4 from four separate analog sources to provide four separate digital outputs Dout1, Dout2, Dout3, and Dout4. In one mode of operation, the ADC circuit 400 may be used to allow independent conversion of two separate analog signals (e.g., Ain1 and Ain2) using conversion paths 201a and 201b while providing dual path operation for a third analog input signal Ain3 from a third source, such as using conversion paths 201c and 201d to provide digital outputs Dout1, Dout2, and DoutD2. Alternatively, conversion paths 201c and 201d may provide independent conversion of input signals Ain3 and Ain4 to provide outputs Dout3 and Dout4, wherein conversion paths 201a and 201b are used for dual path operation of input signal Ain1 to provide output DoutD. In another mode of operation, the ADC circuit may allow separate dual-path conversion of two different input signals Ain1 and Ain3 received at input nodes 202a and 202c, respectively, to provide outputs DoutD and DoutD2.

[0071] However, it should be understood that other possibilities for connections between the input and the conversion path are possible.

[0072] For example, in some applications, more than two different conversion paths may be connected to the same input node to receive and process the same signal. Figure 2 In addition to the first conversion path and the second conversion path described, there may also be at least a third conversion path that can be coupled to the first input node in use to receive and convert the input signal Ain1. When connected to the first input node, the third conversion path can be configured for input signals in a different range than the first conversion path and the second conversion path, for example, so that one conversion path is optimized for full-range signals, one conversion path is configured for mid-range signals, and another conversion path is configured for low-range signals to provide three-path operation. Alternatively, providing the ability to connect both the second conversion path and the third conversion path to the first input node allows the selection of whether to use the second conversion path or the third conversion path for dual-path operation of the first input. This allows flexibility in deciding which input signal to stop processing when the signal from the first input node requires high performance.

[0073] Additionally or alternatively, in some embodiments, a given conversion path may be selectively connected to more than two different input nodes. Figure 2In addition to the first conversion path and the second conversion path described, there may also be at least a third conversion path that is coupled to receive an input signal from a third input node. The second conversion path may be configured to selectively couple to any one of the first input node, the second input node, or the third input node. This allows the second conversion path to be used as an independent path for receiving and converting the input signal Ain2 from the second input node, or to be connected to any one of the first input node or the third input node in a dual-path operation mode, that is, the second conversion path may be used in combination with the first conversion path or the third conversion path to provide dual-path operation for the input signal Ain1 or the input signal Ain3 as required.

[0074] As described above, in some cases, the input signal may be received as a differential signal and / or the conversion path may be a differential path. Figure 5 An example of an ADC circuit 500 with a differential input and a differential conversion path is shown according to one embodiment. Figure 5 The first input node is shown to include inputs 202ap and 202an for receiving components Ain1p and Ain1n of a differential signal from a first source, and similarly, the second input node includes inputs 202bp and 202bn for receiving components Ain2p and Ain2n of a differential signal from a different second source. Figure 5 It is also shown that the analog portions of conversion paths 201a and 201b are differential.

[0075] Various embodiments described herein therefore allow the use of a first conversion path and a second conversion path to process the same signal in a dual-path operating mode, wherein the first conversion path and the second conversion path are optimized for different signal levels. This operating mode can provide good performance, but will increase the power consumption associated with the conversion of the particular analog input signal, because the two conversion paths are actively processing the signal. In some cases, when the input signal is at a low signal level over a relatively extended period of time, high performance may generally be required. However, if the input signal remains at a low level over a relatively extended period of time, the digital output of the input signal will only be derived from the conversion path optimized for the low-level signal, which may be the second conversion path in some of the above examples. Therefore, in some embodiments, the ADC circuit may be configured to be operable to suspend or disable at least some components of the conversion path (e.g., the first conversion path) of the full-scale signal in response to a low signal condition when operating in the second dual-path operating mode to save power. The low signal condition may be detected by the controller 208, and may, for example, include the controller detecting that the digital output of the conversion path optimized for the low-level signal remains below a defined threshold value over a determined period of time, or meets some other defined criteria. Additionally or alternatively, the controller may receive an indication of the signal level from some other monitoring circuit, which may monitor the analog input directly, or some other controller may determine the low signal condition and generate a control signal for the controller 208 .

[0076] In some embodiments, the ADC circuit may be operated in at least a second multipath operating mode to provide an indication of current noise or an indication of dynamic range at the output of the ADC circuit. Figure 2, the controller 208 may therefore output a signal N / DR indicating a noise parameter (e.g., a current SNR) of the circuit and / or indicating a dynamic range. In the second dual-path operating mode, the controller 208 controls the selector to output an output signal DoutD based on the output of the first conversion path 201a or the second conversion path 201b or as a combination of the two paths. When the output signal DoutD is selected entirely from only one of the conversion paths, i.e., 100% of the output signal DoutD is derived from the first conversion path 201a or the second conversion path 201b, the noise floor is due to the associated path as configured in the dual-path mode. The noise floor or indication of the dynamic range of each of the associated paths in this mode may be known and stored. Therefore, based on which conversion path is selected to provide the output signal DoutD, the noise floor of that path may be determined and identified as the current noise floor of the conversion. When the output signal DoutD is provided by the selector 207 as a combination of signals from two conversion paths, for example during cross-fading, the total noise floor will depend on the relevant contribution from each path, which will depend on the settings of the mixer or cross-fader of the selector 207, such as the filter coefficients of the selector 207. The relationship between the relevant settings of the selector 207 and the resulting noise floor can be determined, for example, by calculation, modeling and / or testing, and stored in a lookup table or the like. Therefore, based on the current settings of the selector 207, an indication of the current noise floor or dynamic range can be determined and can be output as a signal N / DR. Such a signal can be used for some downstream processing of the digital output, for example, by outputting the current instantaneous noise floor, it can be determined whether there is any significant signal content. When the controller also receives an indication of the signal amplitude, the controller can additionally or alternatively output an indication of the current SNR.

[0077] Therefore, the embodiments of the present disclosure provide an ADC circuit for converting an input analog signal into a digital signal. The ADC circuit according to the embodiment provides flexibility in the processing of the analog input signal and can be configured to provide multipath processing for a given analog input. If multipath processing is not required, the relevant conversion path can be used independently to convert other signals, which can reduce the circuit area.

[0078] Embodiments are particularly applicable to audio processing circuits, for example, for processing input analog signals from one or more microphones. Note that, as used herein, the term audio should be considered to include signals representing audible sounds that can be heard by a listener, but should also include signals of other frequencies, such as ultrasonic frequencies used for other applications such as machine-to-machine communication or proximity or gesture sensing. The principles can also be applied to signals from other transducers besides microphones, such as various sensor transducers.

[0079] An embodiment may be arranged as part of an audio and / or signal processing circuit, for example an audio circuit such as a codec that may be provided in a host device.A circuit according to an embodiment of the invention may be implemented as an integrated circuit.

[0080] Embodiments may be incorporated into a host electronic device, which may be, for example, a portable device and / or a device operable with battery power. The host device may be a device having one or more microphones provided as part of the host device and / or a connector for wired connection to a microphone of a removable accessory device, which may be removably connected to the host device during use. The host device may include a wireless communication module for receiving input data. The host device may be a communication device such as a mobile phone or smart phone, a computing device such as a notebook, laptop or tablet computing device, a wearable device such as a smart watch. The host device may alternatively be an accessory device for use with any such communication, computing or wearable device. The host device may be a device with voice control or activation functionality.

[0081] The skilled person will recognize that some aspects of the apparatus and methods described above (e.g., discovery and configuration methods) may be embodied as, for example, processor control code on a non-volatile carrier medium such as a disk, CD-ROM or DVD-ROM, a programmed memory such as a read-only memory (firmware) or on a data carrier such as an optical signal carrier or an electrical signal carrier. For many applications, the implementation will be implemented on a DSP (digital signal processor), an ASIC (application specific integrated circuit), or an FPGA (field programmable gate array). Thus, the code may include conventional program code or microcode, or, for example, code for setting up or controlling an ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable apparatus such as a reprogrammable logic gate array. Similarly, the code may include code for a hardware description language such as Verilog TM The code may be distributed among multiple coupled components that communicate with each other, as will be appreciated by the skilled person. Where appropriate, embodiments may also be implemented using code that runs on a field (re)programmable analog array or similar device to configure analog hardware.

[0082] It should be noted that the embodiments mentioned above illustrate rather than limit the present invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single feature or other unit may perform the functions of several units recited in the claims. Any reference numerals or labels in the claims should not be interpreted as limiting their scope.

Claims

1. Analog-to-digital conversion circuit, including: a first input node, the first input node being used to receive a first analog input signal; a second input node, the second input node being used to receive a second analog input signal; a first conversion path, the first conversion path being used to convert an analog signal into a digital signal; a second conversion path, the second conversion path being used to convert the analog signal into a digital signal; The analog-to-digital conversion circuit can selectively operate in the following modes: a first mode, in which the first conversion path is connected to the first input node to convert the first analog input signal into a first digital signal, and the second conversion path is connected to the second input node to convert the second analog input signal into a second digital signal, wherein in the first mode, each of the first conversion path and the second conversion path is configured to process a full scale of the corresponding first analog input signal and the second analog input signal, and the first digital signal and the second digital signal are output as a first output signal and a second output signal, respectively; as well as and a second mode, in which the first conversion path and the second conversion path are both connected to the first input node to convert the first analog input signal into corresponding first digital signals and second digital signals, wherein in the second mode, the first conversion path and the second conversion path are configured to process different signal levels of the first analog input signal, and the selector is configured to select the first digital signal or the second digital signal to be output as an output signal based on an indication of the amplitude of the first analog input signal.

2. The analog-to-digital conversion circuit of claim 1 , wherein in the second mode, the first conversion path is configured to process a full scale of the first analog input signal, and the second conversion path is configured to process a lower amplitude signal level of the first analog input signal.

3. An analog-to-digital conversion circuit as described in claim 1 or claim 2, wherein the first conversion path and the second conversion path each include a corresponding analog front end, and wherein in a second operating mode, the corresponding analog front end of the second conversion path is configured to apply a greater gain to the first analog input signal than the analog front end of the first conversion path. 4 . The analog-to-digital conversion circuit of claim 3 , wherein the analog front end of the second conversion path comprises a programmable gain amplifier.

5. The analog-to-digital conversion circuit of claim 4, comprising a mode controller for controlling the gain of the programmable gain amplifier of the analog front end of the second conversion path to be different in the first mode and the second mode.

6. The analog-to-digital conversion circuit of claim 3, wherein the analog front end of the first conversion path comprises a programmable gain amplifier.

7. An analog-to-digital conversion circuit as described in any one of claims 1 to 2, wherein at least one of the first conversion path and the second conversion path includes a digital gain element, and the digital gain element is used to apply gain to the relevant first digital signal or the second digital signal in the second mode to provide gain matching of the first conversion path and the second conversion path.

8. An analog to digital conversion circuit as claimed in any one of claims 1 to 2, wherein the analog to digital conversion circuit is operable to dynamically switch between the first mode and the second mode in use. 9 . The analog-to-digital conversion circuit according to claim 1 , comprising at least one switch for selectively connecting the second conversion path to the first input node or the second input node. 10 . The analog-to-digital conversion circuit of claim 9 , wherein the second conversion path is configured to be switchably connected to the first input node via a first input resistor, and to be switchably connected to the second input node via a different second input resistor.

11. An analog-to-digital conversion circuit as described in any one of claims 1 to 2, wherein the selector includes an attenuator, which is configured to switch between outputting one of the first digital signal and the second digital signal as a selector output signal and outputting the other of the first digital signal and the second digital signal by performing cross-attenuation between the first digital signal and the second digital signal.

12. The analog-to-digital conversion circuit of any one of claims 1 to 2, further comprising a controller configured to suspend or disable at least some components of the first conversion path in response to a low signal condition when operating in the second mode.

13. The analog-to-digital conversion circuit of claim 12, wherein the low signal condition comprises an amplitude of the second digital signal remaining below a defined threshold for a defined period of time.

14. The analog-to-digital conversion circuit as described in any one of claims 1 to 2 further includes at least one additional conversion path, which is operable in one mode to be connected to an associated additional input node to convert an additional analog input signal received at the additional input node into a digital signal.

15. An analog-to-digital conversion circuit as described in claim 14, wherein the at least one additional conversion path is further operable in another mode to be connected to one of the first input node, the second input node or another additional input node to convert the analog input signal received at the relevant input node into a digital signal.

16. The analog-to-digital conversion circuit of any one of claims 1 to 2, further comprising a limiting controller configured to control the second conversion path to reduce or prevent nonlinear current from being drawn from the first input node due to limiting of the second conversion path when operating in the second mode. 17 . The analog-to-digital conversion circuit of claim 16 , wherein the clipping controller is configured to control the gain of the second conversion path to prevent clipping of the second conversion path.

18. The analog-to-digital conversion circuit of claim 16, wherein the limit controller is configured to reconfigure the second conversion path to provide regulation of a virtual ground node of the second conversion path.

19. An analog-to-digital conversion circuit as claimed in any one of claims 1 to 2, wherein the analog-to-digital conversion circuit is configured to output an indication of transient noise and / or dynamic range.

20. The analog-to-digital conversion circuit of claim 19, comprising means for determining the indication of transient noise and / or dynamic range based on a setting of the selector, the setting determining a contribution of the first digital signal and the second digital signal to the output signal.

21. The analog-to-digital conversion circuit of any one of claims 1 to 2, implemented as an integrated circuit.

22. The analog-to-digital conversion circuit of claim 21, further comprising a first microphone coupled to a first input node of the integrated circuit and a second microphone coupled to a second input node of the integrated circuit.

23. An electronic device comprising an analog to digital conversion circuit as claimed in any preceding claim.

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