Fabrication of quantum devices

Abstract

In the mask stage, a first section of an amorphous mask is formed on a bottom layer of a substrate. The first section includes a first group of grooves that expose the bottom layer. In the mask stage, a second section of an amorphous mask is formed on the bottom layer. The second section includes a second group of grooves that expose the bottom layer. The two sections do not overlap. The open end of one of the grooves in the first group of grooves faces the open end of one of the grooves in the second group of grooves, but the ends are separated by a portion of the amorphous mask. In the semiconductor growth stage, semiconductor material is grown in the first group of grooves and the second group of grooves by selective area growth to form a first sub-network and a second sub-network of nanowires on the bottom layer. The first sub-network and the second sub-network of nanowires are joined to form a single nanowire network.

Description

Technical Field

[0001] The present application relates to a method for manufacturing a quantum device and the generated quantum device, which can be used in a quantum computer, for example. Background Art

[0002] Quantum computing is a type of computing in which inherent quantum mechanical phenomena, such as superposition and entanglement of quantum states, are exploited to perform certain calculations at speeds far exceeding what any classical computer can do. In a "topological" quantum computer, calculations are performed by manipulating quasiparticles that occur in certain physical systems, called "non-abeliananyons." Anyons have unique physical properties that distinguish them from both fermions and bosons. Non-Abelian anyons also have unique properties relative to Abelian anyons. It is these unique properties that serve as the basis for topological quantum computing, in which information is encoded as the topological properties of non-Abelian anyons; in particular, the weaving of their spacetime world lines. This has certain benefits compared to other models of quantum computing. A key benefit is stability, because quantum weaving is not affected by perturbations on a scale that could cause error-induced quantum decoherence in other types of quantum computers.

[0003] Broadly speaking, two types of physical systems have so far been considered as potential hosts for non-Abelian anyons, namely the "5 / 2 fractional quantum Hall" system in condensed matter physics, and (more recently) semiconductor-superconductor (SE / SU) nanowires. Regarding the latter, the key advance in the field has been the realization that non-Abelian anyons in the form of "Majorana zero modes" (MZMs) can form in a semiconductor (SE) region coupled to a superconductor (SU). Based on this phenomenon, networks of SE / SU nanowires, each comprising a section of semiconductor coated with a superconductor, can be used to create qubits.

[0004] A qubit, or quantum bit, is an element on which a measurement with two possible outcomes can be performed, but which at any given time (when not being measured) is actually in a quantum superposition of two states corresponding to different outcomes.

[0005] "Topological" qubits are qubits implemented based on the described non-Abelian anyon technology in the form of MZMs. A non-Abelian anyon is a quasiparticle, which means that it is not a particle itself, but an excitation in an electron liquid that behaves at least partially like a particle. In particular, anyons are quasiparticles that occur in two-dimensional systems (two degrees of freedom in space). Majorana zero modes are special bound states of such quasiparticles. Under certain conditions, these states can be formed close to the semiconductor / superconductor interfaces in SE / SU nanowire networks in a way that enables them to be manipulated as qubits for the purpose of quantum computing. Regions or "segments" of the nanowire network between MZMs are said to be in the "topological" regime. Summary of the invention

[0006] The present invention summary is provided to introduce selected concepts in a simplified form, and these concepts will be further described in the following detailed description. The present invention summary is not intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is also not limited to the implementation method that solves any or all disadvantages pointed out herein.

[0007] While recent advances in fabrication techniques have led to significant improvements in the quality of nanowire networks, the methods involved all face scalability and / or quality challenges that impose limits on the size and complexity of nanowire networks that can be fabricated using these methods.

[0008] Various micro / nano fabrication methods can be used to produce the high-quality semiconductor (as well as superconductors and insulators) structures required for quantum devices, for potential use in the field of quantum computing. Particular challenges exist in the case of epitaxial structures (in-plane line networks), where masks are used to direct the growth process, which may be kinetically or / and thermodynamically controlled.

[0009] One challenge involves defect engineering. Defect-free regions in nanowire networks are limited in size (typically a few micrometers). Defects in the structure occur randomly within the structure at sizes exceeding a critical size. This is detrimental to device quality, as defective regions may occur within active regions of the device, negatively affecting electron transport.

[0010] Another challenge concerns scalability. In some specific cases, the maximum achievable size of the generated structures (e.g. networks) is limited to tens of micrometers due to fundamental kinetic and / or thermodynamic limitations. This makes some fabrication methods non-scalable, even though they can produce high-quality structures at a smaller level. There is a natural need to make such methods scalable for large-scale applications.

[0011] Embodiments of the present invention provide methods of fabricating nanowire structures that not only produce high quality structures, but can also do so in a scalable manner to allow the creation of large and potentially complex nanowire networks.

[0012] According to one aspect disclosed herein, a method for manufacturing a quantum device is provided, the method comprising: in a mask stage, forming a first section of an amorphous mask on an underlying layer of a substrate, wherein the first section includes a first group of grooves exposing the underlying layer; in a mask stage, forming a second section of an amorphous mask on the underlying layer, wherein the second section includes a second group of grooves exposing the underlying layer, wherein the first section and the second section are non-overlapping, and wherein an open end of one of the grooves in the first group of grooves faces an open end of one of the grooves in the second group of grooves, but the two open ends are separated by a portion of the amorphous mask; in a semiconductor growth stage, growing semiconductor material in the first group of grooves and the second group of grooves by selective area growth to form a first subnetwork and a second subnetwork of nanowires on the underlying layer; and joining the first subnetwork and the second subnetwork of nanowires to form a single nanowire network on the underlying layer.

[0013] The first section and the second section may be formed simultaneously. That is, the first group of grooves and the second group of grooves may be formed simultaneously. Alternatively, the first section and the second section may be formed sequentially.

[0014] Thus, the separated grooves form a first portion and a second portion of an overall (i.e., wider or larger) groove (i.e., channel) that defines the nanowire, but has a discontinuity in the overall groove formed by the portion of the mask. In other words, the portion of the mask effectively acts as a discontinuity in a longer groove formed by the separated grooves. The portion is preferably of the order of a few nanometers in the direction of the groove. Some selective area growth techniques are characterized in that the probability of a groove being filled increases with a decrease in surface area. In this case, due to fundamental kinetic and / or thermodynamic limitations, the maximum achievable size of the resulting structure (e.g., network) is limited to only tens of microns, and it is beneficial to segment a large mask into smaller segments, which can increase the chance of a fully grown nanowire network.

[0015] Embodiments of the present invention use a segmented approach to build a single (i.e., larger) nanowire network from two or more sub-networks (i.e., smaller networks) of nanowires. This enables growth methods (that cannot produce large structures) to be used on a larger scale (e.g., wafer scale). Embodiments also enable efficient defect engineering within large-scale nanowire networks because defects are constrained to the separation between mask segments, i.e., between the open end of one of the first set of grooves and the open end of one of the second set of grooves.

[0016] In an embodiment, the joining may include merging by lateral growth of semiconductor material during a semiconductor growth phase.

[0017] Alternatively, the joining may include connecting an open end of one of the first set of trenches with an open end of one of the second set of trenches via an electrical conductor in a subsequent stage of the semiconductor growth stage.

[0018] In an embodiment, the bottom layer may be a wafer of substrate.Alternatively, one or more intermediate layers may be provided between the mask and the wafer.

[0019] In an embodiment, the open ends of the first trenches of the first group may be separated from the open ends of the first trenches of the second group at the inactive region of the nanowire network.

[0020] Not all regions (e.g., points or regions) within a nanowire network are used for quantum and / or electrical purposes. Although entire portions of the network play specific roles in quantum computing, the requirements for crystal quality for different portions are different. The portions where quantum effects "occur" have the highest requirements for crystal quality. These portions are called "active regions." In other words, the necessary quantum or electrical effects (e.g., quantum computing) are typically confined to certain regions in the nanowire network, such as at certain connections in the network. The active (or operational) region of a nanowire network refers to any region that is consistent with the effect or where the effect is expected to occur. In other words, the operational region is the active region, or the working region of the quantum device. In contrast, the non-operational region refers to any region that is inconsistent with the effect or where the effect is not expected to occur. Therefore, the separation between the first and second segments of the mask, i.e., the portion of the mask that separates the open end of one of the first set of grooves from the open end of one of the second set of grooves, can be placed to coincide with the non-operational region of the mask. The inventors assume that defects (if any) in the nanowire structure occur at the separation rather than at random locations. This therefore allows defects to be confined to the non-operating areas rather than occurring randomly throughout the operating areas, thereby improving the overall quality of the device.

[0021] In an embodiment, the first and second networks of trenches may be formed by etching an amorphous mask from an underlying layer. Alternatively, the trenches may be formed using nano-imprinting or other patterning techniques.

[0022] In an embodiment, the respective patterns of the first and second trenches may be defined by photolithography.

[0023] In an embodiment, the amorphous mask may be a dielectric. In an embodiment, the bottom layer may be an insulating material.

[0024] In an embodiment, the semiconductor material may be grown by epitaxy techniques. For example, the semiconductor material may be grown by molecular beam epitaxy.

[0025] In an embodiment, the method may include, during the superconductor growth phase, growing a layer of superconductor material at least partially on the nanowire network.

[0026] In an embodiment, the layer of superconductor material may be applied using a particle beam.

[0027] In an embodiment, the superconductor material may be grown by epitaxy.

[0028] According to another aspect disclosed herein, a quantum device can be provided, which includes: a substrate and an amorphous mask formed on a bottom layer of the substrate, wherein the amorphous mask includes a first segment and a second segment, the first segment includes a first group of grooves, and the second segment includes a second group of grooves, wherein the first segment and the second segment are non-overlapping, and wherein the open ends of the first grooves of the first group of grooves are separated from the open ends of the first grooves of the second group of grooves and face the open ends of the first grooves of the second group of grooves; and a nanowire network on the bottom layer, wherein the nanowire network is formed by the joining of a first sub-network and a second sub-network of nanowires on the mask, wherein the first sub-network and the second sub-network of nanowires include semiconductor materials grown in selective areas in the first group of grooves and the second group of grooves.

[0029] In an embodiment, the apparatus may include an electrical conductor joining open ends of first grooves of the first set of grooves and the second set of grooves.

[0030] According to another aspect disclosed herein, a method of operating a device may be provided, wherein the method includes inducing at least one Majorana zero-mode MZM in one or more nanowires of a nanowire network, wherein the at least one MZM is induced by cooling a superconductor to a superconductor temperature and applying a magnetic field to the device. The induction of the at least one MZM may further include gating at least one nanowire of the one or more nanowires using an electrostatic potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to better understand the present technology and to show how the embodiments can be implemented, reference is made to the following drawings, which are examples only:

[0032] Figure 1 schematically illustrates an example method for making a nanowire network;

[0033] Figure 2A and 2B An example of a selective area grown nanowire network is illustrated;

[0034] Figure 3An example SEM image of a portion of a large-scale (>10 μm) nanowire network is shown;

[0035] Figure 4 and Figure 4A Example SEM images of small-scale (<7 μm) nanowire networks are shown;

[0036] Figure 5 and 5A schematically illustrates an example sub-network of nanowires joined to form a single nanowire network;

[0037] Figure 6 An example SEM image is illustrated showing the segmentation method for a 30 μm line being segmented into 10 μm segments, and the inset shows a close-up of the gaps between the segments;

[0038] Fig. 7A and 7B schematically illustrates examples of an uninterrupted mask and examples of segmented mask defects occurring at random locations within a nanowire; and

[0039] Figure 8 An example cross-sectional TEM of a nanowire with defects occurring at random locations within the nanowire is illustrated. DETAILED DESCRIPTION

[0040] Epitaxial semiconductor-superconductor materials are promising platforms for superconducting electronics and superconducting quantum computing. In the context of topological quantum computing, superconducting nanowires with strong spin-orbit coupling can support topological excitations that can serve as the basis for fault-tolerant quantum information processing.

[0041] Current approaches to synthesizing semiconductor superconductor materials for superconducting nanowire electronics are either based on two-dimensional planar materials (see, e.g., Shabani et al. PRB 93, 155402 (2016)) or bottom-up grown nanowire materials (see, e.g., Krogstrup et al. Nature Mater 14, 400-406 (2015)). Both approaches face challenges in scalability for different reasons.

[0042] In particular, certain mask-guided fabrication methods can produce high-quality structures on a small scale but are not scalable to larger structures. Figure 3 is a scanning electron microscope (SEM) image of a mask used to guide the growth of a nanowire network. Masks larger than 10 μm have not been completely filled with material after growth (see the circled portion of the image). In contrast, Figure 4 and Figure 4Ais a SEM image showing a small-scale nanowire network that has been grown by completing the filling of a smaller mask. Here, the feature sizes of the mask openings are each less than 7 μm.

[0043] Furthermore, in the case of large-scale networks that may be realized, the problem of defect formation arises as defects are formed at random locations within the network. Fig. 7A , where the nanowires are grown using an uninterrupted mask, as was the case in the previous method. Here, defects 702a, 702 occur at random locations. Figure 8 The cross-sectional image of is a transmission electron microscope (TEM) image of a nanowire, which shows a real example of defects occurring in the nanowire.

[0044] To address these and other issues, embodiments of the present invention use a segmented approach to fabricating quantum devices, whereby a mask design for a large network is broken down into smaller segments. Once growth occurs in the smaller segments forming sub-networks of nanowires, the sub-networks can be joined (e.g., merged). For example, the sub-networks can be joined by lateral extensions of the crystal. The resulting structure (network) will resemble an uninterrupted design, but with defects (if any) confined to the locations of intentional mask breaks. This is achieved in a manner that allows for the fabrication of a quantum device with a desired quality. Figure 7B , where defects 702a occur at break locations 704, rather than at random locations throughout the nanowire 706. This solves the defect problem. As for the scalability problem, each sub-network is grown independently, ensuring that each of them is below the critical achievable size for the specific materials and growth conditions. Any number of fully grown sub-networks can be joined to form a larger network. This ensures unfettered scalability of the nanowire network.

[0045] refer to Figure 1 , 5 5A, an example three-phase fabrication method will be described. The fabrication method can be used to create networks of semiconductor (SE) and / or semiconductor / superconductor (SE / SU) nanowires, which in turn can form the basis of quantum devices or circuits (e.g., for quantum computers) or other hybrid semiconductor-superconductor platforms. In particular, the method is particularly suitable for fabricating SE / SU nanowire networks capable of hosting stable MZMs, which can form the basis of trouble-free topological quantum computing. Here, SE / SU nanowires refer to semiconductor wires coated with superconductors.

[0046] An example fabrication method utilizes selective area growth (SAG). SAG is a growth method using a crystal growth vacuum chamber, such as chemical beam epitaxy (CBE), molecular beam epitaxy, and MOCVD. See, for example, GJ Davies Proc. SPIE 2140, Epitaxial Growth Processes, 58 (May 11, 1994); doi: 10.1117 / 12.175795; M Fahed, Doctoral thesis: Selective area growth of in-plane III-V nanostructures using molecular beam epitaxy, 2016. http: / / www.theses.fr / 2016LIL10114; Fukui et al, Appl. Phys. Lett. 58, 2018 (1991); doi: http: / / dx.doi.org / 10.1063 / 1.105026.

[0047] Because SE / SU nanowire networks are created using SAG, the entire nanowire network or multiple such networks can be fabricated as a whole on a substrate. The substrate and nanowire network can be directly incorporated into the final product without the need to transfer the nanowires to a different surface.

[0048] The fabrication of quantum devices involves building up a wafer by depositing multiple layers or materials on a substrate, usually in different patterns. The entire process involves multiple steps as different layers are built up. For the following description, "wafer" will be referred to herein as the base layer, while "substrate" will refer to the wafer plus any other layers that have been deposited on the wafer at the current stage of the fabrication process.

[0049] In the first stage I (mask stage), an amorphous mask 102 is formed on the bottom layer of the substrate 104. The amorphous mask 102 can be made of a dielectric material. The bottom layer of the substrate can be the substrate 104 itself, or it can be an intermediate material layer that has been deposited on the substrate. The amorphous mask 102 is composed of a plurality of segments. The following example will be described in the form of a first segment and a second segment, but it should be understood that the described method is applicable to the case of more than two segments. Each segment includes a group of grooves (e.g., a substrate) exposing a bottom layer having a first segment and a second segment, wherein the first segment includes a first group of grooves exposing a first pattern of the bottom layer, and the second segment includes a second group of grooves exposing a second pattern of the bottom layer. The first segment and the second segment can be formed simultaneously, or one segment can be formed first (e.g., the first segment), and then another segment is formed (e.g., the second segment).

[0050] The first segment and the second segment are formed so that they do not overlap, i.e., their grooves do not spatially overlap or cover the same area of ​​the bottom layer of the substrate. The first segment and the second segment are also formed so that the open end of one of the grooves in the first group of grooves (belonging to the first segment of the mask) faces the open end of one of the grooves in the second group of grooves (belonging to the second segment of the mask). The open ends are separated by a portion of the amorphous mask. That is, this portion of the mask acts as an initial barrier between the open ends of the grooves facing each other. This Figure 5 and 5A This is schematically illustrated in the example of Figure 5 , the groove 502a of the first group of grooves (belonging to the first section of the mask) faces the groove 502b of the second group of grooves (belonging to the second section of the mask). The separation of the grooves is highlighted by the dashed box. In this example, the open end of the groove 502b of the second group of grooves faces the open end of the groove 502c of the third group of grooves (belonging to the third section of the mask). Similarly, in Figure 5A In FIG. 5 , trenches 502a of a first set of trenches 504a (belonging to the first section of the mask) face trenches 502b of a second set of trenches 504b (belonging to the second section of the mask).

[0051] Amorphous materials cannot sustain epitaxial growth. That is, they inhibit growth in the region on the substrate where they are deposited, whereas growth can continue on a crystalline substrate with the mask open.

[0052] Typically, the first section and the second section may be the same size or different sizes. The first section and the second section may be the same shape or different shapes.

[0053] exist Figure 1 In the example of FIG. 1 , a patterned layer of amorphous material 102 (amorphous mask) is formed on top of substrate 104. Side and top views of substrate 104 with amorphous mask 102 are shown in FIG. Figure 1 The left side of is shown. The substrate 104 can be formed of any suitable substrate material, such as InP (indium phosphide), and is an insulating substrate in the described example. In the described example, the mask material 102 is an oxide, but it can be any amorphous material that promotes SAG in the second stage II of the fabrication method (see below).

[0054] The amorphous mask or oxide layer 102 is patterned in such a way that the oxide layer 102 is formed so as to expose the trenches (or narrow strips) of the substrate in the desired areas 106 (i.e. not covered by the mask 102). In this context, the pattern refers to the structure of the desired areas 106, which will eventually become the structure of the nanowire network, since it is the exposed areas 106 in which the SE nanowires are grown. Thus, the size and structure of the nanowires match the size and structure of the exposed areas 106. Although in Figure 1Only one exposed region 106 is shown, nanowires can be grown simultaneously in multiple regions, and all descriptions related to the desired region 106 apply equally to multiple such regions. Thus, the structure of the entire nanowire network can be defined by the structure of the (multiple) exposed regions, which themselves are defined by the structure of the trenches of each segment of the mask. In this example, the strips and the resulting nanowires have a width on the order of tens or hundreds of nanometers.

[0055] The amorphous mask 102 may be formed so as to expose the desired regions 106 in any suitable manner. For example, a uniform, continuous layer of amorphous material (such as an oxide layer) may be deposited on the substrate 104 or other underlying layer, and the exposed regions 106 may then be formed by selectively etching away the amorphous mask 102 from the desired regions 106 (in this case, it is the photolithography and subsequent etching that define the final nanowire network structure). As another example, using a mask, an insulating material 102 may be selectively deposited on the substrate 104 to prevent material (e.g., oxide) 102 from being deposited in the desired regions 106 (in this case, it is the mask that defines the final nanowire network structure). The oxide 102 may be, for example, silicon oxide (SiO x ). More generally, other suitable amorphous materials may be used.

[0056] In the second phase II (semiconductor growth phase, or SAG phase), semiconductor material 108 is grown in the first and second groups of trenches that expose the underlying layer of the substrate. In the case where the underlying layer is the substrate itself, semiconductor material 108 grows on the exposed portion of the substrate. The growth of semiconductor material is initiated in each group of trenches. The selectively grown semiconductor material forms a first sub-network and a second sub-network of nanowires in each trench of the plurality of groups of trenches. Each sub-network of nanowires may include one or more nanowires. Figure 5 As shown in the example of , each segment comprises a single trench, and thus each corresponding sub-network comprises a single nanowire. In contrast, in Figure 5A In the example of , each segment includes a plurality of trenches, and thus each corresponding sub-network includes a plurality of nanowires.

[0057] Return to reference Figure 1 In the example of FIG. 1 , semiconductor material 108 is selectively grown in the desired region 106 , on top of the exposed portion of substrate 104 . Figure 1, where a side view of the substrate 104 is shown. Due to the patterning of the amorphous mask 102, the selectively grown semiconductor 108 forms an in-plane nanowire (i.e., the nanowire grows from the opening as a whole; the growth starts in the z direction, across the entire set of openings defined in the xy plane). The semiconductor material 108 can be, for example, indium arsenide (InAs), indium antimonide (InSb), or any other semiconductor with a relatively large spin-orbit and G-factor, or a collection of more than one material (a heterostructure composed of multiple materials). The SAG semiconductor 108 can be, for example, a confined 2DEG (two-dimensional electron gas) semiconductor or a single material semiconductor.

[0058] SAG is a growth method. SAG refers to the local growth of semiconductors in exposed areas of a substrate, where growth conditions are selected to prevent such growth on the amorphous mask itself. For example, this can be based on chemical beam epitaxy (CBE), molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD). In the context of semiconductors, SAG can refer to a type of epitaxial semiconductor growth (also known as selective area epitaxy) in which a patterned amorphous mask is used to define the intended structure of the semiconductor material to be grown (a form of lithography). Epitaxy refers to the technique of using a first crystal as a seed, thereby growing a second crystal on the first crystal. In SAG, the process is adjusted so that semiconductor growth occurs only on areas of the substrate that are not covered by the amorphous mask 102, and not on the amorphous mask itself, for example, not on the amorphous mask. This is different from other deposition / growth processes, such as uniform deposition (epitaxial or otherwise), when no mask is used, the material is deposited uniformly across the surface regardless of its material composition (as in stage III - see below). SAG may be performed in a high or ultra-high vacuum and may require careful tuning to achieve the desired selective semiconductor growth.

[0059] Any suitable SAG process can be used in the second stage II to create the desired SE nanowires in the exposed region 106. The SAG nanowires are defined by the high symmetry in-plane crystal orientation along the substrate, which also gives well-defined nanowire facets. This makes the SU / SE interface flat (potentially, atomically flat) and well defined.

[0060] SAG itself is known, so it will not be discussed in further detail herein. For reference, see Aseev P. et al., Selectivity Map for Molecular Beam Epitaxy of Advanced III-V Quantum Nanowire Networks, DOI: 10.1021 / acs.nanol ett.8b03733, https: / / pubs.acs.org / doi / 10.1021 / acs.nanol ett.8b03733. For a further description of SAG, see, for example, the references of GJ Davies, M Fahed, and Fukui et al. cited above.

[0061] It can be said that the semiconductor growth phase (i.e., SAG phase II) is such that (at the end of this phase) the semiconductor material 108 fills the desired region 106 (i.e., the region 106 of the underlying layer or substrate 104 not covered by the mask 102) but does not substantially extend (in the plane of the underlying layer or substrate 104 (hereinafter referred to as the xy-plane)) beyond the boundaries of the desired region 106 as defined by the mask 102. In some cases, it may extend outward in a direction orthogonal (perpendicular) to the plane of the underlying layer or substrate 104 (hereinafter referred to as the z-direction) so as to protrude outward from the mask 102. That is, the semiconductor material 108 extends from the underlying layer or substrate 104 a greater distance than the mask 102 in the z-direction. In this way, the semiconductor material 108 forms nanowires that are substantially located in the plane of the underlying layer or substrate 102 (in-situ nanowires).

[0062] Once the first and second subnetworks of nanowires are formed, they are joined to form a single nanowire network. As the sum of the subnetworks, the nanowire network is therefore larger than each of the subnetworks. This allows large-scale networks to be built from smaller subnetworks. The joining of subnetworks can occur naturally. That is, during (or at the end of) the semiconductor growth phase, by lateral growth of the semiconductor, the subnetworks can merge. In other words, the previously separated open ends of the trenches facing each other extend laterally to merge with each other. An example of this phenomenon is shown in Figure 6 is shown in . Figure 6 The top image in the middle illustrates a 30 μm trench 602 that was only partially filled during nanowire growth. The bottom image illustrates three separate 10 μm trenches 604a, 604b, 604c that were completely filled during nanowire growth. This image was taken before merging the trenches. The enlarged image shows the first and second subnetworks of nanowires before merging.

[0063] Alternatively, the first sub-network and the second sub-network may be joined after the semiconductor growth stage (but before any superconductor growth stage, if any). The sub-networks may be connected using an electrical conductor, such as a metal lead or material. That is, the open ends of the separated trenches are connected with a conductive material.

[0064] However, the subnetwork is bonded onto the amorphous mask. That is, the lateral extension of the semiconductor causes the semiconductor material to grow on a portion of the mask that acts as a barrier between the open-ended trenches. Alternatively, an electrical conductor is placed on this portion to connect the open-ended trenches.

[0065] The nature of the SAG process is that the larger a structure grows, the more susceptible it is to forming defects in the form of threading dislocations or similar types of defects. By dividing into segments with intentional breaks in the mask, this attracts defect formation to the vicinity of the intentional breaks and prevents unintended defects from forming elsewhere. This therefore enables control of defects and the formation of any superstructure of arbitrary size.

[0066] During the semiconductor growth phase, several types of semiconductor materials can be grown to form a stack (heterostructure). In an optional third phase III (superconductor growth phase), one or more layers of superconductor material 112 can be grown on at least a portion of the nanowire network. In some examples, other materials (e.g., dielectrics) can be grown. Figure 1 In the example of, a layer of superconducting material is grown using a particle beam 110. Herein, a superconducting material refers to a material that exhibits superconducting properties under at least certain conditions. An example of such a material is aluminum (Al). Alternatively, superconductor material 112 may be niobium (Nb), titanium nitride (TiN) or any other s-wave superconductor. In the following example, a superconductor is epitaxially grown in stage III, and superconductor growth stage III may be referred to as an epitaxial growth stage in this context. However, the technology is not limited to this aspect, and it may be possible to achieve the desired result via non-epitaxial superconductor growth in stage III.

[0067] Superconducting material 112 may be grown in stage III using, for example, molecular beam epitaxy (MBE) or electron beam evaporation.

[0068] At least a portion of the superconductor layer 112 is deposited on top of the SE nanowire 108 such that the portion of the superconductor layer 112 ( Figure 1 The semiconductor layer 108 of the nanowire is directly in contact with the SE 108 of the nanowire, that is, the semiconductor 108 of the nanowire is at least partially covered with the superconducting material.

[0069] This is also a form of epitaxy, but it is not SAG. In particular, in the epitaxial growth stage III, epitaxial growth does occur on the amorphous mask 102 (or dielectric layer), as well as on the SE 108 of the nanowire.

[0070] In some examples, after the growth of one or more layers during stage III, one or more layers of semiconductor material may be grown again.

[0071] In one possible technique, the beam can be angled substantially in the z-direction (the direction perpendicular to the plane of the substrate) such that substantially all of the exposed surfaces of the amorphous mask 102 and the SE material 108 are covered by the SU layer 112. However, in another example as shown, the particle beam 110 is incident on the substrate 104 at a non-zero angle of incidence (deposition angle) relative to the z-direction. As a result of this non-zero deposition angle and the protruding structure of the SE core 108 of the nanowire, the SE of the nanowire is only partially coated with the superconductor layer 112; that is, a portion of the SE nanowire core (labeled as 118) is not coated with the superconductor material. The bulk of the amorphous mask 102 is also coated with the superconductor layer 112, however, due to the angle of the incident beam 110 and the protruding structure of the SE nanowire core 108, a small area (the shaded area) of the amorphous mask 102 adjacent to the protruding SE nanowire 108 is exposed, i.e., is not coated with the SU material. One such shaded area is at Figure 1 The shaded region 120 separates the SE material 108 from a portion of the SU layer 112 in the "side gate" region 122. The portion of the SU layer 112 in the side gate region 122 can be used to form a gate for controlling the nanowires, or (more likely) the SU material can be etched away from this region and replaced with a more suitable gate material. Either way, the shaded gap 120 ensures that the gate operates as expected. Using this "in situ" patterning to form the gap 120 in the SU epitaxy stage III (described above) ensures that material does not need to be etched too close to the delicate nanowires 108.

[0072] The SAG stage II and the superconductor growth stage III can be performed in a vacuum chamber, preferably without moving the substrate 104 between stages. These stages can be achieved under high vacuum or ultra-high vacuum conditions, and these vacuum conditions can be maintained between stages. In addition, this ensures a clean SE / SU interface without unwanted impurities.

[0073] Both the SAG semiconductor growth in stage II and the superconductor growth in stage III require carefully calibrated conditions to enter the corresponding "growth windows" for the two stages to achieve the desired semiconductor and superconductor growth, respectively. Depending on the material type, the growth conditions, temperature and flux are selected. For example, for MBE (which can be used in both semiconductor SAG stage II and superconductor growth stage III), the substrate is usually heated to a temperature of about 500°C or higher to clean the native oxide on the surface. However, in the SE SAG growth stage II and the SU growth stage III, the corresponding temperature windows for the desired growth to occur depend on the composition of the SE material 108 and the SU material 112, respectively. Superconductors can be grown / deposited in situ without breaking the vacuum. In this way, the surface of the SAG is not oxidized in the air and remains clean until the SU is connected, which ensures a clean SE-SU interface.

[0074] The substrate (or bottom layer of the substrate) 104 on which the SE / SU nanowire network is grown and the mask 102 can be incorporated into a final product (such as a quantum circuit or quantum computer) along with the SE / SU nanowire network without transferring the nanowires from the substrate on which the nanowires were originally fabricated.

[0075] In general, as opposed to making a large structure in its entirety, arrays of smaller structures are made, which are then interconnected into a large structure. This can be done by placing mask openings close to each other and allowing the nanostructures to merge during the growth process. This allows large networks to be made without the need for additional materials to connect the structures. This is particularly advantageous for structures where it is critical to maintain the same collection of materials across the entire nanowire network, such as in quantum computing.

[0076] The masking phase may include: 1. depositing an amorphous mask overlying a crystalline substrate, 2. photolithographically defining the locations of all trenches so that the trenches are placed close to each other to achieve segmentation, 3. removing the masking material inside the trenches to open the crystalline material of the substrate to be exposed for epitaxy. 4. growth. The growth phase may include epitaxial growth of the nanowire network.

[0077] The growth stage may utilize metal source selective area growth (MS SAG). MS SAG is a three-step process. During step (i), indium (In) is grown at an elevated temperature T (i) The deposition is carried out under the mask to collect In only inside the mask openings and avoid its accumulation on the mask surface. This is possible due to the higher desorption rate of In adatoms from the amorphous mask compared to the crystalline substrate surface. During step (ii), the substrate is cooled below the critical temperature T (ii) ≤T crit, for the subsequent conversion of In into InSb supplying only Sb flux. Note that despite the fact that only Sb flux is supplied externally, growth still proceeds under the local In-rich regime around the droplet as a metal reservoir. During step (iii), the substrate temperature is raised to T (iii) , at which temperature selective InSb growth can be performed using simultaneously supplied In and Sb fluxes.

[0078] In some examples, the initial selective In deposition of step (i) is at about T (i) =465℃,F In =0.16ML IbSb / s, t = 10 min. These conditions favor selectivity. During step (ii), In is converted to InSb only under the Sb flux at about T (ii) =360℃,F Sb =0.22ML InSb The process is performed under the conditions of t = 10 min and t = 10 min. These conditions are favorable for nucleation. Although the selectivity is not favorable under these conditions, the growth of InSb occurs only inside the mask, because In atoms are present only there and their probability of propagating to the mask is low. During step (iii), the SAG of InSb using the simultaneous supply of In and Sb fluxes at an elevated substrate temperature is approximately T (iii) =430℃,F In =0.03ML InSb / s,F Sb =0.38ML InSb / s, t = 60min. These conditions are favorable for selectivity. Here, T is the substrate temperature, F In and F Sb is in ML per second InSb / s, the fluxes of In and Sb measured in the grown equivalent 2D monolayer, and t is the duration of each step.

[0079] Embodiments of the disclosed technology include topologically protected quantum computing circuits that include nanowire networks formed using such hybrid semiconductor and superconductor regions. Figure 2A and Figure 2B In FIG. 1 , a wire pattern consisting of InAs nanowires grown on an insulating GaAs substrate is shown. In particular, Figure 2A and Figure 2B The fabrication of complex networks based on one-dimensional nanowire networks is shown.

[0080] As previously described, selective area growth (SAG) of nanowire networks can be used to produce Majorana-based topological qubits (which utilize the formation of superconducting islands) in which some portions are topological (T) and some portions are non-topological (e.g., conventional s-wave (S)). The SAG technique can provide a high degree of control over the shape of the device produced and is therefore very useful in producing components used in scalable topological quantum computing. In an example embodiment, one or more Majorana zero-mode MZMs can be induced in at least one nanowire of a nanowire network by cooling the superconductor to a superconducting temperature and applying a magnetic field to the device.

[0081] The examples described herein are understood to be illustrative examples of embodiments of the present invention. Further embodiments and examples are contemplated. Any feature described with respect to any one example or embodiment may be used alone or in combination with other features. In addition, any feature described with respect to any one example or embodiment may also be used in combination with one or more features of any other example or embodiment, or any combination of any other example or embodiment. In addition, equivalents and modifications not described herein may also be adopted within the scope of the present invention, and the scope of the present invention is defined by the claims.

Claims

1. A method for making a quantum device, the method comprising: In a masking stage, a first section of an amorphous mask is formed on a bottom layer of a substrate, wherein the first section includes a first set of trenches exposing the bottom layer; In the masking stage, a second section of the amorphous mask is formed on the bottom layer, wherein the second section includes a second group of grooves exposing the bottom layer, wherein the first section and the second section are non-overlapping, and wherein an open end of one of the grooves in the first group faces an open end of one of the grooves in the second group, but the two open ends are separated by a portion of the amorphous mask; In a semiconductor growth stage, a semiconductor material is grown in the first group of trenches and the second group of trenches by selective area growth to form a first sub-network and a second sub-network of nanowires on the bottom layer; as well as The first sub-network and the second sub-network of nanowires are joined to form a single nanowire network on the bottom layer.

2. The method of claim 1, wherein the joining comprises: During the semiconductor growth phase, merging occurs by lateral growth of the semiconductor material.

3. The method of claim 1, wherein the joining comprises: In a stage subsequent to the semiconductor growth stage, the open end of the one trench in the first group of trenches is connected to the open end of the one trench in the second group of trenches via an electrical conductor or a superconductor. The method of claim 1 , wherein the bottom layer is a wafer of the substrate. 5 . The method of claim 1 , wherein the open ends of the first set of first trenches are separated from the open ends of the second set of first trenches at an inactive region of the nanowire network.

6. The method of claim 1, wherein the first and second networks of trenches are formed by etching the amorphous mask from the underlying layer.

7. The method of claim 1, wherein the respective patterns of the trenches in the first set of trenches and the second set of trenches are defined by photolithography.

8. The method of claim 1 , wherein the growing of the semiconductor material comprises: depositing respective droplets of a first material in the first set of grooves and the second set of grooves; Then, a second material is deposited to convert the first material into the semiconductor material.

9. The method of claim 8, wherein the first material is indium, wherein the second material is antimony, and wherein the semiconductor material is indium antimonide.

10. The method of claim 1, wherein the semiconductor material is grown by epitaxy or evaporation.

11. The method according to claim 1, comprising: In a superconductor growth phase, a layer of superconductor material is grown on at least a portion of the nanowire network.

12. The method of claim 1, wherein the layer of superconductor material is applied using a particle beam.

13. The method of claim 12, wherein the layer of superconductor material is grown by epitaxy.

Images