Improvements in PWM Synchronization Methods and Devices

Abstract

Disclosed is a method for synchronizing an image sensor with a PWM driver operable to drive an arrangement associated with the image sensor, wherein at least one synchronization signal generated by the image sensor is used to reset the PWM driver, and the at least one synchronization signal is delayed before being used to reset the PWM driver such that the turn-on or turn-off of the at least one synchronization signal occurs at a defined time with respect to a sensitive period of operation of the image sensor.

Description

Technical Field

[0001] This application generally relates to delivering power to a shape memory alloy (SMA) actuator. In particular, the present invention relates to delivering power in a controlled manner in a system employing an SMA actuator, which system further includes an image sensor. Background Art

[0002] Systems that include an image sensor tend to be particularly vulnerable to problems associated with electromagnetic interference (EMI). In this regard, images generated by an image sensor exposed to EMI may encounter problems, which may include noise on the generated image. The noise can take the form of one or more visible lines in the image. In certain modes, one or more lines can move across the image in a distracting manner, and this can significantly degrade the image and reduce the user experience.

[0003] This problem is particularly acute in battery-powered devices, as these devices tend to operate with a limited power budget. This has led to the widespread use of pulse width modulation (PWM) techniques, which can improve efficiency but result in increased EMI.

[0004] A specific but non-limiting example of a device that employs PWM techniques and an image sensor is a mobile phone equipped with a camera, whereby image stabilization and / or focusing is achieved with the aid of a shape metal alloy actuator.

[0005] Such a system is shown in Figure 1 in Figure 1 which shows a plan view of the arrangement of shape memory alloy (SMA) actuator wires in an actuator 10. The actuator 10 can be incorporated into any device that includes at least one component that needs to be moved during operation. For example, the actuator 10 can be used to move an optical element of an image capture device, but this is a non-limiting example. The actuator 10 can be incorporated into, for example, a smart phone, a mobile computing device, a laptop computer, a tablet computing device, a security system, a gaming system, an augmented reality system, an augmented reality device, a wearable device, a medical device, a drug delivery device, a drone (air, water, underwater, etc.), a vehicle (e.g., a car, an airplane, a spaceship, a submersible, etc.), and an autonomous vehicle. It should be understood that this is a non-exhaustive list of example devices into which the present actuator can be incorporated. In some cases, miniaturization can be an important design criterion for the actuator.

[0006] In use, the actuator 10 may include a component 2 that needs to be moved. The component 2 may be supported on a support structure 4 by a suspension system in such a way that allows the component 2 to move relative to the support structure 4 in two orthogonal directions, each direction being perpendicular to the main axis P. In operation, the component 2 may move perpendicular to the main axis P in two orthogonal directions, as shown by X and Y.

[0007] In an embodiment, the actuator 10 may include four shape memory alloy (SMA) actuator wires 11 to 14 each connected to the support structure 4 and a movable member 15 for moving the component 2 that needs to be moved. (It should be understood that this is just an example arrangement of an SMA actuator, and the present technology is applicable to actuators having at least two SMA actuator wires). Each of the SMA actuator wires 11 to 14 is kept in tension, thereby applying a force between the movable platform 15 and the support block 16 in a direction perpendicular to the main axis P. In operation, the SMA actuator wires 11 to 14 move the component 2 relative to the support block 16 in two orthogonal directions perpendicular to the main axis P. The SMA actuator wires 11 to 14 each extend perpendicular to the main axis P. In this actuator 10, the SMA actuator wires 11 to 14 may extend in a common plane, which may be beneficial for minimizing the size of the actuator 10 along the main axis P (e.g., the total height or depth of the actuator 10).

[0008] Whether the SMA actuator wires 11 to 14 are perpendicular to the main axis P or are inclined at a small angle with respect to a plane perpendicular to the main axis P, the actuator 10 can be made very compact, especially in the direction along the main axis P. In some embodiments, the SMA actuator wires 11 to 14 may be very thin, typically about 25 μm in diameter, to ensure rapid heating and cooling. The arrangement of the SMA actuator wires 11 to 14 does not increase the footprint of the actuator 10 and can be made very thin in the direction along the main axis P because the SMA actuator wires 11 to 14 are substantially placed in a plane perpendicular to the main axis P, in which plane they remain operative. Then, the height along the main axis may depend on the thickness of other components (such as the crimping members 17 and 18) and the height allowed for manufacturing. In practice, it has been found that the actuator arrangement of the SMA actuator wires 11 to 14 can be manufactured to a height of less than 1 mm. In the example of a smartphone camera, the size of the SMA actuator wires 11 to 14 typically limits the angle between the SMA actuator wires 11 to 14 and the plane perpendicular to the main axis P to less than 20 degrees, and more preferably less than 10 degrees.

[0009] The SMA actuator wires 11 to 14 are connected at one end to the movable platform 15 via respective crimping members 17 and at the other end to the support block 16 via crimping members 18. The crimping members 17 and 18 crimp the wires to mechanically hold the wire (optionally strengthened by using an adhesive). The crimping members 17 and 18 also provide an electrical connection to the SMA actuator wires 11 to 14. However, any other suitable means for connecting the SMA actuator wires 11 to 14 may be optionally used.

[0010] The SMA material has the property that the SMA material undergoes a solid-state phase change when heated, which causes the SMA material to contract. When one of the SMA actuator wires 11 to 14 is heated, the stress therein increases and it contracts. This causes the movement of component 2. Conversely, when one of the SMA actuator wires 11 to 14 is cooled such that the stress therein is reduced, the SMA actuator wire expands under the action of a force from the opposite SMA actuator wire among the SMA actuator wires 11 to 14. This causes component 2 to move in the opposite direction.

[0011] As Figure 1 shown, the SMA actuator wires 11 to 14 have the following arrangement around the main axis P. Each of the SMA actuator wires 11 to 14 is arranged along one side of component 2. Thus, the SMA actuator wires 11 to 14 are arranged in a ring at different angular positions around the main axis P. Thus, the four SMA actuator wires 11 to 14 consist of a first pair of SMA actuator wires 11 and 13 arranged on opposite sides of the main axis P and a second pair of SMA actuator wires 12 and 14 arranged on opposite sides of the main axis P. The first pair of SMA actuator wires 11 and 13 can be selectively driven to move component 2 relative to the support structure 4 in a first direction in the plane, and the second pair of SMA actuator wires 12 and 14 can be selectively driven to move component 2 relative to the support structure 4 in a second direction transverse to the first direction in the plane. Movement in directions other than parallel to the SMA actuator wires 11 to 14 can be driven by a combination of the actuation of these pairs of SMA actuator wires 11 to 14 to provide a linear combination of movements in the lateral direction. Another way of observing this movement is that simultaneous contraction of any pair of the SMA actuator wires 11 to 14 adjacent to each other will drive component 2 in the direction (diagonally in Figure 1 as shown by arrows X and Y) that bisects the two of the SMA actuator wires among the SMA actuator wires 11 to 14.

[0012] Thus, the SMA actuator wires 11 to 14 can be selectively actuated to move the component 2 to any position within the movement range in two orthogonal directions perpendicular to the main axis P relative to the support structure 4. The size of the movement range depends on the geometry and contraction range of the SMA actuator wires 11 to 14 within their normal operating parameters.

[0013] The position of the component 2 perpendicular to the main axis P relative to the support structure 4 is controlled by selectively changing the temperature of the SMA actuator wires 11 to 14. This is achieved by passing a selectively actuating current that provides resistive heating through the SMA actuator wires 11 to 14. The heating is provided directly by the actuating current. Cooling is provided by reducing or stopping the actuating current to allow the component 2 to cool by conduction, convection, and radiation to its surrounding environment.

[0014] The drive signal supplied to the SMA actuator wires is obtained using PWM technology, and the close proximity of the SMA actuator wires to the image sensor can cause the aforementioned EMI problems. Summary of the Invention

[0015] An object of embodiments of the present technology is to solve the above problems and other problems.

[0016] According to a first method of the present technology, a method of synchronizing an image sensor with a PWM driver is provided, the PWM driver being operable to drive an arrangement associated with the image sensor, wherein at least one synchronization signal generated by the image sensor is used to reset the PWM driver, and at least one synchronization signal is delayed before being used to reset the PWM driver such that the turn-on or turn-off of at least one synchronization signal occurs at a defined time with respect to a sensitive period of operation of the image sensor.

[0017] In an embodiment, at least one synchronization signal is delayed such that its turn-on or turn-off occurs outside the sensitive period of operation of the image sensor.

[0018] In an embodiment, the amount of delay varies according to the duty cycle of at least one synchronization signal.

[0019] In an embodiment, the duration of at least one synchronization signal remains unchanged.

[0020] In an embodiment, the pulses of at least one synchronization signal are shortened or lengthened such that its turn-on or turn-off occurs outside the sensitive period of operation of the image sensor.

[0021] In an embodiment, the subsequent pulses of at least one synchronization signal are respectively lengthened or shortened by a time period that substantially corresponds to the shortened or lengthened time period of the previous pulse.

[0022] In an embodiment, at least one synchronization signal is delayed such that its turn-on or turn-off occurs within a sensitive period of operation of the image sensor.

[0023] In an embodiment, at least one synchronization signal is one or more of a frame synchronization signal VSYNC and a line synchronization signal HSYNC.

[0024] In an embodiment, at least one synchronization signal generated by the image sensor is divided before being used to reset the PWM driver.

[0025] According to a second method of the present technology, a non-transitory data carrier is provided that carries control code to implement the method of the first method.

[0026] According to a third method of the present technology, a device is provided that is arranged to perform the method of the first method.

[0027] As will be understood by those skilled in the art, the present technology can be embodied as a system, a method, or a computer program product. Thus, the present technology can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects.

[0028] Furthermore, the present technology can take the form of a computer program product embodied in a computer-readable medium having computer-readable program code embodied thereon. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing items.

[0029] The computer program code for performing the operations of the present technology can be written in any combination of one or more programming languages, including object-oriented programming languages and traditional procedural programming languages. The code components can be embodied as procedures, methods, etc., and can include sub-components that can take the form of instructions or sequences of instructions at any level of abstraction from direct machine instructions of a native instruction set to high-level compiled or interpreted language constructs.

[0030] Embodiments of the present technology also provide a non-transitory data carrier carrying code that, when implemented on a processor, causes the processor to perform any of the methods described herein.

[0031] The technology also provides processor control code to implement the above methods, for example, on a general-purpose computer system or a digital signal processor (DSP). The technology also provides a carrier carrying the processor control code to implement any of the above methods at runtime (especially on a non-transitory data carrier). The code can be provided on a carrier such as a disk, a microprocessor, a CD-ROM or a DVD-ROM, a programmable memory such as a non-volatile memory (e.g., flash memory) or a read-only memory (firmware), or on a data carrier such as an optical signal carrier or an electrical signal carrier. The code (and / or data) for implementing embodiments of the technology described herein can include source, object, or executable code in a conventional programming language (interpreted or compiled) such as C or assembly code, code for setting up or controlling an ASIC (application-specific integrated circuit) or an FPGA (field-programmable gate array), or code for a hardware description language such as Verilog (RTM) or VHDL (very high speed integrated circuit hardware description language). As will be recognized by those skilled in the art, such code and / or data can be distributed among multiple coupled components that communicate with each other. These technologies can include a controller that includes a microprocessor, a working memory, and a program memory coupled to one or more components of the system.

[0032] It will also be apparent to those skilled in the art that all or part of the logical methods according to embodiments of the present technology can be suitably embodied in a logic device including logic elements for performing the steps of the above methods, and such logic elements can include, for example, components such as logic gates in a programmable logic array or an application-specific integrated circuit. Such a logic arrangement can be further embodied in enabling elements to temporarily or permanently establish a logical structure in such an array or circuit using, for example, a virtual hardware description language, which can be stored and transmitted using a fixed or transportable carrier medium.

[0033] In an embodiment, the present technology can be implemented in the form of a data carrier having functional data thereon, the functional data including functional computer data structures to enable the computer system to perform all steps of the above methods when loaded into the computer system or network and thus operated thereon. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Embodiments of the present technology will now be described by way of example only with reference to the drawings, in which:

[0035] Figure 1 A typical SMA actuator arrangement known in the art is shown;

[0036] Figure 2 A schematic diagram of a synchronization arrangement according to an embodiment of the present technology is shown;

[0037] Figure 3 Parts (a) to (c) thereof show timing diagrams illustrating various embodiments of the present technology; and

[0038] Figure 4 Parts (a) to (b) thereof show other timing diagrams illustrating various embodiments of the present technology;

[0039] Figure 5 shows the typical positions of particularly sensitive regions in a timing diagram associated with the operation of an ADC in an image sensor according to an embodiment of the present technology;

[0040] Figure 6 shows a timing diagram associated with an embodiment of the present technology that utilizes power accounting; and

[0041] Figure 7 shows a timing diagram associated with another embodiment of the present technology that utilizes calibration techniques. DETAILED DESCRIPTION

[0042] In a system as Figure 1 shown, PWM technology is employed to generate a drive signal for an SMA actuator wire, and the EMI associated with the drive signal can cause interference / noise in the image signal, which can take the form of one or more lines that appear to move on a display screen showing an image captured by an image sensor.

[0043] The aim of the embodiment is to minimize the interference caused by the lines, and one means of achieving this is to synchronize the main clock (MCLK) signal used to time the image sensor with the PWM drive signal (PWM FREQ).

[0044] This is shown in Figure 2 where an image sensor 100 is shown. As Figure 1 shown, the SMA actuator arrangement 10 is physically adjacent to the image sensor 100. The SMA actuator 10 is driven by a plurality of individual lines that supply signals / power to each individual wire 11 to 14. These signals come from the PWM driver 110 and are the cause of the EMI experienced by the image sensor 100, as indicated by the dashed arrows radiating from the signal lines and the actuator 10 to the image sensor 100.

[0045] The PWM driver 110 generates signals for the actuator according to a scheme controlled by a controller (not shown). The clock signal used to generate these signals is PWM FREQ, which is obtained from a phase-locked loop (PLL) 120. The input to the PLL 120 is the MCLK generated by the master oscillator 130. The MCLK is also used to time the image sensor 100.

[0046] The PLL 120 is used to maintain a known frequency ratio M / N between the main clock input MCLK of the image sensor 100 and the PWM drive frequency PWM FREQ. M and N are integers.

[0047] In practice, designers of devices such as mobile phones typically do not have in-depth knowledge of the operation of the image sensor 100, so it is usually impossible to determine which PWM frequencies are most likely to have an adverse effect on the operation of the image sensor 100. Thus, one approach is to sweep through all possible PWM frequencies and empirically determine which frequencies contribute the most noise to the final image. Then, taking this knowledge into account, the PWM frequencies can be configured so that the image degrades as little as possible.

[0048] The adverse effects may depend on the specific operating mode, so the operating mode and PWM frequency can be considered when determining the optimal PWM frequency in any particular case.

[0049] Better performance can be obtained by employing an additional synchronization reference. In Figure 2 the PWM driver 110 receives the VSYNC input from the VSYNC output terminal of the image sensor 100. It should be noted that even if the MCLK is not used to synchronize the operation of the image sensor and the PWM driver, which may not be possible in all embodiments, then using the VSYNC (or a similar signal) as described below results in improved performance.

[0050] The image sensor 100 generates a synchronization pulse VSYNC at the start of each new image frame. The VSYNC can be referred to as a frame synchronization signal. This VSYNC signal is used to reset the PWM driver 110. This ensures a fixed relationship between the edges of the PWM switch signal supplied to the actuator 10 and the image.

[0051] As Figure 3 shown in part (a) of Figure 3 shown in part (b) of Figure 3 shown in part (c) of

[0052] Figure 3 The up pulse shown in

[0053] Figure 3 is the VSYNC and is related to the three embodiments (a) to (c) shown. Figure 1 The timing pulses shown in each of parts (a) to (c) of Figure 3The signals SMA0 to SMA3. The exact details of the signal forms shown on each wire are not important for understanding the embodiments of the present technology. It is sufficient to know that the signals are applied sequentially to each wire, where the pulse duration is determined in particular according to the movement required by the actuator.

[0054] Along Figure 3 The numbers in the dashed boxes at the bottom of each of the (a) to (c) parts of represent the time slot counts, that is, the sequential counts of the individual time slots corresponding to the signals applied to any one SMA wire.

[0055] The number of PWM time slots included in the PWM subframe is the same as the number of wires in the actuator. In this example, there are four wires in the actuator, so there are four time slots in the subframe. In other examples, there may be other numbers (e.g., eight) of wires and time slots.

[0056] In Figure 3 Part (a) of, an embodiment of the present technology is shown using time slot synchronization. In other words, when the rising edge of the VSYNC signal is received, the current PWM drive time slot (slot 26 in this example) is reset. It can be seen that this causes time slot 26 and the corresponding wire (SMA2) to be driven again immediately after the VSYNC event. Thereafter, the sequence of time slots continues in order. There is no specific relationship between VSYNC and the wire driven when received, so there is also no specific relationship between VSYNC and the wire driven immediately after reception.

[0057] Figure 3 Part (b) of shows another embodiment of the present technology. This embodiment uses subframe synchronization. In other words, when the rising edge of the VSYNC signal is received, the PWM drive is reset to the start of the current subframe. In this example, the VSYNC is received partially through the subframe starting from time slot 24. After the VSYNC is received, time slot 24 is driven again, and then the PWM driver 110 continues to drive the time slots sequentially.

[0058] By using this embodiment, it can be ensured that the same wire (in this case SMA0, but it can be any wire) is always driven first after the VSYNC event. In fact, due to the physical layout of the image sensor and actuator arrangement, each of the SMA actuator wires can have a different impact on the image noise. By synchronizing with SMA0 (or any other wire) in a controlled manner, it is ensured that the power transmission PWM sequence is the same after each VSYNC event, which means that the synthesized image noise is static within the image frame. Static image noise is less likely to be recognized by the human eye, so it is not a big problem in practice.

[0059] Figure 3Part (c) of this shows yet another embodiment of the present technology. This embodiment uses a so-called servo frame synchronization. A servo frame is a time period that defines the interval between resistance measurement events in the SMA actuator system. Again, it is not necessary to fully understand this. It is sufficient to know that a servo frame contains multiple PWM sub-frames.

[0060] In this example, VSYNC is received partially through sub-frames starting from time slot 24. When the VSYNC pulse is received, the sub-frame count is reset to 0, which is the start of the servo frame period. At the very beginning of the servo frame period, in time slot 0, a resistance measurement event occurs on SMA0; and in time slot 1, a resistance measurement event occurs on SMA1, and so on. For each wire in the actuator, these resistance measurement events typically occur once in each servo frame.

[0061] By using this particular embodiment, it can be ensured that the same wire is always driven after each VSYNC event, and the resistance measurement events occur at known times within each image frame. This is advantageous because image sensors are typically more sensitive to EMI during a specific time period, which may be unknown to the designers using such image sensors. Therefore, delaying the PWM pulses for resistance measurement runs the risk of moving the switching edges to a more sensitive area. Thus, if this behavior is consistent with VSYNC, the synthetic image noise will be static within the image frame and thus less noticeable.

[0062] In the above, the rising edge of the VSYNC signal has been referred to. Of course, the falling edge or a change in level can equally be used to indicate the start of a new image frame.

[0063] Furthermore, using VSYNC as a signal indicating the start of a new image frame uses terms common in the field of image sensors. However, other reference signals are also available, and embodiments of the present technology are not intended to be limited by such terms, or even by VSYNC indicating the start of a new image frame. Other reference signals can be used as needed, including reference signals indicating the end of the current frame or any other point between the start and end of the frame. Such reference signals can indicate the timing of internal events of the image sensor.

[0064] An example of another reference signal provided by some image sensors indicates the image capture timing of the analog-to-digital converter (ADC) inside the image sensor.

[0065] There is another reference signal called HSYNC. This signal typically indicates the start of a new line in the image and can be called a line synchronization signal. Thus, for an image consisting of n lines, the image sensor will generate n HSYNC signals for each VSYNC signal. Therefore, the frequency of HSYNC is n times the frequency of VSYNC.

[0066] HSYNC can be used to reset the PWM driver in a manner similar to that already described for VSYNC. This ensures synchronization between the edges of the PWM signal and image capture.

[0067] In a typical SMA actuator system, the PWM frequency is in the range of 20 kHz to 500 kHz, and the HSYNC frequency is typically in the range of 40 kHz to 200 kHz. Thus, the generation of the PWM can be synchronized with the HSYNC signal of the image sensor.

[0068] There are multiple options for achieving this. For example, if the HSYNC and PWM signals cannot be operated at the same frequency or they are asynchronous, then the PWM time slots or sub - frames can be reset based on a divided - down and delayed version of HSYNC. This divided - down and delayed version of HSYNC is referred to herein as SYNC, and Figure 4 Two embodiments of the present technique utilizing the SYNC signal are shown.

[0069] Figure 2 Shows how HSYNC is output from the image sensor 100 and input into the PWM driver 110. In practice, any division and delay of HSYNC can be performed inside the PWM driver 110 or in an external device such as another PLL. However, for conceptual purposes, HSYNC or a modified version of it is provided from the image sensor and provided to the PWM driver 110.

[0070] In Figure 4 the above three waveforms respectively show HSYNC (whose frequency is similar to the PWM frequency), a divided - down version of HSYNC, and a delayed version of this signal. The delay value δ is selected such that any particularly sensitive time periods during the operation of the image sensor can be avoided. In some cases, it can be δ = 0, or a value determined from data related to the image sensor or through empirical measurements.

[0071] In an embodiment, synchronizing to a delayed version of VSYNC may also be useful, in which case Figure 3 the VSYNC event shown can be delayed, and this delayed signal can be used for synchronization purposes.

[0072] Figure 4 Part (a) of Figure 3 is similar to the embodiment shown in part (a) of in that the SYNC pulse here is used to trigger the reset of the PWM driver on a time - slot basis. In other words, upon receiving the SYNC signal, the PWM driver resets such that the active time slot at the time of SYNC reception is re - created, and subsequent time slots are generated sequentially.

[0073] Figure 4 Part (b) of Figure 3 The similarity between the embodiment shown in part (b) of this and that of Figure 3 is that here the SYNC pulse is used to trigger the reset of the PWM driver on a sub-frame basis, such that when the SYNC signal is received, the active sub-frame at that time is recreated. Here, when the SYNC signal is received, the sub-frame starting from time slot 24 is recreated, and subsequent time slots are generated sequentially.

[0074] The internal operation of the ADC has been mentioned above, and at certain points, the ADC can be more vulnerable to EMI than usual. These points can be related to certain operations of the ADC, Figure 5 which has been illustrated.

[0075] Generally, users of image sensors may not be very familiar with the internal operation of the device, especially not with the internal timing of the various operations that occur. In some cases, users may not want to know such internal operations. However, as described herein, in some cases, it is desirable to understand the internal operation so that the timing of signals near the image sensor can be controlled in a way that can avoid or at least mitigate any adverse effects that may adversely affect its performance.

[0076] Figure 5 The operation of the ADC inside the image sensor 100 is shown. The type of ADC used in some image sensors is called a correlated double sampling (CDS) ADC. This type of device takes two samples. The first is a calibration phase where a particular pixel is in a reset state, and the second is a measurement phase where a particular pixel is in an exposure state. The sensor is operable to subtract the reset value from the exposure value to calculate the actual intensity of the light falling on the pixel.

[0077] The trace above (CDS ADC ramp) shows the two samples and the association with HSYNC as shown by the second trace. HSYNC is associated with the operation of the CDS ADC in a deterministic manner.

[0078] The third trace shows areas that are particularly sensitive and are aligned with the ramp operation of the CDS ADC. To avoid adverse effects on the operation of the ADC, it is desirable to avoid PWM switching during these periods.

[0079] Figure 5The following three traces illustrate various ways of arranging the PWM switching according to the relative duty cycle of the PWM pulses under discussion. In the first of these traces, a low duty cycle pulse (duty cycle < a, where a is a predefined value) is shown. Here, the desired pulse is delayed by a time δ such that the rising edge of the pulse just appears outside the sensitive region. In this case, the falling edge also falls outside the sensitive region.

[0080] The second of the following three traces shows a medium duty cycle pulse, where the duty cycle = a. Here, the entire pulse, including the rising and falling edges, is arranged to appear between two of the sensitive regions. This avoids any switching (i.e., edges) during the sensitive period.

[0081] In the third of the following three traces, a high duty cycle pulse (where the duty cycle > a) is shown. In this case, the pulse is arranged to straddle at least one of the sensitive regions. In the example shown, the rising edge of the pulse appears before the first sensitive region, and the pulse continues such that it overlaps with two sensitive regions in total, and its falling edge appears before the third sensitive region.

[0082] Assuming that switching can be avoided in the sensitive region, then a pulse that has a high state simultaneously with the sensitive region is immaterial.

[0083] As Figure 5 shown, regardless of the absolute length (or duty cycle) of a particular pulse, it can always be positioned by an appropriate delay (if required) such that its rising or falling edge avoids the sensitive region.

[0084] Figure 6 Another embodiment is shown that utilizes a technique known as "power accounting". In an embodiment of this technique, the length of time that a particular actuator wire is activated is important, but the relative timing of this activation can be varied without adversely affecting the overall system operation. In this way, if a pulse edge is scheduled to occur during the sensitive period, the edge in question is delayed until after the sensitive period. The pulse under discussion still ends at the originally scheduled time. As a result, the pulse duration is shorter than planned. This will result in a power debit on the particular wire. In a subsequent power pulse applied to that wire, the debit can be cleared by applying a pulse that is extended to account for the previous debit.

[0085] In Figure 6 it, trace (a) shows a number of pulses that are desired to be applied to an actuator wire. The edges of these pulses are all outside the sensitive region, so trace (e) shows the actual pulses applied to that wire. These are the same as the desired pulses.

[0086] Trace (b) shows a plurality of pulses that are desired to be applied to the actuator wire. It can be seen that the fourth pulse among these pulses has a falling edge located in the sensitive region. Therefore, in the actual pulse shown in trace (f), a power credit represented by “+1” is applied, which causes the pulse in question to be extended such that the falling edge avoids the sensitive region. To account for the power credit that now exists for this wire, the next pulse in the sequence is shortened by a time equal to the added time applied to the fourth pulse. This is represented by the “0” shown for the fifth pulse, which indicates that the power credit has been cancelled.

[0087] Trace (c) shows that the falling edge of the first pulse in the desired pulse sequence is located in the sensitive region. Therefore, in trace (g), this pulse is extended as described above. The result of this power credit is again shown by the “+1” for the first pulse in trace (g). To account for this credit, the second pulse in trace (c) is completely removed in trace (g), as indicated by the “0” where it would otherwise appear.

[0088] Trace (d) shows a pulse sequence where the rising edge of the third pulse is located in the sensitive region. Therefore, the rising edge is delayed, as indicated by the “-1” for the third pulse in trace (h). This means a power debit on this wire. To account for this, the next pulse is extended by the same amount that the previous pulse was shortened. This is indicated by the “0” for the fourth pulse in trace (h), and it can be seen that this pulse is longer than the corresponding pulse in trace (d).

[0089] These examples show how power credits and debits are applied and accounted for. In these examples, any debit or credit is considered in the next possible pulse, but this is not always possible and it may be necessary to consider any debit or credit in a later pulse. Ideally, any such accounting should be done as soon as possible after the debit or credit, as the expected heating (and length) of the relevant wire may otherwise be affected.

[0090] The amount of debit or credit applied to a particular wire can be a freely variable amount, or it can also be defined in time units. In both cases, a tally is kept for each wire of the accumulated debit or credit for accounting in subsequent pulses.

[0091] Figure 7Another embodiment of the present technology is shown which utilizes a different approach to switching in the sensitive region. In this embodiment, rather than avoiding switching in the sensitive region, pulses are generated to force switching in the sensitive region. Although at first glance this may seem contradictory, by utilizing the CDS cycle (which is the period between the calibration phase and the measurement phase of the CDS ADC) and ensuring that switching occurs during each of these phases, the effects of switching in the sensitive region can be counteracted. In fact, any errors introduced during the calibration phase will also be introduced during the measurement phase, and since the final output is the difference between these two readings, errors introduced by switching will not affect the result.

[0092] In a multi-wire actuator system, it may not be possible or desirable for all wires to switch during the sensitive period, so only a subset of the wires may be switched in this manner, while the other wires utilize one of the aforementioned techniques. Of course, the wires that make up the subset may change over time.

[0093] exist Figure 7 In Figure 1, this approach is first applied on the first conductor, represented by the first trace. Here, the falling edges of the first two pulses in the sequence fall within the sensitive region. For the subsequent pulses, the pulses fall outside the sensitive region, so there is no problem. However, if Figure 7 As shown in the second trace in , the pulse timing on the second wire causes rising edges to appear in two consecutive sensitive areas.

[0094] In both cases, any errors introduced during the calibration phase are effectively eliminated during the measurement phase and therefore do not cause problems.

[0095] This can be achieved by ensuring that the CDS period and the PWM period (as shown) are configured identically.

[0096] In the foregoing embodiments, the determination of sensitive areas to avoid or minimize switching may be performed based on information provided by the sensor manufacturer. Such information may be provided in the data sheet for a given sensor. However, in most cases, it is expected that sensitive areas are more likely to be determined empirically.

[0097] To do this, the sensor needs to be operated with a known input (i.e. an object that provides input to the sensor). This can take the form of a flat area or a test card, both of which should produce a known output from the sensor. Typically, this will take place in a very (but not completely) dark environment, as this is the environment where noise is most likely to be detected. Ideally, light levels should be controlled accordingly.

[0098] Then, place the actuator or its simulator near the sensor to simulate a real-life scenario and apply switching pulses such that their effects can be observed on the output of the sensor. In this way, the interaction of specific pulses can be observed in the output of the sensor. The switching pulses can refer to one or more output signals of the sensor, such as HSYNC or VSYNC. Other output signals can be provided and any one or more of them can be used for this purpose.

[0099] Additionally or alternatively, the operation of the sensor and the determination of the sensitive area can be performed by a mathematical / physical model.

[0100] Once the determination of the sensitive area has been performed, this data can be used to control the operation of embodiments of the present technology as shown in any one or more of Figures 4 to 7 the above.

[0101] The sensor can be operable in more than one mode, possibly providing different sensitivities or pixel counts. The sensitive area can vary depending on the mode, and thus the determination of the sensitive area can depend on the mode. As mentioned above, any tests or simulations should be repeated for different operating modes of the sensor.

[0102] Embodiments of the present technology utilize VSYNC and HSYNC signals to improve the performance of an image sensor. As elaborated above, embodiments of using VSYNC or HSYNC independently have been described. However, embodiments in which both VSYNC and HSYNC are used produce additional advantages. HSYNC can be used as described above and is particularly related to Figure 4 the above. Then, VSYNC can be used to reset the PWM driver such that the servo frame is reset. As previously mentioned, the servo frame is the time period that defines the interval between resistance measurement events in the SMA actuator system. By resynchronizing the servo frame using VSYNC and the PWM driver using HSYNC, a higher degree of determinacy between the operation of the image sensor and the PWM driver can be achieved.

[0103] By using embodiments of the present technology, the adverse effects of EMI from the PWM components on the image sensor can be mitigated. In particular, the asynchronous nature of the PWM signal with any important timing signals of the image sensor produces multiple lines or stripes that appear to move on the display fed by the image sensor. At the very least, embodiments of the present technology make any such lines or stripes static, and thus they are much less intrusive and tend to be ignored by the user, whereas moving interference patterns cannot be ignored by the user.

[0104] In addition, by selecting one or more of the synchronization schemes described herein, any lines or stripes caused by EMI can be deliberately positioned in locations that do not significantly interfere with the resulting image. For example, one or more lines or stripes can be positioned at or near the extreme edges of the image, where they are less likely to disrupt the image or annoy the user.

[0105] Those skilled in the art will recognize that, although the best mode and other modes considered to be appropriate for carrying out the technology have been described above, the technology should not be limited to the specific configurations and methods disclosed in such a description of the preferred embodiments. Those skilled in the art will recognize that the technology has a wide range of applications, and embodiments can be widely modified without departing from any inventive concept defined in the appended claims.

[0106] In addition, in some embodiments, at least one synchronization signal does not need to be delayed before being used to reset the PWM driver. Accordingly, other aspects of the technology are set forth in the numbered clauses below:

[0107] 1. A method of synchronizing an image sensor with a PWM driver operable to drive an arrangement associated with the image sensor, wherein at least one synchronization signal generated by the image sensor is used to reset the PWM driver.

[0108] 2. The method according to clause 1, wherein the synchronization signal generated by the image sensor is a signal indicating an internal event in the image sensor.

[0109] 3. The method according to clause 1 or 2, wherein at least one synchronization signal is one or more of a frame synchronization signal VSYNC and a line synchronization signal HSYNC.

[0110] 4. The method according to any one of the preceding clauses, wherein at least one synchronization signal is delayed before being used to reset the PWM driver.

[0111] 5. The method according to any one of clauses 3 or 4, wherein the synchronization signal is a frame synchronization signal, and after the PWM driver has been reset, the PWM driver continues by driving a signal for one of the following: the previous time slot; the previous sub-frame; or the previous servo frame.

[0112] 6. The method according to any one of clauses 3 or 4, wherein the synchronization signal is a line synchronization signal, and after the PWM driver has been reset, the PWM driver continues by driving a signal for one of the following: the previous time slot; or the previous sub-frame.

[0113] 7. The method according to clause 5 or clause 6, wherein the line synchronization signal is used to reset the PWM driver based on a previous time slot or a previous sub-frame, and the frame synchronization signal is used to reset the PWM driver based on a servo frame.

[0114] 8. The method according to any one of the preceding clauses, wherein the main clock signal MCLK is used to drive the image sensor, and the same main clock signal is used to drive the PWM driver.

[0115] 9. The method according to clause 8, wherein the PWM driver uses a phase-locked loop to generate a PWM drive signal, and the phase-locked loop is operable to maintain a fixed frequency relationship between the main clock signal and the PWM drive signal.

[0116] 10. The method according to clause 9, wherein the fixed frequency relationship between the main clock signal and the PWM drive signal is M / N, where M and N are integers.

[0117] 11. A non-transitory data carrier carrying control code for implementing the method according to any one of clauses 1 to 10.

[0118] 12. An apparatus arranged to perform the method according to any one of the preceding clauses.

[0119] 13. An apparatus comprising an image sensor and a PWM driver, wherein the PWM driver is operable to drive an arrangement associated with the image sensor, and at least one synchronization signal generated by the image sensor is used to reset the PWM driver.

[0120] 14. The apparatus according to clause 13, wherein the arrangement associated with the image sensor is a shape memory alloy SMA actuator operable to stabilize or focus the image.

Claims

1. A method for synchronizing an image sensor with a Pulse-Width Modulation (PWM) driver, the Pulse-Width Modulation (PWM) driver being operable to drive an arrangement associated with the image sensor, wherein, at least one synchronization signal generated by the image sensor is used to reset the Pulse-Width Modulation (PWM) driver, and wherein the synchronization signal is a frame synchronization signal, and after the Pulse-Width Modulation (PWM) driver has been reset, the Pulse-Width Modulation (PWM) driver continues by driving a signal for one of the following: a previous time slot; a previous sub-frame; or a previous servo frame.

2. The method according to claim 1, wherein, at least one synchronization signal generated by the image sensor is divided in frequency before being used to reset the Pulse-Width Modulation (PWM) driver.

3. The method according to claim 1, wherein, the Pulse-Width Modulation (PWM) driver generates a Pulse-Width Modulation (PWM) drive signal, wherein the Pulse-Width Modulation (PWM) drive signal is asynchronous with the synchronization signal.

4. The method according to claim 1, wherein, the arrangement associated with the image sensor includes a plurality of Shape Memory Alloy (SMA) actuator wires, and wherein the Pulse-Width Modulation (PWM) driver generates a plurality of Pulse-Width Modulation (PWM) drive signals for independently driving the Shape Memory Alloy (SMA) actuator wires.

5. A method for synchronizing an image sensor with a Pulse-Width Modulation (PWM) driver, the Pulse-Width Modulation (PWM) driver being operable to drive an arrangement associated with the image sensor, wherein, at least one synchronization signal generated by the image sensor is used to reset the Pulse-Width Modulation (PWM) driver, and wherein the synchronization signal is a line synchronization signal, and after the Pulse-Width Modulation (PWM) driver has been reset, the Pulse-Width Modulation (PWM) driver continues by driving a signal for one of the following: a previous time slot; or a previous sub-frame.

6. The method according to claim 5, wherein, at least one synchronization signal generated by the image sensor is divided in frequency before being used to reset the Pulse-Width Modulation (PWM) driver.

7. The method according to claim 5, wherein, the Pulse-Width Modulation (PWM) driver generates a Pulse-Width Modulation (PWM) drive signal, wherein the Pulse-Width Modulation (PWM) drive signal is asynchronous with the synchronization signal.

8. The method according to claim 5, wherein, the arrangement associated with the image sensor includes a plurality of Shape Memory Alloy (SMA) actuator wires, and wherein the Pulse-Width Modulation (PWM) driver generates a plurality of Pulse-Width Modulation (PWM) drive signals for independently driving the Shape Memory Alloy (SMA) actuator wires.

9. A method for synchronizing an image sensor with a Pulse-Width Modulation (PWM) driver, the Pulse-Width Modulation (PWM) driver being operable to drive an arrangement associated with the image sensor, wherein, at least one synchronization signal generated by the image sensor is used to reset the Pulse-Width Modulation (PWM) driver, and Wherein, the at least one synchronization signal is delayed before being used to reset the pulse width modulation (PWM) driver, such that the turn-on or turn-off of the pulse width modulation (PWM) drive signal generated by the pulse width modulation (PWM) driver occurs at a defined time with respect to a sensitive period of operation of the image sensor; and The sensitive period includes a period during which electromagnetic interference associated with the pulse width modulation (PWM) drive signal causes interference or noise in the signals of the image sensor.

10. The method according to claim 9, Wherein, The at least one synchronization signal is delayed such that the turn-on or turn-off of the pulse width modulation (PWM) drive signal occurs outside the sensitive period of operation of the image sensor.

11. The method according to claim 9, Wherein, The amount of delay varies according to the duty cycle of the pulses of the pulse width modulation (PWM) drive signal.

12. The method according to claim 10, Wherein, The amount of delay varies according to the duty cycle of the pulses of the pulse width modulation (PWM) drive signal.

13. The method according to claim 10, Wherein, The pulses of the pulse width modulation (PWM) drive signal are shortened or lengthened such that the turn-on or turn-off of the pulse width modulation (PWM) drive signal occurs outside the sensitive period of operation of the image sensor.

14. The method according to claim 13, Wherein, Subsequent pulses of the pulse width modulation (PWM) drive signal are respectively lengthened or shortened by a time period that respectively corresponds to the time period by which the previous pulse was shortened or lengthened.

15. The method according to any one of claims 9-14, Wherein, The pulse width modulation (PWM) drive signal is asynchronous with the synchronization signal.

16. The method according to any one of claims 9-14, Wherein, The arrangement associated with the image sensor includes a plurality of shape memory alloy (SMA) actuator wires, and wherein the pulse width modulation (PWM) driver generates a plurality of pulse width modulation (PWM) drive signals for independently driving the shape memory alloy (SMA) actuator wires.

17. The method according to any one of claims 9-14, Wherein, At least one synchronization signal generated by the image sensor is divided in frequency before being used to reset the pulse width modulation (PWM) driver.

18. A method of synchronizing an image sensor with a pulse width modulation (PWM) driver, the pulse width modulation (PWM) driver being operable to drive an arrangement associated with the image sensor, Wherein, At least one synchronization signal generated by the image sensor is used to reset the pulse width modulation (PWM) driver, and, Wherein a master clock signal (MCLK) is used to drive the image sensor and the same master clock signal is used to drive the pulse width modulation (PWM) driver, Wherein the pulse width modulation (PWM) driver uses a phase-locked loop to generate a pulse width modulation (PWM) drive signal, the phase-locked loop being operable to maintain a fixed frequency relationship between the master clock signal and the pulse width modulation (PWM) drive signal, wherein the fixed frequency relationship between the master clock signal and the pulse width modulation (PWM) drive signal is M / N, where M and N are integers.

19. The method according to claim 18, wherein, the pulse width modulation (PWM) drive signal is asynchronous with the synchronization signal.

20. The method according to claim 18, wherein, the arrangement associated with the image sensor includes a plurality of shape memory alloy (SMA) actuator wires, and wherein the pulse width modulation (PWM) driver generates a plurality of pulse width modulation (PWM) drive signals for independently driving the shape memory alloy (SMA) actuator wires.

21. A non-transitory data carrier carrying control code for implementing the method according to any one of claims 1 - 14 or 18.

22. An apparatus comprising an image sensor and a pulse width modulation (PWM) driver, wherein, the pulse width modulation (PWM) driver is operable to drive an arrangement associated with the image sensor, wherein at least one synchronization signal generated by the image sensor is used to reset the pulse width modulation (PWM) driver, and wherein the synchronization signal is a frame synchronization signal, and after the pulse width modulation (PWM) driver has been reset, the pulse width modulation (PWM) driver continues by driving a signal for one of the following: a previous time slot; a previous sub-frame; or a previous servo frame.

23. The apparatus according to claim 22, wherein, the arrangement associated with the image sensor is a shape memory alloy (SMA) actuator operable to stabilize an image or focus an image.

24. An apparatus comprising an image sensor and a pulse width modulation (PWM) driver, wherein, the pulse width modulation (PWM) driver is operable to drive an arrangement associated with the image sensor, wherein at least one synchronization signal generated by the image sensor is used to reset the pulse width modulation (PWM) driver, and wherein the synchronization signal is a line synchronization signal, and after the pulse width modulation (PWM) driver has been reset, the pulse width modulation (PWM) driver continues by driving a signal for one of the following: a previous time slot; or a previous sub-frame.

25. The apparatus according to claim 24, wherein, the arrangement associated with the image sensor is a shape memory alloy (SMA) actuator operable to stabilize an image or focus an image.

26. An apparatus comprising an image sensor and a pulse width modulation (PWM) driver, wherein, the pulse width modulation (PWM) driver is operable to drive an arrangement associated with the image sensor, wherein at least one synchronization signal generated by the image sensor is used to reset the pulse width modulation (PWM) driver, and wherein the at least one synchronization signal is delayed before being used to reset the pulse width modulation (PWM) driver such that the turning on or off of the pulse width modulation (PWM) drive signal generated by the pulse width modulation (PWM) driver occurs at a defined time with respect to a sensitive period of operation of the image sensor; and the sensitive period includes a period during which electromagnetic interference associated with the pulse width modulation (PWM) drive signal causes interference or noise in the signals of the image sensor.

27. The apparatus according to claim 26, wherein, The arrangement associated with the image sensor is a shape memory alloy (SMA) actuator operable to stabilize or focus the image.

28. An apparatus comprising an image sensor and a pulse width modulation (PWM) driver, wherein, the pulse width modulation (PWM) driver is operable to drive an arrangement associated with the image sensor, wherein at least one synchronization signal generated by the image sensor is used to reset the pulse width modulation (PWM) driver, and wherein a main clock signal (MCLK) is used to drive the image sensor and the same main clock signal is used to drive the pulse width modulation (PWM) driver, wherein the pulse width modulation (PWM) driver uses a phase-locked loop to generate a pulse width modulation (PWM) drive signal, the phase-locked loop being operable to maintain a fixed frequency relationship between the main clock signal and the pulse width modulation (PWM) drive signal, wherein the fixed frequency relationship between the main clock signal and the pulse width modulation (PWM) drive signal is M / N, where M and N are integers.

29. The apparatus according to claim 28, wherein, the arrangement associated with the image sensor is a shape memory alloy (SMA) actuator operable to stabilize or focus the image.

Images