Memory Array and Method for Forming the Same

Abstract

This application relates to a memory array and a method for forming a memory array. A method for forming a memory array includes forming digital lines above and electrically coupling the digital lines to memory cells below them. The digital lines are laterally spaced apart from each other in a vertical cross-section. An upwardly open void space is located laterally between the adjacent digital lines in the vertical cross-section. A masking material covers the conductive material of the digital lines, the masking material being in the upwardly open void space and not sufficient to fill the upwardly open void. The masking material is removed directly above the top of the digital lines to expose the conductive digital line material and leave the masking material above the sidewalls of the conductive digital line material in the upwardly open void space. An insulating material is selectively grown relative to the masking material across the upwardly open void space from the exposed conductive digital line material to form a covered void space between the adjacent digital lines in the vertical cross-section. Structures independent of the method are disclosed.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and to methods for forming memory arrays. Background Art

[0002] Memory is a type of integrated circuit system and is used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Sense lines can interconnect memory cells in a conductive manner along the columns of the array, and access lines can interconnect memory cells in a conductive manner along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to hold or store memory with at least two different selectable states. In a binary system, the states are considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two information levels or states.

[0004] Field effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductive channel region therebetween. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory that is used extensively in modern computers and devices. For example, a modern personal computer may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and enables manufacturers to remotely upgrade devices for enhanced features.

[0006] NAND can be the basic architecture of integrated flash memory. NAND cell devices include at least one selection device coupled in series with a series combination of memory cells (wherein the series combination is generally referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement including vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuitry or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that individually include transistors.

[0007] The memory array may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks) and memory planes, such as shown and described in any of U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. The memory blocks may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact areas for individual word lines, on which vertically extending conductive vias contact to provide electrical access to the word lines. Summary of the invention

[0008] In one aspect, the present invention relates to a method for forming a memory array, comprising: forming digit lines above and electrically coupled to memory cells therebelow, the digit lines being laterally spaced apart from one another in a vertical cross-section, with an upwardly open void space laterally located between immediately adjacent digit lines in the vertical cross-section; covering conductive material of the digit lines with a masking material, the masking material being in the upwardly open void space and being insufficient to fill the upwardly open void; removing the masking material from just above the tops of the digit lines to expose conductive digit line material and leaving the masking material above sidewalls of the conductive digit line material in the upwardly open void space; and selectively growing insulating material from the exposed conductive digit line material across the upwardly open void space relative to the masking material to form a covered void space between the immediately adjacent digit lines in the vertical cross-section.

[0009] In another aspect, the invention relates to a method for forming a memory array, comprising: forming a stack comprising vertically alternating insulating layers and conductive layers, through which strings of channel material of strings of memory cells extend; forming first conductive vias above the strings of channel material and the first conductive vias are individually and directly electrically coupled to individual strings of channel material in the strings of channel material; forming digit lines directly above second conductive vias and the digit lines are electrically coupled to the second conductive vias, the second conductive vias being directly above the first conductive vias and individually and directly electrically coupled to the first conductive vias, the digit lines being laterally spaced apart from each other in a vertical cross-section, the insulating material being laterally located between immediately adjacent digit lines in the vertical cross-section. The invention relates to a method for selectively growing insulating material from the exposed digit lines across the upwardly open void spaces between the adjacent digit lines in the vertical cross-section; vertically removing at least some of the insulating material to expose the sidewalls of the conductive material of the digit lines and forming an upwardly open void space between the adjacent digit lines in the vertical cross-section; forming a masking material over the tops and sidewalls of the digit lines such that the masking material is insufficient to fill the upwardly open void space; removing the masking material from just over the tops of the digit lines to expose such tops and leaving the masking material over the sidewalls of the digit lines in the upwardly open void space; and selectively growing insulating material from the exposed digit lines across the upwardly open void space relative to the masking material to form a covered void space between the adjacent digit lines in the vertical cross-section.

[0010] In another aspect, the present invention relates to a memory array comprising: digit lines located above and electrically coupled to memory cells therebelow, the digit lines being laterally spaced apart from one another in a vertical cross-section; conductive vias located directly below and electrically coupled directly to individual ones of the digit lines; and void spaces laterally located between immediately adjacent digit lines in the vertical cross-section, the void spaces individually comprising at least one of (a) and (b), wherein (a): a top of the void space is below a top of the digit line, and (b): a bottom of the void space is above a bottom of the digit line.

[0011] In another aspect, the invention relates to a memory array comprising: digit lines located above and electrically coupled to memory cells therebelow, the digit lines being laterally spaced apart from one another in a vertical cross-section, the digit lines comprising a conductive material; conductive vias located directly below and electrically coupled directly to individual ones of the digit lines; void spaces laterally located between immediately adjacent digit lines in the vertical cross-section; and wherein at least one of (a) and (b), wherein: (a): a conductive material of a different composition than the conductive digit line material is located above and longitudinally along the sidewalls of the digit line, and (b): a semiconductive material is located above and longitudinally along the sidewalls of the digit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a portion of a substrate under processing according to an embodiment of the present invention and is passed through Figure 2 A diagrammatic cross-sectional view taken along line 1-1 in FIG.

[0013] Figure 2 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0014] Figures 3 to 5 yes Figure 1 and 2 Magnified views of various parts of .

[0015] Figures 6 to 24 is in process according to some embodiments of the present invention Figures 1 to 5 Diagrams of the structure or its parts in sequential cross-section, expansion, enlargement and / or partial views.

[0016] Figures 25 to 28 Alternative example methodological and / or structural embodiments of the present invention are presented. DETAILED DESCRIPTION

[0017] Embodiments of the present invention encompass methods for forming memory arrays, such as arrays of NAND or other memory cells, which may have at least some peripheral control circuitry under the array (e.g., under-array CMOS). Embodiments of the present invention encompass so-called "gate-last" or "replacement-gate" processes, so-called "gate-first" processes, and other processes, whether present or developed in the future, that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass memory arrays that are independent of the method of manufacture (e.g., NAND architecture). Reference Figure 1-24 A first example method embodiment is described.

[0018] Method embodiments of the present invention include forming a digit line above, and in one embodiment, the digit line is electrically coupled directly to a memory cell below it. The memory cell may have any existing or future developed memory cell configuration, such as those that are non-volatile, volatile, include a portion of a random access memory, have a reversibly programmable region, are cross-point memory cells, etc. Figures 1 to 5 An example construction 10 is shown having an array or array region 12 in which vertically extending strings 49 of transistors and / or memory cells 56 have been formed. This includes a base substrate 11 having any one or more of a conductive / conductor / conductive, semiconductive / semiconducting / semiconductive, or insulating / insulator / insulating (i.e., electrically therein) material. Various materials have been vertically formed over the base substrate 11. The materials may be Figures 1 to 5 Next to, vertically inside, or vertically outside of the depicted material. For example, other partially manufactured or fully manufactured components of the integrated circuit system may be provided somewhere above, around, or inside base substrate 11. Control circuitry and / or other peripheral circuitry for operating components within an array of vertically extending strings of memory cells (e.g., array 12) may also be manufactured, and the circuitry may or may not be completely or partially within an array or sub-array. In addition, multiple sub-arrays may also be manufactured and operated independently, sequentially, or otherwise relative to each other. As used herein, a "sub-array" may also be considered an array.

[0019] A conductor layer 16 including a conductor material 17 has been formed over substrate 11. Conductor layer 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or common source lines or plates) for controlling read and write access to transistors and / or memory cells to be formed within array 12. A stack 18 including vertically alternating insulating layers 20 and conductive layers 22 has been formed over conductor layer 16. An example thickness for each of layers 20 and 22 is 22 to 60 nanometers. An example uppermost layer 20 may be thicker / thickest compared to one or more other layers 20 and / or 22. Only a small number of layers 20 and 22 are shown, with stack 18 more likely to include dozens, a hundred, or more (etc.) layers 20 and 22. Other circuitry that may or may not be part of peripheral and / or control circuitry may be between conductor layer 16 and stack 18. For example, multiple vertical alternating layers of conductive and insulating materials of such circuitry may be below the lowest conductive layer 22 and / or above the uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between the conductor layer 16 and the lowest conductive layer 22, and one or more select gate layers may be above the uppermost conductive layer 22 (not shown). Alternatively or in addition, at least one of the depicted uppermost and lowest conductive layers 22 may be a select gate layer. Example insulating layer 20 includes insulating material 24 (e.g., silicon dioxide and / or other materials that may have one or more compositions).

[0020] A channel opening 25 has been formed (e.g., by etching) through the insulating layer 20 and the conductive layer 22 to the conductor layer 16. The channel opening 25 may taper radially inward (not shown), moving deeper into the stack 18. In some embodiments, the channel opening 25 may enter the conductor material 17 of the conductor layer 16 as shown, or may stop at the top of the conductor material (not shown). Alternatively, as an example, the channel opening 25 may stop at the top of or inside the lowest insulating layer 20. The reason for extending the channel opening 25 to at least the conductor material 17 of the conductor layer 16 is to ensure that the channel material is directly electrically coupled to the conductor layer 16 when such a connection is required without using alternative processes and structures to achieve this. An etch stop material (not shown) may be inside or on top of the conductor material 17 of the conductor layer 16 to help stop the etching of the channel opening 25 relative to the conductor layer 16 when required. Such an etch stop material may be sacrificial or non-sacrificial. As an example and for simplicity only, channel openings 25 are shown arranged in groups or columns of staggered rows of four and five openings 25 per row and arranged in laterally spaced memory blocks 58. Herein, a "block" generally includes a "sub-block." Memory blocks 58 may be elongated and oriented longitudinally, for example, along direction 55. Any alternative existing or future developed arrangements and configurations may be used.

[0021] Example memory blocks 58 are shown as being at least partially defined by horizontally elongated trenches 40 formed (e.g., by anisotropic etching) into stack 18. Trenches 40 may have respective bottoms directly against (e.g., on top or inside) conductor material 17 of conductor layer 16 (as shown), or may have respective bottoms above conductor material 17 of conductor layer 16 (not shown). Intervening material 57 is in trenches 40 in stack 18 and may provide lateral electrical isolation (insulation) between laterally adjacent memory blocks 58. This may include one or more of insulating, semiconducting, and conducting materials, and in any event may facilitate shorting of conductive layers 22 relative to each other in finished circuitry construction. An example insulating material is SiO 2 、Si 3 N 4 、Al 2 O 3 and undoped polysilicon. The intervening material 57 may include through array vias (TAVs) and is not shown.

[0022] The transistor channel material may be formed vertically in individual channel openings along the insulating layer and the conductive layer, thus including individual channel material strings that are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure that is laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cell is vertically along the individual charge blocking region. The insulating charge transfer material (e.g., a bandgap engineered structure having a nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material.

[0023] Figures 1 to 5 One embodiment is shown in which charge blocking material 30, storage material 32, and charge transfer material 34 have been formed vertically in individual channel openings 25 along insulating layer 20 and conductive layer 22. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed by, for example, depositing their respective thin layers over stack 18 and within individual channel openings 25 and subsequently planarizing such transistor materials back to at least the top surface of stack 18.

[0024] Channel material 36 is also formed vertically in channel opening 25 along insulating layer 20 and conductive layer 22 and in one embodiment includes individual operative channel material strings 53 having memory cell materials (e.g., 30, 32, and 34) with material 24 in insulating layer 20 horizontally between immediately adjacent channel material strings 53. Due to the proportions, materials 30, 32, 34, and 36 are located in the same region as the channel opening 25. Figure 1 and 2 37. Example channel material 36 includes appropriately doped crystalline semiconductor materials, such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. As shown, a stamp etch may be performed to remove materials 30, 32, and 34 from the base of channel opening 25 to expose conductor layer 16 so that channel material 36 is directly against conductor material 17 of conductor layer 16. Such a stamp etch may occur individually with respect to each of materials 30, 32, and 34 (as shown), or may occur collectively with respect to all materials after deposition of material 34 (not shown). Alternatively and by way of example only, a stamp etch may not be performed, and channel material 36 may be directly electrically coupled to conductor material 17 of conductor layer 16 via a separate conductive interconnect (not shown). Channel opening 25 is shown to include a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, a radially central portion within channel opening 25 may include void space (not shown) and / or be free of solid material (not shown). Regardless, and in one embodiment, conductive material 31 (e.g., conductive plug / via including conductive doped polysilicon) directly abuts lateral inner portion 79 in the upper portion of individual channel material strings 53. One or more of materials 30, 32, 34, and 36 may not extend to the top of conductive material 31 (not shown). Additionally and regardless, conductive material 31 may not extend to the top of stack 18 (not shown), may extend over stack 18 (not shown), and / or may extend below the bottom of uppermost layer 20 (not shown).

[0025] The example conductive layer 22 includes a conductive material 48 that is part of individual conductive lines 29 (e.g., word lines) that are also part of vertically extending strings 49 of individual transistors and / or memory cells 56. A thin insulating liner (e.g., Al2O3) may be formed prior to forming the conductive material 48. 2 O 3 The approximate location of transistor and / or memory cell 56 is Figure 5 Indicated by brackets, and some Figures 1 to 44 and 5. The conductive material 48 may be shown as having ends 50 ( 51 ) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. The conductive material 48 may be shown as having ends 50 ( 52 ) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. The conductive material 48 may be shown as having ends 50 ( 51 ) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. The conductive material 48 may be shown as having ends 50 ( 51 ) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. Figure 5 ). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be considered a memory structure 65 laterally located between control gate region 52 and channel material 36.

[0026] A charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and the individual control gate region 52. Charge blocking may have the following functions in a memory cell: in a program mode, charge blocking may prevent charge carriers from passing from the storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate, and in an erase mode, charge blocking may prevent charge carriers from flowing from the control gate into the storage material. Thus, charge blocking may be used to block charge migration between the control gate region and the storage material of an individual memory cell. The example charge blocking region as shown includes an insulator material 30. By way of further example, the charge blocking region may include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32) where such storage material is insulating (e.g., in the absence of any different composition material between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, the intersection of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any separate composition insulator material 30. Furthermore, the intersection of conductive material 48 and material 30 (if present) in conjunction with insulator material 30 may act as a charge blocking region and alternatively or additionally may act as a lateral outer region of insulating storage material such as silicon nitride material 32. Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0027] refer to Figure 6 and 7 , and in one embodiment, an insulating material 35 (e.g., silicon dioxide and / or silicon nitride) has been formed. Conductive vias 41 (e.g., first conductive vias 41) have been formed thereover and are individually and directly electrically coupled to individual channel material strings 53, e.g., through conductive material 31.

[0028] refer to Figure 8 and 9, insulating material 39 (e.g., silicon dioxide 67 and silicon nitride 68) has been formed over insulating material 35, and conductive vias 42 (e.g., second conductive vias 42) have been formed directly over it and are individually directly electrically coupled to individual first conductive vias 41. The materials / vias 31, 41, and 42 may have different compositions or the same composition relative to any two of each other. For simplicity and clarity of the drawings, materials / vias 31, 41, and 42 are shown as having the same size and shape in horizontal and vertical cross-sections and being completely aligned relative to each other, but of course this is not required. In addition, and in any case, in different horizontal and / or vertical cross-sections through the center of materials / vias 31, 41, and 42, the corresponding sizes and shapes do not need to be constant (although shown as constant).

[0029] refer to Figures 10 to 14 , a digit line 45 including a conductive material 46 has been formed directly above the second conductive via 42 and is directly electrically coupled to the second conductive via. The digit lines 45 are laterally spaced apart from each other in a vertical cross section, for example, by Fig.13 and 14 4 and 5. Insulating material 43 (e.g., silicon nitride 70 over silicon dioxide 71) is laterally located between adjacent digit lines 45 in the vertical cross section. The conductive materials of the via and digit line may have different compositions or the same composition relative to any two of each other. In addition, and by way of example only, the formation of digit line 45 and second conductive via 42 may occur substantially during the same conductive material deposition step, such as in a dual-type damascene process. For the purposes of continuing discussion, digit line 45 may be considered to include bottom 51, top 59, and sidewalls 44.

[0030] refer to Fig.15 and 16 , at least some (all shown) of insulating material 43 (not shown) has been vertically removed (e.g., by selectively timed anisotropic or isotropic etching relative to conductive material 46) to expose sidewalls 44 of conductive digit line material 46 and form upwardly open void spaces 47 between immediately adjacent digit lines 45 in vertical cross-section. In one embodiment and as shown, some insulating material 39 has been removed such that the bottom of void space 47 is below digit line bottom 51.

[0031] refer to Fig.17 and 18, masking material 54 has been formed over the top 59 and sidewalls 44 of the conductive digit line material 46 so that the masking material is insufficient to fill the upwardly open void space 47. Therefore, and in one embodiment, the conductive digit line material 46 is covered by or with the masking material 54 in the upwardly open void space 47. The void space 47 can be considered to include the corresponding base 60 between the adjacent digit lines 45 in the vertical cross-section, and in one embodiment, is also covered with the masking material 54 as shown. Some or all of the masking material 54 may remain in the finished circuit construction. Alternatively, this may eventually be removed entirely. Regardless, in one embodiment, the masking material is insulating, in another embodiment, the masking material is semiconductive (e.g., a less conductively doped semiconductor material, such as lightly doped polysilicon), and in another embodiment, the masking material is conductive (e.g., a metallic material and / or a conductively doped semiconductor material, such as heavily doped polysilicon). Any suitable material may be used. Ideally, masking material 54 is insulating and remains above sidewalls 44 of conductive digit line material 46 in the finished circuit construction, with silicon nitride, silicon dioxide, and / or aluminum oxide being some examples. Insulating materials are more desirable than semiconductive and / or conductive materials for maximizing lateral spacing between immediately adjacent digit lines 45 to minimize parasitic capacitance therebetween, assuming that some or all of masking material 54 remains in void spaces 47 in the finished circuit construction.

[0032] refer to Fig.19 and 20 , masking material 54 has been removed from just above top 59 of conductive digit line material 46 (e.g., by dry anisotropic etching and which may be performed in the absence of any masking material on top of formations 10 at least in array region 12) to expose top 59 and leave masking material 54 above sidewalls 44 of conductive digit line material 46 in upwardly open void spaces 47. In one embodiment and as shown, masking material 54 extends below bottom 51 of digit line 45 along sidewalls 77 of conductive via 42. In one embodiment and as shown, where substrate 60 is covered with masking material 54, as in Fig.17 and 18 In one embodiment, such removal may also remove masking material 54 from the center above substrate 60. In one embodiment and as shown, such removal exposes all of top 59 and leaves all of sidewalls 44 of conductive digit line material 46 covered.

[0033] refer to Figures 21 to 24 , has spanned the upwardly open void space 47 ( Fig.23 and 24Insulating material 61 is selectively grown from exposed conductive digit line material 46 (not specified as such in the embodiment) to form covered void spaces 62 between immediately adjacent digit lines 45 in the vertical cross-section. Any existing or future developed method may be used that enables the selective growth of insulating material 61 from conductive digit line material 46 relative to masking material 54. One skilled in the art is able to select such selective deposition techniques, and exposed portions of masking material 54 and / or conductive digit line material 46 may need to be treated prior to such selective growth to enable such selective growth.

[0034] As an example, silicon dioxide can be selectively deposited relative to tungsten. Specifically, the silicon dioxide surface can first be inhibited from growing silicon dioxide by exposure to (N,N-dimethylamino)-trimethylsilane (DMATMS) or bis(N,N-dimethylamino)-dimethylsilane (DMADMS), hexamethyldisilazane (HMDS), 1H,1H,2H,2H-perfluorooctyltrichlorosilane (FOTS or PFOCTS), or (heptadecafluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane (HDFTEOS), which only bonds to hydroxyl groups to effectively functionalize the silicon dioxide surface without silicon dioxide being deposited. Thereafter, silicon dioxide (containing trace amounts of carbon) can be grown by atomic layer deposition from other surfaces that have not been functionalized (even if exposed to any of DMATMS, DMADMS, HMDS, FOTS, or HDFTEOS), for example, at a susceptor temperature of 300° C. to 500° C., a pressure of 100 to 500 torr, a TEOS flow rate of 1,000 to 20,000 sccm, and an O 3 TEOS was used under flow rate.

[0035] As another example, a spin-on dielectric (SOD) composed of perhydropolysilazane will also be selectively deposited on tungsten relative to silicon dioxide that has been first inhibited as described above. The SOD can be selectively deposited on tungsten at room temperature and then baked at 150°C. 2 In any case, after baking, it can be densified in steam at 500°C to 1,000°C.

[0036] In addition, SiH 4 and N 2 O、CO 2 and NH 3One or more of, for example, at 375° C., a pressure of 1 to 10 torr, an RF power of 100 W to 200 W, and a gas flow rate of 90 sccm to 900 sccm, selectively converting SiO to SiO2, which is first suppressed as described above, x N y Deposited on metal surfaces.

[0037] Alternatively, SiH 4 and NH 3 , for example at 400°C, 1 to 10 torr pressure, 300 W to 400 W RF power and 500 sccm to 700 sccm SiH 4 flow rate and 3,000sccm to 5,000sccm of NH 3 At a flow rate, Si is selectively converted to Si with respect to the first suppressed silicon dioxide as described above. 3 N 4 Deposited on metal surfaces.

[0038] In one embodiment and as shown, material 61 is selectively grown only from top 59 of conductive digit line material 46 because all sidewalls 44 are covered by masking material 54. In one embodiment and as shown, covered void space 62 has been formed to have a corresponding bottom 63 below bottom 51 of digit line 45. In one embodiment and as shown, covered void space 62 has been formed to have a corresponding top 64 above (i.e., higher than) top 59 of digit line 45. Fig.24 Regardless, example construction 10 is shown to include a dielectric material 85 (eg, silicon dioxide and / or silicon nitride) that has subsequently been formed on top of insulating material 61 .

[0039] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used for reference Figures 1 to 24 In the embodiments shown and described.

[0040] Of course, alternative configurations can be created. For example, and by way of example only, Fig.25 An alternative example embodiment configuration 10a is shown in which the covered void space 62a has a corresponding bottom 63a that vertically coincides with the bottom 51 of the digit line 45. The same reference numerals from the above-described embodiments have been used where appropriate, with the suffix "a" indicating certain construction differences. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0041] Fig.26Another alternative embodiment configuration 10b is shown in which the covered void space 62b has a corresponding bottom 63b above the bottom 51 of the digit line 45. The same reference numerals of the embodiments described above have been used where appropriate, with the suffix "b" indicating certain construction differences. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0042] refer to Figures 27 to 28 An alternative example method is described. Like reference numerals from the above described embodiments have been used where appropriate, with certain construction differences indicated by a suffix "c" or by a different reference numeral.

[0043] refer to Fig. 27 , this display is Fig. 20 Masking material 54 has been removed from uppermost portions 73 of sidewalls 44 of conductive digit line material 46, leaving a majority of sidewalls 44 of conductive digit line material 46 covered by masking material 54 in a vertical cross-section. In one embodiment, uppermost portions 73 of sidewalls 44 do not exceed 15% of the height of the digit line from its respective top to its respective bottom.

[0044] refer to Fig.28 , insulating material 61c has selectively grown from top 59 and uppermost sidewall portions 73 of conductive digit line material 46 across the upwardly open void space relative to masking material 54 to form covered void space 62c between immediately adjacent digit lines 45 in vertical cross-section. This can result in void space top 64c being below digit line top 59 as shown.

[0045] Alternative embodiment configurations may result from the method embodiments described above or otherwise. In any event, embodiments of the invention encompass memory arrays that are independent of the method of manufacture. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the method embodiments described above may incorporate, form and / or have any of the properties described with respect to the device embodiments.

[0046] An embodiment of the present invention includes a memory array (eg, 12) including a digit line (eg, 45) above and electrically coupled to a memory cell (eg, 56) below it. In a vertical cross section (eg, Figures 26 to 28), the digit lines are laterally spaced relative to each other. The conductive vias (e.g., 42) are directly below the digit lines and are directly electrically coupled to individual ones of the digit lines. The void spaces (e.g., 62b, 62c) are laterally located between immediately adjacent digit lines in the vertical cross-section. The void spaces individually include at least one of (a) and (b), wherein (a): the top (e.g., 64c) of the void space (e.g., 62c) is below the top (e.g., 59) of the digit line, and (b): the bottom (e.g., 63b) of the void space (e.g., 62b) is above the bottom (e.g., 51) of the digit line. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0047] An embodiment of the present invention includes a memory array (eg, 12) including a digit line (eg, 45) above and electrically coupled to a memory cell (eg, 56) below the digit line. Fig.24 4 (a) and (b) are laterally spaced from each other in a vertical cross section of the digit line and include conductive material (e.g., 46). Conductive vias (e.g., 42) are directly below the digit lines and are electrically coupled directly to individual ones of the digit lines. Void spaces (e.g., 62, 62a, 62b, 62c) are laterally located between immediately adjacent digit lines in the vertical cross section. The memory array includes at least one of (a) and (b), wherein (a): conductive material (e.g., 54) of a different composition than the conductive digit line material is over and longitudinally along the sidewalls of the digit lines, and (b): semiconductive material (e.g., 54) is over and longitudinally along the sidewalls of the digit lines. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0048] The above processing or construction may be viewed as an array with respect to components formed as a single stack or single stack of such components or within a single stack or single stack, the stack or stack being above or as part of an underlying base substrate (although a single stack / stack may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed at any location as part of the final construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / stacks may be provided or fabricated above and / or below the stacks / stacks shown in the figures or described above. In addition, the arrays of components may be the same or different in different stacks / stacks relative to each other, and different stacks / stacks may have the same thickness or different thicknesses relative to each other. Intervening structures may be provided between vertically adjacent stacks / stacks (e.g., additional circuitry and / or dielectric layers). In addition, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be fabricated individually and sequentially (eg, one on top of another), or two or more stacks / stacks may be fabricated substantially simultaneously.

[0049] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0050] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top-on", "bottom", "above", "below", "under", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate (i.e., within 10 degrees) and can be relative to the substrate processed during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" refers to a direction along the surface of the main substrate (i.e., not forming a degree with the surface) and can be referenced to the substrate during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction inclined at least 45° from just horizontal. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc., relative to a field effect transistor, refer to the orientation of the channel length of the transistor, and in operation, the current flows between the source / drain regions along the orientation. For a bipolar junction transistor, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc. refers to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or within 10° of vertical.

[0051] Furthermore, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to each other. And, the use of "above" without a preceding "directly" requires only that some portion of the stated region / material / component that is above another stated region / material / component is vertically outside of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the discussed region / material / component that is below / below another discussed region / material / component is vertically inside of the other discussed region / material / component (i.e., regardless of whether there is any lateral overlap of the two discussed regions / materials / components).

[0052] Any of the materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any case may be continuous or discontinuous over any material overlying it. When one or more example compositions are provided for any material, the material may include, consist essentially of, or consist of the one or more compositions. In addition, unless otherwise stated, each material may be formed using any suitable existing or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0053] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different composition" only requires that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when the material or region is not uniform. If the two stated materials or regions do not directly abut against each other, then in the case where such materials or regions are not homogeneous, "different composition" only requires that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when the stated materials, regions or structures are in at least some physical contact relative to each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, “over,” “on,” “adjacent,” “along,” and “against” without being preceded by “directly” encompass “directly against” as well as configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical touching contact with each other.

[0054] As used herein, region-material-components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one region-material-component to another region-material-component, and the flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0055] Any use of "rows" and "columns" herein is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along such "rows" and "columns". "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, regardless of function. Regardless, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may columns. Furthermore, rows and columns may intersect at 90° relative to each other, or at one or more other angles (i.e., other than straight angles).

[0056] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconductor / semiconductive materials. "Metallic material" is any one or combination of elemental metals, mixtures or alloys of two or more elemental metals, and any one or more conductive metal compounds.

[0057] As used herein, any use of "selective" with respect to etching, removing, removal, deposition, forming, and / or formation is such action performed on one stated material relative to another stated material acted upon in a ratio of at least 2:1 by volume. Additionally, any use of selectively depositing, selectively growing, or selectively forming is deposition, growth, or formation of one material relative to another stated material or materials for at least the first 75 angstroms in a ratio of at least 2:1 by volume.

[0058] Unless otherwise indicated, the use of "or" herein includes either and both.

[0059] Summarize

[0060] In some embodiments, a method for forming a memory array includes forming digit lines above and electrically coupled to memory cells below the digit lines. The digit lines are laterally spaced relative to each other in a vertical cross-section. An upwardly open void space is laterally located between the immediately adjacent digit lines in the vertical cross-section. The conductive material of the digit lines is covered with a masking material, the masking material being in the upwardly open void space and insufficient to fill the upwardly open void. The masking material is removed from just above the top of the digit lines to expose the conductive digit line material and leave the masking material above the sidewalls of the conductive digit line material in the upwardly open void space. Insulating material is selectively grown from the exposed conductive digit line material across the upwardly open void space relative to the masking material to form a covered void space between the immediately adjacent digit lines in the vertical cross-section.

[0061] In some embodiments, a method for forming a memory array includes forming a stack including vertically alternating insulating layers and conductive layers. A channel material string of a memory cell string extends through the insulating layer and the conductive layer. A first conductive via is formed above the channel material string and is individually and directly electrically coupled to an individual channel material string in the channel material string. A digit line is formed directly above a second conductive via and is electrically coupled to the second conductive via, which is directly above the first conductive via and is individually and directly electrically coupled to the first conductive via. The digit lines are laterally spaced relative to each other in a vertical cross section. Insulating material is laterally located between adjacent digit lines in the vertical cross section. At least some of the insulating material is vertically removed to expose the sidewalls of the conductive material of the digit line and form an upwardly open void space between the adjacent digit lines in the vertical cross section. Masking material is formed above the top and sidewalls of the digit line so that the masking material is insufficient to fill the upwardly open void space. The masking material is removed from directly above the tops of the digit lines to expose such tops and to leave the masking material above the sidewalls of the digit lines in the upwardly open void spaces. Insulating material is selectively grown from the material of the exposed digit lines relative to the masking material across the upwardly open void spaces to form covered void spaces between the immediately adjacent digit lines in the vertical cross-section.

[0062] In some embodiments, a memory array includes memory cells over which digit lines are formed and electrically coupled to memory cells below the digit lines. The digit lines are laterally spaced relative to each other in a vertical cross section. Conductive vias are directly below the digit lines and are electrically coupled directly to individual ones of the digit lines. A void space is laterally located between immediately adjacent digit lines in the vertical cross section. The void space individually includes at least one of (a) and (b), wherein (a): a top of the void space is below a top of the digit line, and (b): a bottom of the void space is above a bottom of the digit line.

[0063] In some embodiments, a memory array includes memory cells over which digit lines are formed and electrically coupled to the digit lines below. The digit lines are laterally spaced relative to each other in a vertical cross section. The digit lines include conductive material. Conductive vias are directly below the digit lines and are directly electrically coupled to individual ones of the digit lines. Void spaces are laterally located between immediately adjacent digit lines in the vertical cross section. The memory array includes at least one of (a) and (b), wherein (a): conductive material having a composition different from that of the conductive digit line material is above and longitudinally along the sidewalls of the digit line, and (b): semiconductive material is above and longitudinally along the sidewalls of the digit line.

[0064] As specified, the subject matter disclosed herein has been described in language more or less specific in terms of structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array, which includes: forming digital lines above and electrically coupling the digital lines to memory cells below them, the digital lines being laterally spaced apart from each other in a vertical cross-section, and upwardly open void spaces being laterally located between adjacent ones of the digital lines in the vertical cross-section; covering the conductive material of the digital lines with a masking material, the masking material being in the upwardly open void spaces and not sufficient to fill the upwardly open voids; removing the masking material directly above the top of the digital lines to expose the conductive digital line material and leaving the masking material above the sidewalls of the conductive digital line material in the upwardly open void spaces; and selectively growing an insulating material across the upwardly open void spaces relative to the masking material from the exposed conductive digital line material to form covered void spaces between adjacent digital lines in the vertical cross-section.

2. The method according to claim 1, which includes a string of channel materials extending through vertically alternating insulating layers and conductive layers, and the memory cells individually include: channel material of one of the string of channel materials; a gate region, which is a portion of a conductive line in one of the conductive layers; and a memory structure, which is laterally located between the gate region and the channel material of one of the string of channel materials in the one conductive layer.

3. The method according to claim 1, wherein, the upwardly open void spaces include corresponding substrates between adjacent digital lines in the vertical cross-section; the covering includes covering the substrates with the masking material; and the removing includes removing the masking material from the center of the substrates.

4. The method according to claim 1, which includes forming conductive vias directly below the digital lines and the conductive vias being directly electrically coupled to individual ones of the digital lines, and the covering includes forming the masking material extending below the bottom of the digital lines along the sidewalls of the conductive vias.

5. The method according to claim 1, wherein the masking material is insulating and remains above the sidewalls of the conductive digital line material in a finished circuit configuration.

6. The method according to claim 1, wherein the masking material is semi-conductive and remains above the sidewalls of the conductive digital line material in a finished circuit configuration.

7. The method according to claim 1, wherein the masking material is conductive and remains above the sidewalls of the conductive digital line material in a finished circuit configuration.

8. The method according to claim 1, which includes treating the masking material before the selectively growing to enable the selectively growing.

9. The method according to claim 1, wherein the removing leaves the masking material above all the sidewalls of the conductive digital line material in the vertical cross-section, and the selectively growing is only from the top of the conductive digital line material.

10. The method according to claim 1, wherein, Removing the uppermost portion of the sidewalls of the conductive digital line material that are exposed in the vertical cross-section and leaving most of the sidewalls of the conductive digital line material covered by the masking material in the vertical cross-section; Selectively growing from the top and uppermost sidewall portions of the conductive digital line material; and The covered void space has a corresponding top below the top of the digital line.

11. The method according to claim 10, comprising forming a conductive via directly below the digital line and the conductive via being directly electrically coupled to an individual digital line among the digital lines, the uppermost portion of the sidewall not exceeding 15% of the height of the digital line from its corresponding top to its corresponding bottom.

12. The method according to claim 1, comprising forming the covered void space to have a corresponding top above the top of the digital line.

13. The method according to claim 1, which comprises: Forming a conductive via directly below the digital line and the conductive via being directly electrically coupled to an individual digital line among the digital lines; and Forming the covered void space to have a corresponding bottom below the bottom of the digital line.

14. The method according to claim 1, which comprises: Forming a conductive via directly below the digital line and the conductive via being directly electrically coupled to an individual digital line among the digital lines; and Forming the covered void space to have a corresponding bottom vertically coincident with the bottom of the digital line.

15. The method according to claim 1, which comprises: Forming a conductive via directly below the digital line and the conductive via being directly electrically coupled to an individual digital line among the digital lines; and Forming the covered void space to have a corresponding bottom above the bottom of the digital line.

16. The method according to claim 1, wherein the upwardly open void space is formed by etching the insulating material between the adjacent digital lines in the vertical cross-section.

17. The method according to claim 1, comprising forming the digital line to be directly electrically coupled to the memory cell below it.

18. A method for forming a memory array, which comprises: Forming a stack including vertically alternating insulating layers and conductive layers, a channel material string of a memory cell string extending through the insulating layers and conductive layers; Forming a first conductive via above the channel material string and the first conductive via being individually directly electrically coupled to an individual channel material string among the channel material strings; Forming a digital line directly above a second conductive via, and the digital line being electrically coupled to the second conductive via, the second conductive via being directly above the first conductive via and individually directly electrically coupled to the first conductive via, the digital lines being laterally spaced apart from each other in the vertical cross-section, and insulating material being located laterally between the adjacent digital lines in the vertical cross-section; Vertically remove at least some of the insulating material to expose the sidewalls of the conductive material of the digital lines and form an upwardly open void space between the adjacent digital lines in the vertical cross-section; Form a masking material above the top and sidewalls of the digital lines such that the masking material is not sufficient to fill the upwardly open void space; Remove the masking material directly above the top of the digital lines to expose such tops and leave the masking material above the sidewalls of the digital lines in the upwardly open void space; And Selectively grow an insulating material across the upwardly open void space relative to the masking material from the exposed digital lines to form a covered void space between the adjacent digital lines in the vertical cross-section.

19. A memory array, which Comprises: Digital lines, which are above and electrically coupled to memory cells below them, and the digital lines are laterally spaced apart from each other in a vertical cross-section; Conductive vias, which are directly below and directly electrically coupled to individual ones of the digital lines; And Void spaces, which are laterally located between the adjacent digital lines in the vertical cross-section, and each of the void spaces individually includes at least one of (a) and (b), where (a): The top of the void space is below the top of the digital lines; and (b): The bottom of the void space is above the bottom of the digital lines.

20. The memory array according to claim 19, which includes (a).

21. The memory array according to claim 19, which includes (b).

22. The memory array according to claim 19, wherein the memory cells include memory cell strings, and the memory cell strings include strings of channel material.

23. The memory array according to claim 22, which includes NAND.

24. A memory array, which Comprises: Digital lines, which are above and electrically coupled to memory cells below them, and the digital lines are laterally spaced apart from each other in a vertical cross-section, and the digital lines include conductive material; Conductive vias, which are directly below and directly electrically coupled to individual ones of the digital lines; Void spaces, which are laterally located between the adjacent digital lines in the vertical cross-section; and At least one of (a) and (b), where (a): A conductive material different in composition from the conductive digital line material is above the sidewalls of the digital lines and longitudinally along the sidewalls of the digital lines; And (b): A semiconductive material is above the sidewalls of the digital lines and longitudinally along the sidewalls of the digital lines.

25. The memory array according to claim 24, which includes (a).

26. The memory array according to claim 24, which includes (b).

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