A memory array

Abstract

The application relates to the technical field of integrated circuits, and provides a memory array, each column of memory cells comprising: a plurality of memory cells arranged in a column in an arrangement direction, a first edge region of each memory cell being provided with a bit line contact and a complementary bit line contact, the plurality of memory cells comprising a memory cell pair comprising a first memory cell and a second memory cell in an adjacent relationship, a second edge region of the first memory cell and the second memory cell being connected to form a connection region, the connection region being located between the first edge region of the first memory cell and the second edge region of the second memory cell; two bit lines connected to the bit line contacts of the first memory cell and the second memory cell in a one-to-one corresponding manner; and two complementary bit lines connected to the complementary bit line contacts of the first memory cell and the second memory cell in a one-to-one corresponding manner. The technical scheme provided by the embodiment of the application can reduce the load on the bit lines and improve the running speed of an FPGA comprising the memory array.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a memory array. BACKGROUND

[0002] In an FPGA, due to a large number of functional modules and a large number of devices, the metal wiring resources are relatively scarce. As an indispensable module, the memory is usually distributed in multiple columns in the entire FPGA, and thus occupies a large number of wiring resources.

[0003] Currently, in the memory, one column of configuration bits corresponds to one column of bit lines (occupying longitudinal wiring resources). When the number of bits of each column of storage unit pairs is larger, the load of the bit line is heavier. Taking a column of 132-bit storage unit pairs as an example, there are two bit lines, and each bit line carries 132 storage units.

[0004] However, the more the load of the bit line is, the slower the running speed will be, and the functional failure will be caused after entering the 28-nm process design. SUMMARY

[0005] Embodiments of the present application provide a memory array, by arranging the bit line contact and the complementary bit line contact on both sides of the connection area of the two storage units, so that the two storage units are connected to different bit lines and complementary bit lines, the load on each bit line is reduced by half, the running speed of the storage unit pair is improved, the function and performance are guaranteed, and the wiring resources in the direction of the word line are saved by half.

[0006] In a first aspect, embodiments of the present application provide a memory array, comprising:

[0007] a plurality of storage units arranged in a column according to an arrangement direction, a first edge area of each storage unit is provided with a bit line contact and a complementary bit line contact, the plurality of storage units comprises a storage unit pair comprising a first storage unit and a second storage unit in an adjacent relationship, a second edge area of each of the first storage unit and the second storage unit is connected to form a connection area, and the connection area is located between the first edge area of each of the first storage unit and the second storage unit;

[0008] two bit lines, each of which is connected to the bit line contact of each of the first storage unit and the second storage unit in each storage unit pair in a one-to-one correspondence;

[0009] two complementary bit lines, each of which is connected to the complementary bit line contact of each of the first storage unit and the second storage unit in each storage unit pair in a one-to-one correspondence;

[0010] wherein each storage unit is connected to a word line, and the first storage unit and the second storage unit in the storage unit pair share one word line.

[0011] In the embodiment of the present application, the bit line contact and the complementary bit line contact are arranged on both sides of the connection area of the two storage units, so that the two storage units are connected to different bit lines and complementary bit lines, the load on each bit line is reduced by half, the operation speed of the pair of storage units is improved, and the function and performance are guaranteed. The number of word lines is reduced by half, so that the wiring resources in the direction of the word line are saved by half.

[0012] In a possible implementation, the plurality of storage units are arranged in a column in the arrangement direction in the manner of a first storage unit, a second storage unit, a second storage unit, and a first storage unit;

[0013] The first edge area of each of the two adjacent first storage units in the plurality of storage units is connected, so that the two adjacent first storage units share the bit line contact and the complementary bit line contact.

[0014] The first edge area of each of the two adjacent second storage units in the plurality of storage units is connected, so that the two adjacent second storage units share the bit line contact and the complementary bit line contact.

[0015] In the embodiment of the present application, the two adjacent storage units share the bit line contact and the complementary bit line contact, the splicing area is reduced, and the length of the memory array in the column direction is reduced.

[0016] In a possible implementation, the storage unit includes:

[0017] The plurality of transistors at least include two transfer transistors, two pull-down transistors, and two pull-up transistors arranged symmetrically with respect to a target center line, the target center line being a center line of the column storage unit in the arrangement direction;

[0018] The connection area includes at least the active areas on both sides of the polysilicon of the two pull-up transistors and the two pull-down transistors, away from the active area of the transfer transistor; the first edge area includes at least the active areas on both sides of the polysilicon of the two transfer transistors, away from the connection area; the active area of one of the transfer transistors in the first edge area is provided with the bit line contact, and the active area of the other transfer transistor is provided with the complementary bit line contact.

[0019] In a possible implementation, the storage unit includes:

[0020] The storage unit includes:

[0021] The first metal layer to the Nth metal layer are arranged on the plurality of transistors from bottom to top, the second metal layer is provided with two bit lines and two complementary bit lines, and N is a positive integer greater than 1;

[0022] The first insulating layer to the Nth insulating layer are arranged between the plurality of transistors, the first metal layer, and the adjacent two metal layers.

[0023] The insulating layer of the first edge region is provided with an interlayer via hole, so that the bit line is connected to the bit line contact and the complementary bit line is connected to the complementary bit line contact.

[0024] In a possible implementation, the two bit lines and the two complementary bit lines of the first memory cell and the second memory cell in the connection region are respectively connected.

[0025] The two bit lines are located on one side of the target center line, and the two complementary bit lines are located on the other side of the target center line.

[0026] In a possible implementation, the polysilicon in the pull-up transistor above the target center line is connected to the active region on the side close to the transmission transistor of the active region on both sides of the polysilicon in the pull-down transistor below the target center line through the first metal layer.

[0027] The polysilicon in the pull-up transistor below the target center line is connected to the active region on the side close to the transmission transistor of the active region on both sides of the polysilicon in the pull-down transistor above the target center line through the self-locking line in the second metal layer.

[0028] In the embodiments of the present application, the self-locking structure is formed by the interconnection of the two pull-up transistors and the two pull-down transistors, so as to buffer the data.

[0029] In a possible implementation, the polysilicon in the transmission transistor of each memory cell away from the target center line is provided with a word line contact.

[0030] The word line contacts respectively provided by the first memory cell and the second memory cell in the memory cell pair are connected to the same word line.

[0031] In a possible implementation, each memory cell in the plurality of memory cells is provided with a ground line contact and a power line contact.

[0032] The column memory cells comprise:

[0033] A ground line connected to the ground line contact provided by each memory cell;

[0034] A power line connected to the power line contact provided by each memory cell;

[0035] The first memory cell and the second memory cell in the memory cell pair share the ground line contact provided by the active region of the pull-down transistor of the connection region and the power line contact provided by the active region of the pull-up transistor; the insulating layer of the connection region is provided with an interlayer via hole, so that the power line is connected to the power line contact and the ground line is connected to the ground line contact.

[0036] In a possible implementation, the power lines are arranged in the second to i-th metal layers, the ground lines are arranged in the second metal layer, and the word lines are arranged in the second to j-th metal layers, i and j are both positive integers greater than 2.

[0037] The power lines in the second to i-th metal layers are connected to the power line contacts through the interlayer via holes arranged in the first to i-1-th insulating layers of the connection region; the word lines in the second to j-th metal layers are connected to the word line contacts through the interlayer via holes arranged in the first to j-1-th insulating layers; and the word lines, the power lines and the ground lines of the first and second memory cells in the connection region are connected respectively.

[0038] In a possible implementation, i is 4 and / or j is 5.

[0039] The ground lines are arranged on the side away from the target center line of the two bit lines and / or the two complementary bit lines.

[0040] The power lines in the second metal layer are perpendicular to the bit lines, and the power lines in the fourth metal layer are parallel to the bit lines.

[0041] The word lines in the second metal layer are parallel to the bit lines, the word lines in the fifth metal layer are perpendicular to the bit lines, and are located in the connection region.

[0042] In the embodiments of the present application, the word lines are arranged in the second to fifth metal layers, and the power lines are arranged in the second to fourth metal layers, so that the word lines and the power lines are shared.

[0043] In a second aspect, the embodiments of the present application provide an FPGA including the memory array of any of the first aspect.

[0044] The FPGA provided by the embodiments of the present application has the bit line contacts and the complementary bit line contacts arranged on the two sides of the connection region of the two memory cells, so that the two memory cells are connected to different bit lines and complementary bit lines, the load on each bit line is reduced by half, the running speed of the memory cell pair is improved, the function and performance are guaranteed, the word lines are reduced by half, and the wiring resources in the direction of the word line are saved by half. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0046] Figure 1 Layout design of the memory array provided by the embodiments of the present application (omitting the second to fifth metal layers);

[0047] Figure 1a a layout design of a transistor in Figure 1

[0048] Figure 1b a layout design of a first metal layer in Figure 1

[0049] Figure 2 a layout design of an omitted second metal layer in Figure 1

[0050] Figure 3 a layout design of an omitted third metal layer in Figure 1

[0051] Figure 4 a layout design of an omitted fourth metal layer in Figure 1

[0052] Figure 5 a layout design of an omitted fifth metal layer in Figure 1

[0053] Figure 6 a structure diagram of a 64x2 bit single decoding memory provided by the present application;

[0054] In the drawings, reference numerals:

[0055] 100 - memory cell; 101 - semiconductor substrate; 102 - active region; 103 - polysilicon; 104 - edge region; 104a - bit line contact; 104b - complementary bit line contact; 105 - connection region; 105a - ground line contact; 105b - power line contact; 110 - pair of memory cells; 111 - first memory cell; 112 - second memory cell; PG - transfer transistor; PGa - storage node; PGb - word line contact; PD - pull-down transistor; PU - pull-up transistor; Pua - active region contact; Pub - self-locking contact; L1 - center line of the arrangement direction of the column memory cells; L2 - reference direction; M1 - first metal layer; M2 - second metal layer; M2a - self-locking line; M3 - third metal layer; M4 - fourth metal layer; M5 - fifth metal layer. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly and completely below in combination with specific embodiments and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. ​​​​​​

[0057] In addition, the terms "first", "second", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated order of limiting the features. Thus, features defined with "first", "second" can explicitly or implicitly include one or more of the features. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized.

[0058] In a first aspect, the embodiments of the present application provide a memory array, each row storage unit in the memory array is connected to a word line, each column storage unit is connected to two bit lines, two complementary bit lines, a ground line and a power line. It should be understood that the number of ground lines and power lines can be set according to actual needs, and the embodiments of the present application do not make specific limitations, and the following will be described by taking two ground lines and one power line as an example. In practical applications, the memory array can include a plurality of column storage units, and the embodiments of the present application do not make specific limitations, and the specific needs are determined according to actual needs. Since the structure of each column storage unit is the same, the following will be described by taking one column storage unit. Figure 1 The embodiments of the present application provide a layout design of a memory array. Please refer to Figure 1 Any column storage unit in the memory array includes a plurality of storage units 100, and the plurality of storage units 100 are arranged in a column in the direction indicated by L1. The plurality of storage units 100 include a storage unit pair 110 composed of a first storage unit 111 and a second storage unit 112 in an adjacent relationship. The first storage unit 111 is connected to a bit line and a complementary bit line, and the second storage unit 112 is connected to another bit line and another complementary bit line. In other words, a bit line and a complementary bit line are connected to the first storage unit 111 in each storage unit pair 100, and another bit line and another complementary bit line are connected to the second storage unit 112 in each storage unit pair 100, so that the load on each bit line is reduced by half, thereby improving the operating speed of the storage unit pair and guaranteeing its function and performance. Each storage unit 100 is connected to a word line, the first storage unit 111 and the second storage unit 112 share a word line, in other words, the two row storage units where the first storage unit 111 and the second storage unit 112 are located share a word line, so that the wiring resources in the direction of the word line are saved by half. The first storage unit 111 and the second storage unit 112 in the storage unit pair 100 share a power line and are respectively connected to two ground lines. In other words, a power line is connected to each storage unit 100, and two ground lines are respectively connected to each storage unit 100.

[0059] The working principle of the memory array will be described below:

[0060] When a write operation is performed on the memory array, a word line is selected by the row address decoder, at least two memory cells 100 connected with the word line are selected by the column address decoder, at least two read-write circuits connected with the at least two memory cells 100 are controlled in a write state, and data at the input-output end is written into the at least two memory cells 100 through the at least two read-write circuits.

[0061] When a read operation is performed on the memory array, a word line is selected by the row address decoder, at least two memory cells 100 connected with the word line are selected by the column address decoder, at least two read-write circuits connected with the at least two memory cells 100 are controlled in a read state, and data in the at least two memory cells 100 connected with the at least two read-write circuits is read out to the input-output end through the at least two read-write circuits.

[0062] It should be understood that when one of the word lines is selected by the address decoder, the word line is at a high level, and all the memory cell pairs connected with the word line are turned on, and then the bit line and the complementary bit line perform read-write operation on the memory cell pairs connected therewith and turned on through the read-write circuit pair.

[0063] Figure 6 A structure diagram of a 64*2bit single-decoding memory provided in the present application includes a 6-line-64-line address decoder, a memory array, and read-write control.

[0064] When a read operation is performed on the memory, the six-bit address code A0-A5 is sent to the address decoder to select a word line, and then the transistors of the first memory cell 111 and the second memory cell 112 connected with the word line are turned on. Then the read-write circuit is controlled in a read state, and data in the first memory cell 111 and the second memory cell 112 connected with the selected word line is sent out to I / O1-I / O2.

[0065] When a write operation is performed on the memory, the six-bit address code A0-A5 is sent to the address decoder to select a word line resource, and then the transistors of the first memory cell 111 and the second memory cell 112 connected with the word line are turned on. Then the read-write circuit is controlled in a write state, and data at the I / O1-I / O2 end is written into the first memory cell 111 and the second memory cell 112 connected with the selected word line.

[0066] It should be noted that in the embodiments of the present application, the read-write mode of the FPGA configuration memory with a single-decoding structure is described, which cannot be understood as a limitation of the present application. The present application is also applicable to the address decoding memory with a double-decoding structure.

[0067] In the embodiments of the present application, one word line is shared by two rows of storage units, thereby saving a large amount of horizontal wiring resources; meanwhile, the first storage unit 111 and the second storage unit 112 in each storage unit pair are connected to different bit lines, thereby reducing the load of the bit lines, making the storage speed of the memory array faster and the reliability stronger.

[0068] Each storage unit pair 110 has the same structure, and the overall structure of the storage unit pair 110 will be described below by means of specific embodiments. For ease of description, two bit lines are provided, which are BL0 and BL1, two complementary bit lines are provided, which are BLB0 and BLB1, two ground lines are provided, which are VSSD0 and VSSD1, a power supply line is provided, which is VC, and a word line is provided, which is WL. The following description will be made by taking BL0, BL1, BLB0, BLB1, VSSD0, VSSD1, VC, and WL as examples. Meanwhile, BL0 and BLB0 are connected to the first storage unit 111, and BL1 and BLB1 are connected to the second storage unit 112.

[0069] Figure 1a A layout design of a transistor of a storage unit is provided for the embodiments of the present application, in order to clarify the features of the present application, Figure 1a The first to Nth metal layers and the first to Nth insulating layers are not shown. For ease of description, the following description will be made in more detail by taking the reference direction L2 and the center line L1 of the row storage units along the arrangement direction as examples.

[0070] Please refer to Figure 1a The first storage unit 111 includes at least an edge region 104 and a connection region 105, and the second storage unit 112 includes at least an edge region 104 and a connection region 105. The first storage unit 111 and the second storage unit 112 are connected together through the connection region 105. It should be understood that the first storage unit 111 and the second storage unit 112 share the active region in the connection region 105; the connection region 105 can be understood as a region located on the opposite side of the edge region 104 of the storage unit 100, in other words, the connection region 105 and the edge region 104 are located on both sides of the center line of the storage unit 100 along the L2 direction.

[0071] In a feasible implementation, in order to realize that the first storage unit 111 and the storage unit 20 are connected to different bit lines and complementary bit lines, the active region in the edge region 104 of each of the first storage unit 111 and the second storage unit 112 is provided with a bit line contact 104a and a complementary bit line contact 104b. Among them, the bit line contact 104a in the edge region 104 of the first storage unit 111 is connected to BL0, and the complementary bit line contact 104b is connected to BLB0; the bit line contact 104a in the second edge region 104 of the second storage unit 112 is connected to BL1, and the complementary bit line contact 104b is connected to BLB1, so that the load connected by one bit line is reduced by half, thereby improving the operating speed of the storage unit pair and guaranteeing its function and performance.

[0072] In order to reduce the splicing area while ensuring that the first storage unit 111 and the second storage unit 112 can be connected to different bit lines, please refer to Figure 1 In a feasible implementation, the plurality of storage units 100 are arranged in a column in the direction indicated by L1 according to the arrangement mode of the first storage unit 111, the second storage unit 112, the second storage unit 112, and the first storage unit 111, and the adjacent two first storage units 111 share the bit line contact 104a and the complementary bit line contact 104b provided on the active region connected thereto, and the adjacent second storage units 112 share the bit line contact 104a and the complementary bit line contact 104b provided on the active region connected thereto.

[0073] In order to ensure the separation of the bit lines while reducing the length of the column storage unit in the longitudinal direction, the ground line contact 105a and the power line contact 105b are provided on the active region of the connection region 105. The first storage unit 111 and the second storage unit 112 share the ground line contact 105a, the first storage unit 111 is connected to VSSD0 and VSSD1 through the ground line contact 105a, and the second storage unit 112 is also connected to VSSD0 and VSSD1 through the ground line contact 105a, thereby separating the bit lines and the complementary bit lines of the two storage units while realizing the connection of VSSD0 and VSSD1 of the two storage units. The first storage unit 111 and the second storage unit 112 share the power line contact 105b, the first storage unit 111 is connected to VC through the power line contact 105b, and the second storage unit 112 is also connected to a VC through the power line contact 105b, further ensuring that the bit lines and the complementary bit lines of the two storage units can be separated while realizing the connection of VC of the two storage units.

[0074] In this embodiment, by placing bit line contacts and complementary bit line contacts on both sides of the connection area between two memory cells, the two memory cells are connected by different bit lines and complementary bit lines. This reduces the load on each bit line by half, thereby improving the operating speed of the memory cell pair and ensuring its functionality and performance. Reducing the number of word lines by half also saves half the wiring resources in the word line routing direction. By having adjacent memory cells share bit line contacts and complementary bit line contacts, the splicing area of ​​the memory cell pair is reduced, and the length of the column memory cell in the column direction is reduced.

[0075] The above is a description of the storage cell 110 in this application. Since the structures of the first storage cell 111 and the second storage cell 112 are similar, the only difference being the connecting bit lines and complementary bit lines, the following will be based on the above... Figure 1a The storage unit 110 described herein will be described in detail below, and the first storage unit 111 involved in this application will be described in detail below.

[0076] Figure 1a The layout of the active region 102 and the polysilicon 103 is shown. The active region 102 is... Figure 1a The rectangular area filled with a slash ("\") is polysilicon 103. Figure 1a The area is a long rectangular region perpendicular to L1, filled with a grid pattern. Please continue to refer to [the relevant documentation]. Figure 1a The first memory cell 111 includes: a semiconductor substrate 101, a transfer transistor PG, a pull-down transistor PD formed on the semiconductor substrate 101, and first to Nth metal layers stacked from bottom to top on the transfer transistor PG, the transfer transistor PG, and the pull-down transistor PD. Figure 1a (The first to Nth metal layers are not shown). The semiconductor substrate 101 includes silicon, and other exemplary components include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, germanium, and / or other suitable materials. Metal layers are typically used for better metal wiring. The value of N needs to be set according to the actual wiring requirements; optionally, N is 5, and the following description will use N=5 as an example. The transfer transistor PG, pull-down transistor PD, and pull-up transistor PU are each symmetrically distributed with L1. It should be understood that the connection region refers to the active region shared by the first memory cell 111 and the second memory cell 112, and the first to Nth metal layers connected together; the first edge region refers to the active region on the left side of the polysilicon in the two transfer transistors PG in the first memory cell 111, and the first to Nth metal layers connected together.

[0077] Figure 1b It shows Figure 1 The structure of the first metal layer M1 in the reference. Figure 1a Continue to refer toFigure 1b The transfer transistor PG, the pull-down transistor PD, and the pull-up transistor PU of the first storage unit 111 above the L1 are described.

[0078] The active region between the polysilicon 103 in the transfer transistor PG and the pull-down transistor PD is shared; the active region left to the polysilicon in the pull-up transistor PU is connected to the active region shared between the transfer transistor PG and the pull-down transistor PD through the first metal layer M1. Of course, in actual application, the connection of the active region can also be made through other metal layers besides the first metal layer M1, which is not specifically limited in the embodiments of the present application, and the specific needs are determined in combination with the actual needs. It should be understood that the pull-up transistor PU is P-type heavily doped, N-well, and P-type high threshold voltage transistor identification to make electrodes, and the pull-down transistor PD and the transfer transistor PG are N-type heavily doped and N-type high threshold voltage transistor identification to make electrodes.

[0079] The transfer transistor PG is connected to BL0, and is provided with a bit line contact 104a, a storage node PGa, and a word line contact PGb. Among them, the bit line contact 104a is arranged in the active region left to the polysilicon in the transfer transistor PG. It should be understood that the active region left to the polysilicon in the transfer transistor PG is made into a drain. In other words, BL0 is connected to the drain of the transfer transistor PG through the bit line contact 104a and the first metal layer M1. The storage node PGa is arranged in the active region right to the polysilicon in the transfer transistor PG. The word line contact PGb is arranged on the polysilicon outside the active region in the transfer transistor PG. It should be understood that the polysilicon in the transfer transistor PG is made into a gate. In other words, WL is connected to the gate of the transfer transistor PG through the word line contact PGb and the first metal layer M1.

[0080] The pull-down transistor PD is connected to VSSD0, and is provided with a ground line contact 105a. The ground line contact 105a is arranged in the active region right to the polysilicon in the pull-down transistor PD. It should be understood that the active region right to the polysilicon in the pull-down transistor PD is made into a source. In other words, VSSD0 is connected to the source of the pull-down transistor PD through the ground line contact 105a and the first metal layer M1.

[0081] The pull-up transistor PU is connected to VC and is provided with a power line contact 105b, an active region contact PUa, and a self-locking contact PUb. The power line contact 105b is located in the active region on the right side of the polysilicon in the pull-up transistor PU. It should be understood that the active region on the right side of the polysilicon in the pull-up transistor PU forms the active electrode. In other words, VC is connected to the source of the pull-up transistor PU through the power line contact 105b and the first metal layer M1. The active region contact PUa is located in the active region on the left side of the polysilicon in the pull-up transistor PU. The active region on the left side of the polysilicon in the pull-up transistor PU is connected to the active region shared by the transmission transistor PG and the pull-down transistor PD through the active region contact PUa and the first metal layer M1. The self-locking contact PUc is located on the polysilicon in the pull-up transistor PU. It should be understood that a gate is formed on the polysilicon in the pull-up transistor PU.

[0082] It should be understood that the transmission transistor PG, pull-down transistor PD, and pull-up transistor PU of the first memory cell 111 below and above L1 have the same structure. The only difference is that the transmission transistor PG in the first memory cell 111 below L1 is equipped with a complementary bit line contact 104b. BLB0 is connected to the drain of the transmission transistor PG through the complementary bit line contact 104b and the first metal layer M1. The pull-down transistor PD below L1 is connected to VSSD1. The transmission transistor PG, pull-down transistor PD, and pull-up transistor PU of the first memory cell 111 and the second memory cell 112 have the same configuration. The difference is that the bit line contact 104a of the transmission transistor PG above L1 in the second memory cell 112, located on the right side of the active region of the polysilicon, is connected to BL1, and the complementary bit line contact 104b of the transmission transistor PG above L1, located on the right side of the active region of the polysilicon, is connected to BLB1.

[0083] In practical applications, the two pull-down transistors PD and two pull-up transistors PU in the first storage cell 111 form a self-locking structure, thereby achieving data caching. For a feasible implementation, please refer to... Figure 1a and 1b The polysilicon in the pull-up transistor PU above L1 is connected to the active region on the left side of the polysilicon in the pull-down transistor PD below L1 through the self-locking contact PUb and the first metal layer M1. Figure 2 It shows Figure 1 For the layout design of the second metal layer (not shown), please refer to [reference needed]. Figure 1a and Figure 2The polysilicon in the pull-up transistor PU2 below L1 is connected to the active region on the left side of the polysilicon in the pull-down transistor PD above L1 via its self-locking contact PUb and the self-locking line M2a in the second metal layer M2. Alternatively, self-locking lines can be provided in other metal layers; this embodiment does not specifically limit this, and the metal layer for providing the self-locking lines needs to be determined based on the actual situation.

[0084] It should be noted that the polysilicon in the pull-up transistor PU above L1 and the pull-up transistor PU below L1 is separated by a partition layer in the middle of the same circuit. Figure 1 (Not shown in the image).

[0085] The wiring of the first to fifth metal layers in the first storage cell 111 and the connection relationship between different metal layers will be described in more detail next.

[0086] Figures 2 to 5 They are shown respectively Figure 1 The layout design of the second metal layer M2 to the fifth metal layer M5 is omitted. Please refer to [reference needed]. Figures 2 to 5 In one possible implementation, VSSD0, BL0, BL1, BLB0, BLB1, and VSSD1 are disposed in the second metal layer M2, WL is disposed in the second metal layer M2 to the fifth metal layer M5, and VC is disposed in the second metal layer M2 to the fourth metal layer M4. Two word lines are disposed in the second metal layer M2 to the fourth metal layer M4. For ease of distinction, these two word lines are designated WL01 and WL02, and the following description will use WL01 and WL02 as examples. Specifically, WL01 in the second metal layer is connected to the polysilicon in the transmission transistor PG via the word line contact PG1 above L1; WL02 is connected to the polysilicon in the transmission transistor PG via the word line contact PG1 below L1.

[0087] It should be understood that, although Figures 1 to 5None of the insulating layers are shown, but in actual practice, an insulating layer is provided between any two adjacent metal layers, the first metal layer and the active region 102, and typically requires the provision of a via to provide electrical interconnection to and between the various devices on the semiconductor substrate 101 and the various devices on the semiconductor substrate 101. Optionally, electrical interconnection of the various metal layers is achieved through the provision of conductive plugs between the active region 102, the polysilicon 103 and the first metal layer Ml, the first metal layer Ml, the first metal layer Ml and the second metal layer M2, the second metal layer M2, the second metal layer M2 and the third metal layer M3, the third metal layer M3, the third metal layer M3 and the fourth metal layer M4, the fourth metal layer M4, the fourth metal layer M4 and the fifth metal layer M5. While only five metal layers are shown in the embodiment, any number of metal layers can be provided in actual practice and used to implement the present application. Each metal layer can comprise a conductive material of aluminum, an aluminum alloy (e.g., aluminum / silicon / copper), copper, a copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, silicide, polysilicon and / or other suitable conductive material. In actual practice, a damascene and / or dual damascene process is used to form the metal layers. Each insulating layer can comprise a suitable dielectric material of tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or an MLI structure of doped silicon oxide such as borophosphosilicate glass (BPSG), fused quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric material insulated from each other. The conductive plugs of the vias can comprise copper, tungsten and / or other suitable conductive material. The VSSD, the BL, the BLB, the VC, the WL can each comprise a conductive material of aluminum, an aluminum alloy (e.g., aluminum / silicon / copper), copper, a copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, silicide, polysilicon and / or other suitable conductive material.

[0088] In some possible implementations, the conductive plugs provided in each insulating layer under the second metal layer M2 of the connection region 105 connect the VSSD to implement the connection of VSSD0 and VSSD1 in the second metal layer M2 to the corresponding ground contact 105a. It should be understood that the conductive plug provided in the bottommost insulating layer under the second metal layer M2 is directly above the ground contact 105a.

[0089] The conductive plugs provided in each insulating layer under the fourth metal layer M4 of the connection region 105 connect the VC to implement the connection of the VC in the second metal layer M2 to the fourth metal layer M4 and connect the VC to the power line contact 105b. It should be understood that the conductive plug provided in the bottommost insulating layer under the fourth metal layer M2 is directly above the power line contact 105b.

[0090] The conductive plug of each insulating layer under the second metal layer M2 of the edge region 104 is provided with a connection of BL0 and BLB0 to realize the connection of BL0 and BLB0 in the second metal layer to the corresponding bit line contact 104a and the complementary bit line contact 104b. Specifically, the conductive plug of the bottommost insulating layer under the second metal layer M2 is arranged directly above the bit line contact 104a and the complementary bit line contact 104b; two conductive plugs in the insulating layers of the first metal layer M1 and the second metal layer M2, one is arranged directly below BL0 for connecting BL0, and the other is arranged directly below BLB0 for connecting BLB0. The second storage unit 112 and the first storage unit 111 are similar, but in the second edge region 20, two conductive plugs in the insulating layers of the first metal layer M1 and the second metal layer M2, one is arranged directly below BL1 for connecting BL1, and the other is arranged directly below BLB1 for connecting BLB1.

[0091] The wiring of each metal layer will be described in detail below.

[0092] Please refer to Figure 2 , the second metal layer M2 is sequentially provided from top to bottom with WL01, VSSD0, BL0, BL1, BLB0, BLB1, VSSD1, WL02 parallel to L1, VC perpendicular to L1, and self-locking line M2a, wherein the VC is located in the connection region 105.

[0093] Please refer to Figure 3 , the third metal layer M3 is sequentially provided from top to bottom with WL01, VC, and WL02 perpendicular to L1, wherein the WL01, VC, and WL02 are located in the connection region 105.

[0094] Please refer to Figure 4 , the fourth metal layer M4 is sequentially provided from top to bottom with WL01, VC, and WL02 parallel to L1, wherein the VC is arranged in the middle region of the first storage unit 111, so that the first storage unit 111 and the second storage unit 112 share the VC.

[0095] Please refer to Figure 5 , the fifth metal layer M5 is provided with WL perpendicular to the arrangement direction L1, and the WL is located in the connection region 105.

[0096] It should be understood that the above-provided wiring in the second to fifth metal layers M5 is only one possible implementation, and the embodiments of the present application do not intend to limit the wiring manner in the second to fifth metal layers M5, which can be determined according to actual needs.

[0097] The above is a detailed introduction to the storage unit pair. By using the above storage unit pair, the bit line is doubled, the load on each bit line is reduced by half, the running speed is faster than before, and the function and performance are more secure than before; and the word line is reduced by half, saving half of the wiring resources in the word line direction. At the same time, a reasonable layout design is adopted, and the size and running speed of the memory array are considered.

[0098] In a second aspect, the embodiments of the present application provide an FPGA. The FPGA comprises the memory array of any of the above embodiments.

[0099] The FPGA provided by the embodiments of the present application improves the running speed of the storage unit pair, guarantees the function and performance by setting the bit line contact and the complementary bit line contact on both sides of the connection area of the two storage units to connect the two storage units to different bit lines and complementary bit lines, thereby reducing the load on each bit line by half; and saves half of the wiring resources in the word line direction by reducing the word line by half.

[0100] The above only describes the embodiments of the present application and is not intended to limit the present application. The present application can have various changes and modifications for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the scope of claims of the present application.

Claims

1. A memory array comprising: Each column of storage units in the memory array comprises: a plurality of storage units arranged in a column along an arrangement direction, each of the storage units is provided with a bit line contact and a complementary bit line contact at a first edge region thereof, the plurality of storage units comprises a storage unit pair comprising a first storage unit and a second storage unit in an adjacent relationship, the second edge regions of the first storage unit and the second storage unit are connected to form a connection region, the connection region is located between the first edge regions of the first storage unit and the second storage unit; two bit lines connected to the bit line contacts of the first storage unit and the second storage unit of each of the storage unit pairs respectively; two complementary bit lines connected to the complementary bit line contacts of the first storage unit and the second storage unit of each of the storage unit pairs respectively; wherein each of the storage units is connected to a word line, the first storage unit and the second storage unit of the storage unit pair share a word line; the plurality of storage units are arranged in a column along the arrangement direction in the order of the first storage unit, the second storage unit, the second storage unit, and the first storage unit.

2. The memory array of claim 1, wherein, the first edge regions of two adjacent first storage units of the plurality of storage units are connected to share the bit line contacts and the complementary bit line contacts; the first edge regions of two adjacent second storage units of the plurality of storage units are connected to share the bit line contacts and the complementary bit line contacts.

3. The memory array of claim 1, wherein, The storage unit comprises: a plurality of transistors, at least comprising two transfer transistors, two pull-down transistors, and two pull-up transistors symmetrically arranged about a target center line, the target center line being a center line of the column of storage units along the arrangement direction; wherein the connection region comprises active regions on both sides of polysilicon of the two pull-up transistors and the two pull-down transistors away from active regions of the transfer transistors; the first edge region comprises active regions on both sides of polysilicon of the two transfer transistors away from the connection region; an active region of one of the transfer transistors in the first edge region is provided with a bit line contact, and an active region of the other transfer transistor is provided with a complementary bit line contact.

4. The memory array of claim 3, wherein, The storage unit comprises: a first metal layer to an Nth metal layer arranged from bottom to top on the plurality of transistors, the second metal layer being provided with the two bit lines and the two complementary bit lines, N being a positive integer greater than 1; a first insulating layer to an Nth insulating layer arranged between the plurality of transistors and the first metal layer and between adjacent two metal layers; wherein the insulating layer of the first edge region is provided with an interlayer via hole to connect the bit line to the bit line contact and the complementary bit line to the complementary bit line contact.

5. The memory array of claim 4, wherein, the two bit lines and the two complementary bit lines of the first storage unit and the second storage unit in the connection region are connected respectively; the two bit lines are located on one side of the target center line, and the two complementary bit lines are located on the other side of the target center line.

6. The memory array of claim 4, wherein, The polysilicon in the pull-up transistor above the target center line is connected to the active area of the polysilicon in the pull-down transistor below the target center line through the first metal layer, and the active area is close to the active area of the side of the transmission transistor; The polysilicon in the pull-up transistor below the target center line is connected to the active area of the polysilicon in the pull-down transistor above the target center line through the self-locking line in the second metal layer, and the active area is close to the active area of the side of the transmission transistor.

7. The memory array of claim 4, wherein, The polysilicon in the transmission transistor of each storage unit away from the target center line is provided with a word line contact; The word line contacts provided by the first storage unit and the second storage unit in the storage unit pair are connected to the same word line.

8. The memory array of claim 4, wherein, Each of the storage units is provided with a ground line contact and a power line contact; The column storage unit comprises: A ground line connected to the ground line contact provided by each of the storage units; A power line connected to the power line contact provided by each of the storage units; The active area of the pull-down transistor provided by the connection area is shared by the ground line contact of the first storage unit and the second storage unit in the storage unit pair, and the active area of the pull-up transistor is provided with a power line contact; The interlayer via provided by the insulating layer of the connection area is used to connect the power line to the power line contact and the ground line to the ground line contact.

9. The memory array of claim 8, wherein the power line is provided in the second to i-th metal layers, the ground line is provided in the second metal layer, and the word line is provided in the second to j-th metal layers, wherein i and j are positive integers greater than 2; wherein The power line in the second to i-th metal layers is connected to the power line contact through the interlayer via provided by the 1st to i-1st insulating layers of the connection area; the word line in the second to j-th metal layers is connected to the word line contact through the interlayer via provided by the 1st to j-1st insulating layers; and the word line, power line and ground line of the first storage unit and the second storage unit in the connection area are connected respectively.

10. The memory array of claim 9, wherein i is 4 and / or j is 5; The ground line is provided on the side away from the target center line of the two bit lines and / or the two complementary bit lines; The power line in the second metal layer is perpendicular to the bit line, and the power line in the fourth metal layer is parallel to the bit line; The word line in the second metal layer is parallel to the bit line, and the word line in the fifth metal layer is perpendicular to the bit line, which is located in the connection area.

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