Method for real-time programming and verification of memory cells based on counter and ECC feedback

Abstract

The present application is directed to a method for programming and verifying a memory cell on the fly based on a counter and ECC feedback. The present invention relates to a method for operating a memory cell, comprising: reading previous user data from the memory cell; writing new user data and merging the new user data with the previous user data into a write register; generating mask register information, wherein the mask register information indicates the bits whose logic values ​​of the previous user data stored in the memory cell will be switched or will not be switched; counting the number of first logic values ​​and second logic values ​​to be written using the mask register information, respectively; storing the number of the first logic values ​​and the second logic values ​​into a first counter and a second counter, respectively; and applying a programming pulse to the memory cell according to the mask register information.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 075,502 filed by Muzzetto et al. on October 20, 2020, entitled “ON-THE-FLY PROGRAMMING AND VERIFYING METHOD FOR MEMORY CELLS BASED ON COUNTERS AND ECC FEEDBACK” and international patent application No. PCT / IB2020 / 000080 filed by Muzzetto et al. on March 3, 2020, entitled “ON-THE-FLY PROGRAMMING AND VERIFYING METHOD FOR MEMORY CELLS BASED ON COUNTERS AND ECC FEEDBACK”, each of which is assigned to the assignee of this case, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The following relates generally to operating a memory array, and more particularly to a method of just-in-time programming and verification of memory cells based on counters and ECC feedback.TECHNICAL FIELD The present invention relates to a method of just-in-time programming and verification of memory cells based on counters and ECC feedback. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, a binary device has two states, usually represented as a logical "1" or a logical "0". In other systems, more than two states can be stored. To access the stored information, a component of the electronic device can read or sense the stored states in the memory device. To store information, a component of the electronic device can write or program the states in the memory device.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory cells can maintain their stored logic state for a long time, even in the absence of external power. Volatile memory device cells may lose their stored state over time unless they are periodically refreshed by an external power source.

[0006] Generally speaking, improving memory devices may include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. When memory cells exhibit variable electrical characteristics, particularly when memory devices have three-dimensional (3D) memory cell arrays, more robust reading techniques may be needed to increase memory cell performance and reliability. Summary of the invention

[0007] An example of a method is described. The method may include: reading previous user data from a memory cell; writing new user data; merging the new user data with the previous user data into a write register; generating mask register information, and wherein the mask register information indicates whether a logic value of a bit of the previous user data stored in the memory cell is to be switched or not to be switched; using the mask register information to count the number of first logic values ​​and second logic values ​​to be written, respectively; storing the number of the first logic values ​​and the second logic values ​​into a first counter and a second counter, respectively; and applying a programming pulse to the memory cell according to the mask register information.

[0008] An example of a circuit for operating a memory cell is described. The circuit may include an access circuit that may be configured to: read previous user data from a memory cell; write new user data and merge the new user data with the previous user data into a write register; generate mask register information, and wherein the mask register information indicates whether a logic value of a bit of the previous user data stored in the memory cell is to be switched or not to be switched; use the mask register information to count the number of first logic values ​​and second logic values ​​to be written, respectively, and store the number of the first logic values ​​and the second logic values ​​in a first counter and a second counter, respectively; and apply a programming pulse to the memory cell according to the mask register information. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1An example of a memory device diagram illustrating a three-dimensional (3D) memory cell array with a method supporting just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure.

[0010] Figure 2 An example of a 3D memory array supporting a method of just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure is described.

[0011] Figure 3 A and 3B illustrate examples of hysteresis curves that support methods for just-in-time programming and verification of memory cells based on counter and ECC feedback according to examples of the present disclosure.

[0012] Figure 4 An example of a codeword for a memory array supporting a method of just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure is illustrated.

[0013] Figure 5 A block diagram illustrating an apparatus supporting a method of just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure.

[0014] Figure 6 A block diagram illustrating the programming phase of preparing a memory device of the present disclosure for operation according to the disclosed method.

[0015] Figure 7 An example of a method of just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure is described.

[0016] Figure 8 Several curves are illustrated indicating the lower power consumption during the programming phase using the disclosed method compared to conventional methods.

[0017] Fig. 9 An example of a programming phase of a method for just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure is described.

[0018] Fig.10 A block diagram illustrating a memory controller that can support a method of just-in-time programming and verification of memory cells based on counters and ECC feedback according to examples of the present disclosure.

[0019] Fig.11 A diagram illustrating a system including devices that can support a method of just-in-time programming and verification of memory cells based on counters and ECC feedback according to examples of the present disclosure. DETAILED DESCRIPTION

[0020] In a memory device, such as a self-select memory (SSM) cross-point device or a ferroelectric (FeRAM) non-volatile memory device, during an access operation to program data corresponding to a codeword in memory cells of an array, codeword data (and possibly associated parity bits) are received at input terminals of the memory device. A memory controller analyzes the input data and determines the number of bits in different logic states; for example, the memory controller determines how many logic 0s and / or how many logic 1s are present in the codeword. The memory controller can manipulate or encode the codeword to reduce programming voltage, improve cycling, reduce power, and reduce disturbance.

[0021] The memory device may have been written (for example after a verification phase in the factory), and the cells therefore contain a logic value "1" or "0". The memory content may be read in any case. Only after the reading phase can a write be performed. The codeword CW may be programmed, but the codeword in which the new value is programmed may already be stored in the memory cell, and the cell therefore contains a series of "1" and "0" logic values.

[0022] A proper codeword (CW) analysis may be performed, which compares the logic value already stored in the codeword with the number of "1"s or "0"s that will be used later during the write algorithm. This analysis is performed after storing only the number of "1"s or "0"s of the codeword in a volatile (or non-volatile) counter. This allows the number of cells to be programmed to be reduced. If a logic value of "1" is required to be programmed in a memory cell where a logic value of "1" is already stored in this memory cell, nothing may need to be done and the programming phase of the cell may be omitted. This action is called masking. A register may be provided and all programmed or masked bits may be stored in the register.

[0023] The programming pulses are shifted on those bits that have already been stored with the same logic value of the bits of the new codeword. Even during the programming phase of the remaining bits (i.e. the bits whose logic value will be modified), the rising programming pulses can be stopped as soon as the logic value of the bit changes, thereby avoiding stressing the bit with a higher voltage value. In order to implement this procedure, at least one register containing the codeword to be programmed and one register containing the codeword already programmed can be provided. From these two registers, a new register containing the mask (i.e. the bits that can remain intact) can be extracted. The third register may even be unnecessary or not used, since the codeword to be written can be stored in the register of the sense amplifier. In any case, the third register will be a temporary register. The comparison between the codeword to be written and the codeword already stored can produce an "online" mask register that is then used to implement the write phase.

[0024] The mask register of this solution may provide various advantages if compared with known solutions, since the read register is available as the output of the sense amplifier, while the write register contains the codeword to be written.

[0025] At this point, a ramped cell programming bias can be applied to the memory cell. By applying a ramped bias voltage, the bit-by-bit programming phase can be stopped as soon as the cell reaches a certain threshold that is passed on to subsequent cells. In contrast, if a single programming pulse (e.g., Fig. 9 The programming pulses shown in the left figure of FIG), then the cells with lower thresholds can be stressed more. The programming phase represents a two-step programming plus verification. Thus, each cell can be programmed and sensed so that if it has not been sufficiently programmed, additional programming pulses can be applied until the moment it switches to the desired logic value.

[0026] In very negative situations where the entire program-plus-verify algorithm is still given a negative report on the switching of the memory cell, a final series of blind pulses can be foreseen, in the sense that they do not need to be verified but try to force the desired logic value in the cell. Since the cell can be masked during the programming phase, there will be a maximum voltage value that can be applied to the cell during the write phase. If the programming phase is completed, but there are still some (or only one) slow cells that are unwilling to switch, then there are generally two options: flag the error, or apply some additional pulses with a voltage value higher than the maximum standard voltage. However, the final additional pulse may not be verified. Any verification cycle may take several milliseconds to complete. However, this possible disadvantage may occur very rarely and may involve one or two bits that are at the maximum value. For about 99% of the conventional bits, a relatively low bias voltage has been applied.

[0027] It should be noted. Depending on the number of "1" or "0" contained in the codeword, it may be convenient to mask the cells with a logical value of "1" or a logical value of "0". Therefore, two counters can be used, CNT1 containing the number of "1"s and CNT0 containing the number of "0". The two different values ​​can be maintained because the number of bits that prevent the acquisition of a logical value from the other bits of the number has been masked. The total number of bits can be given by the "0" bit plus the "1" bit plus the masking bit. Since there are three variables, at least two records are provided to obtain the total number of bits.

[0028] Then, subsequent actions can be performed. For example, a logic value "0" is programmed, followed by a logic value "1", which is a write sequence WS1 that can be used when the number of logic values ​​"0" is large. As an alternative, a write sequence WS2 can be performed, and if the number of logic values ​​"1" is large, then a logic value "1" is programmed, followed by a logic value "0". The third write sequence WS3 can be applied only when there is only one bit to be programmed per tile, and this is a specific case where parallel programming can be applied. In a tile, the bits can share the same word line, but opposite polarities can be provided for the pulse for the logic value "0" and the pulse for the logic value "1". Therefore, if there is one bit per tile (and in different tiles), then even logic values ​​"0" and "1" can be programmed simultaneously (in parallel), because in the tile where the logic value "1" is to be written, one polarity can be applied, and in the tile where 0 is to be written, the opposite polarity can be applied. In contrast, if there are more bits per tile, ie, more bits share the same word line, then logical values ​​"0" and "1" cannot be programmed in parallel because the word line can have a single voltage value at a time.

[0029] In other words, a logic value "0" may be programmed with a certain polarity, and at the end of the programming phase for logic value "0", a logic value "1" may be programmed with the opposite polarity, and vice versa. Alternatively, if the logic values ​​"0" and "1" are in units of bits that are physically separated in different tiles, they may even be programmed in parallel with different polarities.

[0030] However, there may be a risk of having stuck cells that push the voltage too high during the programming phase. In this case, a verification phase may be performed immediately after the programming phase to avoid stressing the cells. This may be referred to as just-in-time programming and verification, which also means online. Furthermore, it should be noted that the write sequence of the proposed solution is based on ECC feedback and counters. ECC may be used to solve the problem of stressing stuck cells too much. If the programming phase is current except for a single bit of information obtained from the ECC, the codeword has been programmed at a reasonable voltage level, and only one final bit may be subjected to an additional programming pulse. In any case, the output codeword will be repairable.

[0031] In some examples, the use of a counter-based write algorithm with ECC feedback enables the opportunity to verify the write program pattern, which can save time and power consumption and increase reliability. In some examples, not using extra time to perform verification can reduce the average voltage program, and less interference and more cycles can provide increased reliability.

[0032] Features of the present disclosure introduced above are further described below in the context of a memory array in a memory device. Specific non-limiting examples are then described for illustrating various features of methods for just-in-time programming and verification of memory cells based on counters and ECC feedback according to some examples (e.g., memory arrays including PCM cells or three-dimensional cross-point (e.g., 3DXPoint) memory cells, chalcogenide-based memory cells, etc.). These and other features of the present disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flow charts relating to methods for just-in-time programming and verification of memory cells based on counters and ECC feedback. However, as will be appreciated by those skilled in the art, other alternatives and different variations may be considered and are within the scope of the present disclosure.

[0033] Figure 1 An example memory device 100 is illustrated according to an example of the present disclosure. The memory device 100 may also be referred to as an electronic memory device. Figure 1 1 is an illustrative representation of various components and features of memory device 100. Thus, it should be understood that the components and features of memory device 100 are shown to illustrate functional interrelationships and may not represent their actual physical locations within memory device 100. Figure 1 1 , memory device 100 includes a 3D memory array 102. 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some examples, each memory cell 105 may be programmable to store two states, represented as logic 0 and logic 1. In some examples, memory cell 105 may be configured to store more than two logic states. In some examples, memory cell 105 may include PCM cells (e.g., 3D XPoint memory cells), chalcogenide-based memory cells, or other types of memory cells. Although Figure 1 Some of the elements contained in the drawings are labeled with numerical designators, while other corresponding elements are not labeled, but are the same or will be understood to be similar, in order to increase visibility and clarity of the features depicted.

[0034] The 3D memory array 102 may include two or more two-dimensional (2D) memory arrays formed adjacent to each other (e.g., one on top of the other or right next to each other). This may increase the number of memory cells 105 that may be placed or created on a single die or substrate compared to a 2D array, which in turn may reduce production costs or increase performance of the memory device, or both. Figure 1, 3D memory array 102 includes two levels of memory cells 105; however, the number of levels may not be limited to two. Each level may be aligned or positioned so that memory cells 105 may be aligned (exactly aligned, overlapping aligned, or approximately aligned) with each other across each level, thereby forming a memory cell stack 145. In some cases, memory cell stack 145 may include PCM cells (e.g., 3D XPoint memory cells) placed one on top of another.

[0035] In some examples, each row of memory cells 105 is connected to an access line 110, and each column of memory cells 105 is connected to a bit line 115. The access lines 110 and the bit lines 115 may be substantially perpendicular to each other and may form an array of memory cells. Figure 1 As shown in , two memory cells 105 in a memory cell stack 145 may share a common conductive line, such as a bit line 115. That is, the bit line 115 may be in electronic communication with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. In other examples, each of the memory cells 105 (e.g., the upper memory cell, the lower memory cell) may be configured with its own bit line. In such cases, the memory cells may be separated by an insulating layer. Other configurations may not be possible, for example, the third layer may share an access line 110 with the lower layer. In general, one memory cell 105 may be located at the intersection of two conductive lines, such as an access line 110 and a bit line 115. This intersection may be referred to as the address of the memory cell. The target memory cell 105 may be a memory cell 105 located at the intersection of a powered access line 110 and a bit line 115; that is, the access line 110 and the bit line 115 may be powered so as to read or write the memory cell 105 at their intersection. Other memory cells 105 that are in electronic communication with (eg, connected to) the same access line 110 or bit line 115 may be referred to as non-target memory cells 105 .

[0036] As discussed above, an electrode may be coupled to the memory cell 105 and the access line 110 or the bit line 115. The term electrode may refer to an electrical conductor, and in some cases, may serve as an electrical contact to the memory cell 105. An electrode may include a trace, a wire, a conductive line, a conductive layer, etc., which provides a conductive path between elements or components of the memory device 100. In some examples, the memory cell 105 may include a chalcogenide alloy disposed between a first electrode and a second electrode. One side of the first electrode may be coupled to the access line 110, and the other side of the first electrode is coupled to the chalcogenide alloy. In addition, one side of the second electrode may be coupled to the bit line 115, and the other side of the second electrode may be coupled to the chalcogenide alloy. The first electrode and the second electrode may be the same material (e.g., carbon) or may be different. In other examples, the memory cell 105 may include additional electrodes to divide the chalcogenide alloy into two parts, such as Figure 2 . The first portion of the chalcogenide alloy may have a different composition than the second portion of the chalcogenide alloy. In some examples, the first portion of the chalcogenide alloy may have a different function than the second portion of the chalcogenide alloy. The additional electrode may have the same material (e.g., carbon) as the first electrode and / or the second electrode or be different from the first electrode and / or the second electrode.

[0037] Operations such as reading and writing can be performed on the memory cell 105 by energizing or selecting the access line 110 and the digit line 115. In some examples, the access line 110 may also be referred to as the word line 110, and the bit line 115 may also be referred to as the digit line 115. References to word lines and bit lines or the like are interchangeable without loss of understanding or operation. Energizing or selecting the word line 110 or the digit line 115 may include applying a voltage to the corresponding line. The word line 110 and the digit line 115 may be made of a conductive material, such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, a conductive doped semiconductor, or other conductive materials, alloys, compounds, or the like.

[0038] In some architectures, the logic storage device (e.g., capacitor, resistor) of the memory cell 105 may be electrically isolated from the digit line 115 by a selection component. The word line 110 may be connected to the selection component and may control the selection component. For example, the selection component may be a transistor and the word line 110 may be connected to the gate of the transistor. Energizing the word line 110 creates an electrical connection or closed circuit between the logic storage device of the memory cell 105 and its corresponding digit line 115. The digit line 115 may then be accessed to read or write the memory cell 105. Upon selecting the memory cell 105, the resulting signal may be used to determine the stored logic state. In some cases, the first logic state may correspond to no current or a negligible small current, while the second logic state may correspond to a finite amount of current. In some cases, the memory cell 105 may include a 3D XPoint memory cell or a self-select memory (SSM) cell, both of which have two terminals and may not use a separate selection component. Thus, one terminal of the 3D XPoint memory cell or SSM cell may be electrically connected to word line 110 , and another terminal of the 3D XPoint memory cell or SSM cell may be electrically connected to digit line 115 .

[0039] Access to the memory cells 105 may be controlled by a row decoder 120 or a column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and energize the appropriate word line 110 based on the received row address. Similarly, the column decoder 130 may receive a column address from the memory controller 140 and energize the appropriate digit line 115. For example, the 3D memory array 102 may include a plurality of word lines 110 labeled WL_B1 (or WL_T1) to WL_BM (or WL_TM) and a plurality of digit lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Thus, by energizing a word line 110 and a digit line 115 (e.g., WL_B2 and DL_3), the memory cells 105 at their intersections may be accessed.

[0040] Upon access, the memory cell 105 may be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, a voltage may be applied to the memory cell 105 (using the corresponding word line 110 and bit line 115), and the presence of the resulting current may depend on the applied voltage and the threshold voltage of the memory cell 105. In some cases, more than one voltage may be applied. Additionally, if the applied voltage does not result in current, other voltages may be applied until the sensing component 125 detects current. By evaluating the voltage that results in current, the stored logical state of the memory cell 105 may be determined. In some cases, the magnitude of the voltage may be ramped up until current is detected (e.g., the memory cell 105 is turned on, switched on, conducting, or becomes activated). In other cases, predetermined voltages may be applied in sequence until current is detected. Likewise, a current may be applied to the memory cell 105, and the magnitude of the voltage used to produce the current may depend on the resistance or threshold voltage of the memory cell 105.

[0041] The sensing component 125 may include various transistors or amplifiers in order to detect and amplify the difference in the signal, which may be referred to as latching. The detected logic state of the memory cell 105 may then be output as output 135 by the column decoder 130. In some cases, the sensing component 125 may be part of the column decoder 130 or the row decoder 120. Alternatively, the sensing component 125 may be connected to or in electronic communication with the column decoder 130 or the row decoder 120. Figure 1 An alternative option for arranging the sense components 125-a is also shown (in the dashed box).One of ordinary skill in the art will appreciate that the sense components can be associated with either the column decoder or the row decoder without losing their functional purpose.

[0042] Memory cell 105 may be set or written by similarly energizing associated word line 110 and digit line 115, and at least one logic value may be stored in memory cell 105. Column decoder 130 or row decoder 120 may accept data to be written to one or more memory cells 105, such as input / output 135.

[0043] In some memory architectures, accessing a memory cell 105 may degrade or destroy the stored logic state, and a rewrite or refresh operation may be performed to return the original logic state to the memory cell 105. In DRAM, for example, a capacitor may be partially or completely discharged during a sensing operation, thereby destroying the stored logic state. Therefore, the logic state may be rewritten after the sensing operation. In addition, energizing a single word line 110 may cause all memory cells 105 in the row to discharge; therefore, some or all memory cells 105 in the row may need to be rewritten. But in non-volatile memories such as SSM, PCM (such as 3D XPoint memory), FeRAM, or 3D NAND memory, accessing a memory cell 105 may not destroy the logic state, and therefore the memory cell 105 may not need to be rewritten after access.

[0044] The memory controller 140 may control the operation (e.g., reading, writing, rewriting, refreshing, discharging) of the memory cells 105 through various components such as the row decoder 120, the column decoder 130, and the sensing component 125. In some cases, one or more of the row decoder 120, the column decoder 130, and the sensing component 125 may be co-located with the memory controller 140. The memory controller 140 may generate row and column address signals in order to energize the desired word lines 110 and digit lines 115. The memory controller 140 may also generate or control various voltages or currents used during operation of the memory device 100.

[0045] The memory controller 140 may receive user data through the input / output 135. In some examples, the memory controller 140 may read previous user data from the memory cell and write new user data, and merge the new user data with the previous user data into a write register. Then, mask register (MR) information may be generated, and wherein the mask register information may indicate bits of the previous user data stored in the memory cell whose logic values ​​are to be switched or not switched. In some examples, the memory controller 140 may count the number of first logic values ​​(logic "0") and second logic values ​​(logic "1") to be written respectively using the MR information, and store the number of the first logic values ​​and the second logic values ​​in a first counter and a second counter, respectively. In some examples, the memory controller 140 may apply a programming pulse to the memory cell according to the mask register information.

[0046] In general, the amplitude, shape, polarity, and / or duration of the applied voltages or currents discussed herein may be adjusted or varied, and may be different for the various operations discussed in operating the memory device 100. Furthermore, one, multiple, or all memory cells 105 within the memory array 102 may be accessed simultaneously; for example, multiple or all cells of the memory array 102 may be accessed simultaneously during a reset operation, in which all memory cells 105 or a group of memory cells 105 are set to a single logic state.

[0047] Figure 2 An example of a memory array 200 that supports a method of programming and verifying memory cells on the fly based on counters and ECC feedback according to an example of the present disclosure is illustrated. The memory array 200 may be a reference Figure 1 An example of a portion of memory array 102 is depicted. Figure 2 As depicted, memory array 200 includes a plurality of materials to construct memory cells 105-a. Each memory cell 105-a is stacked in a vertical direction (eg, perpendicular to the substrate) to form a memory cell stack (eg, memory cell stack 145). Memory cell 105-a may be a reference Figure 1 1. The memory array 200 may therefore be referred to as a 3D memory array. The architecture of the memory array 200 may be referred to as a cross-point architecture. Figure 2 Some of the elements contained in the drawings are labeled with numerical designators, while other corresponding elements are not labeled, but are the same or will be understood to be similar, in order to increase visibility and clarity of the features depicted.

[0048] The memory array 200 also includes word lines 110 - a and bit lines 115 - a , which may be reference lines. Figure 1 Examples of word lines 110 and bit lines 115 are depicted. Figure 2 The description of the material between the word line 110-a and the bit line 115-a depicted in FIG. Figure 1 2. The memory array 200 includes an electrode 205, a logic storage element 210, a selector device element 220, and a substrate 225. The logic storage element 210, the electrode 205-b, and the selector device element 220 may be collectively referred to as a memory element 230. In some examples, a single component (not shown, the selector device element 220, the logic storage element 210, and the electrode 205-b are replaced with the memory element 230) including a chalcogenide alloy may serve as both a logic storage element and a selector device. The electrode 205-a may be in electronic communication with the bit line 115-a, and the electrode 205-c may be in electronic communication with the word line 110-a.

[0049] The insulating material depicted as empty space may be electrically and thermally insulating. As described above, in PCM technology, various logic states may be stored by changing the resistance of the logic storage element 210 in the memory cell 105-a, which in turn exhibits a varying threshold voltage of the memory cell 105-a. In some cases, storing various logic states includes passing a current through the memory cell 105-a, causing the logic storage element 210 in the memory cell 105-a to generate heat, or (e.g., completely or partially) melting the material of the logic storage element 210 in the memory cell 105-a. Other storage mechanisms, such as threshold voltage modulation, may be employed in chalcogenide-based memories.

[0050] In some cases, the memory array 200 may include an array of memory cell stacks, and each memory cell stack may include a plurality of memory cells 105-a. The memory array 200 may be made by forming a stack of conductive materials, such as word lines 110-a, wherein each conductive material is separated from adjacent conductive materials by an electrically insulating material therebetween. The electrically insulating material may include an oxide or nitride material, such as silicon oxide, silicon nitride, or other electrically insulating material. These materials may be formed over a substrate 225, such as a silicon wafer, or any other semiconductor or oxide substrate. Subsequently, various process steps may be utilized to form material between the word lines 110-a and the bit lines 115-a so that each memory cell 105-a may be coupled to the word lines 110-a and the bit lines 115-a.

[0051] The selector device element 220 may be connected to the logic storage element 210 via the electrode 205-b. In some examples, the positioning of the selector device element 220 and the logic storage element 210 may be flipped. The composite stack including the selector device element 220, the electrode 205-b, and the logic storage element 210 may be connected to the word line 110-a via the electrode 205-c, and to the bit line 115-b via the electrode 205-a. The selector device element 220 may assist in selecting a particular memory cell 105-a, or may help prevent stray current from flowing through an unselected memory cell 105-a adjacent to the selected memory cell 105-a. The selector device element 220 may include an electrically nonlinear component (e.g., a non-ohmic component), such as a metal-insulator-metal (MIM) junction, a bidirectional threshold switch (OTS), or a metal-semiconductor-metal (MSM) switch, as well as other types of two-terminal selector devices, such as a diode. In some cases, the selector device element includes a chalcogenide alloy. In some examples, the selector device includes an alloy of selenium (Se), arsenic (As), silicon (Si), and germanium (Ge).

[0052] As discussed above, Figure 2The memory cell 105-a may include a material having a variable resistance. The variable resistance material may refer to various material systems, including, for example, metal oxides, chalcogenides, etc. Chalcogenide materials are materials or alloys that include at least one of the elements sulfur (S), tellurium (Te), or selenium (Se). Many chalcogenide alloys may be possible, for example, germanium-antimony-tellurium alloy (Ge-Sb-Te) is a chalcogenide material. Other chalcogenide alloys not explicitly described herein may also be used.

[0053] To set the low resistance state, the memory cell 105-a may be heated by passing an electric current through the memory cell 105-a. The heating caused by an electric current flowing through a material having a finite resistance may be referred to as Joule or Ohmic heating. Joule heating may therefore be related to the resistance of an electrode or phase change material. Heating the phase change material to a high temperature (but below its melting temperature) may cause the phase change material to crystallize and form a low resistance state. In some cases, the memory cell 105-a may be heated by methods other than Joule heating, such as by using a laser. To set the high resistance state, the phase change material may be heated to above its melting temperature, for example, by Joule heating. The amorphous structure of the molten material may be quenched or locked by suddenly removing the applied current to rapidly cool the phase change material.

[0054] In some cases, after a number of cycling operations (e.g., a series of read or write operations), the memory cell 105-a may exhibit different electrical characteristics. For example, after receiving the same programming pulse to store a logic state 1 (e.g., a set (SET) programming pulse), if the memory cell 105-a is relatively new (e.g., a PCM cell with a smaller number of read or write operations) compared to a memory cell 105-a that has cycled through a larger number of read or write operations, then the threshold voltage of the memory cell 105-a (e.g., a PCM cell) corresponding to the logic state 1 may be different. Additionally, in some cases, the chalcogenide material (e.g., the logic storage element 210) in the memory cell 105-a may experience a change in its resistance (which may also be referred to as drift) after programming (e.g., crystallization or quenching) of the chalcogenide material during a write operation. Such a change in resistance may result in a change in the threshold voltage of the memory cell 105-a and may prevent accurate reading of information from the memory cell 105-a (e.g., a PCM cell) after a certain period of time has passed. In some examples, the amount of change may vary with ambient temperature.

[0055] In some examples, memory cell 105-a may be configured to store encoded user data, which includes modified user data (or in some cases, original user data) and a number of parity bits that may be added thereto. In some cases, the encoded user data stored in memory cell 105-a has been modified to include a predetermined number of bits having a logic state of 1. Depending on the encoding scheme employed, the number of bits having a logic state of 1 may be different. In some cases, the number of bits having a logic state of 1 may be 50% (or other percentage) of the bits containing the encoded user data. In some examples, memory cell 105-a may be configured to store user data, while another group of memory cells 105-a is configured to store count information. The count information may represent the number of bits having a logic state of 1 in the user data. In some cases, the count information may be read in advance before reading the user data to extract the number of bits having a logic state of 1 in the user data. Additionally or alternatively, the count information may be determined when reading the user data.

[0056] Some examples of memory cells may include memory elements and selection devices, and other examples of memory cells may include memory elements selected using techniques that do not include selection devices. In some examples, a polarity-dependent signal may be used to program or read a memory cell 105-a (e.g., a self-selected memory cell) that includes a chalcogenide material. In such examples, the memory cell 105-a may be programmed to a logic state by applying a first signal having a first voltage and a first polarity. When the first signal is used to program a particular memory cell 105-a, the elements within the memory cell may separate, resulting in ion migration. The ions may migrate toward a particular electrode 205, depending on the polarity of the first signal applied to the memory element. For example, when a signal having a first polarity is used, ions in the memory cell 105-a may migrate toward the first electrode, and when a signal having a second polarity is used, may migrate toward the second electrode. The first polarity of the signal may refer to a signal having a current flowing in a first direction (e.g., from the second electrode to the first electrode) across the memory cell. The second polarity of the signal may refer to a signal having a current flowing across the memory cell in a second direction different from the first direction (eg, from a first electrode to a second electrode).

[0057] The memory cell may be read by applying a read signal across the memory cell. The threshold voltage experienced during a read operation may be based on the distribution of ions in the memory cell, the polarity of the read signal, and / or the polarity of the programming signal. For example, if the memory cell has a given distribution based on a programming signal used to program the memory cell, then when a first read signal having a first polarity is used, the threshold voltage detected during a read operation may be different than when a second read signal having a second polarity is used. Depending on the polarity of the memory cell, this concentration of migrating ions may represent a logical "1" or logical "0" state. The description of ion migration represents an example of a mechanism for a memory cell to achieve the results described herein.

[0058] In some examples, such as for thresholding of a memory cell or a self-selected memory cell, some or all of the set of logical states supported by the memory cell may be associated with an amorphous state of the chalcogenide material (e.g., the material in a single state may be operable to store different logical states). The material used in the memory element 230 may be based on an alloy (e.g., the alloys listed herein), and may be operated during normal operation of the memory cell so as to undergo changes to different physical states. For example, a memory cell may have a high threshold voltage state that may correspond to a first logical state (e.g., a reset (RESET) state) and a low threshold voltage state that may correspond to a second logical state (e.g., a set (SET) state).

[0059] During a programming (writing) operation of a memory cell (e.g., including electrode 205-a, memory element 230, and electrode 205-c), the polarity used for the writing operation can affect (e.g., determine, set, program) a particular behavior or characteristic of the material of memory element 230, such as the threshold voltage of the material. The difference in the threshold voltage of the material of memory element 230 depending on the logical state stored by the material of memory element 230 (e.g., the difference between the threshold voltage when the material is storing a logical state '0' and a logical state '1') can correspond to a read window of memory element 230.

[0060] In some examples, a memory device may include multiple arrays or stacks stacked on top of one another. For example, a memory device may include a first array or stack of memory cells (e.g., array 200) located above a substrate 225, and a second array or stack of memory cells (not shown) above the first array or stack 200. The memory cells of each stack 200 may each include a first electrode 205-c, a memory element 230 (e.g., including a chalcogenide material), and a second electrode 205-a, which may form a memory stack. The memory stack may also include other layers and materials. In some examples, the memory cells of the first stack and the second stack may have a common conductive line so that the corresponding memory cells of each stack may share a bit line 115 or a word line 110, as shown in reference to Figure 1 As described. For example, bit line 115-a may be shared by vertically adjacent memory cells. In some cases, memory cell 105-a may be an example of a phase change memory cell or a self-select memory cell.

[0061] The architecture of memory array 200 may be referred to as a cross-point architecture, in which memory cells are formed at the topological intersections between word lines and bit lines. This cross-point architecture may provide relatively high density data storage at a lower production cost than other memory architectures. For example, the cross-point architecture may have memory cells with reduced area and thus increased memory cell density compared to other architectures. For example, the architecture may have a 4F2 memory cell area, where F is the minimum feature size, compared to other architectures (such as those with a three-terminal selector component) having a 6F2 memory cell area. For example, a DRAM may use a transistor, which is a three-terminal device, as a selector component for each memory cell and may have a larger memory cell area than a cross-point architecture.

[0062] In some examples, one or more of the memory stacks may include a memory element 230 that includes a chalcogenide material. For example, the memory element 230 may include a chalcogenide glass, such as an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some examples, a chalcogenide material having primarily Se, As, and Ge may be referred to as a SAG alloy. In some examples, a SAG alloy may include Si, and such a chalcogenide material may be referred to as a SiSAG alloy. In some examples, the chalcogenide glass may include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each of which may be in atomic or molecular form.

[0063] The following will be in the context of self-select (SSM) and / or 3D cross-point (e.g., 3D XPoint) memory cell devices, such as reference Figures 4 to 11to describe several examples; however, the same principles and solutions can be implemented in the context of ferroelectric (FeRAM) devices, the basic functionality of which is Figure 3 A and 3B, with appropriate adjustments.

[0064] Figure 3 3A and 3B illustrate examples of nonlinear electrical characteristics of a ferroelectric memory cell with hysteresis curves 300-a and 300-b according to various examples as disclosed herein. Hysteresis curves 300-a and 300-b illustrate example ferroelectric memory cell write and read processes, respectively. Hysteresis curves 300-a and 300-b depict charge Q stored on a ferroelectric capacitor as a function of voltage difference V.

[0065] Ferroelectric materials are characterized by spontaneous electric polarization, i.e., they maintain a non-zero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. The electric polarization within a ferroelectric capacitor brings a net charge at the surface of the ferroelectric material and attracts opposite charges through the capacitor terminals. Therefore, the charge is stored at the interface between the ferroelectric material and the capacitor terminals. Because the electric polarization can be maintained for a relatively long time, or even indefinitely, in the absence of an externally applied electric field, charge leakage can be significantly reduced compared to capacitors used in, for example, DRAM arrays. This can reduce the need to perform refresh operations.

[0066] Hysteresis curves 300-a and 300-b can be understood from the perspective of a single terminal of a capacitor. As an example, if the ferroelectric material has a negative polarization, positive charge accumulates at the terminal. Similarly, if the ferroelectric material has a positive polarization, negative charge accumulates at the terminal. In addition, the voltage in hysteresis curves 300-a and 300-b represents the voltage difference across the capacitor and is directional. For example, a positive voltage can be achieved by applying a positive voltage to the terminal in question (e.g., the cell plate) and maintaining the second terminal (e.g., the cell bottom) at ground (or approximately zero volts (0V)). A negative voltage can be applied by maintaining the terminal in question grounded and applying a positive voltage to the second terminal, that is, a positive voltage can be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to produce the voltage differences shown in hysteresis curves 300-a and 300-b.

[0067] As depicted in hysteresis curve 300-a, the ferroelectric material can maintain either positive polarization or negative polarization with zero voltage difference, resulting in two possible charged states: charge state 305 and charge state 310. Figure 3A and 3B, charge state 305 represents a logical 1 and charge state 310 represents a logical 0. In some examples, the logic values ​​of the respective charge states may be inverted to accommodate other schemes for operating the memory cell.

[0068] A logical 0 or 1 can be written to a memory cell by applying a voltage to control the electric polarization of the ferroelectric material and, therefore, the charge on the capacitor terminals. For example, applying a net positive voltage 315 across the capacitor causes charge to accumulate until charge state 305-a is reached. After removing voltage 315, charge state 305-a follows path 320 until it reaches charge state 305 at zero voltage. Similarly, charge state 310 is written by applying a net negative voltage 325, which causes charge state 310-a. After removing negative voltage 325, charge state 310-a follows path 330 until it reaches charge state 310 at zero voltage. Charge states 305-a and 310-a may also be referred to as remanent polarization (Pr) values, i.e., the polarization (or charge) remaining after the external bias (e.g., voltage) is removed. A coercive voltage is the voltage when the charge (or polarization) is zero.

[0069] To read or sense the stored state of the ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge Q changes, and the degree of change depends on the initial charge state, i.e., the final stored charge (Q) depends on whether the initial stored charge state is 305-b or 310-b. For example, hysteresis curve 300-b illustrates two possible stored charge states 305-b and 310-b. A voltage 335 may be applied across the capacitor. In other cases, a fixed voltage may be applied to the cell plate, and although depicted as a positive voltage, voltage 335 may be negative. In response to voltage 335, charge state 305-b may follow path 340. Likewise, if charge state 310-b was initially stored, it follows path 345. The final positions of charge state 305-c and charge state 310-c depend on one or more factors, including a particular sensing scheme and circuit.

[0070] In some cases, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if a capacitor is electrically connected to a digit line and voltage 335 is applied, the voltage of the digit line may rise due to its intrinsic capacitance. The voltage measured at the sensing component may not be equal to voltage 335, and may actually depend on the voltage of the digit line. Therefore, the position of the final charge states 305-c and 310-c on the hysteresis curve 300-b may depend on the capacitance of the digit line and may be determined by load line analysis, i.e., charge states 305-c and 310-c may be defined relative to the capacitance of the digit line. Therefore, the voltage of the capacitor, voltage 350 or voltage 355, may be different and may depend on the initial state of the capacitor.

[0071] By comparing the digital line voltage with the reference voltage, the initial state of the capacitor can be determined. The digital line voltage can be the difference between the voltage 335 and the final voltage across the capacitor (voltage 350 or voltage 355), that is, the difference between the voltage 335 and the voltage 350 or the difference between the voltage 335 and the voltage 355. The reference voltage can be generated so that its magnitude is between the two possible voltages of the two possible digital line voltages to determine the stored logical state, that is, whether the digital line voltage is higher or lower than the reference voltage. After comparison by the sensing component, the sensed digital line voltage can be determined to be higher or lower than the reference voltage, and the stored logical value (that is, logical 1 or 0) of the ferroelectric memory cell can be determined. As is clear from the above description, the logical value assigned to the memory cell depends not only on the digital line voltage, but also on the reference voltage used for comparison. Independent of how the reference voltage is accurately and precisely selected and generated, there is a situation where it is unreliable (and even impossible) to perform a read operation with a separate reference voltage for all memory cells.

[0072] In some cases, a ferroelectric memory cell may retain an initial logic state after a read operation. For example, if charge state 305-b is stored, during a read operation, the charge state may follow path 340 to charge state 305-c, and after removing voltage 335, the charge state may return to initial charge state 305-b by following path 340 in the opposite direction. In some cases, a ferroelectric memory cell may lose its initial logic state after a read operation. For example, if charge state 310-b is stored, during a read operation, the charge state may follow path 345 to charge state 305-c, and after removing voltage 335, the charge state may relax to charge state 305-b by following path 340.

[0073] Figure 4 An example of a codeword for a memory array supporting a method for just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure is described. Figure 1 A codeword 400 of a memory device 100 of the embodiment of the present invention may include a data (DATA) area 480 for storing codeword data, and an optional parity (PARITY) area 485 that may include parity data associated with the codeword data. In some examples, the parity data may be error correction parity bits.

[0074] A codeword bit counter (CODEWORD BIT COUNTER) area 490 associated with DATA 480 and PARITY 485 is provided for storing a number of bits of DATA 480 and PARITY 485 in predefined logic states. The number of bits in the bit counter area (COUNT[N:0]) depends on the total DATA 480 and PARITY 485 bit counts and the specific encoding used. Each bit counter bit (COUNT[N:0]) can also be stored with its dummy value (COUNT#[N:0]) to improve the reliability of the information therein. The CODEWORD BIT COUNTER 490 bits can be stored in different arrangements, such as a majority voting arrangement. In some instances, this can be further protected by error correction.

[0075] When data for programming in the memory is received at the input terminals, the memory controller analyzes the data and determines the encoding to be applied and finally the number of bits in a predefined state (e.g. how many bits are stored in the memory cell as a logic 1 state).

[0076] The information stored in the CODEWORD BIT COUNTER 490 area is used during subsequent access operations to retrieve the codeword data, as will be explained in detail below.

[0077] Figure 5 Block diagram 500 shows a memory array 505 supporting a method of just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure. Memory array 505 may be referred to as an electronic memory device and may be an example of a component of a memory arrangement as described herein.

[0078] Memory array 505 may include one or more memory cells 510, memory controller 515, word lines 520, reference components 530, sensing components 535, digital lines 540, and latches 545. These components may be in electronic communication with each other and may perform one or more functions described herein. In some cases, memory cells 510 may include 3DXP memory cells. In some aspects, memory controller 515 may include bias components 550 and timing components 555. In some instances, sensing components 535 may act as reference components 530. In other cases, reference components 530 may be optional.

[0079] Memory controller 515 may be in electronic communication with word lines 520, digit lines 540, and sense elements 535, which may be reference lines. Figure 1 and 2 1. The components of the memory array 505 may be in electronic communication with each other and may perform the operations described above with reference to FIG. Figure 3 and 4 In some cases, reference component 530 , sense component 535 , and latch 545 can be components of memory controller 515 .

[0080] In some examples, digit line 540 is in electronic communication with sense component 535 and memory cell 510. Memory cell 510 can be writable in a logic state, such as a first, second, or third logic state. Word line 520 can be in electronic communication with memory controller 515 and memory cell 510. Sense component 535 can be in electronic communication with memory controller 515, digit line 540, latch 545, and reference line 560. Reference component 530 can be in electronic communication with memory controller 515 and reference line 560. Sense control line 565 can be in electronic communication with sense component 535 and memory controller 515. These components can also be in electronic communication with other components inside and outside of memory array 505 in addition to the components not listed above via other components, connections, or buses.

[0081] The memory controller 515 may be configured to energize the word line 520 or the digit line 540 by applying voltages to those respective nodes. For example, the bias component 550 may be configured to apply voltages to operate the memory cell 510 to read or write the memory cell 510 as described above. In some cases, the memory controller 515 may include a row decoder, a column decoder, or both, as described herein. This may enable the memory controller 515 to access one or more memory cells 105, as described in detail in FIG. Figure 1 The bias component 550 may also provide a voltage to the reference component 530 in order to generate a reference signal for the sensing component 535. In addition, the bias component 550 may provide a voltage for the operation of the sensing component 535.

[0082] In some examples, the memory controller 515 can use a timing component 555 to perform its operations. For example, the timing component 555 can control the timing of various word line selections or bit line biases, including the timing for switching and voltage application to perform memory functions such as reading and writing as discussed herein. In some cases, the timing component 555 can control the operation of the bias component 550.

[0083] Reference component 530 may include various components to generate a reference signal for sensing component 535. Reference component 530 may include circuitry configured to generate a reference signal. In some cases, reference component 530 may be implemented using other 3D XPoint memory cells. Sensing component 535 may compare a signal from memory cell 510 (via digital line 540) to the reference signal from reference component 530. After determining the logic state, sensing component may then store the output in latch 545, where the output may be used according to the operation of the electronic device of which memory array 505 is a part. Sensing component 535 may include a sense amplifier in electronic communication with latch 545 and memory cell 510.

[0084] At least some of the memory controller 515 and / or its various subcomponents may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions of at least some of the memory controller 515 and / or its various subcomponents may be performed by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. At least some of the memory controller 515 and / or its various subcomponents may be physically located at various locations, including being distributed so that portions of the functions are implemented by one or more physical devices at different physical locations. In some instances, at least some of the memory controller 515 and / or its various subcomponents may be independent and distinct components according to various instances of the present disclosure. In other examples, the memory controller 515 and / or at least some of its various subcomponents may be combined with one or more other hardware components including, but not limited to, an I / O component, a transceiver, a network server, another computing device, one or more other components described in the present disclosure, or a combination thereof according to various examples of the present disclosure.

[0085] Figure 6 A schematic flow chart showing the sequence of actions performed during the programming phase of the report.

[0086] The first input action is represented by box 610, where the programming algorithm focuses on the incoming write data. The new data is merged with the previously corrected data in the register. New ECC parity bits are calculated at this stage. The old codeword is read from the memory cells, and the sequence of write data allows a new mask register to be obtained, which is used to identify bits of the already stored sequence that do not need to be reprogrammed because their logic value already corresponds to the logic value of the corresponding bit of the new codeword to be written.

[0087] In block 620 , the algorithm continues to count the number of ones and zeros and stores them in counters CNT1 and CNT0 , respectively.

[0088] Next, in block 630, the write sequence may begin. For example, a logic value of "0" is programmed, followed by a logic value of "1", which is a sequence WS1 that may be used if the number of logic values ​​of "0" is large. As an alternative, a sequence WS2 may be performed, and if the number of logic values ​​of "1" is large, then a logic value of "1" is programmed, followed by a logic value of "0". A third sequence WS3 may be applied only if there is only one bit to be programmed per tile, and this is a specific case where parallel programming may be applied. Within a tile, bits may share the same word line, but opposite polarities may be provided for pulses for logic value "0" and for logic value "1". Thus, if there is one bit per tile (and in different tiles), then even logic values ​​of "0" and "1" may be programmed simultaneously (in parallel), because in the tile in which logic value "1" is to be written, one polarity may be applied, and in the tile in which 0 is to be written, the opposite polarity will be applied. In contrast, if there are more bits per tile, ie, more bits share the same word line, then logical values ​​"0" and "1" cannot be programmed in parallel because the word line can have a single voltage value at a time.

[0089] Figure 7 A write sequence attempt and repeat algorithm with ECC1 is illustrated. In the illustrated example, CNTX=CNT1 (for logic value "1") or CNT0 (for logic value "0"), MaxTrial=maximum number of re-pulses, and the ECC syndrome is feedback to the programming logic to check for errors. In some examples, if a logic value "1" is programmed, then a logic value "0" is in an idle state, and vice versa. In some examples, once switching is detected, the cell is connected to an idle voltage.

[0090] First, a counter is set, as well as a variable regarding the maximum number of attempts allowed. Then, according to one or the other of the sequences WS1 or WS2, and therefore according to the upward or downward voltage value to be applied, the programming ramp is started.

[0091] Until there is a number of programmed cells equal to the number of counters minus 1 (where minus 1 is to be assumed as the corrective power of the ECC), a correctly programmed codeword has not been obtained, i.e. a codeword that the ECC is able to correct. Therefore, the loop continues up to the value CNT-1 (while further checks are performed on upper values ​​of the bias voltage that will remain below Vmax).

[0092] During this cycle, two verification steps may be performed. If a logic value "0" is programmed first, the ECC may return an erroneous value, such as a false positive. Since the logic value "1" has not yet been programmed, and if an indication is obtained from the ECC about the fact that the codeword is correct, there may be many errors due to the fact that the logic value "1" has not yet been programmed, and when the ECC has a codeword with many errors as input, the reported result may also be erroneous. Therefore, it is not worthwhile to require feedback from the ECC but from the counter. If a logic value "1" is being programmed, it is better to require whether a syndrome "0" has been reached, which is a condition in which the codeword does not have a failure.

[0093] Conversely, if a logic value of "0" is being programmed, then if the counter value has been reached, the logic value may be at the maximum value required. Once the counter minus 1 value has been reached, it may be determined whether the number of programmed bits corresponding to the counter value has been reached. This is allowed if the maximum number of attempts or the maximum voltage value has not been reached. If one or the other of those two conditions has been reached (and the counter value has not been reached), then there may be an error in the entire programming sequence, and ECC1 may be obtained. Therefore, in a subsequent programming phase, when a syndrome value may be requested, a value of "1" will be obtained, but this does not mean that the output codeword is necessarily erroneous, but only that there is an error inside that can be corrected by ECC1. The presence of two errors is much lower than the probability assessment, so that it can be ignored.

[0094] Different approaches may be employed depending on which of the write algorithms is executed. During the programming phase of a logic value "0", there is only a counter, while during the programming phase of a logic value "1", there is also an ECC. If an error occurs during the programming phase of a logic value "1", all corrected bits will need to be obtained during the subsequent programming phase of a logic value "0". Conversely, if a single error occurs during the initial programming phase of a logic value "0", correct data will be obtained from the ECC during the subsequent programming phase of a logic value "1".

[0095] The programming sequence stops at CNT-1 because statistically the last bit may present problems or may be programmed using a higher voltage value and after the testing phase it can be decided how to handle the final additional bit already in progress with reference to the information about the correctness of the previous programming phases.

[0096] Figure 8A power consumption comparison of the current programming algorithm and the proposed solution is shown. The right graph 800b in the figure reports the voltage and the time used to complete the programming phase. The programming pulse includes applying a rising voltage, such as a voltage ramp 801, to the memory cell. The cell is initially at a logic state "1" threshold at a programming voltage (part 802 of the programming voltage ramp) in the range of E1 to E2, and is not biased. Only the cell that is initially in the logic state "0" is biased at a programming voltage (part 803 of the programming voltage ramp) in the range of E3 to E4 to set the threshold. The threshold voltage distribution of the memory cell is shown in the dotted line of two cells in the logic "1" and logic "0" states. In the left graph 800a, if a single programming pulse 804 is applied, the cell with a lower threshold will be pressurized more. Therefore, the average voltage programming and therefore the power consumption is reduced relative to the current programming algorithm.

[0097] Fig. 9 An example of a programming phase of a method for just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure is described. Fig. 9 An example of WS1 990 after a read cycle is illustrated. The blue line 991 shows the time of the programming phase and logic value "0" and the subsequent programming phase of logic value "1". The average programming voltage of logic value "0" is between E3 and E4, for example, taking the average value 1 / 2 (E3+E4). When the counter value (i.e., CNT0) has been reached, the programming phase of logic value "0" is stopped. Then, attention may be called to other logic values ​​"1" that may still be programmed.

[0098] The rising positive red ramp 992 for programming logic value "1" is activated and continues with values ​​between E3 and E4, averaging 1 / 2(E3+E4), until CNT1-1. At this point, a situation may be entered where the codeword may be correct. If a single slow bit is missing, a few extra pulses may be applied to force the switching of the slow bit. In either case, a condition has been reached where the codeword may be correct by the ECC. Therefore, the ECC may be checked at this time.

[0099] If at the end of a programming phase there is only one bit to correct, the error may even remain and a signal may be sent to the controller to suggest refreshing only the codewords for which the error has been reported. For example, having obtained a programmed codeword with a single error (still correctable by ECC) may suggest a shift to another memory location, a new programming phase for the codeword, which will replace this last one.

[0100] Fig.10 1 is a block diagram illustrating a memory controller 1015 that can support a method of just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure. The memory controller 1015 can be a reference to Figure 1 The memory controller 140 described herein or see Figure 5 1065 and a timing component 1055, which may be referred to in detail in conjunction with FIG. Figure 5 Depicted are examples of bias component 550 and timing component 555. Memory controller 1015 may also include a signal manager 1045 that provides control signals to different components in the memory device, and in particular cooperates with bias component 1065 and timing component 1055 to bias memory cells during access operations.

[0101] The memory controller 1015 may also include a program manager 1098 to manage access operations during the programming phase. For example, the program manager may manage codeword programming operations, such as reference Figure 6 As described. Through its programming manager 1098, the memory controller 1015 may receive user data. In some examples, the memory controller 1015 may read previous user data from the memory cell, and write new user data, and merge the new user data with the previous user data into a write register. Then, mask register information may be generated, and wherein the mask register information may indicate the bits of the previous user data stored in the memory cell whose logic values ​​will be switched or not switched. In some examples, the memory controller 1015 may use the mask register information to count the number of first logic values ​​(logic "0") and second logic values ​​(logic "1") to be written, respectively, and store the number of first logic values ​​and second logic values ​​in a first counter and a second counter, respectively. In some examples, the memory controller 1015 may apply programming pulses to the memory cell according to the mask register information.

[0102] The memory controller 1015 may also include a read manager 1099 to manage access operations during read accesses (e.g., codeword reads). For example, the read manager, in cooperation with the sense manager 1050, the reference voltage manager (or VREF manager) 1035, and the cell count manager 1040, may implement the methods described herein. Figures 6 to 7The method described herein. Each memory cell in a codeword is determined to be in one or another logic state relative to a reference voltage, and under the control of VREF manager 1035, the reference voltage is modified until the count of cells in a predefined logic state, as determined by cell count manager 1040, satisfies a criterion. In some instances, the criterion is a match between the memory cell count (as determined relative to the last changed reference voltage) and the number of bits expected to be in that logic state, the data of which bits in the predetermined logic state having been retrieved from the memory location where they were stored during the last programming operation. In some instances, the criterion may include the memory cell count differing from the expected number of bits in the predefined logic state by more than the detection capability of an error correction engine (ECC). In these cases, under the control of ECC manager 1097, an error correction algorithm may be applied to the memory cells of the codeword, as sensed relative to the last modified reference voltage. In a trial and repeat approach, the ECC algorithm may be applied multiple times.

[0103] The bias component 1065 and the timing component 1055 in the memory controller, as well as the VREF manager 1035, the signal manager 1045, the program manager 1098, the read manager 1099, the sense manager 1050, the VREF manager 1035, the cell count manager 1040, the ECC manager 1097, and other components or modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0104] Fig.11 A diagram illustrating a system including a device that can support a method for just-in-time programming and verification of memory cells based on counters and ECC feedback according to an example of the present disclosure. The device 1105 can be as described above (e.g., with reference to Figure 1 ) or include examples of components of memory device 100 described in the foregoing. Device 1105 may include components for bidirectional communication, including components for transmitting and receiving communications, including memory controller 1115, memory unit 1110, basic input / output system (BIOS) component 1125, processor 1130, I / O component 1135, and peripheral component 1140. These components may communicate electronically via one or more buses, such as bus 1101.

[0105] The memory controller 1115 can operate one or more memory cells as described herein. Specifically, the memory controller 1115 can be configured to support the described methods of programming and verifying memory cells on the fly based on counters and ECC feedback. In some cases, the memory controller 1115 can include row components, column components, or a combination thereof, as described in reference to 1.

[0106] Memory cell 1110 may be a reference Figure 1and 5 Examples of memory cells 105 or 510 are described, and may store information (eg, in the form of logic states) as described herein.

[0107] BIOS component 1125 is a software component including BIOS operating as firmware that can initialize and run various hardware components. BIOS component 1125 can also manage the data flow between the processor and various other components such as peripheral components, I / O control components, etc. BIOS component 1125 can include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0108] The processor 1130 may include an intelligent hardware device (e.g., a general purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, discrete gate or transistor logic components, discrete hardware components). In some cases, the processor 1130 may be configured to operate the memory array using a memory controller. In other cases, the memory controller may be integrated into the processor 1130. The processor 1130 may be configured to execute computer readable instructions stored in the memory to perform various functions.

[0109] I / O controller 1135 can manage input and output signals of device 1105. I / O controller 1135 can also manage peripheral devices that are not integrated into the device. In some cases, I / O controller 1135 can represent a physical connection or port to an external peripheral device. In some cases, I / O controller 1135 can utilize, for example, 1105. The I / O controller 1135 may be a memory device that is used to store and retrieve information from the memory cells 1110, including receiving information associated with a sensed logical state of one or more of the memory cells 1110, or providing information associated with a logical state written to one or more of the memory cells 1110.

[0110] Peripheral components 1140 may include any input or output device, or an interface for such a device. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

[0111] Input 1141 may represent a device or signal external to device 1105 that provides input to device 1105 or its components. This may include a user interface or an interface with other devices or between other devices. In some cases, input 1141 may be managed by I / O controller 1135 and may interact with device 1105 via peripheral components 1140.

[0112] Output 1142 may represent a device or signal external to device 1105 that is configured to receive output from device 1105 or any of its components. Examples of output 1142 may include a display, an audio speaker, a printing device, another processor or printed circuit board, or other device. In some cases, output 1142 may be a peripheral element that interfaces with device 1105 via peripheral component 1140. In some cases, output 1142 may be managed by I / O controller 1135.

[0113] The components of device 1105 may include circuits designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as conductive wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements. Device 1105 may be a computer, server, laptop, notebook, tablet, mobile phone, wearable electronic device, personal electronic device, etc. Or device 1105 may be a part or element of such a device.

[0114] In some examples, a method of operating a memory cell is described. The method may include: reading previous user data from the memory cell; writing new user data and merging the new user data with the previous user data into a write register; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cell whose logic values ​​are to be switched or not to be switched; counting the number of first logic values ​​and second logic values ​​to be written using the mask register information, respectively; storing the number of first logic values ​​and second logic values ​​into first counters and second counters, respectively; and applying a programming pulse to the memory cell according to the mask register information.

[0115] In some examples, an apparatus as described herein may perform one or more methods. The apparatus may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: reading previous user data from a memory cell; writing new user data and merging the new user data with the previous user data into a write register; generating mask register information, wherein the mask register information indicates bits of the previous user data stored in the memory cell whose logic values ​​are to be switched or not to be switched; counting the number of first logic values ​​and second logic values ​​to be written using the mask register information, respectively; storing the number of first logic values ​​and second logic values ​​into a first counter and a second counter, respectively; and applying a programming pulse to the memory cell according to the mask register information.

[0116] Some examples of the methods and apparatus described herein may further include operations, features, circuits, logic, means, or instructions for comparing the logic value of each bit in the new user data to the logic value of each bit in the previous user data.

[0117] In some examples of the methods and apparatus described herein, for bits whose logic values ​​will switch, the programming pulses can stop rising once the logic value of the bit can switch, and for bits whose logic values ​​do not switch, the programming pulses can shift.

[0118] In some examples of the methods and apparatus described herein, each memory cell can be programmed and sensed such that when a memory cell may not be fully programmed, additional programming pulses can be applied until such time as the memory cell can switch to a desired logic value.

[0119] Some examples of the methods and apparatus described herein may further include operations, features, circuits, logic, means, or instructions for calculating a new ECC parity.

[0120] Some examples of the methods and apparatus described herein may further include operations, features, circuits, logic, components, or instructions for performing the following steps: counting the number of memory cells that can be triggered to switch during the application of a programming pulse; and applying a programming pulse to the memory cells using the counter information and ECC feedback, and wherein the ECC feedback indicates information between a comparison between the number of switched cells and the number of first logic values ​​and the second logic value.

[0121] In some examples of the methods and apparatus described herein, new user data written to a memory cell may be repairable according to ECC feedback.

[0122] In some examples of the methods and apparatus described herein, the programming pulse can be less than a threshold value.

[0123] In some examples of the methods and apparatus described herein, the programming pulse can be selected from a ramp, a step, a variable slew rate ramp, a variable step staircase, or any combination thereof.

[0124] In some examples of the methods and apparatus described herein, when the number of first logic values ​​may be greater than the number of second logic values, the first logic value may be programmed followed by the second logic value; when the number of second logic values ​​may be greater than the number of first logic values, the second logic value may be programmed followed by the first logic value; and when there may be only one bit to be programmed per tile, the first logic value and the second logic value may be programmed simultaneously.

[0125] Another apparatus is described. The apparatus may include an access circuit configured to: read previous user data from a memory cell; write new user data and merge the new user data with the previous user data into a write register; generate mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cell whose logic values ​​are to be switched or not to be switched; count the number of first logic values ​​and second logic values ​​to be written using the mask register information, respectively; store the number of first logic values ​​and second logic values ​​into a first counter and a second counter, respectively; and apply a programming pulse to the memory cell according to the mask register information.

[0126] In some examples of the apparatus, the access circuitry may compare a logic value of each bit in the new user data with a logic value of each bit in the previous user data when writing the new user data and merging the new user data with the previous user data into the write register.

[0127] In some examples of the apparatus, the access circuit may, when applying a programming pulse to a memory cell according to mask register information, stop raising the programming pulse for a bit whose logic value is to be switched once the logic value of the bit is switchable, and shift the programming pulse for a bit whose logic value is not to be switched.

[0128] In some examples of the apparatus, sensing circuitry is used to sense each memory cell so that when a memory cell may not have been fully programmed, additional programming pulses can be applied until such time as the memory cell can switch to a desired logic value.

[0129] In some examples of the apparatus, the access circuitry may calculate new ECC parity when writing new user data and merging the new user data with previous user data into the write register.

[0130] In some examples of the apparatus, the access circuitry may be further configured to count the number of memory cells that may be triggered to switch during application of a programming pulse, and apply programming pulses to the memory cells using the counter information and ECC feedback, and wherein the ECC feedback indicates information of a comparison between the number of switched cells and the number of first and second logic values.

[0131] In some examples of an apparatus, new user data written to a memory cell may be repairable according to ECC feedback.

[0132] In some examples of the apparatus, the programming pulse may be less than a threshold value.

[0133] In some examples of the apparatus, the programming pulses can be selected from a ramp shape, a staircase, a variable slew rate ramp, a variable step staircase, or any combination thereof.

[0134] In some instances of the device, when the number of first logic values ​​can be greater than the number of second logic values, the first logic value can be programmed and then the second logic value can be programmed; when the number of second logic values ​​can be greater than the number of first logic values, the second logic value can be programmed and then the first logic value can be programmed; and when there can be only one bit to be programmed per tile, the first logic value and the second logic value can be programmed simultaneously.

[0135] The description herein provides examples and does not limit the scope, applicability or examples set forth in the appended claims. Changes may be made to the functions and arrangements of the elements discussed without departing from the scope of the present disclosure. Some examples may appropriately omit, replace or add various operations, procedures or components. Also, features described with respect to some examples may be combined in some other examples.

[0136] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0137] As used herein, the term "virtual ground" refers to a node of a circuit that maintains a voltage of approximately zero volts (0V), or more generally represents a reference voltage of a circuit or device that includes the circuit that may or may not be directly coupled to a ground terminal. Therefore, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V, or a virtual 0V, in a stable state. Virtual grounding can be implemented using various electronic circuit elements such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are also possible. "Virtual ground" or "virtual grounding" means connecting to approximately 0V, or some other reference voltage of a device.

[0138] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components or a coupling or may include an intermediate component. In other words, components that are "connected to" or "coupled to" are in electronic communication with each other. Components in electronic communication may actively exchange electrons or signals (e.g., in a powered circuit) or may not actively exchange electrons or signals (e.g., in a powered circuit), but may be configured and operable to exchange electrons or signals after the circuit is powered. For example, two components that are physically connected or coupled via a switch (e.g., a transistor) communicate electronically regardless of the state of the switch (e.g., open, closed).

[0139] The phrase "coupled between" may refer to the order of components relative to each other, and may refer to electrical coupling. In one example, component "B" electrically coupled between component "A" and component "C" may refer to the order of components "ABC" or "CBA" in an electrical sense. In other words, an electrical signal (e.g., voltage, charge, current) may be transferred from component A to component C by means of component B.

[0140] A description that component B is "coupled between component A and component C" should not be interpreted as excluding other intervening components in the described order. For example, component "D" may be coupled between component A and component B as described (e.g., as examples involving component orders "ADBC" or "CBDA") while still supporting component B being electrically coupled between component A and component C. In other words, use of the phrase "coupled between" should not be understood to necessarily involve an exclusive sequential order.

[0141] Additionally, a description that component B is "coupled between component A and component C" does not exclude a second, different coupling between component A and component C. For example, component A and component C may be coupled to each other in a separate coupling that is parallel to the coupling level via component B. In another example, component A and component C may be coupled via another component "E" (e.g., component B is coupled between component A and component C, and component E is coupled between component A and component C). In other words, the use of the phrase "coupled between" should not be understood as an exclusive coupling between components.

[0142] The term "isolation" refers to a relationship between components where electrons are not currently able to flow between the components; if there is an open circuit between the components, the components are isolated from each other. For example, two components physically coupled by a switch can be separated from each other when the switch is turned on.

[0143] As used herein, the term "short" refers to a relationship between components in which a conductive path is established between the components via activation of a single intermediate component between the two components in question. For example, a first component shorted to a second component may exchange electrons with the second component when a switch between the two components is closed. Thus, shorting may be a dynamic operation of the application of a voltage and / or charge flow between components (or lines) in electronic communication.

[0144] As used herein, the term "terminal" may not indicate a physical boundary or connection point of a circuit element. In fact, a "terminal" may refer to a reference point of a circuit associated with a circuit element, which may also be referred to as a "node" or "reference point."

[0145] The devices discussed herein, including memory devices, circuits, and the like, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0146] The transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped or degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (e.g., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0147] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the appended claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. For the purpose of providing an understanding of the described technology, the detailed description includes specific details. However, embodiments may be implemented without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0148] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by the reference label following a dashed line and a second label that distinguishes among similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0149] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor; however, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, a combination of multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0150] The functions described herein can be implemented by hardware, software executed by a processor, firmware, or any combination thereof. If implemented by software executed by a processor, the function can be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software, hardware, firmware, hard wiring, or any combination of these executed by a processor. The features of the implementation functions can also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. In addition, as used herein (included in the claims), as used in an item list (e.g., an item list preceded by a phrase such as "at least one of" or "one or more of"), the "or" used indicates a list containing endpoints, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

[0151] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term "substantially") need not be absolute, but is close enough to achieve the advantage of the characteristic, or close enough that the characteristic in question is true in the context of the relevant aspects of the disclosure.

[0152] As used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on".

[0153] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Those skilled in the art will readily appreciate various modifications to the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of operating a memory cell, comprising: reading previous user data from the memory unit; Writing new user data and merging the new user data with the previous user data into a write register; generating mask register information, wherein the mask register information indicates whether a logic value of a bit of the previous user data stored in the memory cell is to be switched or not to be switched; respectively counting the number of first logic values ​​and second logic values ​​to be written using the mask register information; storing the number of the first logic value and the second logic value in a first counter and a second counter, respectively; as well as According to the mask register information, a programming pulse is applied to the memory cell; wherein: When the number of the first logic values ​​is greater than the number of the second logic values, programming the first logic values ​​and then programming the second logic values; When the number of the second logic values ​​is greater than the number of the first logic values, programming the second logic value and then programming the first logic value; and When there is only one bit to be programmed per tile, the first logic value and the second logic value are programmed simultaneously.

2. The method of operating a memory cell according to claim 1, further comprising, in the step of writing the new user data and merging the new user data with the previous user data into the write register, The logic value of each bit in the new user data is compared with the logic value of each bit in the previous user data.

3. The method of operating a memory cell according to claim 1 , further comprising, in the step of applying the programming pulse to the memory cell according to the mask register information, For bits whose logic values ​​are to switch, the programming pulse is stopped once the logic value of the bit switches, and for bits whose logic values ​​are not to switch, the programming pulse is shifted.

4. The method of operating a memory cell according to claim 1, wherein: Each memory cell is programmed and sensed so that when a memory cell is not fully programmed, additional programming pulses are applied until such time as the memory cell switches to the desired logic value.

5. The method of operating a memory cell according to claim 1 , further comprising, in the step of writing the new user data and merging the new user data with the previous user data into the write register, comprising: Calculate new ECC parity.

6. The method of operating a memory cell according to claim 5, further comprising: counting a number of said memory cells triggered to switch during said application of said programming pulses; as well as The programming pulses are applied to the memory cells using counter information and ECC feedback, and wherein the ECC feedback indicates information indicative of a comparison between a number of switched cells and the number of the first logic value and the second logic value.

7. The method of operating a memory cell according to claim 6, wherein: The new user data written into the memory cells may be repaired according to the ECC feedback.

8. The method of operating a memory cell according to claim 1, wherein the programming pulse is smaller than a threshold value.

9. The method of operating a memory cell according to claim 1, wherein: The programming pulse is selected from a ramp shape, a step, a variable slew rate ramp, a variable step staircase, or any combination thereof.

10. A circuit for operating a memory cell, comprising: An access circuit configured to: reading previous user data from the memory unit; Writing new user data and merging the new user data with the previous user data into a write register; generating mask register information, wherein the mask register information indicates whether a logic value of a bit of the previous user data stored in the memory cell is to be switched or is not to be switched; respectively counting the number of first logic values ​​and second logic values ​​to be written using the mask register information; storing the number of the first logic value and the second logic value in a first counter and a second counter, respectively; as well as According to the mask register information, a programming pulse is applied to the memory cell; wherein: When the number of the first logic values ​​is greater than the number of the second logic values, programming the first logic values ​​and then programming the second logic values; When the number of the second logic values ​​is greater than the number of the first logic values, programming the second logic value and then programming the first logic value; and When there is only one bit to be programmed per tile, the first logic value and the second logic value are programmed simultaneously.

11. The circuit for operating a memory cell according to claim 10, wherein the access circuit will write the new user data and merge the new user data with the previous user data into the write register, The logic value of each bit in the new user data is compared with the logic value of each bit in the previous user data.

12. The circuit for operating a memory cell according to claim 10, wherein the access circuit will, when applying the programming pulse to the memory cell according to the mask register information, For a bit whose logic value is to be switched, once the logic value of the bit switches, the programming pulse is stopped from rising, and For bits whose logic value is not to switch, the programming pulse is shifted.

13. The circuit for operating a memory cell according to claim 10, further comprising: Sensing circuitry is used to sense each memory cell so that when a memory cell has not been fully programmed, additional programming pulses are applied until the memory cell switches to the desired logic value.

14. The circuit for operating a memory cell according to claim 10, wherein the access circuit will write the new user data and merge the new user data with the previous user data into the write register, Calculate new ECC parity.

15. The circuit for operating a memory cell according to claim 14, wherein the access circuit is further configured to: counting a number of said memory cells that are triggered to switch during said application of said programming pulses; and The programming pulses are applied to the memory cells using counter information and ECC feedback, and wherein the ECC feedback is indicative of information of a comparison between a number of switched cells and the number of the first logic value and the second logic value.

16. The circuit for operating a memory cell according to claim 15, wherein: The new user data written into the memory cells may be repaired according to the ECC feedback.

17. The circuit for operating a memory cell according to claim 10, wherein the programming pulse is less than a threshold value.

18. The circuit for operating a memory cell according to claim 10, wherein: The programming pulse is selected from a ramp shape, a step, a variable slew rate ramp, a variable step staircase, or any combination thereof.

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