Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device is provided. The method includes providing a substrate in which a main region including a first cell region and a first peripheral region, and an edge region including a second cell region and a second region are defined; sequentially forming a mold layer, a support layer, a mask layer, and a preliminary pattern layer on the substrate; exposing the preliminary pattern layer to light to simultaneously form a first pattern and a second pattern on the mask layer of the first cell region and the second cell region, respectively; forming an etching stop layer on the second pattern; and etching the mask layer using the etching stop layer and the first pattern to form a hole pattern in the mold layer and the support layer of the first cell region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0026023, filed with the Korean Intellectual Property Office on March 2, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to methods for manufacturing semiconductor devices. Background Technology

[0004] Semiconductor devices have been developed to enable high-speed operation at low voltages, and semiconductor device manufacturing processes have been developed to increase integration density. Therefore, in highly integrated semiconductor devices, a high proportion of patterns can be spaced with fine pitch and fine width.

[0005] In some highly integrated devices, patterns beyond the application scope of dual patterning (DPT) may be required, and extreme ultraviolet (EUV) lithography has been introduced to meet this need. If manufacturers follow the process sequence used in DPT when using EUV lithography, it may reduce the reliability of the semiconductor device or potentially increase the number of process steps. Summary of the Invention

[0006] This disclosure provides a method for manufacturing a semiconductor device that simplifies the process while increasing the integration density of the semiconductor device.

[0007] This disclosure also provides a method for manufacturing a semiconductor device that improves the reliability of a device including the semiconductor device while increasing the integration density of the semiconductor device.

[0008] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0009] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: providing a substrate in which a main region including a first unit region and a first peripheral region is defined, and an edge region including a second unit region and a second region; sequentially forming a molding layer, a support layer, a mask layer and a preliminary patterning layer on the substrate; exposing the preliminary patterning layer to simultaneously form a first pattern and a second pattern on the mask layer of the first unit region and the second unit region, respectively; forming an etch stop layer on the second pattern; and using the etch stop layer and the first pattern to etch the mask layer to form a hole pattern in the molding layer and the support layer of the first unit region.

[0010] According to an aspect of the present disclosure, a method of manufacturing a semiconductor device includes providing a substrate in which a main area including a first cell area and a first peripheral area, and an edge area including a second cell area and a second area are defined; sequentially forming a mold layer, a support layer, a mask layer, an anti-reflective coating layer, and a preliminary pattern layer on the substrate; exposing the preliminary pattern layer to form a first pattern and a second pattern on the anti-reflective coating layer of the first cell area and the second cell area, respectively; forming an etch stop layer on the second pattern, the etch stop layer not being formed on the main area; and etching the mask layer using the etch stop layer and the first pattern to form a hole pattern in the mold layer and the support layer of the first cell area.

[0011] According to an aspect of the present disclosure, a method of manufacturing a semiconductor device includes providing a substrate in which a main area including a first cell area and a first peripheral area, and an edge area including a second cell area and a second area are defined; sequentially forming a mold layer, a support layer, a mask layer, an anti-reflective coating layer, and a preliminary pattern layer on the substrate; exposing the preliminary pattern layer to form a first pattern and a second pattern on the anti-reflective coating layer of the first cell area and the second cell area, respectively; forming an etch stop layer on the second pattern, the etch stop layer not being formed on the main area; and etching the mask layer using the etch stop layer and the first pattern to form a hole pattern in the mold layer and the support layer of the first cell area. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

[0013] Figure 1 is a plan view showing a portion of a wafer according to some embodiments of the present inventive concept;

[0014] Figure 2 is Figure 1is a cross-sectional view taken along line B-B’ of

[0015] Figure 3 is a cross-sectional view taken along line B-B’ of Figure 2

[0016] Figures 4 to 19 is a diagram showing intermediate steps of a method of manufacturing a semiconductor device according to some embodiments of the inventive concept;

[0017] Figure 20 and Figure 21 is a diagram showing intermediate steps of a method of manufacturing a semiconductor device according to some other embodiments of the inventive concept; and

[0018] Figure 22 and Figure 23 is a diagram showing intermediate steps of a method of manufacturing a semiconductor device according to some other embodiments of the inventive concept. DETAILED DESCRIPTION

[0019] Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant descriptions thereof will be omitted. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should be noted that aspects described with respect to one embodiment can be incorporated into different embodiments, although not specifically described with respect thereto. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination.

[0020] Figure 1 is a plan view showing a portion of a wafer according to some embodiments of the inventive concept. Figure 2 is a cross-sectional view taken along line B-B’ of Figure 1 is a cross-sectional view taken along line B-B’ of

[0021] Referring to Figure 1 and Figure 2 , the wafer 1 can include a plurality of chip regions 10 and a plurality of edge regions 20 positioned to surround or encircle the plurality of chip regions 10 at edges of the wafer 1.

[0022] Each of the plurality of chip regions 10 can include a first cell region CA1 and a first peripheral region PA1. The first peripheral region PA1 can include a first core region PA1_1 and a first surrounding region PA1_2.

[0023] ​Each of the multiple edge regions 20 may include a second unit region CA2 and a second peripheral region PA2. The second peripheral region PA2 may include a second core region PA2_1 and a second surrounding region PA2_2.

[0024] Figure 2 The specific shapes, layouts, and arrangements of the unit regions CA1 and CA2 and the peripheral regions PA1 and PA2 shown are merely examples, and various modifications can be made within the technical spirit of various embodiments of the inventive concept.

[0025] Figure 3 It is along Figure 2 A cross-sectional view taken from line B-B'.

[0026] Figure 3 It shows Figure 2 A cross-sectional view of each of the first unit region CA1, the first peripheral region PA1, the second unit region CA2, and the second peripheral region PA2.

[0027] refer to Figure 3 The semiconductor device 100 may include a lower structure 101 formed in the cell regions CA1 and CA2 and the peripheral regions PA1 and PA2.

[0028] Although not shown, the lower structure 101 may include a base substrate, an active region formed on the base substrate, a device isolation film defining the active region, a source / drain region, a word line, a bit line, a contact region, etc.

[0029] Furthermore, unit elements (not shown) for forming semiconductor devices, such as various types of active or passive elements, and interlayer insulating films (not shown) covering at least partially the unit elements, can be formed in the lower structure 101. The unit element can be, for example, a cell transistor, such as dynamic random access memory (DRAM) or flash memory. The cell transistor can be, for example, a DRAM memory cell transistor having a cell size of 6F² or 4F², but embodiments of the present invention are not limited thereto.

[0030] The base substrate may include silicon (Si), such as crystalline Si, polycrystalline silicon, or amorphous Si. In some other embodiments, the base substrate may include a semiconductor such as germanium (Ge), or a compound semiconductor such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0031] The contact area can connect the capacitor 170 to the source / drain region formed on the base substrate. The contact area can be formed of, for example, polysilicon.

[0032] In each of the plurality of chip regions 10 (see Figure 2 ), in the first cell region CA1, a lower electrode structure ES1 composed of the lower electrodes 172 and the first and second supports 122a and 124a, a gate dielectric film 174a located on and at least partially covering the lower electrode structure ES1, and an upper electrode 176a can be formed on the lower structure 101. The lower electrodes 172, the dielectric film 174a, and the upper electrode 176a can constitute a capacitor 170.

[0033] In some embodiments, each of the lower electrodes 172 can be connected to a contact region (not shown) formed in the lower structure 101. In this embodiment, the lower electrodes 172 are shown in a columnar shape, but embodiments of the inventive concept are not limited thereto. For example, the lower electrodes 172 can have a cylindrical shape, but embodiments of the inventive concept are not limited thereto.

[0034] The dielectric film 174a can be formed to be located on and at least partially cover the lower electrodes 172 and the supports 122a and 124a. In some embodiments, the dielectric film 174a can include silicon oxide or a high dielectric constant (high-k) material. In some other embodiments, the dielectric film 174a can include, for example, a composite layer having a double structure of a silicon oxide layer and a silicon nitride layer, or a silicon oxide layer with a surface nitrided. The high-k material can include, for example, at least one or a combination of materials including, but not limited to, aluminum oxide (AlOx), tantalum oxide (TaxOy), titanium oxide (TiOx), yttrium oxide (YxOy), zirconium oxide (ZrOx), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfOx), hafnium silicon oxide (HfSixOy), lanthanum oxide (LaxOy), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (PrxOy).

[0035] The upper electrode 176a can be formed to be located on and at least partially cover the lower electrode structure ES1 composed of the lower electrodes 172a, the supports 122a and 124a, and the gate dielectric film 174a. The upper electrode 176a can include, for example, one or more of titanium, titanium nitride, tantalum nitride, platinum, tungsten, doped polysilicon, doped silicon germanium, etc.

[0036] In some embodiments, the upper electrode 176a can be made of the same material as the lower electrode 172, but embodiments of the inventive concept are not limited thereto.

[0037] The support members 122a and 124a can function to support the lower electrode 172 formed on the lower structure 101 to prevent the lower electrode 172 from collapsing or reduce the possibility of the lower electrode 172 collapsing. In some embodiments, the support members 122a and 124a can include a material such as silicon nitride, tantalum oxide, and / or titanium oxide.

[0038] In the cell region in each of the plurality of edge regions 20 (see Figure 2 ), i.e., in the second cell region CA2, a dummy structure DS1 in which a first mold film 112b, a first support member film 122b, a second mold film 114b, and a second support member film 124b are sequentially stacked can be formed on the lower structure 101. A dielectric film 174b and an upper electrode 176b can be sequentially formed on the second support member film 124b of the dummy structure DS1. The dielectric film 174b and the upper electrode 176b can be made of the same materials as the dielectric film 174a and the upper electrode 176a formed in the first cell region CA1, respectively.

[0039] The first support member 122a of the first cell region CA1 and the first support member film 122b of the second cell region CA2 can be formed by patterning the first support member layer 122, which will be described below with reference to Figure 4 In addition, the second support member 124a of the first cell region CA1 and the second support member film 124b of the second cell region CA2 can be formed by patterning the second support member layer 124, which will be described below with reference to Figure 4

[0040] Accordingly, the first support member film 122b and the second support member film 124b can be positioned at substantially the same height as the first support member 122a and the second support member 124a formed in the first cell region CA1, respectively. In addition, the first support member film 122b and the second support member film 124b can be made of the same materials as the first support member 122a and the second support member 124a formed in the first cell region CA1, respectively.

[0041] The first mold film 112b and the second mold film 114b can be formed of a material that is etched selectively different from the support member films 122b and 124b. For example, when the support member films 122b and 124b are made of silicon nitride, the mold films 112b and 114b can be made of silicon oxide, but embodiments of the inventive concept are not limited thereto.

[0042] In some embodiments, as Figure 3 ​As shown in FIG. 1, the first mold film 112b and the second mold film 114b can be partially recessed by etching, and the gate dielectric film 174a can be coated on the sidewalls of the etched first mold film 112b and the second mold film 114b, and the upper electrode 176a can be located on the gate dielectric film 174a on the sidewalls and at least partially cover the gate dielectric film 174a on the sidewalls. However, embodiments of the present inventive concept are not limited thereto. As an example, the sidewalls of the first mold film 112b and the second mold film 114b can be aligned with the sidewalls of the first support film 122b of the second cell area CA2.

[0043] The interlayer insulating film 190 can be formed in each of the peripheral areas in the lower structure 101, i.e., each of the plurality of chip areas 10 (see Figure 2 ) and the first peripheral area PA1 and the second peripheral area PA2 in each of the plurality of edge areas 20 (see Figure 2 ). The interlayer insulating film 190 may, for example, include silicon oxide, but embodiments are not limited thereto.

[0044] Figures 4 to 19 is a diagram illustrating an intermediate step of a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept. Figures 4 to 19 is a cross-sectional view illustrated according to a process sequence, and a cross-section B-B’ of Figure 2 is illustrated according to a process sequence.

[0045] Referring to Figure 4 , the first mold layer 112 and the first support layer 122, the second mold layer 114, the second support layer 124, the carbon-containing layer 130, the first mask layer 141, the second mask layer 142, the anti-reflective coating 150, and the preliminary pattern layer 160P can be sequentially formed on the lower structure 101 in the first cell area CA1 and the second cell area CA2 and the first peripheral area PA1 and the second peripheral area PA2.

[0046] The first mold layer 112, the first support layer 122, the second mold layer 114, the second support layer 124, the carbon-containing layer 130, the first mask layer 141, the second mask layer 142, the anti-reflective coating 150, and the preliminary pattern layer 160P may, for example, each be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a spin coating process, or the like.

[0047] The first mold layer 112 and the second mold layer 114 can serve as a sacrificial film in order to form the lower electrode 172 (see Figure 3 ) by a subsequent process. In some embodiments, the first mold layer 112 and the second mold layer 114 may, for example, include silicon oxide.

[0048] The first support layer 122 and the second support layer 124 can be material layers for forming the first support layer 122a (see Figure 3 ) and the second support layer 124a (see Figure 3 ), respectively, of the lower electrode 172 (see Figure 3 ). In some embodiments, the first support layer 122 and the second support layer 124 can be formed of a material that is etch-selective to the first mold layer 112 and the second mold layer 114. For example, when the first mold layer 112 and the second mold layer 114 are made of silicon oxide, the first support layer 122 and the second support layer 124 can be made of silicon nitride. However, embodiments are not limited thereto.

[0049] The carbon-containing layer 130 is, for example, an amorphous carbon layer (ACL). The carbon-containing layer 130 according to some embodiments of the inventive concept can be formed as a single plane before the stack of the first mask layer 141, the second mask layer 142, the anti-reflective coating 150, and the preliminary pattern layer 160P. That is, the carbon-containing layer 130 can be planarized so as to have a substantially uniform height (in the Z direction) with respect to the lower structure 101 on the different regions CA1, PA1, CA2, and PA2. In addition, the carbon-containing layer pattern 130P can be formed to serve as an etch mask pattern.

[0050] The first mask layer 141 and the second mask layer 142 can be material layers for forming the first preliminary hole pattern 140P1 (see Figure 8 ) and the second preliminary hole pattern 140P2 (see Figure 8 ). Each of the first mask layer 141 and the second mask layer 142 can be formed of a material that is etch-selective to each other.

[0051] In some embodiments, the first mask layer 141 can include silicon oxide, and the second mask layer 142 can include a spin-on hard mask (SOH). However, embodiments are not limited thereto.

[0052] An anti-reflective coating (ARC layer) 150 can be formed on the second mask layer 142. The ARC layer 150 can include silicon nitride or silicon oxynitride. For example, the ARC layer 150 can be silicon oxynitride. The ARC layer 150 can be thinner than the preliminary pattern layer 160P to be described below.

[0053] The ARC layer 150 can reduce or prevent diffuse reflection when the preliminary pattern layer 160P is exposed, and thus, can be used to perform a photolithography process.

[0054] The preliminary patterning layer 160P is a material layer used to form the first pattern P1 and the second pattern P2. Although shown as a single layer, according to some embodiments, the preliminary patterning layer 160P may include multiple material layers. The preliminary patterning layer 160P may include a photoresist. According to some embodiments, the preliminary patterning layer 160P may include a carbon compound.

[0055] refer to Figure 5 The initial pattern layer 160P can be exposed to form a pattern layer 160 including a first pattern P1 and a second pattern P2. That is, the pattern layer 160 can be formed using a photolithography process, and the first pattern P1 and the second pattern P2 can be formed simultaneously.

[0056] The pattern layer 160 can completely cover the first peripheral region PA1 and the second peripheral region PA2 in the Z direction, and partially cover the first unit region CA1 and the second unit region CA2 in the Z direction.

[0057] In the plan view, the pattern layers 160 on the first unit region CA1 and the second unit region CA2 can have parallel line shapes or parallel strip shapes. A first pattern P1 and a second pattern P2 can be respectively set on the first unit region CA1 and the second unit region CA2.

[0058] The height in the Z direction between the base substrate and the highest point of the first pattern P1 is the same as the height in the Z direction between the base substrate and the highest point of the second pattern P2. The ARC layer 150 may be located on the bottom surface of the first pattern P1 and the second pattern P2, and may be partially exposed between portions of the pattern layer 160.

[0059] Extreme ultraviolet (EUV) light can be used to expose the initial pattern layer 160P, and thus, the first pattern P1 and the second pattern P2 can be formed simultaneously. Embodiments of the inventive concept are not limited thereto, and may include, for example, light and electron beams from light sources such as ArF or KrF.

[0060] refer to Figure 6 A first redo layer 160R1 can be formed on the pattern layer 160 in the first unit region CA1, the first peripheral region PA1, the second unit region CA2, and the second peripheral region PA2.

[0061] The first redo layer 160R1 can be, for example, a silicon oxynitride layer. The first redo layer 160R1 can also be an etch-selective patterning layer 160, as will be referred to below. Figure 7 The first etch stop layer 161_1 described is made of a different material. If the first etch stop layer 161_1 is provided, for example, on the first cell region CA1 or not provided on the second cell region CA2, the first etch stop layer 161_1 can be removed.

[0062] The first rework layer 160R1 can be formed conformally on the pattern layer 160 by an atomic layer deposition (ALD) process, but embodiments of the inventive concept are not limited thereto.

[0063] Referring to Figure 7 A first etch stop layer 161_1 can be formed on the first rework layer 160R1 in the second cell area CA2 and the second peripheral area PA2.

[0064] The first etch stop layer 161_1 can include a photo-sensitive etch stop (PSES) mask layer. In some other embodiments, the first etch stop layer 161_1 can be formed of a material that is etch-selective to the pattern layer 160, the ARC layer 150, and the second mask layer 142, but embodiments of the inventive concept are not limited thereto. Figure 7 Instead, the first etch stop layer 161_1 can be located on the second cell area CA2 and at least partially cover the second cell area CA2 in the Z-direction only, and not on the second peripheral area PA2 and at least partially cover the second peripheral area PA2, but embodiments of the inventive concept are not limited thereto.

[0065] The first etch stop layer 161_1 can be formed of a material that is etch-selective to the pattern layer 160, the ARC layer 150, and the second mask layer 142. The first etch stop layer 161_1 can include, for example, at least one of a carbon compound, silicon oxide, silicon nitride, silicon oxynitride, a metal film, a photoresist, a spin-on glass (SOG), and / or a spin-on hard mask (SOH).

[0066] Referring to Figure 8 The first mask layer 141 and the second mask layer 142 located in the first cell area CA1 and the second cell area CA2 are etched using the first pattern P1 located in the first cell area CA1 and the second pattern P2 located in the second cell area CA2 as etch mask patterns (see Figure 7 ), thereby forming a first preliminary hole pattern 140P1 and a second preliminary hole pattern 140P2 that serve as mask patterns.

[0067] During the process of forming the first preliminary hole pattern 140P1 and the second preliminary hole pattern 140P2, the first etch stop layer 161_1, the pattern layer 160, the ARC layer 150, and the second mask layer 142 can be removed. However, due to the presence of the first etch stop layer 161_1, while the first preliminary hole pattern 140P1 penetrates or extends through the first mask layer 141 in the first cell area CA1, the second preliminary hole pattern 140P2 does not extend through the first mask layer 141 in the second cell area CA2.

[0068] In addition, due to the presence of the first etch stop layer 161_1, a height difference in the Z-direction can occur in the first mask layer 141 between the first cell area CA1 and the second cell area CA2. As shown in FIG. 2B, the first preliminary hole pattern 140P1 can be formed to have a first height H1 in the first cell area CA1, and the second preliminary hole pattern 140P2 can be formed to have a second height H2 in the second cell area CA2.Figure 8 The top surface of the first cell region CA1 can be lower than the top surface of the second cell region CA2, as shown in FIG. 1B.

[0069] Referring to FIG. 1B, Figure 8 and Figure 9 A carbon-containing layer 130 in the first cell region CA1 can be etched using the first preliminary hole pattern 140P1 in the first cell region CA1 and the second preliminary hole pattern 140P2 in the second cell region CA2 as an etching mask pattern to form a carbon-containing layer pattern 130P.

[0070] Since the etching selectivity is different between the first mask layer 141 and the carbon-containing layer 130, the second preliminary hole pattern 140P2 in the second cell region CA2 can not penetrate or extend through the first mask layer 141 when penetrating or etching through the carbon-containing layer 130 in the first cell region CA1.

[0071] However, embodiments of the inventive concept are not limited thereto, and although not shown, a portion of the carbon-containing layer 130 can be etched in the second cell region CA2 during the above-described process operations.

[0072] Referring to FIG. 1B, Figure 10 The first molding layer 112, the first support layer 122, the second molding layer 114, and the second support layer 124 in the first cell region CA1 can be etched using the carbon-containing layer pattern 130P as an etching mask pattern to form a capacitor hole pattern 172H in the first cell region CA1.

[0073] During the process of forming the capacitor hole pattern 172H, a portion of the first mask layer 141 and the carbon-containing layer 130 can be removed, and due to Figure 8 the difference in height formed in FIG. 1B, and the difference in etching selectivity between the first mask layer 141 and the carbon-containing layer 130, a height difference in the Z direction can occur in the carbon-containing layer 130.

[0074] The top surface of the first cell region CA1 can be lower than the top surface of the first peripheral region PA1 and the second cell region CA2 in the Z direction, and the top surface of the first peripheral region PA1 can be lower than the top surface of the second cell region CA2 in the Z direction.

[0075] Before the operation of Figure 11 A gray ash and stripping process can be performed on the carbon-containing layer 130 remaining on the second support layer 124.

[0076] Referring to FIG. 1B, Figure 11A plurality of lower electrodes 172 in the capacitor hole pattern 172H can be formed. Thereafter, a support mask layer 180, and first and second support pattern layers 182a and 182b can be sequentially formed on the upper surfaces of the second support layer 124 and the lower electrodes 172 in the first and second cell areas CA1 and CA2, and the first and second peripheral areas PA1 and PA2.

[0077] The first and second support pattern layers 182a and 182b can include a photoresist, and according to some embodiments, the preliminary pattern layer 160 can include a carbon compound. However, embodiments of the inventive concept are not limited thereto.

[0078] In some embodiments, the support mask layer 180 can include silicon oxide or a spin-on hard mask (SOH), but embodiments of the inventive concept are not limited thereto.

[0079] The first support pattern layer 182a is disposed on the support mask layer 180 in the first cell area CA1. In a plan view, the first support pattern layer 182a can have a linear shape parallel to each other, a bar shape parallel to each other, a square shape, or a circular shape, but embodiments of the inventive concept are not limited thereto. Thus, a portion of the support mask layer 180 can be exposed in the first cell area CA1.

[0080] In the drawings, the portion of the support mask layer 180 exposed by the first support pattern layer 182a and the lower electrodes 172 do not overlap each other in a plan view, but according to other embodiments of the inventive concept, can at least partially overlap each other.

[0081] The second support pattern layer 182b can be located on the support mask layer 180 in the second cell area CA2 in the Z direction and completely cover the support mask layer 180 in the second cell area CA2.

[0082] Reference Figure 12 The support mask layer 180 can be etched along the first and second support pattern layers 182a and 182b to form a support mask pattern. A portion of the second support layer 124 under the support mask pattern can be removed to form a support opening SG1 along the second support 124a and the sidewall of the support mask pattern.

[0083] According to some embodiments of the inventive concept, a plurality of support openings SG1 can be formed in the first cell area CA1.

[0084] Reference Figure 13 A portion of the second molding layer 114 located in the first cell area CA1, and the first and second peripheral areas PA1 and PA2 can be removed (seeFigure 12 ), to expose the first support layer 122. The removal of the second mold layer 114 (see Figure 12 ) located in the first cell area CA1 and the first and second peripheral areas PA1 and PA2 can be performed by a lift-off process using limulus amebocyte lysate (LAL) coloration, a wet etching process, a graying and lift-off process, or the like.

[0085] In the removal process of the second mold layer 114 (see Figure 12 ) located in the first cell area CA1 and the first and second peripheral areas PA1 and PA2, since the second mold film 114b located in the second cell area CA2 is covered by the second support film 124b, the second mold film 114b in the second cell area CA2 can not be removed. However, according to an embodiment, as shown in Figure 13 , a portion of a sidewall of the second mold film 114b located in the second cell area CA2 is removed, so that the sidewall of the second mold film 114b can be concavely formed.

[0086] Referring to Figure 13 and Figure 14 , a portion of the first support layer 122 in the support opening SG1 can be removed to form the first support 122a and the first support film 122b. Also, the first mold layer 112 can be removed.

[0087] In addition, according to some embodiments of the inventive concept, when a portion of the second support layer 124 is removed in Figure 12 , a portion of the first support layer 122 can be removed by patterning.

[0088] Then, when the second mold layer 114 is removed and the second mold film 114b is formed in Figure 13 , the first mold layer 112 can be removed and the first mold film 112b can be formed.

[0089] Referring to Figure 15 , the support mask layer 180 remaining on the upper surface of the second support 124a, the second support film 124b, and the lower electrode 172 can be removed to form the lower electrode structure ES1 and the dummy structure DS1.

[0090] The removal of the remaining support mask layer 180 can be performed by a dry etching process, a wet etching process, or a graying and lift-off process, but embodiments of the inventive concept are not limited thereto.

[0091] Referring to Figure 16 and Figure 17The dielectric films 174a and 174b and the upper electrode material 176x can be formed in order on the first and second cell regions CA1 and CA2 and the first and second peripheral regions PA1 and PA2, and at least partially cover the first and second cell regions CA1 and CA2 and the first and second peripheral regions PA1 and PA2.

[0092] In Figure 16 , the same material is not used to form the dielectric films 174a and 174b in the first and second peripheral regions PA1 and PA2, but embodiments of the present inventive concept are not limited thereto. According to some embodiments, the dielectric films 174a and 174b and the upper electrode material 176x can be formed in order in the first and second peripheral regions PA1 and PA2.

[0093] In some embodiments, the dielectric films 174a and 174b can include, for example, silicon oxide or a high-k material. The upper electrode material 176x can include, for example, one or more of titanium, titanium nitride, tantalum nitride, platinum, tungsten, doped polysilicon, doped silicon germanium, etc.

[0094] The upper electrode material 176x can be formed, for example, by a PVD process, a CVD process, an MOCVD process, an ALD process, or a MOALD process, but embodiments of the present inventive concept are not limited thereto. In addition, as shown in Figure 17 , according to some embodiments, when the sidewalls of the first and second mold films 112b and 114b are concave, the upper electrode material 176x can be at least partially filled therein.

[0095] Referring to Figure 18 , the dielectric film (not shown) and the upper electrode material 176x located in the first and second peripheral regions PA1 and PA2 can be removed by performing a removal process, thereby forming the dielectric film 174a and the upper electrode 176a located in the first cell region CA1 and the dielectric film 174b and the upper electrode 176b located in the second cell region CA2. Accordingly, the first and second cell regions CA1 and CA2 can be electrically insulated.

[0096] Although not shown, the removal process can include performing an anisotropic etching process using a cell closure mask layer (not shown) formed on the first and second cell regions CA1 and CA2 and at least partially covering the first and second cell regions CA1 and CA2 as an etching mask after the cell closure mask layer is formed. However, embodiments of the present inventive concept are not limited thereto.

[0097] Referring to Figure 19An interlayer insulating film 190 can be formed on and at least partially cover the first and second peripheral areas PA1 and PA2. In some embodiments, the interlayer insulating film 190 can be formed on and at least partially cover the first and second cell areas CA1 and CA2 and the first and second peripheral areas PA1 and PA2.

[0098] The interlayer insulating film 190 can include silicon oxide, for example, but embodiments of the present inventive concept are not limited thereto.

[0099] Figure 20 and Figure 21 are diagrams illustrating intermediate steps of a method of manufacturing a semiconductor device according to some other embodiments of the present inventive concept.

[0100] Figure 20 and Figure 21 will focus on the differences in the description of the embodiments of Figure 6 and Figure 7 . In the drawings, the same components are denoted by the same reference numerals, and redundant descriptions thereof will be omitted.

[0101] Before the step of Figure 20 , the process steps of Figure 4 and Figure 5 are performed. Referring to Figure 20 , a portion of the ARC layer 150 can be etched along the first and second patterns P1 and P2 to expose the upper surface of the second mask layer 142. Further, a second rework layer 160R2 can be formed along the upper surface of the pattern layer 160, the sidewall of the ARC layer 150, and the upper surface of the second mask layer 142.

[0102] The second rework layer 160R2 can include the same material as the first rework layer 160R1 of Figure 6 , but is different from the first rework layer 160R1 in that the second rework layer 160R2 can physically contact the upper surface of the second mask layer 142.

[0103] Referring to Figure 21 , a second etching stop layer 161_2 can be formed on the second rework layer 160R2 in the second cell area CA2 and the second peripheral area PA2. The second etching stop layer 161_2 can include the same material as the first etching stop layer 161_1 of Figure 7 , but is different from the first etching stop layer 161_1 in that the second etching stop layer 161_2 can be disposed on the second rework layer 160R2. Thereafter, the process of Figures 8 to 19 is performed.

[0104] Figure 22 and Figure 23 are diagrams showing intermediate steps of a method of manufacturing a semiconductor device according to some other embodiments of the inventive concept.

[0105] Figure 22 and Figure 23 The description of Figure 6 and Figure 7 will focus on the differences from the description of the embodiments of

[0106] Prior to the operations of Figure 22 , process operations of Figure 4 and Figure 5 are performed. Referring to Figure 22 and Figure 23 , a portion of the ARC layer 150 and a portion of the second mask layer 142 are etched along the first pattern P1 and the second pattern P2 to expose the upper surface of the first mask layer 141, and thus, the first mask pattern 150P1 and the second mask pattern 150P2 can be formed.

[0107] In the process of forming the first mask pattern 150P1 and the second mask pattern 150P2, a portion of the ARC layer 150 can be removed to expose the upper surface of the ARC layer 150.

[0108] A third rework layer 150R can be formed along the upper surface of the ARC layer 150, the sidewall of the second mask layer 142, and the upper surface of the first mask layer 141. The third rework layer 150R can include the same material as the first rework layer 160R1 of Figure 6 , but is different from the first rework layer 160R1 in that the third rework layer 150R can physically contact the upper surface of the first mask layer 141.

[0109] Thereafter, a third etch stop layer 151 can be formed on the third rework layer 150R in the second cell region CA2 and the second peripheral region PA2. The third etch stop layer 151 can include the same material as the first etch stop layer 161_1 of Figure 7 , but is different from the first etch stop layer 161_1 in that the third etch stop layer 151 can be disposed on the third rework layer 150R. Thereafter, process operations of Figures 8 to 19 are performed.

[0110] When the semiconductor device manufacturing method according to some embodiments of the inventive concept is performed, after the first pattern P1 and the second pattern P2 are formed in the pattern layer 160, the first to third etching stoppers 161_1, 161_2, and 151 are formed. Accordingly, a height difference can not occur in the first cell area CA1, and thus, when the hole pattern 172H is formed at the edge of the first cell area CA1, a pattern defect can be reduced or prevented.

[0111] Further, when the first to third etching stoppers 161_1, 161_2, and 151 are formed, and then the first pattern P1 and the second pattern P2 are formed in the pattern layer 160 without causing a height difference, a process operation such as generating a stepped portion in the carbon-containing layer 130 can be added, and thus, costs can increase.

[0112] Further, because the second pattern P2 can be used as an alignment mark pattern, when the first to third etching stoppers 161_1, 161_2, and 151 are formed after the first pattern P1 and the second pattern P2 are formed, the first to third etching stoppers 161_1, 161_2, and 151 can be formed at a target point without adding a process for an alignment mark pattern.

[0113] However, the effects of the embodiments are not limited to those described herein. The above and other effects of the embodiments will become more apparent by describing in detail the embodiments with reference to the accompanying drawings.

Claims

1. A method of manufacturing a semiconductor device, comprising: providing a substrate defining a main region including a first cell region and a first peripheral region, and an edge region including a second cell region and a second peripheral region, in the substrate; forming, in order, a mold layer, a support layer, a mask layer, and a preliminary pattern layer on the substrate; exposing the preliminary pattern layer to form a first pattern and a second pattern on the mask layer in the first cell region and the second cell region, respectively, simultaneously; forming an etch stop layer covering the second pattern in the second cell region and the second peripheral region; and etching the mask layer using the etch stop layer and the first pattern to form a hole pattern in the mold layer and the support layer in the first cell region. a height between the substrate and a highest point of the first pattern is equal to a height between the substrate and a highest point of the second pattern.

2. The method of claim 1, wherein, the etch stop layer is not formed on the main region.

3. The method of claim 1, wherein, the first pattern and the second pattern are formed using extreme ultraviolet (EUV) light.

4. The method of claim 1, wherein, 5. The method of claim 1, further comprising: forming an anti-reflective coating between the preliminary pattern layer and the mask layer. forming the hole pattern includes:

6. The method of claim 1, wherein, forming a mask pattern on the mask layer using the etch stop layer and the first pattern; and etching the mold layer and the support layer using the mask pattern. the mask pattern includes a first preliminary hole pattern formed in the first cell region, and a second preliminary hole pattern formed in the second cell region, 7. The method of claim 6, wherein, wherein the first preliminary hole pattern extends through the mask pattern, and wherein the second preliminary hole pattern does not extend through the mask pattern.

8. The method of claim 1, further comprising: forming a redo layer on the first pattern and the second pattern before forming the etch stop layer.

9. The method of claim 8, further comprising: forming an anti-reflective coating between the preliminary pattern layer and the mask layer; and etching the anti-reflective coating along sides of the first pattern and the second pattern before forming the redo layer. the mask layer includes a first mask layer and a second mask layer on the first mask layer, and wherein the etch stop layer and the second mask layer include a same material.

10. The method of claim 9, wherein, the mask layer includes a first mask layer and a second mask layer on the first mask layer, the method further comprising:

11. The method of claim 8, wherein, forming an anti-reflective coating between the preliminary pattern layer and the mask layer; and etching the anti-reflective coating along sides of the first pattern and the second pattern before forming the redo layer.

12. A method of manufacturing a semiconductor device, comprising: providing a substrate defining a main region including a first cell region and a first peripheral region, and an edge region including a second cell region and a second peripheral region, in the substrate; forming, in order, a mold layer, a support layer, a mask layer, an anti-reflective coating, and a preliminary pattern layer on the substrate; ​ ​ exposing the preliminary pattern layer to light to form a first pattern and a second pattern on the antireflective coating of the first cell region and the second cell region, respectively; forming an etch stop layer covering the second pattern in the second cell region and the second peripheral region, the etch stop layer not being formed on the main region; and using the etch stop layer and the first pattern to etch the mask layer to form a hole pattern in the mold layer and the support layer of the first cell region.

13. The method of claim 12, wherein, The first pattern and the second pattern are formed simultaneously.

14. The method of claim 12, further comprising: etching the antireflective coating along sides of the first pattern and the second pattern; and forming a redo layer on the first pattern and the second pattern before forming the etch stop layer.

15. The method of claim 12, wherein, Forming the hole pattern includes: forming a first mask pattern on the mask layer using the etch stop layer and the first pattern; and etching the mold layer and the support layer through the first mask pattern in the first cell region.

16. The method of claim 15, wherein, forming a second mask pattern on the mask layer using the etch stop layer and the second pattern in the second cell region, and wherein the second mask pattern does not extend through the mask layer.

17. A method of manufacturing a semiconductor device, comprising: providing a substrate defining a main region including a first cell region and a first peripheral region, and an edge region including a second cell region and a second peripheral region; forming, in order, a mold layer, a support layer, a mask layer, an antireflective coating, and a preliminary pattern layer on the substrate; exposing the preliminary pattern layer to light to form a first pattern and a second pattern on the antireflective coating of the first cell region and the second cell region, respectively; forming an etch stop layer covering the second pattern in the second cell region and the second peripheral region, the etch stop layer not being formed on the main region; using the etch stop layer and the first pattern to form a hole pattern in the first cell region extending through the mold layer, the support layer, and the mask layer, the hole pattern not being formed in the first peripheral region, the second cell region, and the second peripheral region; forming a lower electrode in the hole pattern; exposing an upper surface of the support layer such that an upper end of the support layer on the first cell region, an upper end of the support layer on the first peripheral region, an upper end of the support layer on the second cell region, and an upper end of the support layer on the second peripheral region are at the same level; forming a support mask layer on the support layer; patterning the support mask layer to form a support mask pattern; using the support mask pattern to form a support opening extending through the support layer; removing the mold layer; forming a capacitor dielectric layer on the lower electrode; forming an upper electrode on the capacitor dielectric layer; forming an interlayer insulating layer on the upper electrode; and planarizing the interlayer insulating layer.

18. The method of claim 17, wherein, a height between the substrate and a highest point of the first pattern is equal to a height between the substrate and a highest point of the second pattern.

19. The method of claim 17, wherein, the first pattern and the second pattern are formed using extreme ultraviolet (EUV) light.

20. The method of claim 17, wherein, the mask layer includes a first mask layer, and a second mask layer on the first mask layer, the method further includes: etching the anti-reflective coating and the second mask layer along sides of the first pattern and the second pattern; and forming a rework layer on the first pattern and the second pattern prior to forming the etch stop layer.

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