Semiconductor device and method for manufacturing the same

Abstract

A method for manufacturing a semiconductor device includes: forming a lower array including a plurality of lower electrodes on a semiconductor substrate, a support for supporting the lower electrodes, and a dielectric layer formed on the lower electrodes and the support; forming a gap-fill layer covering side portions and an upper portion of the lower array; forming a covering portion covering the upper portion of the lower array on the gap-fill layer; performing a retraction process on the gap-fill layer to form a gap-fill electrode aligned with the covering portion; and forming a low-resistivity electrode on the gap-fill electrode.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2020-0025900, filed on Mar. 2, 2020, the entire content of which is incorporated herein by reference. Technical Field

[0002] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a capacitor and a method of manufacturing the same. Background Art

[0003] An upper electrode of a capacitor formed in a memory cell region and a contact plug formed in a peripheral circuit region may need to be electrically disconnected from each other. However, as semiconductor devices are miniaturized, the distance between the upper electrode and the contact plug in the peripheral circuit region decreases, which may cause an electrical short circuit between the upper electrode and the contact plug in the peripheral circuit region. Summary of the Invention

[0004] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same that can prevent an electrical short circuit between a contact plug and an upper electrode.

[0005] According to an embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a lower array including: a plurality of lower electrodes on a semiconductor substrate, a support supporting the lower electrodes, and a dielectric layer formed on the lower electrodes and the support; forming a gap-fill layer covering side portions and an upper portion of the lower array; forming a covering portion on the gap-fill layer covering the upper portion of the lower array; performing a retraction process of the gap-fill layer to form a gap-fill electrode aligned with the covering portion; and forming a low-resistivity electrode on the gap-fill electrode.

[0006] According to another embodiment of the present invention, a semiconductor device includes: a peripheral circuit region including a lower interconnect; a contact plug connected to the lower interconnect; and a memory cell region including: a multi-layer support laterally spaced apart from the contact plug, a lower electrode supported by the multi-layer support, and an upper electrode filling a space between the lower electrodes, wherein the upper electrode includes: a liner electrode conformally covering the lower electrode and the support; and a gap-fill electrode including a gap-fill electrode upper portion and a support-side side portion, the gap-fill electrode upper portion being located at a higher level than the lower electrode to cover the multi-layer support and the lower electrode above the liner electrode, the support-side side portion being thinner than the gap-fill electrode upper portion and being close to an edge portion of the multi-layer support.

[0007] These and other features and advantages of the present invention will become apparent to those of ordinary skill in the art to which the present invention pertains from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0009] Figure 1B is Figure 1A an enlarged view of the portion 100A shown in

[0010] Figures 2A to 2P is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0011] Figure 3 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0012] Figures 4A to 4D is a cross-sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[0013] Figure 5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0014] Figure 6A is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0015] Figure 6B is Figure 6A an enlarged view of the portion 400A shown in DETAILED DESCRIPTION

[0016] Various embodiments of the present invention will be described in more detail below with reference to the drawings. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, in the various drawings and embodiments of the present invention, the same reference numerals refer to the same parts.

[0017] The drawings are not necessarily to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When a first layer is referred to as being "on" a second layer or on a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer exists between the first layer and the second layer or the substrate. Further, features described in one embodiment may be used in combination with one or more features described in another embodiment, as long as the combination does not depart from the scope and spirit of the described and claimed present invention.

[0018] Figure 1A is a cross-sectional view showing a semiconductor device 100 according to an embodiment of the present invention. Figure 1B is Figure 1A an enlarged view of the portion 100A shown in

[0019] See Figure 1A and Figure 1B , the semiconductor device 100 may include a memory cell region R1 and a peripheral circuit region R2. A plurality of capacitors may be formed in the memory cell region R1. Each capacitor may include a lower electrode 105, a dielectric layer 106, and an upper electrode 107.

[0020] A plurality of lower electrodes 105 may be arranged in the memory cell region R1. Although Figure 1A four lower electrodes 105 are shown as an example, the present disclosure is not limited thereto. Each lower electrode 105 may be electrically connected to the substrate 101 via a corresponding unit contact plug 103. The unit contact plug 103 may penetrate the lower interlayer dielectric layer 102 above the substrate 101 to be coupled to the substrate 101. An etch stop layer 104 may be formed above the lower interlayer dielectric layer 102, and the bottom of the lower electrode 105 may penetrate the etch stop layer 104 to be coupled to their respective unit contact plugs 103.

[0021] The substrate 101 may be any semiconductor substrate suitable for semiconductor processing. For example, the substrate 101 may include: silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multiple layers. In one embodiment, the substrate 101 may be formed of a semiconductor material containing silicon. In another embodiment, the substrate 101 may include another semiconductor material, such as germanium. In yet another embodiment, the substrate 101 may be formed of a semiconductor material containing silicon and may also include another semiconductor material such as germanium. In yet another embodiment, the substrate 101 may include a III / V group semiconductor substrate, such as a compound semiconductor substrate (e.g., GaAs). In one embodiment, the substrate 101 may include a Silicon-On-Insulator (SOI) substrate.

[0022] The lower interlayer dielectric layer 102 may include, for example, silicon oxide. The lower interlayer dielectric layer 102 may be or include: high density plasma oxide (HDP oxide), TEOS (TetraEthylOrthoSilicate), PE-TEOS (plasma enhanced tetraethyl orthosilicate), O3-TEOS (O3-tetraethyl orthosilicate), USG (undoped silicate glass), PSG (phosphosilicate glass), BSG (borosilicate glass), BPSG (borophosphosilicate glass), FSG (fluorosilicate glass), SOG (spin-on glass), TOSZ (Tonen SilaZene), or a combination thereof. In one embodiment, the lower interlayer dielectric layer 102 may include, for example, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0023] The unit contact plug 103 may include a semiconductor material, a metal material, or a combination thereof. For example, the unit contact plug 103 may include, for example, polysilicon, tungsten, titanium nitride, titanium silicide, or a combination thereof. According to one embodiment of the present invention, the unit contact plug 103 may be formed by laminating polysilicon, titanium silicide, titanium nitride, and tungsten in that order. Although not shown, bit lines may be disposed between adjacent unit contact plugs 103, and buried word lines may be disposed in the substrate 101. The unit contact plug 103 may also be referred to as a storage node contact plug.

[0024] The etch stop layer 104 may have an etch selectivity with respect to the lower interlayer dielectric layer 102. The etch stop layer 104 may include, for example, silicon nitride.

[0025] The plurality of lower electrodes 105 may be supported by one or more supports 111 and 112. The supports 111 and 112 may be multi-layer supports, and this embodiment shows a two-layer support including a lower support 111 and an upper support 112. According to another embodiment of the present invention, the supports 111 and 112 may be multi-level layers having three or more levels (or layers). The upper support 112 may be located at a higher level than the lower support 111. The upper support 112 may support the upper outer wall of the lower electrode 105, and the lower support 111 may mainly support the lower outer wall compared to the upper outer wall of the lower electrode 105. The positions of the upper support 112 and the lower support 111 may be modified in different ways. The lower support 111 and the upper support 112 may include a dielectric material. The lower support 111 and the upper support 112 may include, for example, silicon nitride, silicon carbonitride, or a combination thereof. The lower support 111 and the upper support 112 may be the same material or different materials. The lower support 111 may be thinner than the upper support 112.

[0026] The dielectric layer 106 may be formed to cover the surfaces of the lower electrode 105, the lower support member 111, and the upper support member 112, and the upper electrode 107 may be formed over the dielectric layer 106. The lower electrode 105, the lower support member 111, the upper support member 112, and the dielectric layer 106 may be collectively referred to as the "lower array". The lower array may have a structure including an upper portion and side portions on both sides of the upper portion. The lower array may further include blank spaces between the lower electrodes 105 and blank spaces between the lower support member 111 and the upper support member 112. The blank spaces of the lower array may be filled with portions of the upper electrode 107. The lower array may be formed in the memory cell region R1 and may not be formed in the peripheral circuit region R2. The upper electrode 107 may be located in the memory cell region R1 and cover at least the upper portion and the side portions of the lower array. The lower array may also be referred to as a "covered target structure" covered by the upper electrode 107.

[0027] The upper electrode 107 may include: a liner electrode 108, a gap-fill electrode 109, and a low-resistivity electrode 110. The liner electrode 108 may be conformally formed over the dielectric layer 106, and the gap-fill electrode 109 may fill the space between adjacent lower electrodes 105 over the liner electrode 108, and the low-resistivity electrode 110 may be formed over the gap-fill electrode 109. The gap-fill electrode 109 may be embedded between the liner electrode 108 and the low-resistivity electrode 110.

[0028] The lower electrode 105 may include a conductive material. The lower electrode 105 may include, for example, polysilicon, metal, metal nitride, conductive metal oxide, metal silicide, noble metal, or a combination thereof. The lower electrode 105 may include at least one of the following: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), or tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and combinations thereof. According to another embodiment of the present invention, the lower electrode 105 may include titanium nitride (TiN). The lower electrode 105 may include titanium nitride formed by an atomic layer deposition (ALD) process (ALD-TiN). According to another embodiment of the present invention, the lower electrode 105 may include a stacked structure of titanium nitride and tungsten. According to another embodiment of the present invention, the lower electrode 105 may include a stacked structure of titanium nitride and polysilicon.

[0029] The dielectric layer 106 may include, for example, silicon oxide or silicon nitride. The dielectric layer 106 may include a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include: hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), niobium pentoxide (Nb2O5), or strontium titanate (SrTiO3). According to another embodiment of the present invention, the dielectric layer 106 may be formed as a composite layer including two or more layers of the above high-k materials. In this embodiment of the present invention, the dielectric layer 106 may be formed of a zirconia-based material having good leakage current characteristics while sufficiently reducing the thickness of the equivalent oxide film (EOT). For example, it may include ZAZ (ZrO2 / Al2O3 / ZrO2). According to another embodiment of the present invention, the dielectric layer 106 may include: TiO2 / ZrO2 / Al2O3 / ZrO2, TiO2 / HfO2 / Al2O3 / HfO2, Ta2O5 / ZrO2 / Al2O3 / ZrO2, or Ta2O5 / HfO2 / Al2O3 / HfO2.

[0030] The liner electrode 108 may include a metal-containing material. The liner electrode 108 may include a metal, a metal nitride, or a combination thereof. According to an embodiment of the present invention, the liner electrode 108 may be formed of a metal nitride such as titanium nitride.

[0031] The gap-fill electrode 109 may include a semiconductor material. The gap-fill electrode 109 may have good step coverage, filling the space between adjacent lower electrodes 105 without voids. The gap-fill electrode 109 may include silicon, silicon germanium, silicon carbide, silicon carbide germanium, or a combination thereof. According to an embodiment of the present invention, the gap-fill electrode 109 may be formed of, for example, silicon germanium.

[0032] The low-resistivity electrode 110 may include a metal-containing material. The low-resistivity electrode 110 may include: a metal, a metal nitride, a metal silicide, or a combination thereof. The low-resistance electrode 110 may include: tungsten, tungsten nitride, tungsten silicide, or a combination thereof. According to an embodiment of the present invention, the low-resistivity electrode 110 may be formed of tungsten nitride.

[0033] As an example of the upper electrode 107, the stack of the liner electrode 108 / gap-fill electrode 109 / low-resistivity electrode 110 may include a stack of titanium nitride / silicon germanium / tungsten nitride.

[0034] The peripheral circuit region R2 may include a lower-level interconnect PM. The lower-level interconnect PM may be located on the lower-level interlayer dielectric layer 102 of the peripheral circuit region R2. The lower-level interconnect PM may include a metallic material. Although not shown, the lower-level interconnect PM may be coupled to the peripheral circuit transistors of the peripheral circuit region R2. The peripheral circuit transistors may include at least one control circuit for controlling the memory cells.

[0035] The upper-level interlayer dielectric layer 113 may be formed over the upper electrode 107 and the lower-level interconnect PM. The upper-level interlayer dielectric layer 113 may remove a step between the memory cell region R1 and the peripheral circuit region R2. The first contact plug 114 may be formed to penetrate the upper-level interlayer dielectric layer 113 of the memory cell region R1, and the first contact plug 114 may be coupled to the low-resistivity electrode 110 of the upper electrode 107. The second contact plug 115 may be formed to penetrate the upper-level interlayer dielectric layer 113 of the peripheral circuit region R2, and the second contact plug 115 may be coupled to the lower-level interconnect PM. The first contact plug 114 and the second contact plug 115 may be respectively coupled to the upper-level interconnect 116.

[0036] The upper electrode 107 may include an upper electrode edge portion 107E, and the upper electrode edge portion 107E may be located in the edge portion R1E of the memory cell region R1. The upper electrode edge portion 107E may be provided by the low-resistivity electrode side portion 110S. The low-resistivity electrode side portion 110S may not be located in the peripheral circuit region R2. The low-resistivity electrode side portion 110S may be located in the edge portion R1E of the memory cell region R1. The upper electrode edge portion 107E may include an upper electrode edge bottom 107LE.

[0037] The gap-fill electrode 109 may fill the space between the lower electrodes 105 over the liner electrode 108. The gap-fill electrode 109 may include a gap-fill electrode upper portion 109T and a gap-fill electrode side portion 109S. The gap-fill electrode side portion 109S may extend vertically from the gap-fill electrode upper portion 109T. The gap-fill electrode upper portion 109T may be located at a higher level than the lower electrode 105, and the gap-fill electrode side portion 109S may have a shape that is recessed by a retraction process to be laterally spaced apart from the second contact plug 115. The gap-fill electrode side portion 109S may cover the side portions of the lower array. The gap-fill electrode upper portion 109T may cover the upper portion of the lower array.

[0038] The gap-fill electrode side portion 109S may be located in the edge portions R1E on both sides of the memory cell region R1. See Figure 1B, the side portion 109S of the gap filling electrode may include a plurality of side portions S1, S2, S3, and S4 of the gap filling electrode. The side portions S1, S2, S3, and S4 of the gap filling electrode may include: a first side portion S1 of the gap filling electrode, a second side portion S2 of the gap filling electrode, a third side portion S3 of the gap filling electrode, and a fourth side portion S4 of the gap filling electrode. The first side portion S1 of the gap filling electrode may cover the edge portion of the upper support member 112, and the third side portion S3 of the gap filling electrode may cover the edge portion of the lower support member 112. The second side portion S2 of the gap filling electrode may be located between the first side portion S1 and the third side portion S3 of the gap filling electrode and may be close to the side surface of the outermost lower electrode 105 of the memory cell region R1. The fourth side portion S4 of the gap filling electrode may be located between the third side portion S3 of the gap filling electrode and the etch stop layer 104 and may be close to the side surface of the outermost lower electrode 105 of the memory cell region R1. The second side portion S2 and the fourth side portion S4 of the gap filling electrode may extend from the first side portion S1 and the third side portion S3 of the gap filling electrode, respectively. The fourth side portion S4 of the gap filling electrode may be located at a level lower than that of the lower support member 111. The first side portion S1 and the third side portion S3 of the gap filling electrode may be referred to as the side edge portions of the support member, and the second side portion S2 and the fourth side portion S4 of the gap filling electrode may be referred to as the side edge portions of the lower electrode.

[0039] The thickness D2 of the first side portion S1 and the second side portion S3 of the gap filling electrode may be thinner than the thickness D1 of the upper portion 109T of the gap filling electrode. The second side portion S2 and the fourth side portion S4 of the gap filling electrode may be thicker than the first side portion S1 and the third side portion S3 of the gap filling electrode. The second side portion S2 and the fourth side portion S4 of the gap filling electrode may be thinner than the upper portion 109T of the gap filling electrode. According to another embodiment of the present invention, the second side portion S2 and the fourth side portion S4 of the gap filling electrode may have the same thickness as or be thicker than the upper portion 109T of the gap filling electrode. The side portion 109S of the gap filling electrode may have a vertical profile.

[0040] The gap-fill electrode 109 may further include a lateral edge portion 109E extending from a side portion 109S of the gap-fill electrode to cover a bottom edge of the lower array. The lateral edge portion 109E may extend laterally from a fourth side portion S4 of the gap-fill electrode. A distance L1 between the lateral edge portion 109E and the second contact plug 115 may be shorter than a distance L2 between a first side portion to a fourth side portion S1, S2, S3, S4 of the gap-fill electrode and the second contact plug 115. A bottom portion 107LE of an upper electrode edge may be provided by the lateral edge portion 109E of the gap-fill electrode 109. A distance between an upper electrode edge portion 107E and the second contact plug 115 may be the same as the distance L1 between the lateral edge portion 109E of the gap-fill electrode 109 and the second contact plug 115. A distance between the bottom portion 107LE of the upper electrode edge and the second contact plug 115 may be the same as the distance L1 between the lateral edge portion 109E of the gap-fill electrode 109 and the second contact plug 115. An edge portion of the dielectric layer 106 may be located below the upper electrode edge portion 107LE.

[0041] The low-resistivity electrode 110 may include a low-resistivity electrode upper portion 110T covering an upper portion 109T of the gap-fill electrode and a low-resistivity electrode side portion 110S covering a side portion 109S of the gap-fill electrode.

[0042] The lateral edge portion 109E of the gap-fill electrode 109 and the low-resistivity electrode side portion 110S may be self-aligned. In other words, a bottom of the low-resistivity electrode side portion 110S may not cover a side surface of the lateral edge portion 109E of the gap-fill electrode 109.

[0043] The low-resistivity electrode 110 may completely cover the upper portion 109T of the gap-fill electrode and the side portion 109S of the gap-fill electrode, and an end portion of the lateral edge portion 109E of the gap-fill electrode 109 may not be covered by the low-resistivity electrode side portion 110S. A thickness of the low-resistivity electrode 110 may be uniform over the upper portion 109T of the gap-fill electrode and the side portion 109S of the gap-fill electrode. The low-resistivity electrode 110 may not fill a space between the lower electrodes 105. For example, the liner electrode 108 and the gap-fill electrode 109 may be located on the dielectric layer 106 between adjacent lower electrodes 105.

[0044] As described above, the gap-fill electrode 109 may cover the side and upper portions of the memory cell region R1 and fill the space between the lower electrodes 105, and the low-resistivity electrode 110 may cover the side and upper portions of the memory cell region R1 without filling the space between the lower electrodes 105. The upper electrode edge portion 107LE (i.e., the lateral edge portion 109E of the gap-fill electrode 109), the edge portion of the liner electrode 108, and the edge portion of the dielectric layer 106 may be located between the lower portion of the low-resistivity electrode side portion 110S and the etch stop layer 104.

[0045] Figures 2A to 2P is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0046] Refer to Figure 2A , a lower interlayer dielectric layer 12 may be formed on the semiconductor substrate 11 that defines the memory cell region R1 and the peripheral circuit region R2. A plurality of cell contact plugs 13 penetrating the lower interlayer dielectric layer 12 may be formed. The cell contact plugs 13 may penetrate the interlayer dielectric layer 12 to be coupled to the semiconductor substrate 11. The cell contact plugs 13 may include: a silicon plug, a metal plug, or a combination thereof. Although not shown, buried word lines may be formed in the semiconductor substrate 11. Before forming the cell contact plugs 13, a plurality of bit lines (not shown) may be further formed on the semiconductor substrate 11. The cell contact plugs 13 may be respectively coupled to respective impurity regions (not shown) formed in the semiconductor substrate 11. Although not shown in Figure 2A , the memory cell region R1 may further include an edge portion (refer to Figure 1A "R1E" in

[0047] The semiconductor substrate 11 may be any material suitable for semiconductor processing. The semiconductor substrate 11 may be formed of a silicon-containing material. The semiconductor substrate 11 may include: silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or multiple layers. The semiconductor substrate 11 may include another semiconductor material such as germanium. The semiconductor substrate 11 may include a III / V group semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The semiconductor substrate 11 may include a silicon-on-insulator (SOI) substrate.

[0048] The lower interlayer dielectric layer 12 may include, for example, silicon oxide. The lower interlayer dielectric layer 12 may include: high density plasma oxide (HDP oxide), TEOS (tetraethyl orthosilicate), PE-TEOS (plasma enhanced tetraethyl orthosilicate), O3-TEOS (O3-tetraethyl orthosilicate), USG (undoped silicate glass), PSG (phosphosilicate glass), BSG (borosilicate glass), BPSG (borophosphosilicate glass), FSG (fluorosilicate glass), SOG (spin-on glass), TOSZ (Tonen SilaZene), or a combination thereof. Additionally, the lower interlayer dielectric layer 12 may be formed of, for example, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0049] The cell contact plug 13 may be formed in the memory cell region R1. The lower layer interconnect PM may be formed in the peripheral circuit region R2. The lower layer interconnect PM may include a metal material. The lower layer interconnect PM may be formed later than the cell contact plug 13. According to another embodiment of the present invention, a contact pad (not shown) may be further formed on the cell contact plug 13, and the contact pad and the lower layer interconnect PM may be formed simultaneously.

[0050] A molded structure may be formed on the cell contact plug 13, the lower layer interconnect PM, and the lower interlayer dielectric layer 12. The molded structure may include a stack of an etch stop layer 14, a first molding layer 15, a first support layer 16, a second molding layer 17, and a second support layer 18. The molded structure may be formed over the memory cell region R1 and the peripheral circuit region R2.

[0051] The etch stop layer 14 may be formed of a material having an etch selectivity with respect to the lower interlayer dielectric layer 12 and the first molding layer 15. The etch stop layer 14 may include, for example, silicon nitride or silicon oxynitride.

[0052] The first molding layer 15 may include a dielectric material. The first molding layer 15 may be silicon oxide (SiO2). The first molding layer 15 may be formed to be thicker than the first support layer 16. The first molding layer 15 may be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The first molding layer 15 may include impurity-doped silicon oxide doped with phosphorus or boron. The first molding layer 15 may include: USG, PSG, BSG, BPSG, FSG, or a combination thereof. The impurity-doped silicon oxide is easily removed in subsequent processes due to its high etch rate with respect to the etch solution.

[0053] The first support layer 16 may be formed of a material having an etch selectivity with respect to the first molding layer 15 and the second molding layer 17. The first support layer 16 may include, for example, silicon nitride or silicon carbonitride (SiCN).

[0054] The second molding layer 17 may include a dielectric material. For example, the second molding layer 17 may be silicon oxide (SiO2). The second molding layer 17 may be formed to be thicker than the first support layer 16. The second molding layer 17 may be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The second molding layer 17 may include impurity-doped silicon oxide doped with phosphorus or boron. The second molding layer 17 may include: USG, PSG, BSG, BPSG, FSG, or a combination thereof. The impurity-doped silicon oxide is easily removed in subsequent processes due to its fast etching rate relative to the etching solution. The first molding layer 15 and the second molding layer 17 may be made of the same material or different materials.

[0055] According to another embodiment of the present invention, the first molding layer 15 and the second molding layer 17 may be silicon materials, such as amorphous silicon or polycrystalline silicon.

[0056] The second support layer 18 may be formed of a material having an etching selectivity with respect to the second molding layer 17. The second support layer 18 may include, for example, silicon nitride or silicon carbonitride (SiCN).

[0057] The first support layer 16 and the second support layer 18 may be made of the same material or different materials. The first support layer 16 and the second support layer 18 may be formed of, for example, silicon nitride. According to another embodiment of the present invention, the first support layer 16 may be formed of, for example, silicon nitride, and the second support layer 18 may be formed of, for example, silicon carbonitride. The second support layer 18 may be thicker than the first support layer 16. In one embodiment, the second support layer 18 and the first support layer 16 may be thinner than the second molding layer 17, respectively.

[0058] According to another embodiment of the present invention, another support layer may be further formed. For example, the support structure may be a multi-layer support layer structure.

[0059] See Figure 2B, a plurality of openings 19 can be formed. In one embodiment, each opening 19 can be formed by using a mask layer (not shown) and etching the molding structure. To form the opening 19, the second support layer 18, the second molding layer 17, the first support layer 16, and the first molding layer 15 can be sequentially etched by using the mask layer as an etching stop layer. The etching process for forming the opening 19 can stop at the etching stop layer 14. The opening 19 can be formed by a dry etching process, a wet etching process, or a combination thereof. The opening 19 can be referred to as a hole in which respective lower electrodes (or storage nodes) will be formed. Each opening 19 can have a high aspect ratio. For example, each opening 19 can have an aspect ratio of at least 1:1 or higher. For example, the opening 19 can have an aspect ratio of 10:1 or higher. As used herein, the aspect ratio can refer to the ratio of the height H to the width W.

[0060] Subsequently, the etching stop layer 14 can be etched to expose the upper surface of the cell contact plug 13 under the opening 19.

[0061] The mask layer for forming the opening 19 can include a hard mask material, a photoresist, or a combination thereof. The hard mask material can include amorphous silicon, an oxide, amorphous carbon, silicon oxynitride, or a combination thereof. In one embodiment, the photoresist can include an argon fluoride (ArF) photoresist or an extreme ultraviolet (EUV) photoresist.

[0062] The opening 19 can be formed by a double patterning process. For example, the mask layer for forming the opening 19 can have a mesh pattern formed by combining the results of two spacer patterning processes.

[0063] In one embodiment, a molding structure pattern including a plurality of openings 19 can be formed by the above-described series of etching processes. The molding structure pattern can be a stack of the etching stop layer 14, the first molding layer 15, the first support layer 16, the second molding layer 17, and the second support layer 18.

[0064] The opening 19 can be formed in the memory cell region R1, and the openings 19 can be arranged at a high density. For example, the diameter of each opening 19 can be about 20 to 150 nm, and the gap between adjacent openings 19 can be about 20 to 50 nm.

[0065] See Figure 2C, the lower electrode 20 can be formed in each opening 19. The lower electrode 20 can fill the interior of the opening 19. The lower electrode 20 can be columnar. To form the columnar lower electrode 20, a conductive material can be deposited to fill the opening 19 by gap filling, and then a planarization process can be performed. The lower electrode 20 can include, for example, polysilicon, metal, metal nitride, conductive metal oxide, metal silicide, noble metal, or a combination thereof. The lower electrode 20 can include at least one of the following: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), or tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and combinations thereof. In this embodiment of the present invention, the lower electrode 20 can include titanium nitride (TiN). The lower electrode 20 can include titanium nitride formed by atomic layer deposition (ALD-TiN). The lower electrode 20 can include cylindrical titanium nitride and polysilicon filling the interior of the cylindrical titanium nitride.

[0066] According to another embodiment of the present invention, the lower electrode 20 can include a stacked structure of titanium nitride and tungsten.

[0067] See Figure 2D , a support mask layer 21 can be formed. The support mask layer 21 can include, for example, photoresist or amorphous carbon. The support mask layer 21 can be patterned to be located in the memory cell region R1. The support mask layer 21 can not be located in the peripheral circuit region R2.

[0068] Subsequently, a part of the second support layer 18 can be etched by using the support mask layer 21. The upper support opening 21S and the upper support 18S can be formed by etching the second support layer 18.

[0069] The upper support 18S can have a planar shape. The upper support 18S can contact the upper sidewall of the lower electrode 20. Some surfaces of the second molding layer 17 can be exposed by the upper support 18S. The upper support 18S can be shaped to partially surround the upper sidewall of the lower electrode 20. As described above, the upper support 18S can prevent the lower electrode 20 from collapsing in the subsequent process of removing the second molding layer 17.

[0070] In another embodiment, from a top-down perspective, the upper support opening 21S can be shaped to partially expose the upper sidewalls of three adjacent lower electrodes 20. According to still another embodiment of the present invention, the upper support opening 21S can be shaped to partially expose the upper sidewalls of at least four lower electrodes 20. The cross-section of the upper support opening 21S can have a triangular, square, parallelogram, pentagonal, hexagonal, or honeycomb shape.

[0071] In yet another embodiment, the upper sidewalls of all the lower electrodes 20 may be partially exposed by the upper layer support openings 21S. This may be referred to as a full-open lower electrode array.

[0072] According to yet another embodiment of the present invention, the upper sidewalls of at least one of the lower electrodes 20 may not be exposed by the upper layer support openings 21S. For example, among the lower electrodes 20, there may be at least one lower electrode 20 that is not exposed by the upper layer support member opening 21S but is completely covered by the upper layer support member 18S. This may be referred to as a 1-span lower electrode array.

[0073] See Figure 2E , the second molding layer 17 under the upper layer support opening 21S may be selectively removed. As a result, the surface of the first support layer 16 may be exposed. The first wet leaching process 22 may be performed to remove the second molding layer 17. The first wet leaching process 22 may be performed using an etching solution capable of selectively removing the second molding layer 17. For example, when the second molding layer 17 includes silicon oxide, the second molding layer 17 may be removed by wet etching using hydrofluoric acid (HF).

[0074] See Figure 2F , a part of the first support layer 16 may be etched by using the support mask layer 21. For example, the first support layer 16 may be etched by a self-aligned etching process using the support mask layer 21 and the upper layer support member 18S. The lower layer support opening 23 and the lower layer support member 16S may be formed by etching the first support layer 16.

[0075] The lower layer support member 16S may contact a partial sidewall of the lower electrode 20. Some surfaces of the first molding layer 15 may be exposed by the lower layer support member 16S. The lower layer support member 16S may have a shape that partially surrounds the sidewall of the lower electrode 20 at a level lower than that of the upper layer support member 16S. In this way, the lower layer support member 16S may prevent the lower electrode 20 from collapsing in a subsequent process of removing the first molding layer 15.

[0076] See Figure 2G , the first molding layer 15 under the lower layer support opening 23 may be selectively removed. The second wet leaching 22' may be performed to remove the first molding layer 15. The second wet leaching 22' may be performed using an etching solution capable of selectively removing the first molding layer 15. For example, when the first molding layer 15 includes silicon oxide, the first molding layer 15 may be removed by a wet etching process using hydrofluoric acid (HF). After removing the first molding layer 15, the support mask layer 21 may be peeled off.

[0077] Through the above series of processes, a lower support member 16S and an upper support member 18S of the wall supporting the lower electrode 20 can be formed. The lower support member 16S and the upper support member 18S can be formed in the memory cell region R1. The lower support member 16S and the upper support member 18S can protrude by extending further horizontally from the edge of the memory cell region R1 than the lower electrode 20. Except for the portions in contact with the lower support member 16S and the upper support member 18S, the outer wall surface of the lower electrode 20 can be exposed.

[0078] Refer to Figure 2H , a dielectric layer 24 can be formed over the lower electrode 20. The dielectric layer 24 can include a high-k material having a higher dielectric constant than silicon oxide. The high-k material can include: hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), niobium pentoxide (Nb2O5), or strontium titanate (SrTiO3). According to another embodiment of the present invention, the dielectric layer 24 can be formed of a composite layer including two or more layers of the above high-k materials. In this embodiment of the present invention, the dielectric layer 24 can be formed of a zirconia-based material having good leakage current characteristics while sufficiently reducing the equivalent oxide thickness (EOT). For example, it can include ZAZ (ZrO2 / Al2O3 / ZrO2). According to another embodiment of the present invention, the dielectric layer 106 can include: TiO2 / ZrO2 / Al2O3 / ZrO2, TiO2 / HfO2 / Al2O3 / HfO2, Ta2O5 / ZrO2 / Al2O3 / ZrO2, or Ta2O5 / HfO2 / Al2O3 / HfO2.

[0079] The lower electrode 20, the lower support member 16S, the upper support member 18S, and the dielectric layer 24 formed through the above series of processes can be collectively referred to as the "lower array". The lower array can have a structure including an upper portion and side portions on both sides of the upper portion. The lower array can also include blank spaces between the lower electrodes 20 and blank spaces between the lower support member 16S and the upper support member 18S. The blank spaces in the lower array can be filled with portions of a subsequent upper electrode TE. The lower array can be formed in the memory cell region R1 and can not be formed in the peripheral circuit region R2. The lower array can also be referred to as a "coverage target structure" covered by a subsequent upper electrode TE.

[0080] Hereinafter, a method for forming an upper electrode TE for covering the lower array will be described with reference to Figures 2I to 2P the description.

[0081] Refer to Figure 2I, an inner liner layer 25 that forms part of the upper electrode can be formed over the dielectric layer 24. The inner liner layer 25 can include a metal-based material. The inner liner layer 25 can include a metal nitride. The inner liner layer 25 can include titanium nitride. The inner liner layer 25 can be referred to as a titanium nitride inner liner.

[0082] A gap filling layer 26A that forms part of the upper electrode can be formed over the inner liner layer 25. The gap filling layer 26A can fill the space between the lower electrodes 20 over the inner liner layer 25. The gap filling layer 26A and the inner liner layer 25 can be different materials. The gap filling layer 26A can include a carbon-containing conductive material. The gap filling layer 26A can include a material containing carbon and silicon. The gap filling layer 26A can be silicon carbide. According to another embodiment of the present invention, the gap filling layer 26A can include a seam (not shown) located between the lower electrodes 20.

[0083] The gap filling layer 26A can include an upper portion 26AT and a side portion 26AS. The upper portion 26AT of the gap filling layer 26A can refer to the portion vertically positioned from the upper surface of the lower electrode 20, and the side portion 26AS of the gap filling layer 26A can refer to the portion laterally positioned from the outermost lower electrode 20. The gap filling layer 26A can cover the dielectric layer 24 and the lower electrodes 20 over the inner liner layer 25. The side portion 26AS of the gap filling layer 26A can be located at the edge portion of the memory cell region R1 and can include a side protrusion 26P. The side protrusion 26P can have different shapes according to the shapes of the lower layer support 16S and the upper layer support 18S. The side portion 26AS of the gap filling layer 26A can extend from the edge portion of the memory cell region R1 to cover the edge of the peripheral circuit region R2. The gap filling layer 26A can further include an edge portion 26AL, and the edge portion 26AL of the gap filling layer 26A can extend to cover the peripheral circuit region R2 and the edge portion of the memory cell region R1.

[0084] See Figure 2J , a covering layer 27A can be formed over the gap filling layer 26A. The covering layer 27A can include a material having an etching selectivity with respect to the gap filling layer 26. The covering layer 27A can include, for example, an oxide, a nitride, amorphous carbon, or a combination thereof. The covering layer 27A can be conformally formed according to the shape of the gap filling layer 26. The covering layer 27A can cover both the memory cell region R1 and the peripheral circuit region R2. The covering layer 27A can cover the side protrusion 26P of the gap filling layer 26A.

[0085] See Figure 2K, a mask layer 27M can be formed over the cover layer 27A. The mask layer 27M can be shaped to only cover the upper part of the memory cell region R1. The mask layer 27M can include a photoresist pattern, amorphous carbon, an oxide, or a nitride. The mask layer 27M can be a material that has an etching selectivity with respect to the cover layer 27A and the gap fill layer 26A.

[0086] A portion of the cover layer 27A can be exposed at the edge portion of the memory cell region R1 through the mask layer 27M. For example, the side portion of the cover layer 27A can be exposed by the mask layer 27M.

[0087] The mask layer 27M can not be formed in the peripheral circuit region R2. The edge portion of the mask layer 27M can be located in the memory cell region R1 and can not extend into the peripheral circuit region R2. The edge portion of the mask layer 27M can be defined such that the cover layer 27A remains in the memory cell region R1 after a subsequent etching process. The edge portion of the mask layer 27M can have a size that exposes the edge portion of the memory cell region R1.

[0088] Subsequently, a retraction process of the cover layer 27A can be performed. For example, the side portion of the cover layer 27A can be etched by using the mask layer 27M. As a result, a covering portion 27 can be formed. The position of the edge portion of the covering portion 27 can retreat toward the memory cell region R1 to be closer to the memory cell region R1 than the position of the edge portion of the cover layer 27A.

[0089] The covering portion 27 can be shaped to only cover the upper part of the memory cell region Rl. The edge portion of the covering portion 27 can be located inside the memory cell region R1 and can not extend into the peripheral circuit region R2. The edge portion of the covering portion 27 can be defined such that the gap fill layer 26A remains in the memory cell region R1 after a subsequent etching process.

[0090] A portion of the gap fill layer 26A can be exposed at the edge portion of the memory cell region R1 through the covering portion 27. For example, the side protrusion 26P and the side portion 26AS of the gap fill layer 26A can be exposed by the covering portion 27.

[0091] See Figure 2L , the mask layer 27M can be removed.

[0092] Subsequently, a retraction process of the gap-fill layer 26A can be performed. The retraction process of the gap-fill layer 26A can be performed by a dry etching process. According to another embodiment of the present invention, the retraction process of the gap-fill layer 26A can be performed by a wet etching process (e.g., a leaching process). The side portions 26AS and the side protrusions 26P of the gap-fill layer 26A can be dry-etched by using the covering portion 27 as an etching stopper layer. The side protrusions 26P of the gap-fill layer 26A can be cut by etching the side portions of the gap-fill layer 26A. As a result, the gap-fill electrode 26 can be formed. The position of the side portion 26S of the gap-fill electrode 26 can be laterally retracted toward the memory cell region R1 to be closer to the memory cell region R1 than the position of the side portion 26AS of the gap-fill layer 26A. According to another embodiment of the present invention, a retraction process of the gap-fill layer 26A can be performed, and the mask layer 27M can be retained, and in this case, the mask layer 27M can be removed after the retraction process of the gap-fill layer 26A.

[0093] The gap-fill electrode 26 can include a gap-fill electrode upper portion 26T and a gap-fill electrode side portion 26S. The gap-fill electrode upper portion 26T can maintain the same thickness as the upper portion 26AT of the gap-fill layer 26A. The gap-fill electrode side portion 26S can have a thinner thickness than the side portion 26AS of the gap-fill layer 26A. The gap-fill electrode 26 can further include a gap-fill electrode edge bottom portion 26L, and the gap-fill electrode edge bottom portion 26L can have a thinner thickness than the edge portion 26AL of the gap-fill layer 26A.

[0094] Referring to Figure 2M , the covering portion 27 can be removed. After removing the covering portion 27, the gap-fill electrode upper portion 26T can be exposed. The gap-fill electrode side portion 26S can include a first side portion S1 and a second side portion S2. The gap-fill electrode side portion 26S can further include a third side portion S3 and a fourth side portion S4. The first side portion S1 of the gap-fill electrode side portion 26S can be laterally positioned in the upper layer support 18S, and the third side portion S3 can be laterally positioned in the lower layer support 16S. The second side portion S2 of the gap-fill electrode side portion 26S can be a part that fills the space between the upper layer support 18S and the lower layer support 16S above the liner electrode 25. The fourth side portion S4 of the gap-fill electrode side portion 26S can be a part that fills the space between the lower layer support 16S and the etch stop layer 14 above the liner electrode 25.

[0095] The gap-fill electrode side portion 26S can have a vertical profile 26V. The gap-fill electrode side portion 26S can be located at the edge portion of the memory cell region R1 and not at the edge portion of the peripheral circuit region R2.

[0096] The gap-fill electrode 26 may have a non-conformal shape. For example, the upper portion 26T of the gap-fill electrode may have a first thickness D1. The first side portion S1 of the side portion 26S of the gap-fill electrode may have a second thickness D2. The first thickness D1 may be thicker than the second thickness D2. The bottom portion 26L of the edge of the gap-fill electrode may have a third thickness D3, and the third thickness D3 may be thinner than the first thickness D1. The upper portion 26T of the gap-fill electrode may have a relatively large thickness required to prevent deterioration of cell characteristics. Thus, according to this embodiment of the present invention, the thickness of the side portion 26S of the gap-fill electrode can be selectively reduced without losing the first thickness D1 of the upper portion 26T of the gap-fill electrode. As a comparative example, when the thickness of the side portion 26S of the gap-fill electrode is relatively thick, the size of the memory cell region R1 may increase, which results in a reduction of the net die.

[0097] According to an embodiment of the present invention, since the gap-fill layer 26A retreats through a retraction process to form the gap-fill electrode 26, the edge portion of the upper electrode can be reduced. The size of the memory cell region R1 can be reduced by reducing the thickness of the side portion 26S of the gap-fill electrode. This may increase the net die, thereby improving productivity.

[0098] See Figure 2N , a low-resistivity electrode 28 may be formed over the gap-fill electrode 26. The low-resistivity electrode 28 may include a metal, a metal nitride, a conductive metal nitride, or a combination thereof. The low-resistivity electrode 28 may include: titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium, iridium, ruthenium oxide, iridium oxide, or a combination thereof. According to an embodiment of the present invention, the low-resistivity electrode 28 may be formed of tungsten nitride (WN).

[0099] As described above, the liner electrode 25, the gap-fill electrode 26, and the low-resistivity electrode 28 may be the upper electrodes of the capacitor.

[0100] The low-resistivity electrode 28 may cover the memory cell region R1 and the peripheral circuit region R2. The low-resistivity electrode 28 may not fill the space between adjacent lower electrodes 20.

[0101] See Figure 2O , an upper electrode patterning process may be performed. In the upper electrode patterning process, the low-resistivity electrode 28, the gap-fill electrode 26, and the liner electrode 25 may be sequentially etched by using the upper electrode mask layer 29. The upper electrode mask layer 29 may include a photoresist pattern. The upper electrode mask layer 29 may be a mask for isolating the upper electrode based on the memory blocks in the memory cell region R1.

[0102] The upper electrode TE can be defined by an upper electrode patterning process. The upper electrode TE can include a stack of a liner electrode 25, a gap-fill electrode 26, and a low-resistivity electrode 28. The upper electrode TE can include a bottom of the upper electrode edge 26LE, and the bottom of the upper electrode edge 26LE may not be located in the peripheral circuit region R2. The bottom of the upper electrode edge 26LE can include a bottom of the liner electrode edge 25E, a bottom of the gap-fill electrode edge 26E, and a bottom of the low-resistivity electrode edge 28E. The bottom of the gap-fill electrode edge 26E and the bottom of the liner electrode edge 25E can be self-aligned perpendicular to the bottom of the low-resistivity electrode edge 28E.

[0103] After the upper electrode patterning process, the dielectric layer 24 can be removed from the peripheral circuit region R2. This can be referred to as dielectric layer cutting.

[0104] See Figure 2P , an upper-level interlayer dielectric layer 30 can be formed over the upper electrode TE. For example, the upper-level interlayer dielectric layer 30 can include, for example, silicon oxide. The upper-level interlayer dielectric layer 30 can remove the step formed between the memory cell region R1 and the peripheral circuit region R2. To remove this step, the upper surface of the upper-level interlayer dielectric layer 30 can be planarized.

[0105] Subsequently, a first contact plug 31 and a second contact plug 32 that penetrate the upper-level interlayer dielectric layer 30 can be formed. The first contact plug 31 can be coupled to the low-resistivity electrode 28 of the upper electrode TE, and the second contact plug 32 can be coupled to the lower-level interconnect PM.

[0106] The upper-level interconnect 33 can be formed on the respective upper surfaces of the first contact plug and the second contact plug to be coupled to the first contact plug 31 and the second contact plug 32, respectively.

[0107] See Figures 2A to 2P, a method for manufacturing a semiconductor device may include: forming a lower array including a plurality of lower electrodes 20, a lower layer support 16S / upper layer support 18S, and a dielectric layer 24, where the lower layer support 16S and upper layer support 18S support the lower electrodes 20, and the dielectric layer 24 is formed on the lower electrodes 20 and the lower layer support 16S / upper layer support 18S above the memory cell region R1 of a semiconductor substrate 11 defining a memory cell region R1 and a peripheral circuit region R2; forming a liner layer 25 and a gap-fill layer 26A covering the sides and the top of the lower array; forming a cover portion 27 covering the top of the lower array on the gap-fill layer 26A; performing a retraction process on the gap-fill layer 26A to form a gap-fill electrode 26 aligned with the cover portion 27; forming a low-resistivity electrode 28 on the gap-fill electrode 26; and forming a second contact plug 32 physically spaced apart from an upper electrode TE on the peripheral circuit region R2 spaced apart from the lower array. The gap-fill electrode 26 may further include thin support-side side portions S1 and S3 near the edges of the lower layer support 16S / upper layer support 18S, and lower electrode-side side portions S2 and S4 extending from the support-side side portions S1 and S3. The lower electrode-side side portions S2 and S4 may be thicker than the support-side side portions S1 and S3.

[0108] According to the above embodiment of the present invention, since the gap-fill electrode 26 is formed by a retraction process, the distance L between the side portion (or edge portion) of the upper electrode TE and the second contact plug 32 in the peripheral circuit region R2 can be sufficiently spaced apart.

[0109] As a result, according to the embodiment of the present invention, since the second contact plug 32 and the upper electrode TE are sufficiently insulated, an electrical short circuit between the second contact plug 32 and the upper electrode TE can be prevented. In addition, miniaturization of the semiconductor device can be improved by reducing the size of the memory cell region R1.

[0110] Figure 3 is a cross-sectional view showing a semiconductor device 200 according to another embodiment of the present invention. Figure 3 The semiconductor device 200 may be similar to Figure 1A the semiconductor device 100. Hereinafter, detailed descriptions of overlapping constituent elements will be omitted.

[0111] See Figure 3 , the semiconductor device 200 may include a memory cell region R1 and a peripheral circuit region R2. A plurality of memory cells may be formed to be spaced apart at a predetermined interval in the memory cell region R1.

[0112] A plurality of lower electrodes 105 may be disposed in the memory cell region R1. Each lower electrode 105 may be electrically connected to the substrate 101 via a respective one of the plurality of cell contact plugs 103. The cell contact plugs 103 may penetrate through the lower interlayer dielectric layer 102 formed over the substrate 101 to couple to the substrate 101. An etch stop layer 104 may be formed over the lower interlayer dielectric layer 102, and the bottom of the lower electrode 105 may penetrate through the etch stop layer 104 to couple to their respective cell contact plugs 103.

[0113] The lower electrode 105 may be supported by at least one support member (e.g., support member 111 or 112). The support members 111 and 112 may form a multi-layer structure, where the support member 111 is the lower support member and the support member 112 is the upper support member 112. The upper support member 112 may be located at a higher level than the lower support member 111. The upper support member 112 may support the upper outer wall of the lower electrode 105, and the lower support member 111 may support the outer wall of the lower electrode 105 at a level lower than the upper support member 112. The exact positions of the upper support member 112 and the lower support member 111 may be modified in different ways.

[0114] A dielectric layer 106 may be formed to cover the exposed surfaces of the lower electrode 105, the lower support member 111, and the upper support member 112, and an upper electrode 107 may be formed over the dielectric layer 106. The upper electrode 107 may include: a liner electrode 108, a gap-fill electrode 109, and a low-resistivity electrode 110. The liner electrode 108 may be conformally formed over the dielectric layer 106, and the gap-fill electrode 109 may gap-fill the space between adjacent lower electrodes 105 over the liner electrode 108, and the low-resistivity electrode 110 may cover the gap-fill electrode 109. The gap-fill electrode 109 may be embedded between the liner electrode 108 and the low-resistivity electrode 110. The gap-fill electrode 109 may not be formed between adjacent lower electrodes 105.

[0115] See Figure 3 , the upper electrode 107 may include an upper electrode edge portion 107E, and the upper electrode edge portion 107E may be located at the edge portion of the memory cell region R1. The upper electrode edge portion 107E may be provided by the low-resistivity electrode side portion 110S. The low-resistivity electrode side portion 110S may not be located in the peripheral circuit region R2. The upper electrode edge portion 107E may include an upper electrode edge bottom 107LE’.

[0116] The gap-fill electrode 109 can fill the space between the lower electrodes 105 above the liner electrode 108. The gap-fill electrode 109 can include a gap-fill electrode upper portion 109T and a gap-fill electrode side portion 109S. The gap-fill electrode side portion 109S can extend from the gap-fill electrode upper portion 109T. The gap-fill electrode upper portion 109T can be located at a higher level than the lower electrode 105, and the gap-fill electrode side portion 109S can be in a shape that is recessed by a retraction process to be laterally spaced apart from the second contact plug 115.

[0117] Return to Figure 1B , the gap-fill electrode side portions 109S can be respectively located in the edge portions on both sides of the memory cell region R1. The gap-fill electrode side portions 109S can include a plurality of gap-fill electrode side portions S1, S2, S3, and S4. The gap-fill electrode side portions S1, S2, S3, and S4 can include: a first gap-fill electrode side portion S1, a second gap-fill electrode side portion S2, a third gap-fill electrode side portion S3, and a fourth gap-fill electrode side portion S4. The first gap-fill electrode side portion S1 can cover the edge portion of the upper layer support 112, and the third gap-fill electrode side portion S3 can cover the edge portion of the lower layer support 112. The second gap-fill electrode side portion S2 can be located between the first gap-fill electrode side portion S1 and the third gap-fill electrode side portion S3 to be close to the side surface of the outermost lower electrode 105 of the memory cell region R1. The fourth gap-fill electrode side portion S4 can be located between the third gap-fill electrode side portion S3 and the etch stop layer 104 to be close to the side surface of the outermost lower electrode 105 of the memory cell region R1. The second gap-fill electrode side portion S2 and the fourth gap-fill electrode side portion S4 can respectively extend from the first gap-fill electrode side portion S1 and the third gap-fill electrode side portion S3. The fourth gap-fill electrode side portion S4 can be located at a lower level than the lower layer support 111. The first gap-fill electrode side portion S1 and the third gap-fill electrode side portion S3 can be referred to as support-side edge portions, and the second gap-fill electrode side portion S2 and the fourth gap-fill electrode side portion can be referred to as lower-electrode-side edge portions.

[0118] The thickness D2 of the first gap-fill electrode side portion S1 and the second gap-fill electrode side portion S3 can be thinner than the thickness D1 of the gap-fill electrode upper portion 109T. The second gap-fill electrode side portion S2 and the fourth gap-fill electrode side portion S4 can be thicker than the first gap-fill electrode side portion S1 and the third gap-fill electrode side portion S3. The second gap-fill electrode side portion S2 and the fourth gap-fill electrode side portion S4 can be thinner than the gap-fill electrode upper portion 109T. According to another embodiment of the present invention, the second gap-fill electrode side portion S2 and the fourth gap-fill electrode side portion S4 can be as thick as or thicker than the gap-fill electrode upper portion 109T. The gap-fill electrode side portion 109S can have a vertical profile.

[0119] Figure 3 The gap-fill electrode 109 shown in Figure 1A is different from the gap-fill electrode 109 shown in , and may not include the lateral edge portion 109E. The bottom of the upper electrode edge 107LE' may not include the lateral edge portion 109E.

[0120] The low-resistivity electrode 110 may include a low-resistivity electrode upper portion 110T covering the upper portion 109T of the gap-fill electrode and a low-resistivity electrode side portion 110S covering the side portion 109S of the gap-fill electrode. The low-resistivity electrode side portion 110S may completely cover the side portion 109S of the gap-fill electrode. As a result, the side portion 109S of the gap-fill electrode can be sealed to the outside by the low-resistivity electrode 110 and the liner electrode 108. The edge portions of the low-resistivity electrode side portion 110S and the liner electrode 108 may be vertically self-aligned. The bottom of the upper electrode edge 107LE' may not include the lateral edge portion 109E. The bottom of the upper electrode edge 107LE' may be provided by the edge bottom of the low-resistivity electrode side portion 110S and the liner electrode 109.

[0121] Figures 4A to 4D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0122] First, a covering portion 27 can be formed through Figures 2A to 2K the series of processes shown in .

[0123] Subsequently, as shown in Figure 4A a retraction process of the gap-fill layer 26A can be performed. For example, the side portion 26AS of the gap-fill layer 26A can be etched by using the covering portion 27 as an etch stop layer. The side protrusion 26P of the gap-fill layer 26A can be cut by etching the side portion 26AS of the gap-fill layer 26A. As a result, a gap-fill electrode 26' can be formed. The position of the edge portion of the gap-fill electrode 26' can be retracted toward the memory cell region R1 to be closer to the memory cell region R1 than the position of the edge portion of the gap-fill layer 26A.

[0124] The gap-fill electrode 26' may include an upper portion 26T and a side portion 26S'. The upper portion 26T of the gap-fill electrode 26' may maintain the same thickness as the upper portion 26AT of the gap-fill layer 26A. The thickness of the side portion 26S' of the gap-fill electrode 26' may be thinner than the thickness of the side portion 26AS of the gap-fill layer 26A. Different from Figure 2L the gap-fill electrode 26 shown in , Figure 4A the gap-fill electrode 26' shown in may not include an edge portion. For example, the retraction process of the gap-fill layer 26A can be further performed such that the gap-fill electrode 26' only includes the side portion 26S.Figure 4A The side portion 26S' of Figure 2L can be thinner than the side portion 26S of

[0125] Referring to Figure 4B , the covering portion 27 can be removed. Since the covering portion 27 is removed, the upper portion 26T of the gap-fill electrode 26 can be exposed.

[0126] The side portion 26S' of the gap-fill electrode 26' can be located at the edge of the memory cell region R1 and can not be located at the edge of the peripheral circuit region R2.

[0127] Subsequently, a low-resistivity electrode 28 can be formed over the gap-fill electrode 26'. The low-resistivity electrode 28 can include a metal, a metal nitride, a conductive metal nitride, or a combination thereof. The low-resistivity electrode 28 can include: titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium, iridium, ruthenium oxide, iridium oxide, or a combination thereof. According to an embodiment of the present invention, the low-resistivity electrode 28 can be formed of tungsten nitride (WN).

[0128] As described above, the liner electrode 25, the gap-fill electrode 26', and the low-resistivity electrode 28 can be the upper electrodes of the capacitor.

[0129] The low-resistivity electrode 28 can cover the memory cell region R1 and the peripheral circuit region R2.

[0130] Referring to Figure 4C , an upper electrode patterning process can be performed. In the upper electrode patterning process, the low-resistivity electrode 28, the gap-fill electrode 26', and the liner electrode 25 can be sequentially etched by using the upper electrode mask layer 29. The upper electrode mask layer 29 can include a photoresist pattern. The upper electrode mask layer 29 can be a mask for separating the upper electrodes based on the memory blocks in the memory cell region R1.

[0131] The upper electrode TE can be defined by the upper electrode patterning process. The upper electrode TE can include a stack of the liner electrode 25, the gap-fill electrode 26, and the low-resistivity electrode 28. The upper electrode TE can include the bottom of the upper electrode edge 26LE', and the bottom of the upper electrode edge 26LE' can not be located in the peripheral circuit region R2. The bottom of the upper electrode edge 26LE' can include the bottom of the liner electrode edge 25E and the bottom of the low-resistivity electrode edge 28E. The bottom of the liner electrode edge 25E can be self-aligned perpendicular to the bottom of the low-resistivity electrode edge 28E.

[0132] After the upper electrode patterning process, the dielectric layer 24 can be removed from the peripheral circuit region R2. This can be referred to as dielectric layer cutting.

[0133] Referring to Figure 4D, an upper interlayer dielectric layer 30 may be formed over the upper electrode TE. The upper interlayer dielectric layer 30 may include, for example, silicon oxide. The upper interlayer dielectric layer 30 may remove a step formed between the memory cell region R1 and the peripheral circuit region R2. To remove the step, the upper surface of the upper interlayer dielectric layer 30 may be planarized.

[0134] Subsequently, a first contact plug 31 and a second contact plug 32 may be formed to penetrate the upper interlayer dielectric layer 30. The first contact plug 31 may be coupled to the low-resistivity electrode 28 of the upper electrode TE, and the second contact plug 32 may be coupled to the lower interconnect PM.

[0135] The upper interconnect 33 may be formed to be coupled to the first contact plug 31 and the second contact plug 32, respectively.

[0136] According to the above embodiment of the present invention, since the gap-fill electrode 26' is formed by a retraction process, the distance L' between the side portion (or edge portion) of the upper electrode TE and the second contact plug 32 of the peripheral circuit region R2 may be sufficiently spaced apart from each other.

[0137] As a result, since the second contact plug 32 and the upper electrode TE are sufficiently insulated from each other, an electrical short circuit between the second contact plug 32 and the upper electrode TE can be prevented. In addition, this can reduce the size of the memory cell region R1, thereby improving the miniaturization of the semiconductor device.

[0138] Figure 5 is a cross-sectional view showing a semiconductor device 300 according to another embodiment of the present invention. Figure 5 The semiconductor device 300 may be similar to Figure 1A the semiconductor device 100 shown in. Hereinafter, a detailed description of overlapping constituent elements will be omitted.

[0139] See Figure 5 , the semiconductor device 300 may include a memory cell region R1 and a peripheral circuit region R2. A plurality of memory cells (not shown) may be formed to be spaced apart at a predetermined interval in the memory cell region R1.

[0140] A plurality of lower electrodes 105 may be disposed in the memory cell region R1. Each lower electrode 105 may be electrically connected to the substrate 101 via a corresponding one of the plurality of cell contact plugs 103. The cell contact plug 103 may penetrate the lower interlayer dielectric layer 102 over the substrate 101 to be coupled to the substrate 101. An etch stop layer 104 may be formed over the lower interlayer dielectric layer 102, and the bottom of the lower electrode 105 may penetrate the etch stop layer 104 to be coupled to their respective cell contact plugs 103.

[0141] The lower electrode 105 may be supported by at least one support member (e.g., support member 111 or 112). The support members 111 and 112 may form a multi-layer structure, where the support member 111 is the lower support member and the support member 112 is the upper support member. The upper support member 112 may be located at a higher level than the lower support member 111. The upper support member 112 may support the upper outer wall of the lower electrode 105, and the lower support member 111 may support the outer wall of the lower electrode 105 at a level lower than the upper support member 112. The positions of the upper support member 112 and the lower support member 111 may be modified in different ways.

[0142] The dielectric layer 106 may be formed to cover the surfaces of the lower electrode 105, the lower support member 111, and the upper support member 112, and the upper electrode 107 may be formed over the dielectric layer 106. The upper electrode 107 may include a liner electrode 108, a gap-fill electrode 109', and a low-resistivity electrode 110. The liner electrode 108 may be conformally formed over the dielectric layer 106, and the gap-fill electrode 109' may fill the space between adjacent lower electrodes 105 over the liner electrode 108, and the low-resistivity electrode 110 may cover the gap-fill electrode 109'. The gap-fill electrode 109' may be embedded between the liner electrode 108 and the low-resistivity electrode 110.

[0143] See Figure 5 , the upper electrode 107 may include an upper electrode edge portion 107E, and the upper electrode edge portion 107E may be located in the edge portion R1E of the memory cell region R1. The upper electrode edge portion 107E may be provided by the low-resistivity electrode side portion 110S. The low-resistivity electrode side portion 110S may not be located in the peripheral circuit region R2. The upper electrode edge portion 107E may include an upper electrode edge bottom 107LE.

[0144] The gap-fill electrode 109' may fill the space between the lower electrodes 105 over the liner electrode 108. The gap-fill electrode 109' may include a gap-fill electrode upper portion 109T and a gap-fill electrode side portion 109S'. The gap-fill electrode side portion 109S' may be discontinuous with the gap-fill electrode upper portion 109T. The gap-fill electrode upper portion 109T may be located at a level higher than the lower electrodes 105, and the gap-fill electrode side portion 109S' may have a shape that is retracted by a retraction process to be laterally spaced apart from the second contact plug 115.

[0145] The gap-fill electrode side portion 109S' may be located between the upper support member 112 and the lower support member 111. The gap-fill electrode side portion 109S' may be located at a level lower than the lower support member 111.

[0146] The side portion 109S' of the gap-fill electrode may not be located on the sides of the upper support member 112 and the lower support member 111. For example, the liner electrode 108 may be located between the low-resistivity electrode side portion 110S and the upper support member 112, but the side portion 109S' of the gap-fill electrode may not be located therebetween. In addition, the liner electrode 108 may be located between the low-resistivity electrode side portion 110S and the lower support member 111, but the side portion 109S' of the gap-fill electrode may not be located therebetween.

[0147] As described above, Figure 5 the gap-fill electrode 109' may be retracted more toward the memory cell region R1 compared to Figure 1A and Figure 3 the gap-fill electrode 109. As a result, the size of the edge portion of the upper electrode 107 can be further reduced. After all, as the gap-fill electrode 109' is further retracted, the distance L1' between the edge portion (i.e., the side portion) of the upper electrode 107 and the second contact plug 115 in the peripheral circuit region R2 can be further increased. The distance L1' can be greater than Figure 1A and Figure 3 the distance L1 shown in

[0148] Figure 6A FIG. is a cross-sectional view showing a semiconductor device 400 according to another embodiment of the present invention. Figure 6A The semiconductor device 400 may be similar to Figure 1A the semiconductor device 100. Hereinafter, detailed descriptions of overlapping constituent elements will be omitted. Figure 6B FIG. is Figure 6A an enlarged view of a portion 600A of

[0149] Referring to Figure 6A and Figure 6B , the semiconductor device 400 may include a memory cell region R1 and a peripheral circuit region R2. A plurality of memory cells (not shown) may be formed to be spaced apart at a predetermined interval in the memory cell region R1.

[0150] A plurality of lower electrodes 105 may be disposed in the memory cell region R1. Each lower electrode 105 may be electrically connected to the substrate 101 via a corresponding one of the plurality of unit contact plugs 103. The unit contact plug 103 may penetrate the lower interlayer dielectric layer 102 above the substrate 101 to be coupled to the substrate 101. An etch stop layer 104 may be formed above the lower interlayer dielectric layer 102, and the bottom of the lower electrode 105 may penetrate the etch stop layer 104 to be coupled to their respective unit contact plugs 103.

[0151] The lower electrode 105 may be supported by at least one support member (e.g., support member 111 or 112). The support members 111 and 112 may form a multi-layer structure, where the support member 111 is the lower support member and the support member 112 is the upper support member. The upper support member 112 may be located at a higher level than the lower support member 111. The upper support member 112 may support the upper outer wall of the lower electrode 105, and the lower support member 111 may support the outer wall of the lower electrode 105 at a lower level than the upper support member 111. The positions of the upper support member 112 and the lower support member 111 may be modified in different ways.

[0152] A dielectric layer 106 may be formed to cover the surfaces of the lower electrode 105, the lower support member 111, and the upper support member 112, and an upper electrode 107 may be formed over the dielectric layer 106. The upper electrode 107 may include a liner electrode 108, a gap-fill electrode 109", and a low-resistivity electrode 110. The liner electrode 108 may be conformally formed over the dielectric layer 106. The gap-fill electrode 109" may fill the space between adjacent lower electrodes 105 over the liner electrode 108, and the low-resistivity electrode 110 may cover the gap-fill electrode 109". The gap-fill electrode 109" may be embedded between the liner electrode 108 and the low-resistivity electrode 110.

[0153] See Figure 6A and Figure 6B , the upper electrode 107 may include an upper electrode edge portion 107E, and the upper electrode edge portion 107E may be located at the edge portion R1E of the memory cell region R1. The upper electrode edge portion 107E may be provided by the low-resistivity electrode side portion 110S. The low-resistivity electrode side portion 110S may not be located in the peripheral circuit region R2.

[0154] The gap-fill electrode 109" may fill the space between the lower electrodes 105 over the liner electrode 108. The gap-fill electrode 109" may include a gap-fill electrode upper portion 109T and a gap-fill electrode side portion 109S. The gap-fill electrode side portion 109S" may be continuous with the gap-fill electrode upper portion 109T. The gap-fill electrode upper portion 109T may be located at a higher level than the lower electrode 105, and the gap-fill electrode side portion 109S" may have a shape that is retracted by a retraction process to be laterally spaced apart from the second contact plug 115.

[0155] The gap-fill electrode side portion 109S" may be located at the two edge portions of the memory cell region R1. As Figure 6BAs shown, each gap-fill electrode side portion 109S” may include a plurality of gap-fill electrode side portions S11, S12, S13, and S14. The gap-fill electrode side portions S11, S12, S13, and S14 may include: a first gap-fill electrode side portion S11, a second gap-fill electrode side portion S12, a third gap-fill electrode side portion S13, and a fourth gap-fill electrode side portion S14. The first gap-fill electrode side portion S11 may cover an edge portion of the upper support member 112, and the third gap-fill electrode side portion S13 may cover an edge portion of the lower support member 112. The second gap-fill electrode side portion S12 may be located between the first gap-fill electrode side portion S11 and the third gap-fill electrode side portion S13 to be close to a sidewall of the outermost lower electrode 105 of the memory cell region R1. The fourth gap-fill electrode side portion S14 may be located between the third gap-fill electrode side portion S13 and the etch stop layer 104 to be close to a side surface of the outermost lower electrode 105 of the memory cell region R1. The second gap-fill electrode side portion S12 and the fourth gap-fill electrode side portion S14 may extend from the first gap-fill electrode side portion S11 and the third gap-fill electrode side portion S13, respectively. The fourth gap-fill electrode side portion S14 may be located at a level lower than that of the lower support member 111. The first gap-fill electrode side portion S11 and the third gap-fill electrode side portion S13 may be referred to as support member side edge portions, and the second gap-fill electrode side portion S2 and the fourth gap-fill electrode side portion S4 may be referred to as lower electrode side edge portions.

[0156] The thickness D12 of the first gap-fill electrode side portion S11 and the second gap-fill electrode side portion S13 may be thinner than the thickness D1 of the gap-fill electrode upper portion 109T. The second gap-fill electrode side portion S12 and the fourth gap-fill electrode side portion S14 may be thicker than the first gap-fill electrode side portion S11 and the third gap-fill electrode side portion S13. The second gap-fill electrode side portion S12 and the fourth gap-fill electrode side portion S14 may be thinner than the gap-fill electrode upper portion 109T. According to another embodiment of the present invention, the thicknesses of the second gap-fill electrode side portion S12 and the fourth gap-fill electrode side portion S14 may be equal to or thicker than the thickness of the gap-fill electrode upper portion 109T.

[0157] The lateral lengths of the first gap-fill electrode side portion S11 and the second gap-fill electrode side portion S13 may be longer than the lateral lengths of the first gap-fill electrode side portion S12 and the fourth gap-fill electrode side portion S14. For example, the ends of the first gap-fill electrode side portion S11 and the second gap-fill electrode side portion S13 may be shaped to protrude from the ends of the first gap-fill electrode side portion S12 and the fourth gap-fill electrode side portion S14. The first gap-fill electrode side portion S11 and the second gap-fill electrode side portion S13 may be referred to as protruding support member side edge portions.

[0158] The lateral lengths of the first gap filling electrode side portion S11 and the second gap filling electrode side portion S13 can be longer than Figure 1B the lateral lengths of the first gap filling electrode side portion S1 and the third gap filling electrode side portion S3 shown.

[0159] The first gap filling electrode side portion S11 and the second gap filling electrode side portion S13 can be formed by Figure 2K etch-back processing of the side protrusion 26P of the gap filling layer 26A shown in.

[0160] The gap filling electrode side portion 109S” formed by the first gap filling electrode side portion S11 and the second gap filling electrode side portion S13 can have a non-conformal surface.

[0161] According to an embodiment of the present invention, the edge portion of the upper electrode can be reduced by retracting the gap filling layer which is a part of the upper electrode via a retraction process. This can reduce the size of the memory cell region, thereby improving the die.

[0162] Since the gap filling layer which is a part of the upper electrode is retracted by the retraction process, the contact plug in the peripheral circuit region and the upper electrode in the memory cell region can be insulated from each other.

[0163] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Forming a lower array, the lower array including: a plurality of lower electrodes on a semiconductor substrate, a support member supporting the lower electrodes, and a dielectric layer on the lower electrodes and the support member; Forming a gap-fill layer covering sides and an upper portion of the lower array; Forming a covering portion covering the upper portion of the lower array on the gap-fill layer; Performing a retraction process on the gap-fill layer to form a gap-fill electrode aligned with the covering portion; and Forming a low-resistivity layer covering sides and an upper portion of the lower array on the semiconductor substrate; and Etching the low-resistivity layer to cover sides and an upper portion of the lower array to form a low-resistivity electrode on the gap-fill electrode, The low-resistivity electrode including a metal, a metal nitride, a metal silicide, or a combination thereof.

2. The method according to claim 1, wherein The gap-fill layer includes a protruding portion covering a side of the lower array, and the protruding portion is cut by the retraction process.

3. The method according to claim 1, wherein The gap-fill electrode includes: A gap-fill electrode upper portion covering the upper portion of the lower array; and A gap-fill electrode side portion extending from the gap-fill electrode upper portion to cover the side of the lower array, Wherein the gap-fill electrode side portion has a vertical profile.

4. The method according to claim 3, wherein Compared with a side of the gap-fill layer, the gap-fill electrode side portion is laterally retracted.

5. The method according to claim 3, wherein, The gap-fill electrode further includes: A gap-fill electrode edge bottom extending from the gap-fill electrode side portion, Wherein, compared with an edge portion of the gap-fill layer, the gap-fill electrode edge bottom is laterally retracted.

6. The method according to claim 1, wherein, The gap-fill electrode further includes: A support member side side portion covering an edge portion of the support member; and A lower electrode side side portion extending from the support member side side portion, Wherein the lower electrode side side portion is thicker than the support member side side portion.

7. The method according to claim 1, wherein The retraction process includes: Laterally etching the gap-fill layer by using the covering portion as an etch stop layer.

8. The method according to claim 1, wherein, The retraction process includes a dry etching process or a wet leaching process.

9. The method according to claim 1, wherein The gap-fill layer includes a semiconductor material.

10. The method according to claim 1, wherein, The gap-fill layer includes: a silicon layer, a boron-doped silicon layer, a silicon germanium layer, a boron-doped silicon germanium layer, silicon carbide, or a combination thereof.

11. The method according to claim 1, wherein, The covering portion includes a material having an etch selectivity with respect to the gap-fill layer.

12. The method according to claim 1, wherein, The covering portion includes: silicon oxide, silicon nitride, amorphous carbon, or a photoresist.

13. The method according to claim 1, wherein Forming the covering portion covering the upper portion of the lower array on the gap-fill layer includes: Forming a covering material conformally covering sides and an upper portion of the lower array on the gap-fill layer; Forming a mask layer covering the upper portion of the lower array on the covering material; and Removing a part of the covering material by using the mask layer as an etch stop layer to form the covering portion on the lower array.

14. The method according to claim 1, further comprising: After etching the low-resistivity layer to cover the sides of the lower array and the upper part of the lower array over the gap-fill electrode, a portion of the gap-fill electrode is cut to align with the low-resistivity electrode.

15. The method according to claim 1, further comprising: After forming the low-resistivity electrode over the gap-fill electrode, a contact plug physically spaced apart from the low-resistivity electrode is formed in a region spaced apart from the lower array.

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