Semiconductor device and method for manufacturing semiconductor device

Abstract

Disclosed are a structure of a semiconductor device having a core-shell nanostructured channel region between source / drain (S / D) regions of a FET device, and a method of manufacturing a semiconductor device. The semiconductor device includes: a substrate; a stack of nanostructured layers having first and second nanostructured regions disposed on the substrate; and a nanostructured shell region wrapping the second nanostructured region. The nanostructured shell region and the second nanostructured region have semiconductor materials different from each other. The semiconductor device further includes first and second source / drain (S / D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S / D regions. Each of the first and second S / D regions includes an epitaxial region wrapping each first nanostructured region, and the GAA structure wraps each nanostructured shell region.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods for manufacturing semiconductor devices. Background Art

[0002] With the advancement of semiconductor technology, the demand for higher storage capacity, faster processing systems, and higher performance continues to grow. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs) including planar MOSFETs and fin field effect transistors (finFETs). This scaling has increased the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] Some embodiments of the present application provide a semiconductor device, comprising: a substrate; a stack of nanostructured layers having a first nanostructured region and a second nanostructured region disposed on the substrate; a nanostructured shell region wrapping the second nanostructured region, wherein the nanostructured shell region and the second nanostructured region have different semiconductor materials from each other; a first source / drain (S / D) region and a second source / drain region disposed on the substrate, wherein each of the first source / drain region and the second source / drain region includes an epitaxial region wrapping each of the first nanostructured regions; and a gate-all-around (GAA) structure disposed between the first source / drain region and the second source / drain region and wrapping each of the nanostructured shell regions.

[0004] Some other embodiments of the present application provide a semiconductor device, including: a first field-effect transistor (FET), including: a stack of first nanostructured layers disposed on a substrate, wherein each of the first nanostructured layers includes a first nanostructured region and a second nanostructured region, a first nanostructured shell region wrapping the second nanostructured region, wherein the first nanostructured shell region and the second nanostructured region have different semiconductor materials, a first epitaxial region wrapping each of the first nanostructured regions, and a first gate-all-around (GAA) structure disposed on the stack of the first nanostructured layers and wrapping each of the first nanostructured shell regions; and a second field-effect transistor, including: a stack of second nanostructured layers disposed on the substrate, wherein each of the second nanostructured layers includes a third nanostructured region and a fourth nanostructured region, a second nanostructured shell region wrapping the fourth nanostructured region, wherein the second nanostructured shell region and the fourth nanostructured region have different semiconductor materials, and wherein the first nanostructured shell region and the second nanostructured shell region have different material compositions, a second epitaxial region wrapping each of the third nanostructured regions, wherein the conductivity type of the second epitaxial region is different from that of the first epitaxial region, and a second gate-all-around structure disposed on the stack of the second nanostructured layers and wrapping each of the second nanostructured shell regions.

[0005] Some further embodiments of the present application provide a method for manufacturing a semiconductor device, including: forming a stack of nanostructured layers having a first nanostructured region and a second nanostructured region on a substrate; modifying the second nanostructured region to form a nanostructured core region; epitaxially growing a nanostructured shell region wrapping the nanostructured core region; growing a first epitaxial region and a second epitaxial region wrapping each of the first nanostructured regions; forming a gate-all-around (GAA) structure wrapping each of the nanostructured shell regions between the first epitaxial region and the second epitaxial region; and forming a first inner spacer and a second inner spacer along sidewalls of a gate sub-region of the gate-all-around structure, wherein the gate sub-region is embedded in the stack of the nanostructured layers. Description of the Drawings

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A and Figures 1B to 1DAn isometric view and a cross-sectional view of a semiconductor device having a core-shell nanostructure according to some embodiments are shown, respectively.

[0008] Figure 1E and Figures 1F to 1G An isometric view and a cross-sectional view of a semiconductor device having a passivation layer according to some embodiments are shown, respectively.

[0009] Figures 2A to 2D A cross-sectional view of different configurations of a semiconductor device according to some embodiments is shown.

[0010] Figure 3 A flowchart of a method for manufacturing a semiconductor device having a core-shell nanostructure according to some embodiments is shown.

[0011] Figures 4A to 23A Isometric views of a semiconductor device having internal and external spacer structures at various stages of its manufacturing process according to some embodiments are shown.

[0012] Figures 4B to 23B 、 Figures 9C to 23C and Figures 9D to 23D Cross-sectional views of a semiconductor device having internal and external spacer structures at various stages of its manufacturing process according to some embodiments are shown.

[0013] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally denote identical, functionally similar, and / or structurally similar elements. Detailed Description

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component means that the first component is formed in direct contact with the second component. Additionally, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. Except for the orientation shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0016] Note that references in the specification to "an embodiment", "embodiments", "example embodiments", "exemplary", etc. indicate that the described embodiments may include a particular component, structure, or characteristic, but each embodiment does not necessarily include the particular component, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular component, structure, or feature is described in connection with an embodiment, implementation of such component, structure, or feature in connection with other embodiments is within the knowledge of those skilled in the art, whether or not explicitly described.

[0017] It should be understood that the words or terms herein are for the purpose of description rather than limitation, such that the terms or phrases of this specification will be interpreted by those skilled in the relevant art in accordance with the teachings herein.

[0018] As used herein, the term "etch selectivity" refers to the ratio of the etch rates of two different materials under the same etching conditions.

[0019] As used herein, the term "deposition selectivity" refers to the ratio of the deposition rates on two different materials or surfaces under the same deposition conditions.

[0020] As used herein, the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high-k refers to a dielectric constant greater than that of SiO 2 (e.g., greater than 3.9).

[0021] As used herein, the term "p-type" defines a structure, layer, and / or region doped with a p-type dopant such as boron.

[0022] As used herein, the term "n-type" defines a structure, layer, and / or region doped with an n-type dopant such as phosphorus.

[0023] As used herein, the term "nanostructured" defines a structure, layer, and / or region having a horizontal dimension (e.g., along the X and / or Y axes) and / or a vertical dimension (e.g., along the Z axis) less than 100 nm.

[0024] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). Of course, these values are merely examples and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of the value as interpreted by a person of ordinary skill in the art in accordance with the teachings herein.

[0025] The fin structures disclosed herein can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fin structures, and the lithography processes include double patterning processes or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, allowing the creation of patterns having a pitch, for example, smaller than the pitch obtainable using a single direct lithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern the fin structures.

[0026] The present invention provides exemplary structures and methods for improving charge carrier mobility (e.g., hole and / or electron mobility) in FET devices (such as finFETs, all-around-gate FETs, etc.). Increasing the charge carrier mobility can increase the switching speed and drive current of the FET device, resulting in faster and improved FET device performance.

[0027] The exemplary structures and methods provide a channel region having a core-shell nanostructure between source / drain (S / D) regions of an FET device. In some embodiments, the core-shell nanostructure can include a nanostructured core region wrapped by an epitaxially grown nanostructured shell region. The core-shell nanostructure can be configured to induce tensile or compressive strain in the channel region of an n-type or p-type FET device, respectively. Tensile or compressive strain can be induced in the channel region, for example, by doping the nanostructured core or shell region or by using semiconductor materials with lattice mismatch for the nanostructured core or shell region. This induced strain in the channel region can improve the charge carrier mobility in the channel region. The core-shell nanostructure can further be configured to adjust the bandgap of the channel region and / or change the crystal orientation of the surface of the channel region based on the conduction type of the FET device to improve the charge carrier mobility in the channel region. Compared with an FET device without such a core-shell nanostructure, the channel region having a core-shell nanostructure described herein can increase the switching speed and drive current of the FET device by, for example, about 20% to about 40% and about 30% to about 50%.

[0028] According to some embodiments, reference Figures 1A to 1DDescribe the semiconductor device 100 having FETs 102A - 102B. Figure 1A An isometric view of the semiconductor device 100 according to some embodiments is shown. Figures 1B to 1D Cross-sectional views of the semiconductor device 100 taken along line B - B, C - C, and D - D according to some embodiments are shown respectively. In some embodiments, the FETs 102A - 102B can each be a p-type FET or each be an n-type FET or one of each conductive type FET. Even though two FETs are discussed with reference to Figure 1A the semiconductor device 100 can have any number of FETs. Unless otherwise specified, the discussion of elements of the FETs 102A - 102B with the same reference applies to each other. The isometric view and cross-sectional views of the semiconductor device 100 are shown for illustrative purposes and may not be drawn to scale. Figures 1A to 1D For illustrative purposes, an isometric view and cross-sectional views of the semiconductor device 100 are shown and may not be drawn to scale.

[0029] Reference Figures 1A to 1D may be made to form the FETs 102A - 102B on the substrate 106. The substrate 106 can be a semiconductor material such as, but not limited to, silicon. In some embodiments, the substrate 106 can include a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 106 can include (i) an elemental semiconductor such as germanium (Ge); (ii) a compound semiconductor including silicon carbide (SiC), silicon arsenide (SiAs), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), and / or III - V group semiconductor materials; (iii) an alloy semiconductor including silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide phosphide (GaAsP), gallium indium phosphide (GaInP), gallium indium arsenide (GaInAs), gallium indium arsenide phosphide (GaInAsP), aluminum indium arsenide (AlInAs), and / or aluminum gallium arsenide (AlGaAs); (iv) a silicon-on-insulator (SOI) structure; (v) a silicon germanium-on-insulator (SiGe) structure (SiGeOI); (vi) a germanium-on-insulator (GeOI) structure; or (vii) a combination thereof. Additionally, the substrate 106 can be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 106 can be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0030] The FETs 102A - 102B may respectively include fin structures 108A - 108B, passivation layers 109A - 109B, epitaxial fin regions 110A - 110B, gate structures 112A - 112B (also referred to as gate-all-around (GAA) structures 112A - 112B), inner spacers 113A - 113B, and outer spacers 114A - 114B.

[0031] As Figures 1B to 1D shown, the fin structure 108A may include a stack of a fin base 119A and a first semiconductor layer 120 disposed on the fin base 119A, and the fin structure 108B may include a stack of a fin base 119B and a second semiconductor layer 122. In some embodiments, the fin bases 119A - 119B may include a material similar to the substrate 106. The fin bases 119A - 119B may be formed by lithographic patterning and etching of the substrate 106. The first semiconductor layer 120 and the second semiconductor layer 122 may include different semiconductor materials from each other. In some embodiments, the first semiconductor layer 120 and the second semiconductor layer 122 may include semiconductor materials having different oxidation rates and / or etching selectivities from each other. In some embodiments, the first semiconductor layer 120 and the second semiconductor layer 122 may include semiconductor materials similar to or different from the substrate 106. The first semiconductor layer 120 and the second semiconductor layer 122 may include (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors containing III - V group semiconductor materials; (iii) alloy semiconductors, including SiGe, germanium tin, or silicon germanium tin; or (iv) combinations thereof.

[0032] In some embodiments, the first semiconductor layer 120 and the second semiconductor layer 122 may comprise SiGe having Ge in the range from about 25 atomic percent to about 50 atomic percent (where any remaining atomic percent is Si), or may comprise Si without any substantial amount of Ge (e.g., no Ge). The semiconductor material of the first semiconductor layer 120 and the second semiconductor layer 122 may be undoped or may be doped in-situ during their epitaxial growth process using the following dopants: (i) p-type dopants such as boron, indium, or gallium; and / or (ii) n-type dopants such as phosphorus or arsenic. In some embodiments, if the semiconductor device 100 is a complementary metal oxide semiconductor (CMOS) device, the first semiconductor layer 120 may comprise, respectively, Si, SiAs, silicon phosphide (SiP), SiC, or silicon carbon phosphide (SiCP) for the n-type FET 102A or SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), or III-V semiconductor compounds for the p-type FET 102A, and the second semiconductor layer 122 may comprise, respectively, SiGe, SiGeB, GeB, SiGeSnB for the p-type FET 102A or Si, SiAs, SiP, SiC, or SiCP for the n-type FET 102B. In some embodiments, both the first semiconductor layer 120 and the second semiconductor layer 122 may comprise Si, SiAs, SiP, SiC, or SiCP for the n-type FETs 102A - 102B, or SiGe, SiGeB, GeB, SiGeSnB, or III-V semiconductor compounds for the p-type FETs 102A - 102B.

[0033] Each first semiconductor layer 120 may have (i) a nanostructured region 120A wrapped by an epitaxial fin region 110A and underlying inner and outer spacers 113A - 114A ( Figure 1A and Figure 1D ), and (ii) a nanostructured core region 121A wrapped by a nanostructured shell region 121B (see Figure 1B and Figure 1D ). The nanostructured core region 121A and the nanostructured shell region 121B may form a core-shell nanostructured channel region 121 between the S / D regions 126A of the FET 102A. Each core-shell nanostructured channel region 121 may be wrapped by a gate structure 112A ( Figure 1B and Figure 1D ).

[0034] Similarly, each second semiconductor layer 122 may have (i) a nanostructured region wrapped by an epitaxial fin region 110B and underlying inner and outer spacers 113B - 114B ( Figure 1A and Figure 1C)The encapsulated nanostructured region 122A, and (ii) the nanostructured core region 123A encapsulated by the nanostructured shell region 123B (see Figure 1B and Figure 1C ). The nanostructured core region 123A and the nanostructured shell region 123B can form a core-shell nanostructured channel region 123 between the S / D regions 126B of the FET 102A. Each core-shell nanostructured channel region 123 can be encapsulated by the gate structure 112B ( Figure 1B and Figure 1C ).

[0035] The nanostructured core regions 121A and 123A can be located under the respective gate structures 112A-112B, and can be formed by modifying the first nanostructured region 120B and the second nanostructured region 122B (not shown in Figures 1A to 1D ; shown in Figure 18B and Figure 21B ), respectively. The material compositions of the nanostructured core regions 121A and 123A can be similar to the material compositions of the first semiconductor layer 120 and the second semiconductor layer 122, respectively.

[0036] The nanostructured shell regions 121B and 123B can be located under the respective gate structures 112A-112B, and can be epitaxially formed on the respective nanostructured core regions 121A and 123B. In some embodiments, if the semiconductor device 100 is a complementary metal oxide semiconductor (CMOS) device, the nanostructured shell region 121B can include Si, SiAs, silicon phosphide (SiP), SiC, or silicon carbide phosphide (SiCP) for the n-type FET 102A, or Ge, SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), or III-V semiconductor compounds for the p-type FET 102A, and the nanostructured shell region 123B can include Ge, SiGe, SiGeB, GeB, SiGeSnB, or III-V semiconductor compounds for the p-type FET 102A and Si, SiAs, SiP, SiC, or SiCP for the n-type FET 102B, respectively. In some embodiments, the nanostructured shell regions 121B and 123B for the n-type FETs 102A-102B can both include Si, SiAs, SiP, SiC, or SiCP for the n-type FETs 102A-102B, or III-V semiconductor compounds for the p-type FETs 102A-102B. In some embodiments, the semiconductor materials of the nanostructured shell regions 121B and / or 123B can be undoped or can be in-situ doped during their epitaxial growth, using: (i) p-type dopants such as boron, indium, or gallium; and / or (ii) n-type dopants such as phosphorus or arsenic.

[0037] The material and structural compositions of the nanostructured shell regions 121B and 123B can be different from the material compositions of the nanostructured core regions 121A and 123A, respectively. In some embodiments, the nanostructured shell regions 121B and 123B can include semiconductor materials having lattice constants different from the lattice constants of the semiconductor materials of the nanostructured core regions 121A and 123A, respectively. The lattice mismatch between the semiconductor materials of the nanostructured core regions 121A and 123A and the semiconductor materials of the nanostructured shell regions 121B and 123B can be configured to increase the charge carrier mobility in the core-shell nanostructured channel regions 121 and 123, respectively.

[0038] In some embodiments, for the n-type FETs 102A and / or 102B, the nanostructured shell regions 121B and 123B can include semiconductor materials having lattice constants greater than the lattice constants of the semiconductor materials of the nanostructured core regions 121A and 123A, respectively, to induce tensile strain in the resulting core-shell nanostructured channel regions 121 and 123, respectively, which can increase the electron mobility in the core-shell nanostructured channel regions 121 and 123. In some embodiments, for the p-type FETs 102A and / or 102B, the nanostructured shell regions 121B and 123B can include semiconductor materials having lattice constants less than the lattice constants of the semiconductor materials of the nanostructured core regions 121A and 123A, respectively, to induce compressive strain in the resulting core-shell nanostructured channel regions 121 and 123, respectively, which can increase the hole mobility in the core-shell nanostructured channel regions 121 and 123.

[0039] The nanostructured shell regions 121B and 123B can be configured to adjust the crystal orientation of their surface planes to increase the surface mobility of the charge carriers in the resulting core-shell nanostructured channel regions 121 and 123, respectively, thereby resulting in improved FET device performance. Thus, a higher carrier surface mobility can be achieved in the channel regions having the nanostructured shell regions 121B and 123B compared to the channel regions of FET devices without such nanostructured shell regions 121B and 123B. For example, in some embodiments, the hole mobility can be higher at the surface of a semiconductor material having a (111) crystal orientation, and the nanostructured shell regions 121B and 123B can be epitaxially grown to have surfaces having a (111) crystal orientation, which can form the surface planes of the core-shell nanostructured channel regions 121 and 123, respectively.

[0040] Referring to Figure 1B , although in Figure 1BA rectangular cross-section of the nanostructured core regions 121A and 123A is shown, but the nanostructured core regions 121A and 123A can have other geometries (e.g., circular, oval, or polygonal). Additionally, although a rhombic (also known as diamond-shaped) cross-section of the nanostructured shell regions 121B and 123B is shown in Figure 1B , the nanostructured shell regions 121B and 123B can have other geometries (e.g., rectangular, circular, oval, or polygonal). In some embodiments, the nanostructured core regions 121A and 123A can have cross-sections that are respectively similar to or different from the cross-sections of the nanostructured shell regions 121B and 123B.

[0041] Referring to Figures 1B to 1D , the respective vertical dimensions H 1 and H 2 (e.g., thickness or diameter) of the core-shell nanostructured channel regions 121 and 123 along the Z-axis can be in the range of about 5 nm to about 30 nm, while the respective horizontal dimensions W 1 and W 2 (e.g., width or diameter) along the Y-axis can be in the range of about 5 nm to about 50 nm. The ratio of H 1 / W 1 and H 2 / W 2 can be in the range of about 0.2 to about 5, respectively. The thickness of the nanostructured shell regions 121B and 123B surrounding the respective nanostructured core regions 121A and 123A can be in the range of about 0.5 nm to about 5 nm. In some embodiments, the distance between adjacent core-shell nanostructured channel regions 121 and 123 can respectively depend on the thickness of the gate dielectric layers 128A - 128B and can be in the range of about 5 nm to about 20 nm. Additionally, the core-shell nanostructured channel regions 121 and 123 can have respective horizontal dimensions L 1 ( Figure 1D ) and L 2 ( Figure 1C ) along the X-axis. The ratio of L 1 / H 1 and L 2 / H 2 can be in the range of about 2 to about 20. In some embodiments, the dimensions H 1 and H 2 , W 1 and W 2 as well as L 1 and L 2 can be respectively equal to or different from each other. In some embodiments, H 1 / W 1 and H 2 / W 2 and L 1 / H 1 and L 2 / H 2 The ratios of and can be equal to or different from each other. In some embodiments, the vertical dimensions H of the core - shell nanostructured channel regions 121 and 123 1 and H 2 can be equal to or greater than the vertical dimensions H along the Z - axis of the nanostructured regions 120A and 122A 3 and H 4 (e.g., thickness or diameter). In some embodiments, the horizontal dimensions L of the core - shell nanostructured channel regions 121 and 123 1 and L 2 can be equal to or less than the gate lengths GL of the gate structures 112A - 112B 1 and GL 2 .

[0042] Referring to Figures 1A to 1B , the passivation layers 109A - 109B can be respectively disposed on the sidewalls of the nanostructured regions 120A and 122A and on the sidewalls of the fin bases 119A - 119B. The passivation layer 109A can be disposed on the nanostructured region 120A, as Figure 1D shown. As Figure 1C shown, the passivation layer 109B is not disposed on the nanostructured region 122A because a portion of the passivation layer 109B is removed during the formation of the FET 102B as described below. The passivation layers 109A - 109B can improve the surface quality of the surfaces of the fin structures 108A - 108B covered by these passivation layers by reducing or eliminating the vacancies caused by the dangling bonds on these structures. The vacancies can trap charge carriers and reduce the drive current of the FETs 102A - 102B during their operation. Compared with FETs without passivation layers such as 109A - 109B, reducing or eliminating these vacancies can increase the drive current of the FETs 102A - 102B by about 20% to about 50%.

[0043] In some embodiments, the passivation layers 109A - 109B can be nitride, oxide, fluoride, chloride, and / or sulfide films. In some embodiments, the passivation layers 109A - 109B can include fluorine, chlorine, nitrogen, oxygen, hydrogen, deuterium, and / or sulfur atoms, which can bind to the dangling bonds to reduce or eliminate the vacancies on the above - mentioned surfaces of the fin structures 108A - 108B. The passivation layers 109A - 109B can be deposited substantially conformally on these surfaces of the fin structures 108A - 108B and can have a thickness in the range of about 0.5 nm to about 5 nm.

[0044] Referring to Figure 1A andFigures 1C to 1D , the epitaxial fin regions 110A can grow to wrap the nanostructured regions 120A that are not under the inner or outer spacers 113A - 114A. Similarly, the epitaxial fin region 110B can grow to wrap the nanostructured region 122A that is not under the inner or outer spacers 113B - 114B. In some embodiments, as Figures 1E to 1G shown, the epitaxial fin regions 110B - 110A can grow on the fin bases 119B - 119A instead of wrapping the nanostructured regions 122A and 120A respectively. The epitaxial fin regions 110A - 110B can include epitaxially grown semiconductor materials that are similar or different from each other. In some embodiments, the epitaxially grown semiconductor material can include the same material or a different material from that of the substrate 106. The epitaxial fin regions 110A - 110B can have a thickness in the range of about 3 nm to about 6 nm along the sidewalls of the corresponding nanostructured regions 120A and 122A respectively. Although a triangular cross - section of the epitaxial fin regions 110A - 110B is shown in Figures 1C to 1D , the epitaxial fin regions 110A - 110B can have cross - sections of other geometric shapes (e.g., rectangular, semi - circular, or polygonal).

[0045] The epitaxial fin regions 110A - 110B can be p - type for the p - type FETs 102A - 102B respectively, or n - type for the n - type NFETs 102A - 102B. In some embodiments, if the semiconductor device 100 is a CMOS device, the epitaxial fin regions 110A - 110B can be of opposite doping types relative to each other. The p - type epitaxial fin regions 110A - 110B can include SiGe, SiGeB, GeB, SiGeSnB, III - V group semiconductor compounds, or combinations thereof, and a dopant concentration in the range of about 1x10 20 atoms / cm 3 to about 1x10 21 atoms / cm 3 . In some embodiments, each p - type epitaxial fin region 110A - 110B can have multiple sub - regions (not shown), which can include SiGe and can be different from each other based on, for example, doping concentration, epitaxial growth process conditions, and / or the relative concentration of Ge relative to Si. Each sub - region can have a thickness that is similar or different from each other, and the thickness can be in the range of about 0.5 nm to about 5 nm. In some embodiments, the atomic percentage of Ge in the first sub - region can be less than the atomic percentage of Ge in the second sub - region. In some embodiments, the first sub - region can include Ge in the range of about 15 atomic percent to about 35 atomic percent, while the second sub - region can include Ge in the range of about 25 atomic percent to about 50 atomic percent, and any remaining atomic percentage in the sub - region is Si.

[0046] According to some embodiments, multiple sub-regions of the p-type epitaxial fin regions 110A-110B may have varying p-type dopant concentrations relative to each other. For example, the first sub-region may be undoped or may have a dopant concentration lower than the dopant concentration (e.g., the dopant concentration is in the range of about 1x10 20 to about 3x10 22 atoms / cm 3 ), e.g., the dopant concentration is less than about 8x10 20 atoms / cm 3 ).

[0047] In some embodiments, the n-type epitaxial fin regions 110A-110B may have multiple n-type sub-regions (not shown). The first n-type sub-region may have the following materials: SiAs, SiC, or SiCP; the dopant concentration ranges from about 1x10 20 atoms / cm 3 to about 1x10 21 atoms / cm 3 and the thickness is between about 1 nm and about 3 nm. The second n-type sub-region disposed on the first n-type sub-region may have SiP and a dopant concentration in the range of about 1×10 20 atoms / cm 3 to about 1×10 22 atoms / cm 3 The third n-type sub-region disposed on the second n-type sub-region may have a material with a material composition and thickness similar to those of the first n-type sub-region.

[0048] The epitaxial fin regions 110A-110B and the nanostructured regions 120A and 122A thereunder may form source / drain (S / D) regions 126A-126B, respectively. The core-shell nanostructured channel regions 121 and 123 may be inserted between a pair of S / D regions 126A-126B, respectively, as Figures 1C to 1D shown.

[0049] The gate structures 112A - 112B can be multi - layer structures and can respectively wrap the core - shell nanostructured channel regions 121 and 123. For them, the gate structures 112A - 112B can be referred to as gate - all - around (GAA) structures or horizontal gate - all - around (HGAA) structures, and the FETs 102A - 102B can be called GAA FETs 102A - 102B. The spacing 111 between the gate structures 112A - 112B is not drawn to scale, and the gate structures 112A - 112B can be separated from each other by any distance. In some embodiments, similar to the gate structures 112A - 112B, the FETs 102A - 102B can have a common gate structure that wraps the core - shell nanostructured channel regions 121 and 123.

[0050] The gate structures 112A - 112B can respectively include a gate dielectric layer 128A - 128B, a gate work - function metal layer 130A - 130B, and a gate metal fill layer 132A - 132B. As Figure 1B shown, the gate dielectric layer 128A can wrap each core - shell nanostructured channel region 121, thereby electrically isolating the core - shell nanostructured channel regions 121 from each other and from the conductive gate work - function metal layer 130A and the gate electrically. The metal fill layer 132A prevents a short - circuit between the gate structure 112A and the S / D region 126A during the operation of the FET 102A. Similarly, the gate dielectric layer 128B can wrap each core - shell nanostructured channel region 123 and electrically isolate the core - shell nanostructured channel regions 123 from each other and from the conductive gate work - function metal layer 130B and the gate metal fill layer 132B to prevent a short - circuit between the gate structure 112B and the S / D region 126 during the operation of the FET 102B. Although Figure 1B the distance between the adjacent core - shell nanostructured channel regions 121 and 123 is shown to be wide enough for the gate dielectric layers 128A - 128B and the gate work - function layers 130A - 130B to respectively wrap each core - shell nanostructured channel region 121 and 123, these distances can be wider to allow the gate metal fill layers 132A - 132B to respectively wrap each core - shell nanostructured channel region 121 and 123.

[0051] The thickness of each gate dielectric layer 128A - 128B can be in the range of about 1 nm to about 5 nm and can include (i) a silicon oxide, silicon nitride, and / or silicon oxynitride layer, (ii) a high - k dielectric material such as hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 3 ), hafnium silicate (HfSiO4 ), zirconium oxide (ZrO 2 ), zirconium silicate (ZrSiO 2 ), (iii) a high-k dielectric material having an oxide of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) or lutetium (Lu), or (iv) a combination thereof.

[0052] The gate work function metal layers 130A - 130B may include a single metal layer or a stack of metal layers. The stack of metal layers may include metals having work function values that are equal to or different from each other. In some embodiments, each of the gate work function metal layers 130A - 130B may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), metal alloys, and / or combinations thereof. In some embodiments, each of the gate work function layers 130 may include Al-doped metals, such as Al-doped Ti, Al-doped TiN, Al-doped Ta, or Al-doped TaN. In some embodiments, each of the gate work function layers 130 may have a thickness in the range of about 2 nm to about 15 nm.

[0053] In some embodiments, a gate barrier layer (not shown) may be disposed between the gate dielectric layers 128A - 128B and the gate work function metal layers 130A - 130B, respectively. The gate barrier layer may serve as a nucleation layer for subsequently forming the gate work function layers 130A - 130B, and / or may help prevent significant diffusion of metal (e.g., Al) from the gate work function layers 130A - 130B to the underlying layers (e.g., the gate dielectric layers 128A - 128B). The gate barrier layer may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other suitable diffusion barrier materials. In some embodiments, the gate barrier layer may include a substantially fluorine-free metal or metal-containing film. The substantially fluorine-free metal or fluorine-free metal-containing film may include less than 5 atomic percent of fluorine contaminants in ionic, atomic, and / or molecular form. In some embodiments, the thickness of the gate barrier layer may be in the range of about 1 nm to about 10 nm.

[0054] Each gate metal fill layer 132A - 132B may include a single metal layer or a stack of metal layers. The stack of metal layers may include metals different from each other. In some embodiments, each gate metal fill layer 132A - 132B may include a suitable conductive material such as Ti, silver (Ag), Al, titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), Zr, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys, and / or combinations thereof. Although the gate structures 112A - 112B are shown as being similar, the FETs 102A - 102B may have gate structures with different materials and / or electrical characteristics (e.g., threshold voltage, work function value) from each other. Moreover, although the shown gate structures 112A - 112B have a GAA structure, other gate structures (e.g., vertical GAA structures or gate structures without a GAA structure) are also within the scope and spirit of the present disclosure.

[0055] Referring Figures 1C to 1D , each internal spacer 113A may be disposed between a sub-region 110As of the epitaxial region 110A and a sub-region 112As of the gate structure 112A, and each internal spacer 113B may be disposed between a sub-region 110Bs of the epitaxial region 110B and a sub-region 112Bs of the gate structure 112B. Each of the internal spacers 113A - 113B may respectively prevent capacitive coupling between the sub-regions 110As and 112As and between the sub-regions 110Bs and 112Bs. Preventing capacitive coupling between these sub-regions may reduce the parasitic capacitance between the S / D regions 126A - 126B and the gate structures 112A - 112B and improve the device performance of the FETs 102A - 102B.

[0056] In some embodiments, the internal spacers 113A - 113B may include a low-k dielectric material having a dielectric constant less than about 3.9 and / or between about 1 and about 3.5. In some embodiments, the low-k dielectric material may include silicon, oxygen, carbon, and / or nitrogen. The concentrations of silicon, oxygen, carbon, and nitrogen in the low-k dielectric material for the internal spacers 113A - 113B may depend on the desired dielectric constant of the internal spacers 113A - 113B. Variations in the concentrations of silicon, oxygen, carbon, and nitrogen in the low-k dielectric material may change the desired dielectric constant. The low-k dielectric material may include silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), polyamide, carbon-doped oxide, fluorine-doped oxide, hydrogen-doped oxide, or combinations thereof.

[0057] In some embodiments, the internal spacers 113A - 113B may include a low-k dielectric gas having a dielectric constant less than about 3.9 and / or between about 0.5 and about 3.5. The low-k dielectric gas may include air, nitrogen, helium, argon, hydrogen, or other suitable dielectric gases. In some embodiments, the internal spacers 113A - 113B may be in the form of air gaps between sub-regions 110As and 112As and between sub-regions 110Bs and 112Bs, respectively. In some embodiments, the internal spacers 113A - 113B may have materials that are similar or different from each other. In some embodiments, both FETs 102A - 102B may have internal spacers, such as internal spacers 113A - 113B, or one of the FETs 102A - 102B may have an internal spacer, such as internal spacer 113A or 113B. Although Figures 1C to 1D a rectangular cross-section of the internal spacers 113A - 113B is shown in, the internal spacers 113A - 113B may have cross-sections of other geometries (e.g., semi-circular, triangular, or polygonal). In some embodiments, each internal spacer 113A - 113B may have a horizontal dimension (e.g., thickness) in the range of about 3 nm to about 15 nm along the X-axis.

[0058] According to some embodiments, the external spacers 114A - 114B may be disposed on the sidewalls of the respective gate structures 112A - 112B and in physical contact with the respective gate dielectric layers 128A - 128B. The external spacers 114A - 114B may include an insulating material such as silicon oxide, silicon nitride, silicon carbonitride (SiCN), silicon oxynitride (SiOCN), a low-k material, or a combination thereof. The external spacers 114A - 114B may have a low-k material having a dielectric constant less than about 3.9 and / or between about 1 and about 3.5. In some embodiments, each external spacer 114A - 114B may have a thickness in the range of about 2 nm to about 10 nm. In some embodiments, the horizontal distance between the external spacers 114A along the X-axis is greater than the horizontal distance between the internal spacers 113A along the X-axis. Similarly, the horizontal distance between the external spacers 114B along the X-axis is greater than the horizontal distance between the internal spacers 113B along the X-axis.

[0059] The FETs 102A - 102B may be incorporated into an integrated circuit by using other structural components such as gate contact structures, S / D contact structures, conductive vias, wires, interconnect metal layers, etc., which are not shown here for clarity.

[0060] Referring to Figures 1A to 1D, the semiconductor device 100 may further include an etch stop layer (ESL) 116, an interlayer dielectric (ILD) layer 118, and a shallow trench isolation (STI) region 138. The ESL 116 may be disposed on the sidewalls of the outer spacers 114A - 114B and on the epitaxial regions 110A - 110B. The ESL 116 may be configured to protect the gate structures 112A - 112B and / or the S / D regions 126A - 126B. For example, such protection may be provided during the formation of the ILD layer 118 and / or the S / D contact structure (not shown). In some embodiments, the ESL 116 may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN), or a combination thereof. In some embodiments, the ESL 116 may have a thickness in the range of about 3 nm to about 30 nm.

[0061] The ILD layer 118 may be disposed on the ESL 116 and may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable carbon oxide silicon). In some embodiments, the dielectric material is silicon oxide. In some embodiments, the thickness of the ILD layer 118 may be in the range of about 50 nm to about 200 nm.

[0062] The STI region 138 may be configured to provide electrical isolation between the FETs 102A - 102B and adjacent FETs (not shown) on the substrate 106 and / or adjacent active and passive components (not shown) integrated with or deposited on the substrate 106. In an embodiment, the STI region 138 may include multiple layers, such as a nitride layer and / or an oxide layer 138A and an insulating layer 138B disposed on the nitride and / or oxide layer 138A. In some embodiments, the nitride and / or oxide layer 138A may prevent oxidation of the sidewalls of the fin tops 108A2 - 108B2 during the formation of the STI region 138. In some embodiments, the insulating layer 138B may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the STI region 138 may have a vertical dimension in the range of about 40 nm to about 200 nm along the Z-axis.

[0063] The cross-sectional shapes of the semiconductor device 100 and its elements (eg, fin structures 108A- 108B, gate structures 112A- 112B, epitaxial fin regions 110A- 110B, inner spacers 113 - 113B, outer spacers 114A- 114B, and / or STI regions 138 ) are exemplary and are not intended to be limiting.

[0064] Figures 2A to 2D Shown with Figure 1B The core-shell nanostructured channel regions 121 and 123 are shown in different configurations along Figure 1A BB is a cross-sectional view of FET 102A-102B. In some embodiments, instead of Figure 1B FETs 102A-102B shown in FIG. 1 , the semiconductor device 100 may have Figures 2A to 2B FETs 102A-102B are shown, wherein each of FETs 102A-102B has a core-shell nanostructured channel region 121-123. In some embodiments, instead of Figure 1B FETs 102A-102B shown in FIG. 1 , the semiconductor device 100 may have a Figure 2C FETs 102A-102B are shown in FIG, wherein FET 102A has a core-shell nanostructured channel region 121, and FET 102B has a channel region of a stack of nanostructured regions 120B and 122B arranged in an alternating configuration. Figure 1B FETs 102A-102B shown in FIG. 1 , the semiconductor device 100 may have a Figure 2D FETs 102A-102B are shown in FIG, wherein FET 102B has a core-shell nanostructured channel region 123, while FET 102A has a channel region of a stack of nanostructured regions 120B and 122B arranged in an alternating configuration. The material composition of the nanostructured regions 120B and 122B can be similar to the material composition of the first semiconductor layer 120 and the second semiconductor layer 122, respectively.

[0065] Figure 3 1 is a flow chart of an exemplary method 300 for manufacturing a semiconductor device 100 according to some embodiments. For purposes of illustration, reference will be made to a method for manufacturing a semiconductor device 100. Figures 4A to 23A , Figures 4B to 23B , Figures 9C to 23C as well as Figures 9D to 23D An exemplary manufacturing process of the semiconductor device 300 is described in Figure 3 The operations shown in . Figures 4A to 23A are isometric views of semiconductor device 100 at various stages of its fabrication. Figures 4B to 23B , Figures 9C to 23C as well as Figures 9D to 23DCross-sectional views taken along lines B-B, C-C, and D-D of the structure of Figures 4A to 23A according to some embodiments. Depending on the particular application, operations may be implemented in a different order or not implemented at all. It should be noted that method 300 may not produce a complete semiconductor device 100. Accordingly, it should be understood that additional processes may be provided before, during, and after method 300, and some other processes may only be briefly described herein. The above describes the elements of Figures 4A to 23A , Figures 4B to 23B , Figures 9C to 23C , and Figures 9D to 23D that have the same reference numerals as the elements in Figures 1A to 1D and Figures 1A to 1D .

[0066] In operation 305, a fin structure is formed on a substrate. For example, a fin structure 108A*-108B* (shown in Figures 5A to 5B ) having a fin base 119A-119B and a stack of a first semiconductor layer 120 and a second semiconductor layer 122 arranged in an alternating configuration may be formed on a substrate 106, as described with reference to Figures 4A to 5B . In a subsequent process, after removing the second semiconductor layer 122 and the first semiconductor layer 120 from the fin structure 108A*-108B*, respectively, the fin structure 108A*-108B* may form a fin structure 108A-108B (as shown in Figures 1A to 1D ). The process for forming the fin structure 108A*-108B* may include forming a stack layer 108* on the substrate 106, as shown in Figures 4A to 4B . The stack layer 108* may include a first semiconductor layer 120* and a second semiconductor layer 122* stacked in an alternating configuration. The first semiconductor layer 120* and the second semiconductor layer 122* may have respective vertical dimensions H and H in the range of about 5 nm to about 30 nm along the Z-axis. 1 and H 2 .

[0067] ​​​​​​​​​​​​​​​​​​​​​​Each of the first semiconductor layer 120* and the second semiconductor layer 122* may be epitaxially grown on the underlying layer and may include semiconductor materials different from each other. In some embodiments, the first semiconductor layer 120* and the second semiconductor layer 122* may include semiconductor materials having different oxidation rates and / or etching selectivities from each other. In some embodiments, the first semiconductor layer 120* and the second semiconductor layer 122* may include semiconductor materials similar to or different from the substrate 106. The first semiconductor layer 120* and the second semiconductor layer 122* may include (i) elemental semiconductors such as silicon or germanium; (ii) compound semiconductors including group III-V semiconductor materials; (iii) alloy semiconductors including SiGe, germanium tin, or silicon germanium tin; or (iv) combinations thereof. In some embodiments, the first semiconductor layer 120* may include Si, and the second semiconductor layer 122* may include SiGe. In some embodiments, the first semiconductor layer 120* and the second semiconductor layer 122* may include SiGe having about 25 atomic percent to about 50 atomic percent of Ge, where any remaining atomic percent is Si, or may include Si without any substantial amount of Ge (e.g., no Ge).

[0068] The first semiconductor layer 120* and / or the second semiconductor layer 122* may be undoped or may be in-situ doped during their epitaxial growth process using (i) p-type dopants such as boron, indium, or gallium and / or (ii) n-type dopants such as phosphorus or arsenic. For p-type in-situ doping, p-type dopant precursors such as diborane (B 2 H 6 ), boron trifluoride (BF 3 ), and / or other p-type dopant precursors may be used. For n-type in-situ doping, n-type dopant precursors such as phosphine (PH 3 ), arsine (AsH 3 ), and / or other n-type dopant precursors may be used.

[0069] The process for forming the fin structures 108A*-108B* may further include etching the structure formed by forming a patterned hard mask layer (not shown) on the stacked layer 108*. Figure 4A In some embodiments, the hard mask layer may include, for example, a silicon oxide layer formed using a thermal oxidation process and / or a silicon nitride layer formed using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced CVD (PECVD). Figure 4A The etching of the structure may include dry etching, wet etching processes, or a combination thereof. Figure 4A The dry etching process may include using an etchant having: an oxygen-containing gas, a fluorine-containing gas (e.g., CF

[0070] The dry etching process may include using an etchant having: an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4, SF 6 , CH 2 F 2 , CHF 3 , NF 3 and / or C 2 F 6 ), chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , HCl and / or BCl 3 ), bromine-containing gas (e.g., HBr and / or CHBR 3 ), ammonia (NH 3 ), iodine-containing gas, other suitable etching gases and / or plasmas, or combinations thereof. The dry etching process can be performed at a high bias voltage of about 150 V to about 350 V, at a radio frequency power of about 10 W to about 50 W, at a pressure of about 5 Torr to about 50 Torr, and at a temperature in the range of about 25 °C to about 40 °C for a duration in the range of about 10 sec to 40 sec.

[0071] The wet etching process can include etching in diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia (NH 3 ), hydrofluoric acid (HF)-containing, nitric acid (HNO 3 ), acetic acid (CH 3 COOH)-containing solution, or combinations thereof.

[0072] As shown, after etching the stack layer 108*, a fin structure 108A*-108B* with fin bases 119A-119B can be formed. The fin bases 119A-119B have a vertical dimension in the range of about 40 nm to 60 nm along the Z-axis, as Figures 5A to 5B shown. The stack of the first semiconductor layer 120 and the second semiconductor layer 122 formed on the fin bases 119A-119B can have corresponding vertical dimensions H 3 and H 4 along the Z-axis in the range of about 5 nm to about 30 nm, and corresponding horizontal dimensions W 3 and W 4 in the range of about 5 nm to about 50 nm along the Y direction. Each of the ratios of H 1 / W 1 and H 2 / W 2 can be in the range from about 0.2 to about 5. In some embodiments, the dimensions H 3 -H 4 and W 3 -W 4 can be equal to or different from each other respectively. In some embodiments, H 1 / W 1 and H 2 / W 2 The ratios of can be equal to or different from each other, respectively.

[0073] Referring Figure 3 , in operation 310, a passivation layer is formed on the fin structure. For example, passivation layers 109A - 109B can be formed on fin structures 108A* - 108B*, respectively, as referred to Figures 6A to 6B above. The process for forming passivation layers 109A - 109B on fin structures 108A* - 108B* can include using one or more precursor gases having fluorine, chlorine, nitrogen, oxygen, hydrogen, deuterium, NH 3 and / or hydrogen sulfide (H 2 S) to blanket deposit passivation layer 109 on the Figure 5A structure by ALD or CVD process. During the blanket deposition process, the flow rate of one or more precursor gases can be in the range of about 10 sccm to about 1500 sccm. The blanket deposition process can be carried out for a duration in the range of about 10 seconds to about 120 minutes at a pressure of about 10 Torr to about 20 atmospheres and at a temperature of about 100 °C to about 300 °C. The portions of the passivation layer 109 blanket deposited on fin structures 108A* - 108B* can be referred to as passivation layers 109A - 109B, respectively.

[0074] Referring Figure 3 , in operation 315, an STI region is formed on the passivation layer. For example, STI region 138 can be formed on passivation layers 109A - 109B, as referred to Figures 7A to 7B above. The formation of STI region 138 can include (i) depositing a nitride material layer (not shown) on the Figure 6A structure, (ii) depositing a layer of oxide material on the nitride material layer (not shown), (iii) depositing an insulating material layer (not shown) on the oxide material layer, (iv) annealing the insulating material layer, (v) chemically mechanical polishing (CMP) the nitride and oxide material layers and the annealed insulating material layer, and (vi) etching back the polished structure to form Figure 7A the STI region 138 of.

[0075] Suitable methods for depositing oxide and nitride materials such as ALD or CVD can be used to deposit the nitride and oxide material layers. In some embodiments, the insulating material layer can include silicon oxide, silicon nitride, silicon oxynitride, fluorine - doped silicate glass (FSG), or a low - k dielectric material. In some embodiments, the insulating material layer can be deposited using a CVD process, a high - density plasma (HDP) CVD process, using silane (SiH 4 ) and oxygen (O 2) Deposited as a reaction precursor. In some embodiments, a sub-atmospheric CVD (SACVD) process or a high aspect ratio process (HARP) can be used to form the insulating material layer, where the process gas can include tetraethyl orthosilicate (TEOS) and / or ozone (O 3 ).

[0076] In some embodiments, the insulating material layer can be formed by depositing flowable silica using a flowable CVD (FCVD) process. A wet annealing process can follow the FCVD process. The wet annealing process can include annealing the deposited layer of the insulating material in steam at a temperature in the range of about 200 °C to about 700 °C for a duration in the range of about 30 minutes to about 120 minutes. A CMP process can follow the wet annealing process to remove portions of the nitride, oxide, and insulating material layers so that the top surfaces of the nitride, oxide, and insulating material layers are substantially coplanar with the top surfaces of the fin structures 108A*-108B*. An etching process can follow the CMP process to etch back the nitride, oxide, and insulating material layers to form Figure 7A the STI region 138.

[0077] The etch back of the nitride, oxide, and insulating material layers can be implemented by a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the dry etching process can include using a plasma dry etching with octafluorocyclobutane (C 4 F 8 ), argon (Ar), oxygen (O 2 ), and helium (He), fluoroform (CHF 3 ), and helium, carbon tetrafluoride (CF 4 ), difluoromethane (CH 2 F 2 ), chlorine (Cl 2 ), and O 2 , hydrogen bromide (HBr), O 2 , and He, or a combination thereof, at a pressure in the range of about 1 mTorr to about 5 mTorr. In some embodiments, the wet etching process can include using a diluted hydrofluoric acid (DHF) treatment, an ammonium peroxide mixture (APM), a sulfur peroxide mixture (SPM), hot deionized water (DI water), or a combination thereof. In some embodiments, the wet etching process can include using ammonia (NH 3 ) and hydrofluoric acid (HF) as etchants and an inert gas, such as Ar, xenon (Xe), He, or a combination thereof. In some embodiments, the HF and NH used in the wet etching process 3The flow rates can be in the range of about 10 sccm to about 100 sccm, respectively. In some embodiments, the wet etching process can be carried out at a pressure of about 5 mTorr to about 100 mTorr and a high temperature of about 50 °C to about 120 °C.

[0078] Referring Figure 3 , in operation 320, a protective oxide layer is formed on the passivation layer, and a polysilicon structure is formed on the protective oxide layer and the STI region. For example, the protective oxide layers 740A - 740B can be formed on the corresponding passivation layers 109A - 109B, and the polysilicon structures 112A* - 112B* can be formed on the corresponding protective oxide layers 740A - 740B and the STI regions 138, as referring Figures 7A to 7B as described.

[0079] The process for forming the protective oxide layers 740A - 740B can include blanket depositing a layer of oxide material (not shown) on the Figure 6A structure, followed by a high-temperature annealing process and an etching process. The oxide material layer can include silicon oxide and can be blanket deposited using a suitable deposition process such as CVD, ALD, plasma-enhanced ALD (PEALD), physical vapor deposition (PVD), or electron beam evaporation. In some embodiments, the oxide material layer can be blanket deposited using PEALD at an energy in the range of about 400 W to about 500 W and a temperature in the range of about 300 °C to about 500 °C. After the blanket deposition of the oxide material layer, there can be a dry annealing process at a temperature in the range of about 800 °C to about 1050 °C under an oxygen flow. The oxygen precursor concentration can be in the range of about 0.5% to about 5% of the total gas flow rate. In some embodiments, the annealing process can be a rapid process, where the annealing time can be between about 0.5 s and about 5 s. The etching process for forming the protective oxide layers 740A - 740B can not follow the annealing process and can be performed during the formation of the polysilicon structures 112A* - 112B* described below, or can be performed as a separate etching process after the formation of the polysilicon structures 112A* - 112B*.

[0080] After the annealing of the blanket deposited layer of the oxide material of the protective oxide layers 740A - 740B, there can be the formation of the polysilicon structures 112A* - 112B*, as Figures 7A to 7BAs shown. During subsequent processing, the polysilicon structures 112A*-112B* can be replaced in a gate replacement process to form gate structures 112A-112B, respectively. In some embodiments, the process for forming the polysilicon structures 112A*-112B* can include blanket depositing a layer of polysilicon material on an annealed layer of oxidation material for protecting the oxide layers 740A-740B, and etching the blanket-deposited polysilicon material layer through a patterned hard mask layer 742A-742B formed on the polysilicon material layer. In some embodiments, the polysilicon material may not be doped, and the hard mask layers 742A-742B can include oxide layers and / or nitride layers. The oxide layers can be formed using a thermal oxidation process, and the nitride layers can be formed by LPCVD or PECVD. The hard mask layers 742A-742B can protect the polysilicon structures 112A*-112B* from the effects of subsequent processing steps (e.g., during the formation of the inner spacers 113A-113B, outer spacers 114A-114B, epitaxial fin regions 110A-110B, ILD layer 118, and / or ESL 116).

[0081] The blanket deposition of the polysilicon material layer can include CVD, PVD, ALD, or other suitable deposition processes. In some embodiments, the etching of the blanket-deposited polysilicon material layer can include a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching of the blanket-deposited polysilicon material layer can include four etching steps. The first polysilicon etching step can include using a gas mixture having hydrogen bromide (HBr), oxygen (O 2 ), trifluoromethane (CHF 3 ), and chlorine (Cl 2 ). The second polysilicon etching step can include using a gas mixture having HBr, O 2 , Cl 2 , and nitrogen (N 2 ) at a pressure of about 45 mTorr to about 60 mTorr. The third polysilicon etching step can include using a gas mixture having HBr, O 2 , Cl 2 , N 2 , and argon (Ar) at a pressure of about 45 mTorr to about 60 mTorr. The fourth polysilicon etching step can include using a gas mixture having HBr, O 2 , Cl 2 , and N 2A gas mixture. According to some embodiments, together with the polysilicon material, the fourth polysilicon etch step can remove the portion of the annealed blanket deposition layer of the oxide material that protects the oxide layers 740A - 740B and is not covered by the polysilicon structures 112A* - 112B*. The first polysilicon etch step can have a higher polysilicon etch rate than the second, third, and / or fourth polysilicon etch steps. The first polysilicon etch step can be used to etch the undesired portion of the blanket-deposited polysilicon material layer above the fin structures 108A* - 108B*. The second, third, and fourth polysilicon etch steps can be used to etch the undesired portion of the blanket-deposited polysilicon material layer within the high aspect ratio spacer 743.

[0082] In some embodiments, the vertical dimension of the polysilicon structures 112A* - 112B* along the Z-axis on the top surface of the fin structures 108A* - 108B* can be in the range of about 40 nm to about 60 nm. The aspect ratio of the polysilicon structures 112A* - 112B* can be equal to or greater than about 9, where the aspect ratio is the ratio of the vertical dimension of the polysilicon structures 112A* - 112B* along the Z-axis to the horizontal dimension along the Y-axis. In some embodiments, the horizontal dimension (e.g., the spacing) along the Y-axis between the centerlines of adjacent polysilicon structures 112A* - 112B* can be in the range of about 30 nm to about 70 nm.

[0083] After forming the polysilicon structures 112A* - 112B*, the portion of the blanket-deposited oxide layer that is not covered by the polysilicon structures 112A* - 112B* can be removed by a dry or wet etch process, if they were not removed during the formation of Figures 7A to 7B the fourth polysilicon structures 112A* - 112B* of the structure being formed. Figures 7A to 7B The structure has polysilicon structures 112A* - 112B* and protective oxide layers 740A - 740B disposed on the stacks of the nanostructured regions 120B and 122B ( Figure 7B ), respectively, and has stacks of nanostructured regions 120A and 122A ( Figure 7A ) extending from both sides of the polysilicon structures 112A* - 112B* along the X-axis.

[0084] In some embodiments, the protective oxide layers 740A - 740B may have a vertical dimension along the Z - axis (e.g., the thickness on the top surface of the fin structures 108A* - 108B*) and a horizontal dimension in the range of about 1 nm to about 3 nm along the Y - axis (e.g., the thickness on the sidewalls of the fin structures 108A* - 108B*). In some embodiments, the vertical dimension may be equal to or greater than the horizontal dimension. The presence of the protective oxide layers 740A - 740B allows the etching of polysilicon material from the high aspect - ratio spacer 743 (e.g., aspect ratio greater than 1:15, 1:18, or 1:20) during the formation of the polysilicon structures 112A* - 112B*, with substantially no etching and / or damage to the fin structures 108A* - 108B*.

[0085] Referring Figure 3 , in operation 325, external spacers are formed on the sidewalls of the polysilicon structure and on the passivation layer. For example, the external spacers 114A - 114B may be formed on the sidewalls of the polysilicon structures 112A* - 112B* and on the portions of the passivation layers 109A - 109B not covered by the polysilicon structures 112A* - 112B*, as described with reference to Figures 8A to 8B . The process of forming the external spacers 114A - 114B may include blanket - depositing a layer of insulating material (e.g., an oxide or nitride material) on the Figure 7A structure by a CVD, PVD, or ALD process, followed by photolithography and etching processes (e.g., reactive ion etching or other dry - etching processes using a chlorine - or fluorine - based etchant).

[0086] Referring Figure 3 , in operation 330, internal spacers and epitaxial fin regions are formed on the fin structures. For example, the internal spacers 113A - 113B and the epitaxial fin regions 110A - 110B may be formed on the portions of the fin structures 108A* - 108B* (e.g., nanostructured regions 120A and 122B, respectively) that are not under the polysilicon structures 112A* - 112B*, as described with reference to Figures 9A to 13D . Figures 9A to 13D The process steps shown describe the sequential formation of the internal spacers 113A - 113B and the sequential formation of the epitaxial regions 110A - 110B for FETs 102A - 102B having different conductivities from each other. For example, FET 102A may be n - type while FET 102B may be p - type. Before forming the internal spacer 113A and the epitaxial region 110A of FET 102A, FET 102A may be protected by patterning a photoresist layer 946 on FET 102B, as shown in Figures 9B to 9C . For clarity, the photoresist layer 946 is not shown in Figures 9A to 12A .

[0087] The process for forming the internal spacer 113A of the FET 102A can include etching portions of the outer spacer 114 extending along the X-axis from either side of the polysilicon structure 112A* from the stack of nanostructured regions 120A and 122A. The etching process can include a dry etching process using an etchant gas such as CH 4 、O 2 and CH 3 F. The flow rate ratio of CH 4 :O 2 :CH 3 F can be in the range of about 1:1:1 to about 1:2:4. The etching process can be implemented at a high bias voltage of about 300V to about 450V.

[0088] The process for forming the internal spacer 113A can further include etching the nanostructured region 122A from the stack of nanostructured regions 120A and 122A after etching the outer spacer 114A. In some embodiments, the nanostructured regions 120A and 122A can each include Si without any substantial amount of Ge and SiGe (e.g., no Ge and SiGe respectively), and the etching of the nanostructured region 122A can include a dry etching process that has a higher etching selectivity for SiGe than for Si. For example, a halogen-based chemical can exhibit a higher etching selectivity for Ge than for Si. Thus, the halogen gas can etch SiGe faster than Si. In some embodiments, the halogen-based chemical can include a fluorine-based and / or chlorine-based gas. Optionally, the etching of the nanostructured region 122A can include a wet etching process that has a higher etching selectivity for SiGe than for Si. For example, the wet etching process can include using a mixture of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 )(SPM) and / or a mixture of ammonium hydroxide (NH 4 OH) with H 2 O 2 and deionized (DI) water (APM).

[0089] Due to the etching of the nanostructured region 122A, suspended nanostructured regions 120A can be formed with an opening 1048 therebetween, as Figure 10A and Figure 10D shown. Moreover, the etching of the nanostructured region 122A can produce a linear etch profile 122Bs 1 or a curved etch profile 122Bs 2(shown in dashed lines). The etching process can be controlled such that the opening 1048 extends at least along the X-axis under the external spacer 114A, and the sidewalls of the nanostructured region 122B are substantially aligned with the interface 114As between the external spacer 114A and the polysilicon structure 112A*, as Figure 10D shown. In some embodiments, the opening 1048 can further extend along the X-axis under the polysilicon structure 112A*, such that the sidewalls of the nanostructured region 122B are disposed at about 1 nm to about 10 nm from the interface 114As. Extending the opening 1048 under the external spacer 114A or the polysilicon structure 112A* can prevent portions of the nanostructured region 122B from remaining under the external spacer 114A or prevent the formation of the gate structure 112A under the external spacer 114A during subsequent processes (e.g., in operation 340) when replacing the nanostructured region 122B and the polysilicon structure 112A* with the gate structure 112A.

[0090] The process for forming the internal spacer 113A can further include blanket depositing a low-k dielectric material layer (not shown) on the Figure 10A structure until the opening 1048 is filled or partially filled with the low-k dielectric material layer. The blanket deposition process can include using an ALD process or a CVD process. In some embodiments, the blanket deposition process can include multiple deposition and etching process cycles. In each cycle, the etching process can follow the deposition process to prevent voids from forming in the low-k dielectric material layer deposited in the opening 1048 by removing seams that may form during filling the opening 1048 with the low-k dielectric material layer. The etching process in each cycle of the blanket layer deposition process can include a dry etching process using a gas mixture of HF and NF 3 The gas ratio of HF to NF 3 can be in the range of about 1 to about 20. In some embodiments, the low-k dielectric material can include silicon, oxygen, carbon, and / or nitrogen. The low-k dielectric material can include silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), polyamide, carbon-doped oxide, fluorine-doped oxide, hydrogen-doped oxide, or a combination thereof.

[0091] The process for forming the internal spacer 113A can further include etching the blanket-deposited low-k dielectric material layer to etch back the low-k dielectric material layer within the opening 1048 to form the internal spacer 113A and remove other portions of the low-k dielectric material layer from the surface of the FET 102A, as Figure 11A and Figure 11D shown. The etching of the blanket-deposited low-k dielectric material layer can include a dry etching process using a gas mixture of HF and NF 3 The gas ratio of HF to NF 3The gas ratio can be in the range of about 1 to about 20. In some embodiments, the etching can be performed in two etching steps. In the first etching step, the gas ratio of HF to NF 3 can be in the range of about 1 to about 10. The first etching step can remove a portion of the low-k material layer from the surface of the FET 102A and partially etch back the low-k material layer within the opening 1048. In the second etching step, the gas ratio of HF to NF 3 is higher than that in the first etching step and can be in the range of about 5 to about 20. The second etching step can achieve the structure of the inner spacer 113A as shown in Figure 11D . In some embodiments, the interface 113As between the inner spacer 113A and the nanostructured region 122B follows the etching profile of the sidewall of the nanostructured region 122B. For example, when the sidewall of the nanostructured region 122B has a linear etching profile 122Bs 1 ( Figure 10D ), the interface 113As can have a linear profile as shown in Figure 11D , or when the sidewall of the nanostructured region 122B has a curved etching profile 122Bs 2 ( Figure 10D and Figure 11D ), the interface 113As can have a curved profile (not shown).

[0092] Referring to Figures 12A to 12D , after forming the inner spacer 113A, an epitaxial fin region 110A can be grown around the suspended nanostructured region 120A. In some embodiments, the epitaxial fin region 110A can be grown by (i) CVD, such as low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), or any suitable CVD; (ii) molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination thereof. In some embodiments, the epitaxial fin region 110A can be grown by an epitaxial deposition / partial etching process that repeats the epitaxial deposition / partial etching process at least once. In some embodiments, when the nanostructured region 120A includes SiGe, the epitaxial fin region 110A can be p-type, or when the nanostructured region 120A includes Si without any substantial amount of Ge (e.g., no Ge), the epitaxial fin region 110A can be n-type. The p-type epitaxial fin region 110A can include SiGe and can be in-situ doped with a p-type dopant such as boron, indium, or gallium during the epitaxial growth process. For p-type in-situ doping, p-type dopant precursors such as, but not limited to, diborane (B 2 H 6 ), boron trifluoride (BF3 ), and / or other p-type doping precursors. The n-type epitaxial fin region 110A may include Si without any substantial amount of Ge (e.g., no Ge), and may be in-situ doped with an n-type dopant such as phosphorus or arsenic during an epitaxial growth process. For n-type in-situ doping, n-type doping precursors such as, but not limited to, phosphine (PH 3 ), arsine (AsH 3 ), and / or other n-type doping precursors.

[0093] In some embodiments, as Figure 12A and Figure 12D shown, instead of forming the epitaxial fin region 110A around the suspended nanostructured region 120A, the epitaxial fin region 110A may be grown on the fin base 119A as Figure 1E and Figure 1G shown. After forming the inner spacer 113A and removing the suspended nanostructured region 120A, the epitaxial fin region 110A as Figure 1G shown may be grown on the fin base 119A. The process for etching the suspended nanostructured region 120A may include a dry etching process using an etchant gas such as CH 4 , O 2 , and CH 3 F. The flow rate ratio of CH 4 :O 2 :CH 3 F may be in the range of about 1:1:1 to about 1:2:4. The etching process may be performed at a high bias voltage of about 300V to about 450V. The etching of the suspended nanostructured region 120A may include using a wet etching process that has a higher selectivity for Si than for SiGe. For example, the wet etching process may include using a mixture of NH 4 OH and HCl.

[0094] After forming the inner spacer 113A and the epitaxial region 110A of the FET 102A, the photoresist layer 946 may be removed from the FET 102B, and another photoresist layer 1346 (as Figure 13B and Figure 13D shown) may be patterned on the FET 102A to protect the FET 102A during subsequent process steps to form the inner spacer 113B and the epitaxial region 110B of the FET 102B as described with reference to Figures 13A to 15D . For clarity, the photoresist layer 1346 is not shown in Figures 13A to 15A .

[0095] Referring to Figures 13A to 13D, The process for forming the internal spacer 113B may include etching portions of the external spacer 114B extending along the X-axis from either side of the polysilicon structure 112B* from the stack of nanostructured regions 120A and 122A, and subsequently etching the nanostructured region 120A from the stack of nanostructured regions 120A and 122A. The process for etching the portions of the external spacer 114B may include a dry etching process using an etchant gas such as CH 4 、O 2 and CH 3 F. The flow rate ratio of CH 4 :O 2 :CH 3 F may be in the range of about 1:1:1 to about 1:2:4. The etching process may be implemented at a high bias voltage of about 300V to about 450V. The etching of the nanostructured region 120A may include a wet etching process that has a higher selectivity for Si than for SiGe. For example, the wet etching process may include using a mixture of NH 4 OH and HCl.

[0096] Due to the etching of the nanostructured region 120A, suspended nanostructured regions 122A may be formed, with an opening 1348 therebetween, as Figure 13A and Figure 13C shown. Moreover, the etching of the nanostructured region 120A may produce a linear etch profile 120Bs 1 or a substantially triangular etch profile 120Bs 2 (shown in dashed lines) on the sidewalls of the nanostructured region 120B under the polysilicon structure 112B*, as Figure 13C shown. The etch profiles 120Bs 2 ( Figure 13C ) and 122Bs 2 ( Figure 10D ) may be different due to the different crystal structures and / or crystal orientations of the different materials of the nanostructured regions 120B and 122B. For example, the nanostructured region 120B having a Si material may have an etch profile 120Bs 2 , and the nanostructured region 122B having SiGe may have an etch profile 122Bs 2 .

[0097] The process for etching the nanostructured region 120A may be controlled such that the opening 1348 extends at least along the X-axis under the external spacer 114B, and the sidewalls of the nanostructured region 120B are substantially aligned with the interface 114Bs between the external spacer 114B and the polysilicon structure 112B*, as Figure 13CAs shown. In some embodiments, the opening 1348 may further extend along the X-axis under the polysilicon structure 112B*, such that the sidewalls of the nanostructured region 120B are set to be about 1 nm to about 10 nm from the interface 114Bs. Extending the opening 1348 under the outer spacer 114B or the polysilicon structure 112B* can prevent a portion of the nanostructured region 120B from remaining under the outer spacer 114B or prevent the formation of the gate structure 112B under the outer spacer 114B during the subsequent process (e.g., in operation 340) when replacing the nanostructured region 120B and the polysilicon structure 112B* with the gate structure 112B.

[0098] The process for forming the inner spacer 113B may further include blanket depositing a low-k dielectric material layer (not shown) on the Figure 13A structure until the opening 1348 is filled or partially filled with the low-k dielectric material layer. The blanket deposition process may be similar to the process for depositing the low-k dielectric material layer within the opening 1048 for forming the inner spacer 113A.

[0099] The process for forming the inner spacer 113B may further include etching the blanket deposited low-k dielectric material layer to etch back the low-k dielectric material layer within the opening 1348 to form the inner spacer 113B and remove other portions of the low-k material layer from the surface of the FET 102B, as Figure 14A and Figure 14C shown. The etching of the blanket deposited low-k dielectric material layer may include a dry etching process using a gas mixture of HF and NF 3 The gas ratio of HF to NF 3 may be in the range of about 1 to about 20. In some embodiments, the etching may be implemented in two etching steps. In the first etching step, the gas ratio of HF to NF 3 may be in the range of about 1 to about 10. The first etching step may remove portions of the low-k material layer from the surface of the FET 102B and partially etch back the low-k material layer within the opening 1348. In the second etching step, the gas ratio of HF to NF 3 may be higher than that of the first etching step and may be in the range of about 5 to about 20. The second etching step may achieve the structure of the inner spacer 113B as Figure 14C shown. In some embodiments, the interface 113Bs between the inner spacer 113B and the nanostructured region 120B follows the etching profile of the sidewalls of the nanostructured region 120B. For example, when the sidewalls of the nanostructured region 120B have a linear etching profile 122As 1 ( Figure 10D ) the interface 113Bs may have a structure as Figure 14CThe linear profile shown, or when the sidewalls of the nanostructured region 120B have a triangular etch profile 120Bs 2 ( Figure 13C and Figure 14C ), the interface 113Bs may have a triangular profile (not shown).

[0100] Referring Figures 15A to 15D , after forming the internal spacer 113B, an epitaxial fin region 110B may be grown around the suspended nanostructured region 122A. The epitaxial fin region 110B may be grown similar to the epitaxial fin region 110A described with reference to Figures 12A to 12D . In some embodiments, when the nanostructured region 122A includes SiGe, the epitaxial fin region 110B may be p-type, or when the nanostructured region 122A includes Si without any substantial amount of Ge (e.g., no Ge), the epitaxial fin region 110B may be n-type. After forming the internal spacer 113B and the epitaxial region 110B, the photoresist layer 1346 may be removed from the FET 102A, as Figure 15B and Figure 15D shown.

[0101] In some embodiments, similar to the epitaxial fin region 110A, instead of forming the epitaxial fin region 110B around the suspended nanostructured region 122A as Figure 15A and Figure 15D shown, the epitaxial fin region 110B may be grown on the fin base 119B as Figure 1E and Figure 1F shown. After forming the internal spacer 113B and subsequently removing the suspended nanostructured region 122A, an epitaxial fin region 110B such as Figure 1F shown may be grown on the fin base 119B. The process for removing the suspended nanostructured region 122A may include using a dry etch process that has a higher etch selectivity for SiGe than for Si. For example, halogen-based chemistries may exhibit a higher etch selectivity for Ge than for Si. Thus, a halogen gas may etch SiGe faster than Si. In some embodiments, the halogen-based chemistry may include fluorine-based and / or chlorine-based gases. Alternatively, the etching of the nanostructured region 122A may include using a wet etch process that has a higher etch selectivity for SiGe than for Si. For example, the wet etch process may include using a mixture of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 )(SPM) and / or ammonium hydroxide (NH 4 OH) with H 2 O 2A mixture with deionized (DI) water (APM).

[0102] In some embodiments, if the two FETs 102A - 102B have the same conduction type (e.g., n-type or p-type), the process steps for forming the internal spacers 113A - 113B can be implemented simultaneously without using the photoresist layers 946 and 1346. Similarly, if the two FETs 102A - 102B have similar conduction types, after simultaneously forming the internal spacers 113A - 113B, the process steps for forming the epitaxial fin regions 110A - 11B can be implemented simultaneously without using the photoresist layers 946 and 1346.

[0103] Referring to Figure 3 , in operation 335, a core - shell nanostructured channel region is formed between the epitaxial fin regions. For example, the core - shell nanostructured channel regions 121 and 123 can be sequentially formed in the regions of the fin structures 108A* - 108B* located under the polysilicon structures 112A* - 112B*, as described with reference to Figures 16A to 23D . Before forming the core - shell nanostructured channel regions 121 and 123, an ESL 116 can be deposited on the structure of Figure 15A , and an ILD 118 can be deposited on the ESL 116.

[0104] In some embodiments, the ESL 116 can be formed of a material including SiN x , SiO x , SiON, SiC, SiCN, BN, SiBN, SiCBN, or a combination thereof. The formation of the ESL 116 can include blanket depositing a material layer of the ESL 116 on the structure of Figure 15A using PECVD, sub - atmospheric chemical vapor deposition (SACVD), LPCVD, ALD, high - density plasma (HDP), plasma - enhanced atomic layer deposition (PEALD), molecular layer deposition (MLD), plasma pulse chemical vapor deposition (PICVD), or other suitable deposition methods.

[0105] After blanket deposition of the material layer for the ESL 116, blanket deposition of the dielectric material layer for the ILD 118 can follow. In some embodiments, the dielectric material can be silicon oxide. A deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable carbon silicon oxide) can be used to deposit the dielectric material layer. For example, flowable silicon oxide can be deposited using an FCVD process. After the blanket deposition process, thermal annealing of the deposited dielectric material layer can be carried out in steam at a temperature in the range of about 200 °C to about 700 °C for a duration in the range of about 30 minutes to about 120 minutes. As Figure 16A shown, after thermal annealing, a CMP process can be carried out to make the top surfaces of the ESL 116, ILD 118, external spacers 114A - 114B, and polysilicon structures 112A* - 112B* coplanar with each other. During the CMP process, the hard mask layers 742A - 742B can be removed.

[0106] After the CMP process, as Figures 17B to 18B and Figures 17D to 18D shown, the nanostructured core region 121A of the FET 102A can be formed. The process for forming the nanostructured core region 121A can include the following sequential steps: (i) forming a mask layer 1650 (e.g., a photoresist layer or a nitride layer) on the FET 102B, as Figures 16A to 16C shown, (ii) etching the polysilicon structure 112A* and the protective oxide layer 740A from the Figure 16A structure, (iii) removing the nanostructured region 122B from the Figure 16A structure to form the Figure 17A structure, and (iv) etching the nanostructured region 120B of the Figure 17A structure to form the nanostructured core region 121A as shown in Figure 18B and Figure 18D shown. In some embodiments, the first, second, third, and / or fourth polysilicon etch steps described in operation 320 can be used to etch the polysilicon structure 112A* and the protective oxide layer 740A. In some embodiments, the nanostructured region 122B can be removed by using a wet etch process or a dry etch process similar to the one described for etching the nanostructured region 122A with reference to Figures 10A to 10D Due to the etching of the nanostructured region 122B, openings 1752 are formed around the nanostructured region 120B, as Figure 17B and Figure 17D shown. A wet etch process with a higher selectivity for Si over SiGe can be used to selectively etch the nanostructured region 120B to reduce the dimensions of the nanostructured region 120B along the Z - axis and / or Y - axis. For example, the wet etch process can include using NH4 A mixture of OH and HCl. Due to the wet etching process, the nanostructured core region 121A can be formed to have a rectangular cross-section as Figure 18B shown. In some embodiments, the rectangular cross-section of the nanostructured core region 121A can be modified to a circular or elliptical cross-section by performing a thermal annealing process on the Figure 18A structure. The thermal annealing process can include annealing the nanostructured core region 121A for a duration in the range of about 50 seconds to about 90 seconds at a temperature in the range of about 600 °C to about 700 °C and at a pressure in the range of about 10 torr to about 30 torr in hydrogen. The parameters and etchant used to form the nanostructured core region 121A can be controlled such that the fin region 120A located under the epitaxial fin region 110A is not removed.

[0107] After the wet etching process to form the nanostructured core region 121A with a rectangular cross-section ( Figure 18B ) or the thermal annealing process to form the nanostructured core region 121A with a circular or elliptical cross-section (not shown), the nanostructured shell region can grow epitaxially on the nanostructured core region 121A with a rectangular cross-section (as Figure 19B and Figure 19D shown) or on the nanostructured core region 121A with a circular or elliptical cross-section (not shown) to form the core-shell nanostructured channel region 121 ( Figure 19B and Figure 19D ). In some embodiments, the nanostructured shell region 121B can be grown epitaxially by an epitaxial deposition / partial etching process that repeats the epitaxial deposition / partial etching process at least once. This repeated deposition / partial etching process is also referred to as a "cyclic deposition etching (CDE) process". In some embodiments, the nanostructured shell region 121B can be grown epitaxially by selective epitaxial growth (SEG), where an etching gas is added to promote the selective growth of the semiconductor material on the nanostructured core region 121A but not on the Figure 19A other surfaces of the structure.

[0108] In some embodiments, due to epitaxial growth, the nanostructured shell region 121B can be formed to have a rhombic cross-section as Figure 19B shown and a surface plane with a (111) crystal orientation. In some embodiments, by Figure 19AThe structure implements a thermal annealing process to modify the rhombic cross-section of the nanostructured shell region 121B into a circular or elliptical cross-section. The thermal annealing process can include annealing the nanostructured shell region 121B for a period of time in the range of about 50 seconds to about 90 seconds at a temperature in the range of about 600 °C to about 700 °C and at a pressure in the range of about 10 torr to about 30 torr in hydrogen.

[0109] After forming the core-shell nanostructured channel region 121, the core-shell nanostructured channel region 123 of the FET 102B can be formed, as Figures 21A to 22D shown. The process for forming the core-shell nanostructured channel region 123 can include the following sequential steps: (i) removing the mask layer 1650, (ii) forming a mask layer 1850 (e.g., a photoresist layer or a nitride layer) within the opening 1752 (shown in Figure 17B and Figure 17D ) to protect the core-shell nanostructured channel region 121 as shown in Figure 20B and Figure 20D , (iii) etching the polysilicon structure 112B* and the protective oxide layer 740B, (iv) removing the nanostructured region 120B from the structure of Figure 19A to form the structure of Figure 20A , (v) etching the nanostructured region 122B of the structure of Figure 20A to form the nanostructured core region 123A as shown in Figures 21B to 21C , and (vi) epitaxially growing the nanostructured shell region 123B on the nanostructured core region 123A, as shown in Figures 22B to 22C .

[0110] Similar to the etching of the polysilicon structure 112A* and the protective oxide layer 740A, the first, second, third, and / or fourth polysilicon etching steps described in operation 320 can be used to etch the polysilicon structure 112B* and the protective oxide layer 740B. In some embodiments, a wet etching process similar to that described for etching the nanostructured region 120A with reference to Figures 13A to 13D can be used to etch the nanostructured region 120B. Due to the nanostructured region 120B, an opening 1852 is formed around the nanostructured region 122B, as shown in Figures 20B to 20CAs shown. The nanostructured region 122B can be selectively etched using a dry etching process to reduce the dimensions of the nanostructured region 122B along the Z-axis and / or Y-axis. This dry etching process has a higher etching selectivity for SiGe than for Si. For example, halogen-based chemicals can exhibit a higher etching selectivity for Ge than for Si. Therefore, halogen gas can etch SiGe faster than Si. In some embodiments, the halogen-based chemical can include fluorine-based and / or chlorine-based gases. Optionally, the etching of the nanostructured region 122B can include using a wet etching process that has a higher etching selectivity for SiGe than for Si. For example, the wet etching process can include using a mixture of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 )(SPM) and / or a mixture of ammonium hydroxide (NH 4 OH) with H 2 O 2 and deionized (DI) water (APM). The parameters and etchant used to form the nanostructured core region 123A can be controlled such that the fin region 122A located beneath the epitaxial fin region 110B is not removed.

[0111] Due to the etching process, the nanostructured core region 123A can be formed to have a rectangular cross-section as Figure 21B shown. In some embodiments, the rectangular cross-section of the nanostructured core region 123A can be modified to a circular or elliptical cross-section by performing a thermal annealing process on the Figure 21A structure. The thermal annealing process can include annealing the nanostructured core region 123A for a duration in the range of about 50 seconds to about 90 seconds at a temperature in the range of about 600 °C to about 700 °C and at a pressure in the range of about 10 torr to about 30 torr in hydrogen. After the etching process to form the nanostructured core region 123A with a rectangular cross-section ( Figure 18B ) or the thermal annealing process to form the nanostructured core region 123A with a circular or elliptical cross-section (not shown), the nanostructured shell region 123B can be epitaxially grown on the nanostructured core region 123A with a rectangular cross-section (as Figures 22B to 22C shown) or on the nanostructured core region 123A with a circular or elliptical cross-section (not shown) to form the core-shell nanostructured channel region 123 ( Figures 22B to 22C ). In some embodiments, the nanostructured shell region 123A can be epitaxially grown by a CDE process or a SEG process similar to the process used for epitaxially growing the nanostructured shell region 121B.

[0112] In some embodiments, due to epitaxial growth, the nanostructured shell region 123B can form a rhombic cross-section and a surface plane with a (111) crystal orientation as shown in Figure 22B . In some embodiments, the rhombic cross-section of the nanostructured shell region 123B can be modified to a circular or elliptical cross-section by performing a thermal annealing process on the structure of Figure 22A . The thermal annealing process can include annealing the nanostructured shell region 123B for a period of time in the range of about 50 seconds to about 90 seconds at a temperature in the range of about 600 °C to about 700 °C and at a pressure in the range of about 10 torr to about 30 torr in hydrogen. After forming the core-shell nanostructured channel region 123 of the FET 102B, the mask layer 1850 can be removed from the opening 1752 to form the structure of Figures 23A to 23D .

[0113] Referring to Figure 3 , in operation 340, a gate-all-around (GAA) structure is formed on the core-shell nanostructured channel region. For example, the gate structures 112A-112B can be formed to wrap the core-shell nanostructured channel regions 121 and 123, as described with reference to Figures 23A to 23D and Figures 1A to 1D . The process for forming the gate structures 112A-112B can include the following sequential steps: (i) blanket depositing a dielectric material layer for the gate dielectric layers 128A-128B on the structure of Figure 23A , (ii) blanket depositing a work function metal layer for the gate work function metal layers 130A-130B on the dielectric material layer, and (iii) blanket depositing a conductive material layer for the gate metal fill layers 132A-132B on the work function metal layer until the openings 1752 and 1852 are filled. In some embodiments, as shown in Figure 1B , each of the dielectric material layer and the work function metal layer can form a conformal layer within the openings 1752 and 1852 (shown in Figures 23B to 23D ).

[0114] The dielectric material layer for the gate dielectric layers 128A-128B can include silicon oxide and can be formed by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), electron beam evaporation, or other suitable processes. In some embodiments, the dielectric material layer can include (i) a silicon oxide, silicon nitride, and / or silicon oxynitride layer, (ii) a high-k dielectric material such as, for example, hafnium oxide (HfO 2 ), TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2, (iii) a high-k dielectric material having an oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu, or (iv) a combination thereof. The high-k dielectric layer can be formed by ALD and / or other suitable methods.

[0115] The work function metal layer for the work function metal layers 130A - 130B can include Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, Ag, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloys, and / or combinations thereof. In some embodiments, the work function metal layer can include aluminum-doped metals such as aluminum-doped Ti, aluminum-doped TiN, aluminum-doped Ta, or aluminum-doped TaN. The work function metal layer can be deposited using suitable processes such as ALD, CVD, PVD, plating, or combinations thereof. The conductive material layer for the gate electrode 132 can include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Co, Ni, TiC, TiAlC, TaAlC, metal alloys, and / or combinations thereof, and can be formed by ALD, PVD, CVD, or other suitable deposition processes. The deposited dielectric material, work function metal, and conductive material layers can be planarized by a CMP process to form Figure 1A a structure. The CMP process can make the top surfaces of the gate dielectric layers 128A - 128B, the gate work function metal layers 130A - 130B, and the gate metal fill layers 132A - 132B substantially coplanar with the top surface of the ILD layer 118, as Figures 1A to 1D shown.

[0116] After forming the gate structures 112A - 112B, other elements such as S / D contacts, gate contacts, vias, interconnect metal layers, dielectric layers, passivation layers, etc. can be formed, which are not shown for clarity.

[0117] The present disclosure provides example structures and methods for improving charge carrier mobility (e.g., hole and / or electron mobility) in FET devices (such as FETs 102A - 102B). Increasing the charge carrier mobility can increase the switching speed and drive current of the FET device, resulting in faster and improved FET device performance. The example structures and methods provide a channel region having a core - shell nanostructure (such as core - shell nanostructured channel regions 121 and 123) between source / drain (S / D) regions (such as S / D regions 126A - 126B) of the FET device. In some embodiments, the core - shell nanostructure can include a nanostructured core region (such as nanostructured core regions 121A and 123A) wrapped by an epitaxially grown nanostructured shell region (such as nanostructured shell regions 121B and 123B). The core - shell nanostructure can be configured to induce tensile or compressive strain in the channel region of an n - type or p - type FET device, respectively. Tensile or compressive strain can be induced in the channel region, for example, by doping the nanostructured core or shell region or by using semiconductor materials with lattice mismatch for the nanostructured core or shell region. This induced strain in the channel region can improve the carrier mobility in the channel region. The core - shell nanostructure can further be configured to adjust the bandgap of the channel region and / or change the crystal orientation of the surface plane of the channel region based on the conduction type of the FET device to improve the charge carrier mobility in the channel region. Compared to FET devices without such a core - shell nanostructure, the channel regions with the core - shell nanostructure described herein can increase the switching speed and drive current of the FET device by, for example, about 20% to about 40% and about 30% to about 50%.

[0118] In some embodiments, a semiconductor device includes: a substrate; a stack of nanostructured layers having first and second nanostructured regions disposed on the substrate; and a nanostructured shell region wrapping the second nanostructured region. The nanostructured shell region and the second nanostructured region have semiconductor materials different from each other. The semiconductor device further includes first and second source / drain (S / D) regions disposed on the substrate and a gate - all - around (GAA) structure disposed between the first and second S / D regions. Each of the first and second S / D regions includes an epitaxial region wrapping each first nanostructured region, and the GAA structure wraps each nanostructured shell region.

[0119] In some embodiments, the nanostructured shell region and the second nanostructured region have different structural compositions from each other. In some embodiments, the nanostructured shell region and the second nanostructured region have different cross-sections from each other. In some embodiments, the nanostructured shell region has a surface plane with a first crystal orientation, and the second nanostructured region has a surface plane with a second crystal orientation different from the first crystal orientation. In some embodiments, the first crystal orientation is the (111) crystal orientation, and the second crystal orientation is the (100) crystal orientation. In some embodiments, the semiconductor material of the nanostructured shell region has a lattice mismatch with the semiconductor material of the second nanostructured region. In some embodiments, the semiconductor device further includes: a first internal spacer disposed between an epitaxial sub-region of a first source / drain region and a gate sub-region of the all-around gate structure; and a second internal spacer disposed between an epitaxial sub-region of a second source / drain region and a gate sub-region of the all-around gate structure. In some embodiments, the semiconductor device further includes a passivation layer disposed on sidewalls of the first nanostructured region.

[0120] In some embodiments, a semiconductor device includes first and second FETs. The first FET includes a stack of first nanostructured layers disposed on a substrate. Each first nanostructured layer includes first and second nanostructured regions. The first FET further includes a first nanostructured shell region that wraps the second nanostructured region. The first nanostructured shell region and the second nanostructured region have different semiconductor materials from each other. The first FET further includes a first epitaxial region that wraps each first nanostructured region, and a first all-around gate (GAA) structure disposed on the stack of first nanostructured layers. The GAA structure wraps each first nanostructured shell region. The second FET includes a stack of second nanostructured layers disposed on the substrate. Each second nanostructured layer includes third and fourth nanostructured regions. The second FET further includes a second nanostructured shell region that wraps the fourth nanostructured region. The second nanostructured shell region and the fourth nanostructured region have different semiconductor materials from each other, and the first nanostructured shell region and the second nanostructured shell region have different material compositions from each other. The second FET further includes a second epitaxial region that wraps each third nanostructured region and a second GAA structure disposed on the stack of second nanostructured layers. The conductivity type of the second epitaxial region is different from that of the first epitaxial region, and the GAA structure wraps each second nanostructured shell region.

[0121] In some embodiments, the second nanostructured layer has a different material composition from the first nanostructured layer. In some embodiments, the second nanostructured region and the fourth nanostructured region have different material compositions from each other. In some embodiments, the first nanostructured shell region and the second nanostructured shell region have different structural compositions from each other. In some embodiments, the first field effect transistor further includes a first internal spacer and a second internal spacer disposed within a stack of the first nanostructured layer. In some embodiments, the second field effect transistor further includes a third internal spacer and a fourth internal spacer disposed within a stack of the second nanostructured layer.

[0122] In some embodiments, a method of manufacturing a semiconductor device includes: forming a stack of nanostructured layers having a first nanostructured region and a second nanostructured region on a substrate; modifying the second nanostructured region to form a nanostructured core region; epitaxially growing a nanostructured shell region surrounding the nanostructured core region; growing first and second epitaxial regions surrounding each of the first nanostructured regions; forming a gate-all-around (GAA) structure surrounding each of the nanostructured shell regions between the first and second epitaxial regions; and forming first and second internal spacers along sidewalls of gate sub-regions of the GAA structure. The gate sub-regions are embedded within the stack of nanostructured layers.

[0123] In some embodiments, modifying the second nanostructured region includes: selectively etching the second nanostructured region to form the nanostructured core region having a vertical dimension smaller than a vertical dimension of the first nanostructured region. In some embodiments, epitaxially growing the nanostructured shell region surrounding the nanostructured core region includes: epitaxially growing a semiconductor material different from the nanostructured core region. In some embodiments, epitaxially growing the nanostructured shell region includes: epitaxially growing a semiconductor material having a lattice constant different from a lattice constant of the semiconductor material of the nanostructured core region. In some embodiments, forming the stack of nanostructured layers includes: epitaxially growing first semiconductor layers and second semiconductor layers of different compositions in an alternating configuration on the substrate; and etching the first semiconductor layers and the second semiconductor layers to form a first nanostructured layer and a second nanostructured layer. In some embodiments, forming the GAA structure includes: etching the second nanostructured layer to form an opening between adjacent ones of the first nanostructured layers; depositing a gate dielectric material layer within the opening; and depositing a conductive material layer on the gate dielectric material layer to fill the opening.

[0124] The present invention outlines the features of several embodiments, enabling those skilled in the art to better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a substrate; a stack of nanostructured layers having a first nanostructured region and a second nanostructured region disposed on the substrate; a nanostructured shell region encapsulating the second nanostructured region, wherein the nanostructured shell region and the second nanostructured region have different semiconductor materials from each other, and wherein the nanostructured shell region has a surface plane with a first crystal orientation and the second nanostructured region has a surface plane with a second crystal orientation different from the first crystal orientation; a first source / drain region and a second source / drain region disposed on the substrate, wherein each of the first source / drain region and the second source / drain region includes an epitaxial region encapsulating each of the first nanostructured regions; and a fully-depleted surround gate structure disposed between the first source / drain region and the second source / drain region and encapsulating each of the nanostructured shell regions.

2. The semiconductor device according to claim 1, wherein, the nanostructured shell region and the second nanostructured region have different structural compositions from each other.

3. The semiconductor device according to claim 1, wherein, the nanostructured shell region and the second nanostructured region have different cross-sections from each other.

4. The semiconductor device according to claim 1, wherein, the first source / drain region and the second source / drain region are respectively disposed at a first end and a second end of the first nanostructured region.

5. The semiconductor device according to claim 1, wherein, the first crystal orientation is the [111] crystal orientation and the second crystal orientation is the [100] crystal orientation.

6. The semiconductor device according to claim 1, wherein, the semiconductor material of the nanostructured shell region has a lattice mismatch with the semiconductor material of the second nanostructured region.

7. The semiconductor device according to claim 1, further comprising: a first inner spacer disposed between an epitaxial sub-region of the first source / drain region and a gate sub-region of the fully-depleted surround gate structure; and a second inner spacer disposed between an epitaxial sub-region of the second source / drain region and a gate sub-region of the fully-depleted surround gate structure.

8. The semiconductor device according to claim 1, further comprising a passivation layer disposed on sidewalls of the first nanostructured region.

9. A semiconductor device, comprising: a first field-effect transistor, comprising: a stack of first nanostructured layers disposed on a substrate, wherein each of the first nanostructured layers includes a first nanostructured region and a second nanostructured region, a first nanostructured shell region encapsulating the second nanostructured region, wherein the first nanostructured shell region and the second nanostructured region have different semiconductor materials from each other, the first nanostructured shell region has a surface plane with a first crystal orientation and the second nanostructured region has a surface plane with a second crystal orientation different from the first crystal orientation, A first epitaxial region that wraps each of the first nanostructured regions, and A first fully-depleted surround gate structure disposed on the stack of the first nanostructured layers and wrapping each of the first nanostructured shell regions; and A second field effect transistor, comprising: A stack of second nanostructured layers disposed on a substrate, wherein each of the second nanostructured layers includes a third nanostructured region and a fourth nanostructured region, A second nanostructured shell region that wraps the fourth nanostructured region, wherein the second nanostructured shell region and the fourth nanostructured region have different semiconductor materials from each other, and wherein the first nanostructured shell region and the second nanostructured shell region have different material compositions from each other, A second epitaxial region that wraps each of the third nanostructured regions, wherein the conductivity type of the second epitaxial region is different from that of the first epitaxial region, and A second fully-depleted surround gate structure disposed on the stack of the second nanostructured layers and wrapping each of the second nanostructured shell regions.

10. The semiconductor device according to claim 9, wherein, the second nanostructured layer has a different material composition from the first nanostructured layer.

11. The semiconductor device according to claim 9, wherein, the second nanostructured region and the fourth nanostructured region have different material compositions from each other.

12. The semiconductor device according to claim 9, wherein, the first nanostructured shell region and the second nanostructured shell region have different structural compositions from each other.

13. The semiconductor device according to claim 9, wherein, the first field effect transistor further includes a first internal spacer and a second internal spacer disposed within the stack of the first nanostructured layers.

14. The semiconductor device according to claim 9, wherein, the second field effect transistor further includes a third internal spacer and a fourth internal spacer disposed within the stack of the second nanostructured layers.

15. A method for manufacturing a semiconductor device, comprising: forming a stack of nanostructured layers having a first nanostructured region and a second nanostructured region on a substrate; modifying the second nanostructured region to form a nanostructured core region; epitaxially growing a nanostructured shell region that wraps the nanostructured core region, wherein the nanostructured shell region is epitaxially grown to have a surface plane with a first crystal orientation, and the nanostructured core region is formed to have a surface plane with a second crystal orientation different from the first crystal orientation; growing a first epitaxial region and a second epitaxial region that wrap each of the first nanostructured regions; forming a fully-depleted surround gate structure that wraps each of the nanostructured shell regions between the first epitaxial region and the second epitaxial region; and forming a first internal spacer and a second internal spacer along sidewalls of a gate sub-region of the fully-depleted surround gate structure, wherein the gate sub-region is embedded within the stack of the nanostructured layers.

16. The method according to claim 15, wherein, Modifying the second nanostructured region includes: selectively etching the second nanostructured region to form the nanostructured core region having a vertical dimension smaller than the vertical dimension of the first nanostructured region.

17. The method according to claim 15, wherein, epitaxially growing the nanostructured shell region surrounding the nanostructured core region includes: epitaxially growing a semiconductor material different from the nanostructured core region.

18. The method according to claim 15, wherein, epitaxially growing the nanostructured shell region includes: epitaxially growing a semiconductor material having a lattice constant different from the lattice constant of the semiconductor material of the nanostructured core region.

19. The method according to claim 15, wherein, forming the stack of nanostructured layers includes: epitaxially growing first and second semiconductor layers of different compositions in an alternating configuration on the substrate; and etching the first semiconductor layer and the second semiconductor layer to form a first nanostructured layer and a second nanostructured layer.

20. The method according to claim 19, wherein, forming the all-around gate structure includes: etching the second nanostructured layer to form an opening between adjacent ones of the first nanostructured layers; depositing a gate dielectric material layer in the opening; and depositing a conductive material layer on the gate dielectric material layer to fill the opening.

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