Semiconductor device having a neck-shaped semiconductor body and method of forming a semiconductor body of different widths

Abstract

The present invention describes a semiconductor device having a neck-shaped semiconductor body and a method for forming a semiconductor body of different widths. For example, the semiconductor device includes a semiconductor body disposed on a substrate. A gate electrode stack is disposed on a portion of the semiconductor body to define a channel region in the semiconductor body located below the gate electrode stack. A source region and a drain region are defined in the semiconductor body on both sides of the gate electrode stack. A sidewall spacer is disposed adjacent to the gate electrode stack and is disposed on only a portion of the source region and the drain region. The portion of the source region and the drain region located below the sidewall spacer has a greater height and width than the height and width of the channel region of the semiconductor body.

Description

[0001] This application is a divisional application. The original application was a patent application submitted to the China Patent Office on August 21, 2014 (the international application date is December 22, 2011), with application number 201180076423.6, and the name of the invention is "Semiconductor device with neck-shaped semiconductor body and method for forming semiconductor bodies of different widths". Technical Field

[0002] Embodiments of the present invention are in the field of semiconductor devices and processing, and in particular, in the field of semiconductor devices having neck-shaped semiconductor bodies and methods of forming semiconductor bodies of varying widths. Background Art

[0003] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller features enables the density of functional units on the limited substrate area of ​​a semiconductor chip to be increased. For example, shrinking transistor size allows the number of memory devices or logic devices contained on a chip to increase, thereby creating products with greater capacity. However, the pursuit of greater and greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly apparent.

[0004] In the manufacture of integrated circuit devices, multi-gate transistors such as fin-FETs and tri-gate transistors have become more common as device dimensions continue to shrink. In conventional processes, fin-FETs and tri-gate transistors are typically manufactured on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable less complex fin-FET and tri-gate manufacturing processes. In other instances, silicon-on-insulator substrates are preferred due to the improved short channel characteristics of fin-FETs and tri-gate transistors.

[0005] However, scaling multi-gate transistors is not without its challenges. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the external resistance (R ext ) limitation has become critical. Many different techniques have been tried to improve the R ext The techniques include improved contact metal, increased dopant activity, and reduced barrier between semiconductor and contact metal. ext There is still a need for significant improvement in this area. Summary of the invention

[0006] Embodiments of the present invention include semiconductor devices having a neck-shaped semiconductor body and methods of forming semiconductor bodies of varying widths.

[0007] In an embodiment, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed on a portion of the semiconductor body to define a channel region in the semiconductor body below the gate electrode stack. A source region and a drain region are defined in the semiconductor body on both sides of the gate electrode stack. A sidewall spacer is disposed adjacent to the gate electrode stack and disposed on only a portion of the source region and the drain region. The portion of the source region and the drain region below the sidewall spacer has a greater height and width than the height and width of the channel region of the semiconductor body.

[0008] In another embodiment, a method for manufacturing a semiconductor device includes forming a semiconductor body above a substrate. A gate electrode stack is formed on a portion of the semiconductor body to define a channel region in the semiconductor body below the gate electrode stack, and a source region and a drain region in the semiconductor body on both sides of the gate electrode stack. Sidewall spacers are formed at a critical gate electrode stack and formed on only a portion of the source region and the drain region. The portion of the source region and the drain region below the sidewall spacers has a greater height and width than the height and width of the channel region of the semiconductor body.

[0009] In another embodiment, a method for manufacturing a semiconductor device includes forming a hard mask pattern over a substrate. The hard mask pattern includes a first region having fin-forming features, each of which has a first width. The hard mask pattern also includes a second region having fin-forming features, each of which has a second width approximately equal to the first width. Subsequently, a resist layer is formed and patterned to cover the second region and expose the first region. Subsequently, the fin-forming features of the first region are etched to form thinned fin-forming features, each of which has a third width less than the second width. Subsequently, the resist layer is removed. Subsequently, the hard mask pattern is transferred to a substrate to form a first region having fins, each of which has a third width; and a second region having fins is formed, each of which has a second width. Subsequently, a semiconductor device is formed from the fins of the first and second regions.

[0010] In another embodiment, a method for manufacturing a semiconductor device includes forming a hard mask pattern over a substrate. The hard mask pattern includes a first region having fin-forming features, wherein each feature has a first width. The hard mask pattern also includes a second region having fin-forming features, wherein each feature has a second width approximately equal to the first width. Subsequently, the hard mask pattern is transferred to the substrate to form a first region having fins, wherein each fin has a first width; and a second region having fins, wherein each fin has a second width. Subsequently, a resist layer is formed and patterned to cover the second region having the fins and expose the first region having the fins. Subsequently, the fins in the first region are etched to form thinned fins, wherein each thinned fin has a third width less than the second width. Subsequently, the resist layer is removed. Subsequently, a semiconductor device is formed from the fins in the first and second regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A A plan view of a semiconductor device having a neck-shaped semiconductor body according to an embodiment of the present invention is shown.

[0012] Figure 1B The embodiment according to the present invention is shown Figure 1A A cross-sectional view of a semiconductor device taken along the aa' axis.

[0013] Figure 1C The embodiment according to the present invention is shown Figure 1A A cross-sectional view of a semiconductor device taken along the bb' axis.

[0014] Figure 2A A plan view of a semiconductor device having a neck-shaped semiconductor body according to an embodiment of the present invention is shown.

[0015] Figure 2B A plan view of another semiconductor device having a neck-shaped semiconductor body according to another embodiment of the present invention is shown.

[0016] Figure 2C A plan view of another semiconductor device having a neck-shaped semiconductor body according to another embodiment of the present invention is shown.

[0017] Figure 3 A process flow in a method of manufacturing a semiconductor device having a neck-shaped semiconductor body according to an embodiment of the present invention is shown.

[0018] Figure 4 A process flow in a method of manufacturing a semiconductor device having a neck-shaped semiconductor body according to an embodiment of the present invention is shown.

[0019] Figure 5AIncluded are plots comparing drive current gain (eg, %Idsat gain) as a function of silicon channel region thickness (in microns) for a semiconductor device having a neck-shaped semiconductor body in accordance with an embodiment of the present invention compared to a function of silicon channel region thickness for a semiconductor device without a neck-shaped semiconductor body.

[0020] Figure 5B Included are plots comparing drive current gain (eg, %Idlin gain) as a function of silicon channel region thickness (in microns) for a semiconductor device having a neck-shaped semiconductor body in accordance with an embodiment of the present invention compared to a function of silicon channel region thickness for a semiconductor device without a neck-shaped semiconductor body.

[0021] Figure 6 A process flow in a method of manufacturing a semiconductor device having semiconductor bodies of different widths according to an embodiment of the present invention is shown.

[0022] Figure 7 A process flow in a method of manufacturing a semiconductor device having semiconductor bodies of different widths according to an embodiment of the present invention is shown.

[0023] Figure 8 A computing device according to one embodiment of the present invention is shown. DETAILED DESCRIPTION

[0024] Semiconductor devices having neck-shaped semiconductor bodies and methods of forming semiconductor bodies of different widths are described. In the following description, a large number of specific details are set forth to provide a deep understanding of embodiments of the present invention, such as specific integration and material regimes. It is apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts are not specifically described in order not to unnecessarily obscure embodiments of the present invention. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0025] One or more embodiments of the present invention are directed to semiconductor devices having (1) different fin widths in an active channel region compared to a fin width under a spacer, (2) an integrated circuit having at least two different fin widths in different active channel regions on the same die, (3) a patterning process for defining the two different fin widths before actual fin etching, (4) a patterning process for defining the two different fin widths after a sacrificial dummy gate removal process, or a combination thereof. One or more embodiments are directed to improving the drive current of a device such as a transistor, and to creating a circuit having low no-load power and high activation performance.

[0026] The width of the fin in the FinFET affects the threshold voltage (Vt) and the external resistance of the device. For high-performance devices, it may be beneficial to include relatively wide fins with higher Vt and lower resistance. For low-power devices, the situation is just the opposite. At present, the process must be optimized for one of these devices. It may be beneficial to make both devices have optimal performance to optimize product power performance. For example, low-power devices are produced using additional appropriate doping that causes higher Vt and higher junction leakage, which reduces the drive current, especially at low power supply voltages. Alternatively, the process is optimized for low-power devices that cause the drive current of high-performance devices to be reduced. Embodiments of the present invention can enable the optimization of high-performance and low-power devices to be achieved simultaneously by providing two different devices on the same die or by having both low Vt and low external resistance.

[0027] In a first aspect, a semiconductor device having a neck-shaped semiconductor body and a method of forming a semiconductor device having a neck-shaped semiconductor body are provided. This transistor structure has different fin widths in the channel and in the fin region under the spacer. As the fin CD is scaled, the neck-shaped fin can improve the trade-off between short channel effect improvement and external resistance, thereby improving the drive current of the optimal device.

[0028] In the example, Figure 1A A plan view of a semiconductor device having a neck-shaped semiconductor body according to an embodiment of the present invention is shown. Figure 1B The embodiment according to the present invention is shown Figure 1A A cross-sectional view of a semiconductor device taken along the aa' axis. Figure 1C The embodiment according to the present invention is shown Figure 1A A cross-sectional view of a semiconductor device taken along the bb' axis.

[0029] refer to Figures 1A-1C , the semiconductor device 100 includes a semiconductor body 104 disposed above a substrate 102. A gate electrode stack 106 is disposed on a portion of the semiconductor body 104 to define a channel region 108 in the semiconductor body 104 below the gate electrode stack 106. Source and drain regions 110 are defined in the semiconductor body 104 on both sides of the gate electrode stack 106. Sidewall spacers 112 are disposed adjacent to the gate electrode stack 106 and disposed on only a portion of the source and drain regions 110.

[0030] refer to Figure 1B and 1C, the portions of the source and drain regions 110 located below the sidewall spacers 112 have a greater height (H2) and width (W2) than the height (H1) and width (W1) of the channel region 108 of the semiconductor body 104. The heights H1 and H2 are defined as the heights of the respective portions of the semiconductor body 104 above the isolation layer 114, as shown in FIG. Figure 1B and 1C As described in .

[0031] refer to Figure 1A In an embodiment, the portion of the source and drain regions 110 not under the sidewall spacers 112 has a greater height and width (W3) than the height (H2) and width (W2) of the portion of the source and drain regions 110 under the sidewall spacers 112, for example, W3>W2. Alternatively, in another embodiment, the height and width (W3) of the portion of the source and drain regions 110 not under the sidewall spacers 112 are substantially the same as the height (H2) and width (W2) of the portion of the source and drain regions 110 under the sidewall spacers 112, for example, W3=W2.

[0032] In an embodiment, at least a portion of the source and drain regions 110 are embedded portions of the source and drain regions 110. That is, when the source and drain regions 110 are formed, a portion of the original semiconductor body 104 is removed and replaced with a new portion of the semiconductor body 104, such as by epitaxial growth. For example, in one such embodiment, the embedded portions of the source and drain regions 110 are composed of a semiconductor material that is different from the semiconductor material of the channel region 108. In one embodiment, the embedded portions do not include portions of the source and drain regions 110 that are located below the sidewall spacers 112. In another embodiment, the embedded portions include at least a portion, and possibly all, of the portions of the source and drain regions 110 that are located below the sidewall spacers 112.

[0033] In the embodiments, reference Figure 1B and 1C , the substrate 102 is a crystalline substrate, and the semiconductor body 104 (eg, Figure 1B The channel region 108 and Figure 1C The source and drain regions 110 in the semiconductor body 104 are continuous with the crystalline substrate 102. That is, the semiconductor body 104 is formed from the bulk substrate. In an alternative embodiment (not shown), a dielectric layer is disposed between the semiconductor body and the substrate, and the semiconductor body is not continuous with the substrate, for example, as would occur with a silicon-on-insulator (SOI) substrate.

[0034] In an embodiment, the height (H1) of the channel region 108 is approximately in the range of 30-50 nanometers, and the width (W1) is approximately in the range of 10-30 nanometers. In this embodiment, the height (H1) of the channel region 108 is approximately 1-2 nanometers less than the height (H2) of the portion of the source and drain regions 110 located under the sidewall spacers 112. Similarly, the width (W1) of the channel region 108 is approximately 2-4 nanometers less than the width (W2) of the portion of the source and drain regions 110 located under the sidewall spacers 112. In an embodiment, the height (H2) of the portion of the source and drain regions 110 located under the sidewall spacers 112 is approximately 1-7% greater than the height (H1) of the channel region 108. In this embodiment, the width (W2) of the portion of the source and drain regions 110 located under the sidewall spacers 112 is approximately 6-40% greater than the width (W1) of the channel region 108.

[0035] The following describes Figures 1A-1C In a first example, Figure 2A FIG. 2 is a plan view of a semiconductor device having a neck-shaped semiconductor body according to an embodiment of the present invention. Figure 2A , the channel region 108 is coupled to the portions of the source and drain regions 110 that are located below the sidewall spacers 112 by step features 120. The gate electrode stack 106 is depicted as a dashed line to provide transparency to the underlying channel region 108. Likewise, an alternative solution that includes larger portions of the source and drain regions 110 that are not below the spacers 112 is depicted by long dashed lines surrounding the source and drain regions 110.

[0036] In the second example, Figure 2B FIG. 2 is a plan view of another semiconductor device having a neck-shaped semiconductor body according to another embodiment of the present invention. Figure 2B , the channel region 108 is coupled to the portions of the source and drain regions 110 that are located below the sidewall spacers 112 through facet features 130. The gate electrode stack 106 is depicted as a dashed line to provide transparency to the underlying channel region 108. Likewise, an alternative solution that includes larger portions of the source and drain regions 110 that are not below the spacers 112 is depicted by long dashed lines surrounding the source and drain regions 110.

[0037] In the third example, Figure 2C FIG. 2 is a plan view of another semiconductor device having a neck-shaped semiconductor body according to another embodiment of the present invention. Figure 2C, the channel region 108 is coupled to the portions of the source and drain regions 110 that are located below the sidewall spacers 112 by rounded corner features 140. The gate electrode stack 106 is depicted as a dashed line to provide transparency to the underlying channel region 108. Likewise, an alternative solution that includes larger sized portions of the source and drain regions 110 that are not below the spacers 112 is depicted by a long dashed line surrounding the source and drain regions 110.

[0038] Therefore, refer again Figure 2B and 2C In an embodiment, the channel region 108 is coupled to portions of the source and drain regions 110 that are located below the sidewall spacers 112 through graded features (e.g., 120 or 140). In an embodiment, the graded features reduce overlap capacitance and diffusion resistance during operation of the semiconductor device 110.

[0039] In an embodiment, as described in more detail below in conjunction with process flows 600 and 700, semiconductor device 100 is disposed over the same substrate 102 as a second semiconductor device having a channel region. In this embodiment, the narrowest width of the channel region of the second semiconductor device is greater than the narrowest width (e.g., W1) of channel region 108 of semiconductor device 100.

[0040] The semiconductor device 100 may be any semiconductor device including a gate, a channel region, and a source / drain region pair. In an embodiment, the semiconductor device 100 is a semiconductor device such as, but not limited to, a MOS-FET or a micro-electromechanical system (MEMS). In an embodiment, the semiconductor device 100 is a three-dimensional MOS-FET and is an isolated device or one of a plurality of nested devices. It will be appreciated that for a typical integrated circuit, both N-channel and P-channel transistors may be fabricated on a single substrate to form a CMOS integrated circuit.

[0041] The substrate 102 may be composed of a semiconductor material that can withstand the manufacturing process and in which charges can migrate, and thus the semiconductor body 104 may also be composed of such a semiconductor material. In an embodiment, the substrate 102 is a bulk substrate, and the semiconductor body 104 is continuous with the bulk substrate 102. In an embodiment, the substrate 102 is composed of a crystalline silicon, silicon / germanium, or a germanium layer doped with charge carriers, such as but not limited to phosphorus, arsenic, boron, or a combination thereof. In one embodiment, the concentration of silicon atoms in the substrate 102 is greater than 97%, or, alternatively, the concentration of dopant atoms is less than 1%. In another embodiment, the substrate 102 is composed of an epitaxial layer grown on top of a different crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The substrate 102 may also include an insulating layer disposed between the bulk crystalline substrate and the epitaxial layer to form, for example, a silicon-on-insulator substrate. In the example, the semiconductor body 104 may be an isolated semiconductor body. In an embodiment, the insulating layer is composed of a material such as but not limited to silicon dioxide, silicon nitride, silicon oxynitride, or a high-k dielectric layer. Alternatively, the substrate 102 may be composed of a III-V group material. In an embodiment, the substrate 102 is composed of a III-V group material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. The semiconductor body 104 may be composed of a plurality of semiconductor materials, each of which may include additional doping atoms. In one embodiment, the substrate 102 is composed of crystalline silicon, and the charge carrier dopant impurity atoms are, for example, but not limited to, atoms of boron, arsenic, indium, or phosphorus. In another embodiment, the substrate 102 is composed of a III-V group material, and the charge carrier dopant impurity atoms are, for example, but not limited to, atoms of carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium. In another embodiment, the semiconductor body 104 is undoped or only lightly doped. In addition, in one embodiment, halo doping, which is typically used in conventional device manufacturing, may be eliminated in the manufacture of the semiconductor device 100. It should be understood that in an embodiment, the material of the semiconductor body 104 is different from the material of the substrate 102 .

[0042] In another embodiment, the semiconductor device 100 is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, the semiconductor body 104 is composed of or formed from a three-dimensional body. In one such embodiment, the gate electrode stack 106 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, such as in a nanowire device, the semiconductor body 104 is fabricated as a discrete three-dimensional body. In one such embodiment, the gate electrode stack 100 completely surrounds a portion of the semiconductor body 104.

[0043] The gate electrode stack 106 may include a gate electrode and a lower gate dielectric layer. In an embodiment, the gate electrode of the gate electrode stack 106 is composed of a metal gate, and the gate dielectric layer is composed of a high-K material. For example, in one embodiment, the gate dielectric layer is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a natural oxide layer formed by the top layers of the semiconductor body 104. In an embodiment, the gate dielectric layer is composed of a top high-K portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

[0044] In one embodiment, the gate electrode is composed of a metal layer such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function setting fill material formed above the metal work function setting layer. In an embodiment, the gate electrode is composed of a P-type material. In another embodiment, the gate electrode is composed of an N-type material. In another embodiment, the gate electrode is composed of an intermediate bandgap material. In a specific embodiment of this type, the corresponding channel region is undoped or only lightly doped.

[0045] In an embodiment, sidewall spacers 112 are composed of an insulating dielectric material such as, but not limited to, silicon dioxide, silicon carbide, silicon oxynitride, or silicon nitride. Similarly, dielectric layer 114 may be composed of an insulating dielectric material such as, but not limited to, silicon dioxide, silicon carbide, silicon oxynitride, or silicon nitride.

[0046] Methods of forming devices such as those described above are also contemplated within the spirit and scope of embodiments of the present invention. In a first example, Figure 3 A process flow 300 is shown in a method of manufacturing a semiconductor device having a neck-shaped semiconductor body according to an embodiment of the present invention.

[0047] Referring to part A of process flow 300, a thick fin 302 is formed, a sacrificial gate 304 is patterned, a gate spacer 306 is formed by blanket deposition and subsequent etching, and a source-drain region 308 is formed. In addition, an interlayer dielectric film 310 may be deposited and polished to expose the sacrificial gate 304. Referring to part B of process flow 300, the sacrificial gate 304 is removed, and the thick fin 302 is etched to form a thinned fin 312 having a reduced thickness (e.g., reduced by an amount in the range of approximately 1-5 nanometers). Referring to part C of process flow 300, a permanent gate stack 320 is formed over the thinned fin 312. For example, a high-k gate dielectric layer and a metal gate electrode may be formed. In an embodiment, the thinned fin 312 provides an improved short channel effect, while the wider portions of the source and drain regions 308 located below the spacer 306 help reduce external resistance.

[0048] In an embodiment, the sacrificial gate 304 is composed of a material suitable for removal during a replacement gate operation. In one embodiment, the sacrificial gate 304 is composed of polysilicon, amorphous silicon, silicon dioxide, silicon nitride, or a combination thereof. In another embodiment, a protective capping layer (not shown) such as a silicon dioxide or silicon nitride layer is formed over the sacrificial gate 304. In an embodiment, an underlying dummy gate dielectric layer (also not shown) is included. In an embodiment, the sacrificial gate 304 includes a sidewall spacer 306, which may be composed of a material suitable for ultimately electrically isolating the permanent gate structure from an adjacent conductive contact. For example, in one embodiment, the spacer 306 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0049] In an embodiment, the sacrificial gate 304 is removed by a dry etching or wet etching process. In one embodiment, the sacrificial gate 304 is composed of polysilicon or amorphous silicon, and the sacrificial gate 304 is removed by a dry etching process using SF6. In another embodiment, the sacrificial gate 304 is composed of polysilicon or amorphous silicon, and the sacrificial gate 304 is removed by a wet etching process using an aqueous solution of NH4OH or tetramethylamine hydroxide. In one embodiment, the sacrificial gate 304 is composed of silicon nitride, and the sacrificial gate 304 is removed by wet etching using an aqueous solution of phosphoric acid.

[0050] Fin 302 may be thinned to form 312 by any suitable technique that removes a portion of fin 302, such as by utilizing a dry etch or wet etch process, without adversely affecting other semiconductor features present. In one embodiment, fin 302 may be thinned to form 312 by utilizing a dry plasma etch using NF3, HBr, SF6 / Cl, or Cl2.

[0051] In the second example, Figure 4 A process flow 400 in a method of manufacturing a semiconductor device having a neck-shaped semiconductor body according to an embodiment of the present invention is shown. Referring to portion A of process flow 400, a thin fin 412 is formed, a sacrificial gate 404 is patterned, and a thin source-drain region 408 is formed. Referring to portion B of process flow 400, a gate spacer 406 is formed by blanket deposition and subsequent etching, and thick source and drain regions 418 are formed, for example, by epitaxial growth. In addition, an interlayer dielectric film 410 may be deposited and polished to expose the sacrificial gate 404. The sacrificial gate 404 is then removed, as depicted in portion B. Referring to portion C of process flow 400, a permanent gate stack 420 is formed on the thin fin 412. For example, a high-k gate dielectric layer and a metal gate electrode may be formed. In an embodiment, the thin fin 412 provides an improved short channel effect, while the wider portion of the source and drain regions 408 / 418 located below the spacer 406 helps to reduce external resistance. The formation and replacement of the sacrificial gate may be performed as described above in conjunction with process flow 300 .

[0052] Therefore, in an embodiment, a method for manufacturing a semiconductor device includes forming a semiconductor body above a substrate. A gate electrode stack is formed on a portion of the semiconductor body to define a channel region in the semiconductor body below the gate electrode stack, and a source region and a drain region in the semiconductor body on both sides of the gate electrode stack. A sidewall spacer is formed adjacent to the gate electrode stack and formed on only a portion of the source region and the drain region. The portion of the source region and the drain region below the sidewall spacer has a greater height and width than the height and width of the channel region of the semiconductor body.

[0053] In one such embodiment, forming a gate electrode stack includes forming a sacrificial gate electrode stack, removing the sacrificial gate electrode stack, and forming a permanent gate electrode stack. In this embodiment, forming a channel region includes thinning a portion of the exposed semiconductor body after removing the sacrificial gate electrode stack and before forming the permanent gate electrode stack, for example, as described in conjunction with process flow 300. In another such embodiment, forming a gate electrode stack includes forming a sacrificial gate electrode stack, removing the sacrificial gate electrode stack, and forming a permanent gate electrode stack. In this embodiment, forming a source region and a drain region includes expanding a portion of the exposed semiconductor body before removing the sacrificial gate electrode stack, for example, as described in conjunction with process flow 400.

[0054] Figure 5A Curve 500A includes drive current gain (eg, %Idsat gain) as a function of silicon channel region thickness (in microns) for a semiconductor device having a neck-shaped semiconductor body compared to silicon channel region thickness for a semiconductor device without a neck-shaped semiconductor body according to an embodiment of the present invention. Figure 5B A plot 500B is included comparing drive current gain (e.g., %Idlin gain) as a function of silicon channel region thickness (in microns) for a semiconductor device having a neck-shaped semiconductor body and as a function of silicon channel region thickness for a semiconductor device without a neck-shaped semiconductor body according to an embodiment of the present invention. Referring to plots 500A and 500B, a fin formed according to a predefined silicon width (Wsi) is compared to a fin having a thinned silicon width (Wsi) defined during a replacement gate operation (e.g., as described in conjunction with process flow 300). The plots reveal the expected drive current gain for the thinned fin device.

[0055] In a second aspect, a method of forming a semiconductor body of different widths is provided. This process can enable different fin widths to be formed within the same die. Thus, the use of wider fin width devices for high-performance applications and lower fin width devices for low power (low standby leakage) applications can be achieved on the same die.

[0056] In the first example, Figure 6 A process flow 600 is shown in a method of fabricating a semiconductor device having semiconductor bodies of different widths according to an embodiment of the present invention.

[0057] Referring to portion A of process flow 600, the formation of a hard mask 603A / 603B for final fin formation over a substrate 602 (e.g., over a crystalline silicon substrate) includes deposition and patterning of a hard mask layer. The patterned hard mask layer 603A / 603B includes a region 604 for final thin fin formation and a region 606 for final thick fin formation. Referring to portion B of process flow 600, a resist layer 608 is used to mask the fins that will maintain a wider width (e.g., in region 606), and the exposed hard mask 603A is etched to reduce the width of the line. Referring to portion C of process flow 600, the resist layer 608 is then removed (e.g., including an ashing process), and the new hard mask pattern 603A / 603B is transferred to the substrate 602 to form fins 610A and 610B. Alternatively, in an embodiment, additional photolithographic fin thinning may be performed after the fins are etched into the substrate and prior to patterning of the sacrificial gate. In an embodiment, the hard mask regions 603A / 603B are first formed by a spacer patterning flow, which may be used to effectively double the pitch of the photolithography process used to form the features. The process flow 600 maintains the pitch of the spacer patterning flow.

[0058] Thus, in an embodiment, a method for manufacturing a semiconductor device includes forming a hard mask over a substrate. The hard mask pattern includes a first region having fin-forming features, each of which has a first width. The hard mask pattern also includes a second region having fin-forming features, each of which has a second width approximately equal to the first width. Subsequently, a resist layer is formed and patterned to cover the second region and expose the first region. Subsequently, the fin-forming features of the first region are etched to form thinned fin-forming features, each of which has a third width less than the second width. Subsequently, the resist layer is removed. Subsequently, the hard mask pattern is transferred to a substrate to form a first region having a fin, each of which has a third width; and a second region having a fin, each of which has a second width. Subsequently, a semiconductor device is formed using the fins of the first and second regions. In one such embodiment, the substrate is a single crystal silicon substrate, and transferring the hard mask pattern to the substrate includes forming a single crystal silicon fin.

[0059] In the second example, Figure 7 A process flow 700 is shown in a method of fabricating a semiconductor device having semiconductor bodies of different widths according to an embodiment of the present invention.

[0060] Referring to part A of process flow 700, the formation of a hard mask 703A / 703B for fin formation above substrate 702 (e.g., above a crystalline silicon substrate) includes deposition and patterning of a hard mask layer. The patterned hard mask layer 703A / 703B includes an area 704 for thin fin formation and an area 706 for thick fin formation. The hard mask pattern 703A / 703B is then transferred to substrate 702 to form the corresponding fin. Sacrificial gate patterning and the formation of extended source and drain electrodes can then be performed. Similarly, an interlayer dielectric material can be deposited and polished to expose a sacrificial gate. The sacrificial gate is then removed. Referring to part B of process flow 700, a resist layer 708 is used to mask the fin 710B (e.g., in area 706) that will maintain a wider width. Fin thinning etching is used to reduce the fin width of fin 710A. Referring to portion C of process flow 700, resist layer 708 is removed (e.g., including an ashing process), and standard device manufacturing techniques may be performed with thinner fins 710A and wider fins 710B. In an embodiment, hard mask regions 703A / 703B are first formed by a spacer patterning process, which may be used to effectively double the pitch of the photolithography process used to form the features. Process flow 700 maintains the pitch of the spacer patterning process.

[0061] Thus, in an embodiment, a method for manufacturing a semiconductor device includes forming a hard mask pattern over a substrate. The hard mask pattern includes a first region having fin-forming features, wherein each feature has a first width. The hard mask pattern also includes a second region having fin-forming features, wherein each feature has a second width approximately equal to the first width. Subsequently, the hard mask pattern is transferred to the substrate to form a first region having fins, wherein each fin has a first width; and a second region having fins, wherein each fin has a second width. Subsequently, a resist layer is formed and etched to cover the second region having fins and expose the first region having fins. Subsequently, the fins of the first region are etched to form thinned fins, wherein each thinned fin has a third width less than the second width. Subsequently, the resist layer is removed. Subsequently, a semiconductor device is formed using the fins of the first and second regions. In one such embodiment, the substrate is a single crystal silicon substrate, and transferring the hard mask pattern to the substrate includes forming single crystal silicon fins.

[0062] The processes described herein may be used to manufacture one or more semiconductor devices. The semiconductor device may be a transistor or similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Also, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, or a FIN-FET.

[0063] Figure 8 A computing device 800 is shown in accordance with one embodiment of the present invention. The computing device 800 houses a board 802. The board 802 may include a plurality of components, including, but not limited to, a processor 804 and at least one communication chip 806. The processor 804 is physically and electrically coupled to the board 802. In some embodiments, the at least one communication chip 806 is also physically and electrically coupled to the board 802. In other embodiments, the communication chip 806 is part of the processor 804.

[0064] Depending on its application, the computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard drives, compact disks (CDs), digital versatile disks, etc.).

[0065] The communication chip 806 enables wireless communication for the transmission of data to and from the computing device 800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data via non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 806 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G and higher generations. The computing device 800 may include multiple communication chips 806. For example, the first communication chip 806 may be dedicated to shorter-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 806 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0066] The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some embodiments of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors manufactured according to embodiments of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0067] The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. According to another embodiment of the present invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors manufactured according to an embodiment of the present invention.

[0068] In further embodiments, another component housed within computing device 800 may include an integrated circuit die including one or more devices, such as MOS-FET transistors, fabricated in accordance with embodiments of the present invention.

[0069] In various embodiments, computing device 800 may be a laptop, netbook, notebook, ultrabook, smart phone, tablet computer, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, computing device 800 may be any other electronic device that processes data.

[0070] Therefore, a semiconductor device having a neck-shaped semiconductor body and a method for forming a semiconductor body of different widths have been disclosed. In an embodiment, the semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed on a portion of the semiconductor body to define a channel region in the semiconductor body below the gate electrode stack. A source region and a drain region are defined in the semiconductor body on both sides of the gate electrode stack. A sidewall spacer is disposed adjacent to the gate electrode stack and disposed on only a portion of the source region and the drain region. The portion of the source region and the drain region below the sidewall spacer has a greater height and width than the height and width of the channel region of the semiconductor body. In one embodiment, the semiconductor device is disposed above the same substrate as a second semiconductor device having a channel region, and the narrowest width of the channel region of the second semiconductor device is greater than the narrowest width of the channel region of the semiconductor device.

Claims

1. A semiconductor device, comprising: a semiconductor body disposed on a substrate; a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body beneath the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; as well as A sidewall spacer is disposed adjacent to the gate electrode stack and over only a portion of the source region and the drain region, wherein the portions of the source region and the drain region located below the sidewall spacer have a width at which the portions of the source region and the drain region located below the sidewall spacer meet the channel region, and the width is greater than a width of the channel region of the semiconductor body. 2 . The semiconductor device of claim 1 , wherein portions of the source region and the drain region that are not located under the sidewall spacers have a width greater than the width of the portions of the source region and the drain region that are located under the sidewall spacers.

3. The semiconductor device of claim 1, wherein portions of the source region and the drain region not located under the sidewall spacers have substantially the same width as the width of the portions of the source region and the drain region located under the sidewall spacers. 4 . The semiconductor device according to claim 1 , wherein at least a portion of the source region and the drain region is an epitaxial portion of the source region and the drain region. 5 . The semiconductor device of claim 4 , wherein the epitaxial portions of the source region and the drain region include a different semiconductor material than the channel region. 6 . The semiconductor device of claim 1 , wherein the substrate is a crystalline substrate, and the semiconductor body is continuous with the crystalline substrate. 7 . The semiconductor device of claim 1 , wherein a dielectric layer is disposed between the semiconductor body and the substrate, and the semiconductor body is discontinuous with the substrate.

8. The semiconductor device of claim 1, wherein the channel region has a width in the range of 10-30 nanometers, and the width of the channel region is 2-4 nanometers smaller than the width of the portions of the source region and the drain region located under the sidewall spacers.

9. The semiconductor device of claim 1, wherein the widths of the portions of the source region and the drain region located below the sidewall spacers are 6-40% greater than the width of the channel region. 10 . The semiconductor device of claim 1 , wherein the channel region is coupled to the portions of the source region and the drain region under the sidewall spacers through a step feature.

11. The semiconductor device of claim 1, wherein the channel region is coupled to the portions of the source region and the drain region under the sidewall spacers by a graded feature.

12. The semiconductor device of claim 11, wherein the graded feature comprises a facet.

13. The semiconductor device of claim 11, wherein the graded feature comprises rounded corners.

14. The semiconductor device of claim 11, wherein the grading feature reduces overlap capacitance and diffusion resistance during operation of the semiconductor device.

15. The semiconductor device of claim 1, wherein the semiconductor device is disposed over the same substrate as a second semiconductor device having a channel region, and wherein a narrowest width of the channel region of the second semiconductor device is greater than a narrowest width of the channel region of the semiconductor device.

16. A computing device comprising: plate; as well as a device coupled to the board, the device comprising an integrated circuit structure including: a semiconductor body disposed on a substrate; a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body beneath the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and A sidewall spacer is disposed adjacent to the gate electrode stack and over only a portion of the source region and the drain region, wherein the portions of the source region and the drain region located below the sidewall spacer have a width at which the portions of the source region and the drain region located below the sidewall spacer meet the channel region, and the width is greater than a width of the channel region of the semiconductor body.

17. The computing device of claim 16, further comprising: A memory is coupled to the board.

18. The computing device of claim 16, further comprising: A communication chip is coupled to the board.

19. The computing device of claim 16, wherein the device is a packaged integrated circuit die.

20. The computing device of claim 16, wherein the computing device is selected from the group consisting of: a mobile phone, a laptop, a desktop computer, a server, and a set-top box.

21. A semiconductor device comprising: a semiconductor body disposed on a substrate; a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body beneath the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; as well as A sidewall spacer disposed adjacent to the gate electrode stack and over only a portion of the source region and the drain region, wherein the portions of the source region and the drain region located below the sidewall spacer have a width greater than a width of the channel region of the semiconductor body, wherein the channel region has a width in the range of 10-30 nanometers, and the width of the channel region is 2-4 nanometers less than the width of the portions of the source region and the drain region located below the sidewall spacer.

22. A semiconductor device comprising: a semiconductor body disposed on a substrate; a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body beneath the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; as well as A sidewall spacer disposed adjacent to the gate electrode stack and over only a portion of the source region and the drain region, wherein the portions of the source region and the drain region located below the sidewall spacer have a width greater than a width of the channel region of the semiconductor body, wherein the channel region is coupled to the portions of the source region and the drain region located below the sidewall spacer by a step feature.

23. A semiconductor device comprising: a semiconductor body disposed on a substrate; a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body beneath the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; as well as A sidewall spacer disposed adjacent to the gate electrode stack and over only a portion of the source region and the drain region, wherein the portions of the source region and the drain region below the sidewall spacer have a width greater than a width of the channel region of the semiconductor body, wherein the channel region is coupled to the portions of the source region and the drain region below the sidewall spacer by a graded feature, and wherein the graded feature includes a facet.

24. A semiconductor device comprising: a semiconductor body disposed on a substrate; a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body beneath the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; as well as A sidewall spacer is disposed adjacent to the gate electrode stack and above only a portion of the source region and the drain region, wherein the portion of the source region and the drain region located below the sidewall spacer has a width greater than a width of the channel region of the semiconductor body, wherein the semiconductor device is disposed above the same substrate as a second semiconductor device having a channel region, and wherein the narrowest width of the channel region of the second semiconductor device is greater than the narrowest width of the channel region of the semiconductor device.

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