Integrated circuit and method for forming the same

Abstract

Embodiments of the present invention disclose an integrated circuit and a method for forming the same. The integrated circuit includes a first power rail, a second power rail, a signal line, and a first active region of a first group of transistors. The first power rail is on the back side of a substrate and extends in a first direction. The second power rail is on the back side of the substrate and extends in the first direction and is separated from the first power rail in a second direction different from the first direction. The signal line is on the back side of the substrate and extends in the first direction, and is between the first power rail and the second power rail. The first active region of the first group of transistors extends in the first direction and is on a first level of a front side of the substrate opposite the back side.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuits and methods of forming the same. Background Art

[0002] The recent trend of miniaturizing integrated circuits (ICs) has resulted in smaller devices that consume less power but provide more functionality at higher speeds. The miniaturization process has also led to tighter design and manufacturing specifications, as well as reliability challenges. Various electronic design automation (EDA) tools can generate, optimize, and verify standard cell layout designs for integrated circuits, while ensuring that standard cell layout design and manufacturing specifications are met. Summary of the Invention

[0003] In some embodiments, an integrated circuit includes: a first power rail on a back side of a substrate and extending in a first direction; a second power rail on the back side of the substrate, extending in the first direction, and separated from the first power rail in a second direction different from the first direction; a signal line on the back side of the substrate, extending in the first direction, and between the first power rail and the second power rail; and a first active area of ​​a first transistor group, the first active area extending in the first direction and located on a first level of a front side of the substrate opposite to the back side.

[0004] In some embodiments, an integrated circuit includes: a first power rail on a back side of a substrate and extending in a first direction, a second power rail on the back side of the substrate extending in the first direction and separated from the first power rail in a second direction different from the first direction; a first conductive structure on the back side of the substrate, the first conductive structure extending in the first direction and between the first power rail and the second power rail; a first gate extending in the second direction, overlapping at least the first conductive structure, and located on a first level on a front side of the substrate opposite the back side; and a second gate extending in the second direction, overlapping at least the first conductive structure, located on the first level, and separated from the first gate in the first direction, wherein the first conductive structure electrically couples the first gate to the second gate.

[0005] In some embodiments, the method includes: manufacturing a transistor group in a front side of a substrate; manufacturing a first via group in a back side of the substrate opposite to the front side; depositing a first conductive structure group on the back side of the substrate to form a power rail group of a first contact member group electrically connected to the transistor group through the first via group; manufacturing a second via group in the back side of the substrate; and depositing a second conductive structure group on the back side of the substrate to form a signal line group on the back side of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A-Figure 1D is a diagram of a layout design of an integrated circuit according to some embodiments.

[0008] Figure 2A-2B is a diagram of an integrated circuit according to some embodiments.

[0009] Figure 3A-3B is a diagram of a layout design of an integrated circuit according to some embodiments.

[0010] Figure 4A-4B is a diagram of an integrated circuit according to some embodiments.

[0011] Figure 5A is a diagram of a layout design according to various embodiments of the present disclosure.

[0012] Figure 5B is a top view of an integrated circuit according to some embodiments.

[0013] Figure 5C is a diagram of a layout design according to various embodiments of the present disclosure.

[0014] Figure 5D is a top view of an integrated circuit according to some embodiments.

[0015] Figure 6 is a circuit diagram of an integrated circuit according to some embodiments.

[0016] Figure 7A-7B is a diagram of an integrated circuit according to some embodiments.

[0017] Figure 8A-8B is a diagram of an integrated circuit according to some embodiments.

[0018] Figure 9A-9B is a diagram of an integrated circuit according to some embodiments.

[0019] Figure 10 is a circuit diagram of an integrated circuit according to some embodiments.

[0020] Figures 11A-11B is a diagram of an integrated circuit according to some embodiments.

[0021] Figure 12 is a circuit diagram of an integrated circuit according to some embodiments.

[0022] Figures 13A-13Bis a diagram of an integrated circuit according to some embodiments.

[0023] Figures 14A-14B is a diagram of an integrated circuit according to some embodiments.

[0024] Figure 15 is a circuit diagram of an integrated circuit according to some embodiments.

[0025] Figures 16A-16B is a diagram of an integrated circuit according to some embodiments.

[0026] Figure 17 is a flow chart of a method of forming or manufacturing an integrated circuit according to some embodiments.

[0027] Figure 18 is a flow chart of a method of generating a layout design for an integrated circuit according to some embodiments.

[0028] Figure 19 is a functional flow chart of a method of manufacturing an IC device according to some embodiments.

[0029] Figure 20 is a schematic diagram of a system for designing an IC layout and fabricating IC circuits according to some embodiments.

[0030] Figure 21 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. Repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0032] Furthermore, for ease of description, spacing terms such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spacing terms are intended to encompass different orientations of the device in use or during operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and spacing descriptors used herein should be interpreted accordingly.

[0033] According to some embodiments, the integrated circuit includes a first power rail, a second power rail, a signal line, a first gate, and a second gate. In some embodiments, the integrated circuit further includes a first contact and a second contact of the first transistor group.

[0034] In some embodiments, the first power rail is on the back side of the substrate or wafer and extends in a first direction. In some embodiments, the second power rail is on the back side of the substrate, extends in the first direction, and is separated from the first power rail in a second direction different from the first direction. In some embodiments, the signal line is on the back side of the substrate, extends in the first direction, and is between the first power rail and the second power rail.

[0035] In some embodiments, the first gate and the second gate extend in the second direction, overlap at least the signal line, and are located on a first level on a front side of the substrate opposite to the back side.

[0036] In some embodiments, the signal line electrically couples the first gate to the second gate. In some embodiments, the signal line electrically couples the first contact to the second contact.

[0037] In some embodiments, by electrically coupling a first gate and a second gate or electrically coupling a first contact and a second contact through a signal line, at least one upper metal layer track in an integrated circuit of the present disclosure is lowered, resulting in an integrated circuit with better current resistance (IR), electromigration (EM), and resistance-capacitance (RC) metal performance compared to other methods.

[0038] In some embodiments, by positioning the first power rail, the second power rail, and the signal line on the back side of the substrate, the gate density of the integrated circuit of the present disclosure is increased compared to other approaches. In some embodiments, by positioning the first power rail, the second power rail, and the signal line on the back side of the substrate, the integrated circuit of the present disclosure provides greater routing flexibility and increases routing resources compared to other approaches.

[0039] Figure 1A-1D is a diagram of a layout design 100 for an integrated circuit according to some embodiments. Layout design 100 is Figure 2A-2B Layout diagram of integrated circuit 200.

[0040] Figure 1A-1C yes Figure 1D FIG. 1 is a diagram of corresponding portions 100A-100C of layout design 100, which are simplified for ease of illustration. Figure 1D is a diagram of a layout design 100 including portions 100A, 100B, and 100C, and is simplified for ease of illustration.

[0041] For ease of explanation, Figure 1A-Figure 1D Some of the marked elements in Figure 1A-1D In some embodiments, the layout design 100 includes Figure 1A-1D Additional elements not shown.

[0042] Portion 100A includes the buried power (BP) level of layout design 100. Figure 1D The portion 100B includes one or more features of the layout design 100 of the oxide diffusion (OD) level, the gate (POLY) level, the diffusion metal (MD) level, the via buried power (VBP) level, and the via buried signal (VBS) level of the layout design 100. Figure 1D of Figure 1D One or more features of layout design 100 of FIG. 100C includes the metal 0 (M0) level of layout design 100. Figure 1D One or more features of the layout design 100 .

[0043] Layout design 100 can be used for manufacturing Figure 2A-2B integrated circuit 200.

[0044] Layout design 100 has cell boundary 101 a and cell boundary 101 b extending in a first direction X. Layout design 100 has a height (not labeled) extending from cell boundary 101 b to cell boundary 101 a in a second direction Y. In some embodiments, second direction Y is different from first direction X. In some embodiments, layout design 100 abuts other cell layout designs (not shown) along cell boundaries 101 a and 101 b.

[0045] The layout design 100 includes one or more power rail layout patterns 102a or 102b extending along a first direction X and located on a first layout layer. For simplicity, embodiments of the present disclosure use the term “layout pattern”, which is hereinafter also referred to as “pattern” in the rest of the disclosure.

[0046] One or more power rail patterns 102a or 102b are collectively referred to as a "power rail pattern group 102". In some embodiments, the first layout level corresponds to the layout design 100 or 300 ( Figure 1A-1D or Figure 3A-3B), integrated circuit 200 or 400 ( Figure 2A-2B or Figure 4A-4B ), or layout 500A-500B, 700, 800, 900, 1100, 1300, 1400 or 1600 ( Figure 5A-5B 、 Figure 7A-7B 、 Figure 8A-8B 、 Figure 9A-9B 、 Figures 11A-11B 、 Figures 13A-13B 、 Figures 14A-14B or Figures 16A-16B ) of one or more buried power (BP) levels or buried signal (BS) levels.

[0047] The power rail pattern set 102 can be used to manufacture the integrated circuit 200 or 400 ( Figure 2A-2B or Figure 4A-4B ) of the corresponding power rail group 202. In some embodiments, the power rail group 202 is located on the back side 220a of the integrated circuit 200 or 400. In some embodiments, the power rail patterns 102a, 102b, 102c in the power rail pattern group 102 can be used to manufacture the corresponding power rail group 202 ( Figure 2A-2B ) of power rail patterns 202a, 202b, 202c.

[0048] In some embodiments, power rail patterns 102a and 102b of power rail pattern group 102 are positioned along corresponding cell boundaries 101a and 101b of layout design 100. Other configurations, arrangements on other layout levels, or numbers of patterns in power rail pattern group 102 are within the scope of the present disclosure.

[0049] The layout design 100 further includes one or more signal line patterns 103a (collectively referred to as "signal line pattern group 103") extending along the first direction X and located on the first layout layer. In some embodiments, the signal line pattern group 103 includes more than one signal line pattern (e.g., Figure 14B In some embodiments, the signal line pattern group is at the BS level.

[0050] The signal line pattern group 103 can be used to manufacture the integrated circuit 200 or 400 ( Figure 2A-2B or Figure 4A-4B ) of the corresponding signal line group 203. In some embodiments, the signal line group 203 is located on the back side 220a of the integrated circuit 200 or 400. In some embodiments, the signal line pattern 103a can be used to manufacture the corresponding signal line 203a ( Figure 2A-2B ).

[0051] In some embodiments, the signal line pattern 103 a is located between the power rail patterns 102 a and 102 b . In some embodiments, the signal line pattern 103 a of the signal line pattern group 103 is located along the midpoint 101 c of the layout design 100 in the first direction X.

[0052] Other configurations of the signal line pattern group 103 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0053] The layout design 100 further includes one or more active area patterns 104a or 104b (collectively referred to as "active area pattern group 104") extending in the first direction X. The active area patterns 104a, 104b of the active area pattern group 104 are separated from each other in the second direction Y. The active area pattern group 104 can be used to manufacture the corresponding active area group 204 ( Figure 2A-2B In some embodiments, the active area group 204 is located on the front side of the integrated circuit 200 or 400. In some embodiments, the active area patterns 104a, 104b of the active area pattern group 104 can be used to manufacture the active area 204 ( Figure 2A-2B or Figure 4A-4B ) corresponding active regions 204a, 204b.

[0054] In some embodiments, the active area pattern group 104 is referred to as an oxide diffusion (OD) region, which defines at least the integrated circuit 200, 400, 600, 1000, 1200, or 1500 ( Figure 2A-2B 、 Figure 4A-4B 、 Figure 6 、 Figure 10 、 Figure 12 or Figure 15 ) or layout 500A-500B, 700, 800, 900, 1100, 1300, 1400 or 1600 ( Figure 5A-5B 、 Figure 7A-7B 、 Figure 8A-8B 、 Figure 9A-9B 、 Figures 11A-11B 、 Figures 13A-13B 、 Figures 14A-14B or Figures 16A-16B ) source or drain diffusion region.

[0055] In some embodiments, one of the active area patterns 104 a or 104 b in the active area pattern group 104 may be used to fabricate source and drain regions of NMOS transistors of the integrated circuits 600 , 1000 , 1200 , and 1500 , and the other active area pattern 104 a or 104 b in the active area pattern group 104 may be used to fabricate source and drain regions of PMOS transistors of the integrated circuits 600 , 1000 , 1200 , and 1500 .

[0056] In some embodiments, the active area pattern group 104 is located at a second layout level. In some embodiments, the second layout level is higher than the first layout level. In some embodiments, the second layout level corresponds to the layout design 100 or 300 ( Figure 1A-1D or Figure 3A-3B ), integrated circuit 200 or 400 ( Figure 2A-2B or Figure 4A-4B ) or layout 500A-500B, 700, 800, 900, 1100, 1300, 1400 or 1600 ( Figure 5A-5B 、 Figure 7A-7B 、 Figure 8A-8B 、 Figure 9A-9B 、 Figures 11A-11B 、 Figures 13A-13B 、 Figures 14A-14B or Figures 16A-16B ) in one or more active levels or OD levels. In some embodiments, the BP or BS level is lower than the OD level.

[0057] Other configurations of the active area pattern group 104 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0058] The layout design 100 further includes one or more contact patterns 106a, 106b, 106c, or 106d (collectively referred to as "contact pattern group 106") extending in the second direction Y. Each contact pattern in the contact pattern group 106 is separated from adjacent contact patterns in the contact pattern group 106 in the first direction X. The contact pattern group 106 can be used to manufacture a corresponding contact group 206 of the integrated circuit 200. Figure 2A-2B In some embodiments, the contact patterns 106a, 106b, 106c, or 106d of the contact pattern group 106 can be used to manufacture corresponding contacts 206a, 206b, 206c, or 206d of the contact pattern group 206. In some embodiments, the contact pattern group 106 is also referred to as a metal-on-diffusion (MD) pattern group.

[0059] In some embodiments, at least one of the contact patterns 106a or 106b in the contact pattern group 106 can be used to manufacture the source and drain terminals of one of the NMOS or PMOS transistors of the integrated circuits 600, 1000, 1200 and 1500, and at least the contact pattern 106c or 106d in the contact pattern group 106 can be used to manufacture the source and drain terminals of another PMOS or NMOS transistor of the integrated circuits 600, 1000, 1200 and 1500.

[0060] In some embodiments, the contact pattern group 106 overlaps the active area pattern group 104. In some embodiments, at least the contact pattern 106a or 106b is above the active area pattern 104a. In some embodiments, at least the contact pattern 106c or 106d is above the active area pattern 104b.

[0061] The contact pattern group is located on a third layout level. In some embodiments, the third layout level is different from the first layout level and the second layout level. In some embodiments, the third layout level is above the first layout level and the second layout level. In some embodiments, a first portion of the third layout level is above the first layout level and the second layout level, and a second portion of the third layout level is below the first layout level and the second layout level. In some embodiments, the third layout level corresponds to layout design 100 or 300 ( Figure 1A-1D or Figure 3A-3B ), integrated circuit 200 or 400 ( Figure 2A-2B or Figure 4A-4B ) or layout 500A-500B, 700, 800, 900, 1100, 1300, 1400 or 1600 ( Figure 5A-5B 、 Figure 7A-7B 、 Figure 8A-8B 、 Figure 9A-9B 、 Figures 11A-11B 、 Figures 13A-13B 、 Figures 14A-14B or Figures 16A-16B ) in one or more contact levels or MD levels.

[0062] Other configurations of the contact pattern groups 106 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0063] The layout design 100 also includes one or more via patterns 108a or 108b (collectively referred to as "via pattern group 108"). The via pattern group 108 can be used to manufacture a corresponding via group 208 ( Figure 2A-2B In some embodiments, the via patterns 108a, 108b of the via pattern group 108 may be used to manufacture the via group 208 of the integrated circuit 200 ( Figure 2A-2B ) in the corresponding through holes 208a, 208b.

[0064] In some embodiments, the via pattern group 108 is between the power rail pattern group 102 and the active area pattern group 106. In some embodiments, the via pattern group 108 is between the power rail pattern group 102 and the contact pattern group 106.

[0065] The via pattern group 108 is positioned on the layout design 100 or 300 ( Figure 1A-1D or Figure 3A-3B ), integrated circuit 200 or 400 ( Figure 2A-2B or Figure 4A-4B ) or layout 500A-500B, 700, 800, 900, 1100, 1300, 1400 or 1600 ( Figure 5A-5B 、 Figure 7A-7B 、 Figure 8A-8B 、 Figure 9A-9B 、 Figures 11A-11B 、 Figures 13A-13B 、 Figures 14A-14B or Figures 16A-16B ) at a through-hole buried power (VBP) level of one or more of the BP levels. In some embodiments, the VBP level is between the BP level and at least the OD level or the MD level. In some embodiments, the VBP level is between the first layout level and at least the second layout level or the third layout level. Other layout levels are within the scope of the present disclosure.

[0066] Via pattern 108a is between power rail pattern 102a and active area pattern 104a. In some embodiments, via pattern 108a is between power rail pattern 102a and contact pattern 106b. Via pattern 108b is between power rail pattern 102b and active area pattern 104b. In some embodiments, via pattern 108b is between power rail pattern 102b and contact pattern 106c. In some embodiments, at least one via pattern in via pattern group 108 is not included in layout design 100.

[0067] Other configurations of the via pattern group 108 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0068] The layout design 100 also includes one or more via patterns 110a or 110b (collectively referred to as "via pattern group 110"). The via pattern group 110 can be used to manufacture a corresponding via group 210 ( Figure 2A-2B In some embodiments, the through hole patterns 110a and 110b of the through hole pattern group 110 can be used to manufacture the through hole group 210 of the integrated circuit 200 ( Figure 2A-2B ) in the corresponding through holes 210a, 210b.

[0069] In some embodiments, the via pattern group 110 is between the signal line pattern group 103 and the contact pattern group 106 .

[0070] The through hole pattern group 110 is located in the layout design 100 or 300 ( Figure 1A-1D or Figure 3A-3B ), integrated circuit 200 or 400 ( Figure 2A-2B or Figure 4A-4B ) or layout 500A-500B, 700, 800, 900, 1100, 1300, 1400 or 1600 ( Figure 5A-5B 、 Figure 7A-7B 、 Figure 8A-8B 、 Figure 9A-9B 、 Figures 11A-11B 、 Figures 13A-13B 、 Figures 14A-14B or Figures 16A-16B ) in one or more of the via buried signal (VBS) levels. In some embodiments, the VBS level is between the BS level and the MD level. In some embodiments, the VBS level is between the first layout level and at least the third layout level. In some embodiments, the VBS level and the VBP level are the same. Other layout levels are within the scope of the present disclosure.

[0071] The via pattern 110 a is located between the signal line pattern 103 a and the contact pattern 106 a . The via pattern 110 b is located between the signal line pattern 103 a and the contact pattern 106 d . In some embodiments, at least one via pattern in the via pattern group 110 is not included in the layout design 100 .

[0072] Other configurations of the via pattern group 110 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0073] Layout design 100 also includes one or more gate patterns 116a, 116b, or 116c (collectively referred to as "gate pattern group 116") extending in the second direction Y. Gate pattern 116 is separated from adjacent gate patterns in gate pattern group 116 in the first direction X by a first pitch (not shown).

[0074] The gate pattern group 116 can be used to manufacture the integrated circuit 200 ( Figure 2A-2B ) of the corresponding gate group 216. In some embodiments, the gate patterns 116a, 116b, 116c of the gate pattern group 116 are gate groups 216 ( Figure 2A-2B ) in the corresponding gates 216a, 216b, 216c.

[0075] In some embodiments, at least a portion of the gate patterns 116 a, 116 b, or 116 c in the gate pattern group 116 may be used to manufacture the gates of the NMOS transistors of the integrated circuits 600 , 1000 , 1200 , and 1500 , and at least a portion of the gate patterns 116 a, 116 b, or 116 c in the gate pattern group 116 may be used to manufacture the gates of the PMOS transistors of the integrated circuits 600 , 1000 , 1200 , and 1500 .

[0076] The gate pattern group 116 is located above the power rail pattern group 102, the signal line pattern group 103, and the active area pattern group 104. The gate pattern group 116 is located on a fourth layout level (POLY) that is different from the first and second layout levels. In some embodiments, the fourth layout level is the same as the third layout level. In some embodiments, the fourth layout level is different from the third layout level.

[0077] Other configurations of the gate pattern group 116 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0078] The layout design 100 further includes one or more conductive component patterns 112a, 112b, 112c, 112d, or 112e (collectively referred to as "conductive component pattern group 112") extending in the first direction X and located on a fifth layout level. In some embodiments, the fifth layout level is different from the first layout level, the second layout level, the third layout level, and the fourth layout level. In some embodiments, the fifth layout level corresponds to the layout design 100 or 300 ( Figure 1A-1D or Figure 3A-3B ), integrated circuit 200 or 400 ( Figure 2A-2B or Figure 4A-4B ) or layout 500A-500B, 700, 800, 900, 1100, 1300, 1400 or 1600 ( Figure 5A-5B 、 Figure 7A-7B 、 Figure 8A-8B 、 Figure 9A-9B 、 Figures 11A-11B 、 Figures 13A-13B 、 Figures 14A-14B or Figures 16A-16B ) in one or more metal 0 (M0) levels.

[0079] In some embodiments, the M0 level is higher than the OD level, the BPR level, the MD level, and the POLY level.

[0080] The conductive feature pattern set 112 can be used to manufacture a corresponding conductive structure set 212 of the integrated circuit 200 ( Figure 2A-2B The conductive component patterns 112a, 112b, 112c, 112d, 112e can be used to manufacture corresponding conductive structures 212a, 212b, 212c, 212d, 212e ( Figure 2A-2B and Figure 4A-4B ).

[0081] The conductive component pattern group 112 overlaps at least one power rail pattern in the power rail pattern group 102. In some embodiments, the conductive component pattern group 112 overlaps other underlying patterns (not shown for ease of illustration) of the conductive component pattern group 102. For ease of illustration, the layout design does not show via patterns (e.g., via-on-diffusion (VD) or via-on-gate (VG)) located between the conductive component pattern group 112 and at least the gate pattern 112 or the contact pattern group 106.

[0082] In some embodiments, each pattern 112a, 112b, 112c, 112d, 112e of the conductive component pattern group 112 overlaps with a corresponding grid line 114a, 114b, 114c, 114d, 114e of the grid line group 114. The center of each pattern 112a, 112b, 112c, 112d, 112e of the conductive component pattern group 112 is aligned with the corresponding grid line 114a, 114b, 114c, 114d, 114e of the grid line group 114 in the first direction X.

[0083] At least one of the conductive component patterns 112a, 112b, 112c, 112d, or 112e in the conductive component pattern group 112 has a width W1 in the second direction Y. Other widths of the conductive component pattern group 112 are within the scope of the present disclosure. In some embodiments, at least one conductive component pattern in the conductive component pattern group 112 has a width in the second direction Y that is different from the width W1.

[0084] In some embodiments, the conductive component patterns 112a, 112b, 112c, 112d, 112e of the conductive component pattern group 112 correspond to five M0 routing tracks in the layout design 100. Other numbers of M0 routing tracks are within the scope of the present invention. For example, in some embodiments, Figure 5A-5B 、 Figure 8A-8B 、 Figure 9A-9B 、 Figures 13A-13B 、 Figures 14A-14B and Figures 16A-16B Each of the Figure 1A-Figure 1D The number of M0 wiring tracks.

[0085] Other configurations of the conductive feature pattern groups 112 , arrangements on other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0086] Other configurations of layout design 100 , arrangements at other layout levels, or numbers of patterns are within the scope of the present disclosure.

[0087] In some embodiments, conductive feature pattern group 112 is an upper metal layer track located on the M0 layer, Metal 1 (M1) level, on the front side of layout design 100 or 300. In an embodiment, power rail pattern group 102 and signal line pattern group 103 are moved from the front side of layout design 100 or 300 to the back side of layout design 100 or 300, when compared to other approaches. In an embodiment, moving power rail pattern group 102 and signal line pattern group 103 from the front side of layout design 100 or 300 to the back side of layout design 100 or 300 results in layout design 100 or 300 using at least one fewer upper metal layer track in conductive feature pattern group 112, resulting in a layout design having a smaller height and a smaller area compared to other approaches.

[0088] In some embodiments, due to the reduction of at least one upper metal layer track in conductive feature pattern group 112, the width of one or more conductive feature patterns in conductive feature pattern group 112 is increased, thereby resulting in a layout design 100 or 300 having better current resistance (IR), electromigration (EM), and resistance-capacitance (RC) metal performance compared to other approaches. In some embodiments, by utilizing the power rail pattern group 102 or signal line pattern group 103 of the present disclosure, the gate density of the gate pattern group 116 or 316 of the layout design 100 or 300 is increased compared to other approaches. In some embodiments, by utilizing at least the power rail pattern group 102 or signal line pattern group 103 of the present disclosure, the layout design 100 or 300 provides greater routing flexibility and increased routing resources compared to other approaches.

[0089] Figures 2A to 2B is a diagram of an integrated circuit 200 according to some embodiments.

[0090] Figure 2A is a top view of an integrated circuit 200 according to some embodiments. Figure 2B is a cross-sectional view of an integrated circuit 200 according to some embodiments. Figure 2B is a cross-sectional view of the integrated circuit 200 intersecting the plane AA' according to some embodiments. Figure 2A-2B and Figure 4A-4B The same or similar components (as shown below) are given the same reference numerals, and thus detailed descriptions thereof are omitted.

[0091] The integrated circuit 200 is manufactured from the layout design 100. The structural relationship including alignment, length and width and the configuration and layer of the integrated circuit 200 are Figure 1A-1D The structural relationship and configuration of the layout design 100 are similar to the layers. For simplicity, at least Figure 2A-2B Similar detailed description will not be described again.

[0092] The integrated circuit 200 includes at least a power rail group 202 , a signal line group 203 , an active area group 204 , a contact group 206 , a via group 208 , a via group 210 , a conductive structure group 212 , or a gate group 216 .

[0093] Power rail group 202 includes one or more power rails 202a or 202b. In some embodiments, power rail group 202 is configured to provide a first power supply voltage of voltage source VDD or a second power supply voltage of reference voltage source VSS to an integrated circuit such as integrated circuit 200. The first power supply voltage is different from the second power supply voltage.

[0094] In some embodiments, power rail 202a is configured to provide a first power supply voltage of voltage supply VDD, and power rail 202b is configured to provide a second power supply voltage of reference voltage supply VSS. In some embodiments, power rail 202a is configured to provide a second power supply voltage of reference voltage supply VSS, and power rail 202b is configured to provide a first power supply voltage of voltage supply VDD. In some embodiments, power rail group 202 is configured to provide power to active area group 204.

[0095] The signal line group 203 includes at least a signal line 203a. The signal line group 203 is configured to provide routing for signals from an upper layer. For example, in some embodiments, the signal line group 203 is configured to provide routing for signals between active areas of the active area group 204 or between contacts of the group contact 206. In some embodiments, the signal line 203a is configured to electrically couple the drain or source of a PMOS or NMOS transistor with the drain or source of another PMOS or NMOS transistor. In some embodiments, the signal line group 203 is configured to electrically couple the active area group of the integrated circuit 200, resulting in additional routing resources compared to other methods. In some embodiments, the signal line group 203 is configured to electrically couple the gate group 416 ( Figure 4A-4B ), resulting in additional routing resources compared to other methods.

[0096] In some embodiments, the signal line group 203 corresponds to the conductive structure group. In some embodiments, the signal line group 203 is located below at least the gate group 216 , the OD layer, the M0 layer, and the MD layer of the integrated circuit 200 or 400 .

[0097] The set of signal lines 203 is between the set of active areas 204. In some embodiments, the top surface of signal line 203a is below the bottom surface of at least active area 204a or 204b or at least contact 206a, 206b, 206c, or 206d.

[0098] In some embodiments, the power rail group 202 and the signal line group 203 are located on the back side 220 a of the substrate 201 of the integrated circuit 200 or 400. In some embodiments, the active area group 204 is located on the front side 220 b of the substrate 201 of the integrated circuit 200 or 400, with the front side 220 b of the integrated circuit 200 being opposite to the back side 220 a of the integrated circuit 200 or 400 in the second direction Y. By positioning the power rail group 202 or the signal line group 203 on the back side 220 a of the integrated circuit 200, the integrated circuit 200 or 400 occupies less area than other methods.

[0099] Other configurations of the power rail group 202 or the signal line group 203 , arrangements on other layout levels, or numbers of structures are within the scope of the present disclosure.

[0100] Active area group 204 includes one or more active areas 204a or 204b in substrate 201. In some embodiments, active area group 204 corresponds to a planar structure (not shown) of a planar transistor. In some embodiments, active area group 204 corresponds to a fin structure (not shown) of a finFET. In some embodiments, active area group 204 corresponds to a nanosheet structure (not shown) of a nanosheet transistor. In some embodiments, active area group 204 corresponds to a nanowire structure (not shown) of a nanowire transistor. In some embodiments, active area group 204 includes drain and source regions grown by an epitaxial growth process. In some embodiments, active area group 204 includes drain and source regions grown together with epitaxial material at the respective drain and source regions.

[0101] In some embodiments, one of the active areas 204 a or 204 b of the active area group 204 corresponds to the source and drain regions of the NMOS transistors of the integrated circuits 200 , 400 , 600 , 1000 , 1200 , and 1500 , while the other of the active areas 204 b or 204 a of the active area group 204 corresponds to the source and drain regions of the PMOS transistors of the integrated circuits 200 , 400 , 600 , 1000 , 1200 , and 1500 .

[0102] In some embodiments, the active area group 204 is above the power rail group 202 and the signal line group 203. Other configurations of the active area group 204, arrangements on other layout levels, or numbers of structures are within the scope of the present disclosure.

[0103] Contact set 206 includes one or more of contacts 206 a, 206 b, 206 c, or 206 d. In some embodiments, at least one of contacts 206 a, 206 b, 206 c, or 206 d in contact set 206 corresponds to a source and a drain terminal of an NMOS transistor of integrated circuits 200, 600, 1000, 1200, and 1500, and at least another of contacts 206 a, 206 b, 206 c, or 206 d in contact set 206 corresponds to a source and a drain terminal of a PMOS transistor of integrated circuits 200, 600, 1000, 1200, and 1500.

[0104] In some embodiments, contact set 206 is above active area set 204, power rails 202, and signal lines 203. In some embodiments, contact set 206 encloses active area set 204. In some embodiments, a first portion of contact set 206 is above active area 204 and a second portion of contact set 206 is below active area 204.

[0105] Other configurations in the contact set 206 , arrangements on other layout levels, or numbers of contacts are within the scope of the present disclosure.

[0106] The via group 208 includes one or more vias 208a or 208b. In some embodiments, the via group 208 is between the power rail group 202 and the active area group 206. In some embodiments, the via group 208 is between the power rail group 202 and the contact group 206.

[0107] Via 208a is between power rail 202a and active area 204a, thereby providing an electrical connection between power rail 202a and active area 204a. In some embodiments, via 208a is between power rail 202a and contact 206b, thereby providing an electrical connection between power rail 202a and at least contact 206b or active area 204a.

[0108] Via 208b is located between power rail 202b and active area 204b, thereby providing an electrical connection between power rail 202b and active area 204b. In some embodiments, via 208b is located between power rail 202b and contact 206c, thereby providing an electrical connection between power rail 202b and at least contact 206c or active area 204b.

[0109] In some embodiments, at least one via in via group 208 is not included in integrated circuit 200. Other configurations, arrangements on other layout levels, or numbers of vias in via group 208 are within the scope of the present disclosure.

[0110] The through-hole group 210 includes one or more through-holes 210 a or 210 b and is located between the signal line group 203 and the contact group 206 .

[0111] The via 210a is located between the signal line 203a and the contact 206a, thereby providing an electrical connection between the signal line 203a and the contact 206a. The via 210b is located between the signal line 203a and the contact 206d, thereby providing an electrical connection between the signal line 203a and the contact 206d.

[0112] Active region 204a is electrically connected to contact 206a. Contact 206a is electrically coupled to signal line 203a through via 210a. Signal line 203a is electrically coupled to contact 206d through via 210b. Contact 206d is electrically coupled to active region 204b.

[0113] In some embodiments, at least one via in via group 210 is not included in integrated circuit 200. Other configurations, arrangements on other layout levels, or numbers of vias in via group 210 are within the scope of the present disclosure.

[0114] Other electrical connections between one or more of the signal line set 203 , the active area set 204 , the contact set 206 , and the via set 210 are within the scope of the present disclosure.

[0115] Gate group 216 includes one or more gates 216a, 216b, or 216c. In some embodiments, at least a portion of gates 216a, 216b, or 216c in the gate group corresponds to a gate of an NMOS transistor of integrated circuits 200, 600, 1000, 1200, and 1500, and at least a portion of gates 216a, 216b, or 216c corresponds to a gate of a PMOS transistor of integrated circuits 200, 600, 1000, 1200, and 1500. Gate group 216 is above power rail group 202, signal line group 203, and active area group 204.

[0116] Other configurations in gate group 216 , arrangements on other layout levels, or numbers of gates are within the scope of the present disclosure.

[0117] The conductive component set 212 includes one or more conductive components 212a, 212b, 212c, 212d, or 212e.

[0118] The conductive feature group 212 overlaps at least one power rail in the power rail group 202 or the signal line group 203. In some embodiments, the conductive feature group 212 overlaps other underlying features (other layout levels of the integrated circuit 200 or 400 are not shown for ease of illustration). For example, the integrated circuit 200 does not show vias (e.g., VD or VG) between the conductive feature group 212 and at least the gate group 216 or the contact 206 for ease of illustration.

[0119] At least one conductive feature 212a, 212b, 212c, 212d, or 212e in the conductive feature group 212 has a width W1′ in the second direction Y. Other widths of the conductive feature group 212 are within the scope of the present disclosure. In some embodiments, at least one conductive feature in the conductive feature group 212 has a width in the second direction Y that is different from the width W1′.

[0120] Other configurations in the conductive feature group 212 , arrangements on other layout levels, or numbers of conductive features are within the scope of the present disclosure.

[0121] In some embodiments, at least one power rail in power rail group 202, at least one signal line in signal line group 203, at least one contact in contact group 206 or 406, at least one through-hole in through-hole group 208, at least one through-hole in through-hole group 210 or 410, or at least one conductive structure in conductive structure group 212, 512', or 514' comprises one or more layers of conductive material, metal, metal compound, or doped semiconductor. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, or the like, or a combination thereof. In some embodiments, the metal comprises at least Cu (copper), Co, W, Ru, Al, or the like. In some embodiments, the metal compound comprises at least AlCu, W-TiN, TiSi x 、NiSi x , TiN, TaN, etc. In some embodiments, the doped semiconductor includes at least doped silicon, etc.

[0122] In some embodiments, the conductive feature group 212 is an upper metal layer track located at the M0 level or the M1 level on the front side of the integrated circuit 200 or 400. In some embodiments, the power rail group 202 and the signal line group 203 are moved from the front side of the integrated circuit 200 to the back side of the integrated circuit 200, compared to other approaches. In some embodiments, moving the power rail group 202 and the signal line group 203 from the front side of the integrated circuit 200 to the back side of the integrated circuit 200 results in the integrated circuit 200 or 400 using at least one smaller upper metal layer track in the conductive feature group 212, thereby resulting in an integrated circuit (e.g., the integrated circuit 200 or 400) having a smaller height and a smaller area compared to other approaches.

[0123] In some embodiments, by reducing at least one upper metal layer track in the conductive feature group 212, the width of one or more conductive features in the conductive feature group 212 is increased, thereby enabling the integrated circuit 200 or 400 to have better current resistance (IR), electromigration (EM), and resistance-capacitance (RC) metal performance compared to other approaches. In some embodiments, by utilizing the power rail group 202 or signal line group 203 of the present disclosure, the gate density of the gates 216 or 416 of the integrated circuit 200 or 400 is increased compared to other approaches. In some embodiments, by utilizing at least the power rail group 202 or signal line group 203 of the present disclosure, the integrated circuit 200 or 400 provides greater routing flexibility and increased routing resources compared to other approaches.

[0124] Figure 3A-3B is a diagram of a layout design 300 for an integrated circuit according to some embodiments. Layout design 300 is Figure 4A-4B Layout diagram of integrated circuit 400.

[0125] Figure 3A yes Figure 3B For ease of illustration, the corresponding portion 300A of the layout design 300 is simplified. Figure 3B . Figure 3B is a diagram of a layout design 300 and includes a portion 100A ( Figure 1A ), parts 300A and 100C ( Figure 1C ), simplified for ease of explanation. Figure 1A and Figure 1C Some of the marked elements in Figure 3A-Figure 3B In some embodiments, the layout design 300 includes Figure 3A-3B Additional elements not shown.

[0126] Part 300A is Figure 1B The portion 300A includes the OD level, POLY level, MD level, VBP level and VBS level of the layout design 300. Figure 3B One or more components of the layout design 300 .

[0127] Layout design 300 can be used for manufacturing Figure 4A-4B integrated circuit 400.

[0128] Layout design 300 is a copy of layout design 100 ( Figure 1A-1D For example, layout design 300 illustrates an example in which a VBS level (eg, signal line pattern group 203 ) is used for additional routing resources to electrically couple at least gate pattern pair 316 .

[0129] and Figure 1A-1D Compared with the layout design 100, the contact pattern group 306 of the layout design 300 replaces the contact pattern group 106, the via pattern group 310 replaces the via pattern group 110, and the gate pattern group 316 of the layout design 300 replaces the gate pattern group 116, so similar detailed descriptions are omitted.

[0130] The layout design 100 includes a power rail pattern group 102, a signal line pattern group 103, an active area pattern group 104, a contact pattern group 306, a through hole pattern group 108 (in Figure 3A-Figure 3B ), a via pattern group 310 , a conductive feature pattern group 112 , and a gate pattern group 316 .

[0131] The contact pattern group 306 includes one or more contact patterns 306a, 306b, 306c, 306d, 306e, or 306f. At least one of the contact patterns 306a, 306b, 306c, 306d, 306e, or 306f is similar to at least one of the contact patterns 106a, 106b, 106c, or 106d, and thus similar detailed description is omitted.

[0132] The contact pattern set 306 can be used to manufacture a corresponding contact set 406 ( Figure 4A-4B In some embodiments, the contact pattern 306 a , 306 b , 306 c , 306 d , 306 e , or 306 f of the contact pattern group 306 may be used to manufacture a corresponding contact 406 a , 406 b , 406 c , 406 d , 406 e , or 406 f of the contact pattern group 406 .

[0133] In some embodiments, at least one of the contact patterns 306a, 306b, 306c, or 306d in the contact pattern group 306 may be used to fabricate the source and drain terminals of one of the NMOS or PMOS transistors of the integrated circuit 600, 1000, 1200, and at least one of the contact patterns 306e, 306f, 306g, or 306h in the contact pattern group 306 may be used to fabricate the source and drain terminals of another PMOS or NMOS transistor of the integrated circuit 600, 1000, 1200, and 1500.

[0134] In some embodiments, the contact pattern group 306 overlaps the active area pattern group 104. In some embodiments, at least the contact pattern 306a, 306b, 306c, or 306d is above the active area pattern 104a. In some embodiments, at least the contact pattern 306e, 306f, 306g, or 306h is above the active area pattern 104b.

[0135] Other configurations, arrangements on other layout levels, or numbers of patterns in the contact pattern group 306 are within the scope of the present disclosure.

[0136] The via pattern group 310 includes one or more via patterns 310a or 310b. At least one of the via patterns 310a or 310b is similar to at least one of the via patterns 110a or 110b, and thus similar detailed description is omitted.

[0137] The through hole pattern group 310 can be used to manufacture the corresponding through hole group 410 ( Figure 4A-4B In some embodiments, the through hole patterns 310a, 310b of the through hole pattern group 310 can be used to manufacture the through hole group 410 of the integrated circuit 400 ( Figure 4A-4B ) in the corresponding through holes 410a, 410b.

[0138] In some embodiments, the via pattern group 310 is located between the signal line pattern group 103 and the gate pattern group 316. The via pattern 310a is located between the signal line pattern 103a and the gate pattern 316b. In some embodiments, the via pattern 310a is located where the gate pattern 316b overlaps with the signal line pattern 103a. The via pattern 310b is located between the signal line pattern 103a and the gate pattern 316d. In some embodiments, the via pattern 310b is located where the gate pattern 316d overlaps with the signal line pattern 103a. In some embodiments, at least one via pattern in the via pattern group 310 is not included in the layout design 300.

[0139] Other configurations, arrangements on other layout levels, or numbers of patterns in the via pattern group 310 are within the scope of the present disclosure.

[0140] Gate pattern group 316 includes one or more gate patterns 316a, 316b, 316c, 316d, or 316e. At least one of gate patterns 316a, 316b, 316c, 316d, or 316e is similar to at least one of gate patterns 116a, 116b, or 116c, and thus similar detailed description is omitted.

[0141] The gate pattern group 316 can be used to manufacture the integrated circuit 400 ( Figure 4A-4B ) of the corresponding gate group 416. In some embodiments, the gate patterns 316a, 316b, 316c, 316d, 316e of the gate pattern group 316 can be used to manufacture the gate group 416 ( Figure 4A-4B )'s corresponding gates 416a, 416b, 416c, 416d, 416e.

[0142] In some embodiments, at least a portion of the gate patterns 316a, 316b, 316c, 316d, or 316e in the gate pattern group 316 may be used to manufacture the gates of the NMOS transistors of the integrated circuits 600, 1000, 1200, and 1500, and at least a portion of the gate patterns 316a, 316b, 316c, 316d, or 316e in the gate pattern group 316 may be used to manufacture the gates of the PMOS transistors of the integrated circuits 600, 1000, 1200, and 1500.

[0143] The gate pattern 316b overlaps the via pattern 310a and the signal line pattern 103a. The gate pattern 316d overlaps the via pattern 310b and the signal line pattern 103a.

[0144] Other configurations, arrangements on other layout levels, or numbers of patterns in the gate pattern group 316 are within the scope of the present disclosure.

[0145] Other overlapping locations or numbers of overlapping locations between one or more of the gate pattern group 316 , the via pattern group 310 , and the signal line pattern group 103 are within the scope of the present disclosure.

[0146] Figure 4A-4B is a diagram of an integrated circuit 400 according to some embodiments.

[0147] Figure 4A is a top view of an integrated circuit 400 according to some embodiments. Figure 4B is a cross-sectional view of an integrated circuit 400 according to some embodiments. Figure 4B is a cross-sectional view of the integrated circuit 400 intersecting the plane BB′, according to some embodiments.

[0148] The integrated circuit 400 is manufactured from the layout design 400. The structural relationship including alignment, length and width and the configuration and layer of the integrated circuit 400 are Figure 3A and Figure 3B The structural relationship and configuration of the layout design 300 are similar to the layers, and for the sake of simplicity, at least Figure 4A-4B Similar detailed description will not be described again.

[0149] Integrated circuit 400 is an integrated circuit 200 ( Figure 2A-2B For example, integrated circuit 400 illustrates an example where the VBS level (eg, signal line group 203 ) is used for additional routing resources to electrically couple at least gate pair 416 .

[0150] and Figure 3A-Figure 3BCompared with the integrated circuit 400, the contact group 406 of the integrated circuit 400 replaces the contact group 206, the through-hole group 410 of the integrated circuit 400 replaces the through-hole group 210, and the gate group 416 of the integrated circuit 400 replaces the gate group 216, so similar detailed descriptions are omitted.

[0151] The integrated circuit 400 comprises at least a power rail group 202, a signal line group 203, an active area group 204, a contact group 406, a through hole group 208 ( Figure 4A-4B ), the through hole group 410, the conductive structure group 212 or the gate group 416.

[0152] The contact group 406 includes one or more contacts 406a, 406b, 406c, 406d, 406e, or 406f. At least one of the contacts 406a, 406b, 406c, 406d, 406e, or 406f is similar to at least one of the contacts 206a, 206b, 206c, or 206d, and thus similar detailed description is omitted.

[0153] In some embodiments, at least one of the contacts 406a, 406b, 406c, or 406d of the contact group 406 corresponds to the source and drain terminals of one NMOS or PMOS transistor of the integrated circuits 400, 600, 1000, 1200, and 1500, and at least one of the contacts 406e, 406f, 406g, or 406h of the contact group 406 corresponds to the source and drain terminals of another PMOS or NMOS transistor of the integrated circuits 400, 600, 1000, 1200, and 1500.

[0154] In some embodiments, at least contact 406a, 406b, 406c, or 406d is above active region 104a. In some embodiments, at least contact 406e, 406f, 406g, or 406h is above active region 104b.

[0155] Other configurations in the contact set 406 , arrangements on other layout levels, or numbers of contacts are within the scope of the present disclosure.

[0156] The through-hole group 410 includes one or more through-holes 410a or 410b. At least one of the through-holes 410a or 410b is similar to at least one of the through-holes 210a or 210b, and thus similar detailed description is omitted.

[0157] In some embodiments, via group 410 is located between the signal line 203 group and the gate 416 group. Via 410a is located between signal line 203a and gate 416b, thereby providing an electrical connection between the signal line 203a and gate 416b. In some embodiments, via 410a is located at a position where gate 416b overlaps with signal line 203a. Via 410b is located between signal line 203a and gate 416d, thereby providing an electrical connection between the signal line 203a and gate 416d. In some embodiments, via 410b is located at a position where gate 416d overlaps with signal line 203a. In some embodiments, at least one via in via group 410 is not included in integrated circuit 400.

[0158] Other configurations in via group 410 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0159] Gate group 416 includes one or more gates 416a, 416b, 416c, 416d, or 416e. At least one of gates 416a, 416b, 416c, 416d, or 416e is similar to at least one of gates 216a, 216b, or 216c, and thus similar detailed description is omitted.

[0160] In some embodiments, at least a portion of gates 416 a, 416 b, 416 c, 416 d, or 416 e in gate group 416 corresponds to a gate of an NMOS transistor of integrated circuits 400 , 600 , 1000 , 1200 , and 1500 , and at least a portion of gates 416 a, 416 b, 416 c, 416 d, or 416 e in gate group 416 corresponds to a gate of a PMOS transistor of integrated circuits 400 , 600 , 1000 , 1200 , and 1500 .

[0161] Gate 416b overlaps with via 410a and signal line 203a. Gate 416d overlaps with via 410b and signal line 203a. Gate 416b is electrically coupled to signal line 203a through via 410a. Signal line 203a is electrically connected to gate 416d through via 410b.

[0162] Signal line 403 a electrically couples at least a first gate region (e.g., gate 416 b) to at least a second gate region (e.g., gate 416 d) of the integrated circuit, thereby using at least one smaller upper metal layer track in conductive feature group 212, allowing integrated circuit 400 to have a smaller height and a smaller area compared to other approaches.

[0163] In some embodiments, by reducing at least one upper metal layer track in the conductive feature group 212, the width of one or more conductive features in the conductive feature group 212 is increased, thereby resulting in an integrated circuit 400 having better current resistance (IR), electromigration (EM), and resistance-capacitance (RC) metal performance compared to other approaches. In some embodiments, by utilizing the power rail group 202 or signal line group 203 of the present disclosure, the gate density of the gate group 416 of the integrated circuit 400 is increased compared to other approaches. In some embodiments, by utilizing at least the power rail group 202 or signal line group 203 of the present disclosure, the integrated circuit 400 provides greater routing flexibility and increased routing resources compared to other approaches.

[0164] Other configurations in gate group 416 , arrangements on other layout levels, or numbers of gates are within the scope of the present disclosure.

[0165] Other overlapping locations or numbers of overlapping locations between one or more of the gate set 416 , the via set 410 , and the signal line set 203 are within the scope of the present disclosure.

[0166] Figure 5A is a diagram of a layout design 500A according to various embodiments of the present disclosure. Figure 5B is a top view of an integrated circuit 500B according to some embodiments.

[0167] Layout design 500A is a layout diagram of integrated circuit 500B.

[0168] Layout Design 500A is Figures 1A to 1C and Figure 3B 100C, the integrated circuit 500B is a variation of the integrated circuit 200 ( Figure 2A For example, layout design 500A and integrated circuit 500B illustrate an example in which the M0 routing track has four routing tracks.

[0169] and Figure 1C Compared to the portion 100C of the layout design 100 of FIG. 5 , the conductive component pattern group 512 of the layout design 500A replaces the conductive component pattern group 112, and thus similar detailed descriptions are omitted. Figure 2A Compared with the integrated circuit 200, the conductive structure group 512' of the integrated circuit 500B replaces the conductive structure group 212, and thus similar detailed description is omitted.

[0170] The conductive component pattern group 512 includes conductive component patterns 512a, 512b, 512c, and 512d. The conductive component pattern group 512 can be used to manufacture a corresponding conductive structure group 512' ( Figure 5B). The conductive structure group 512' includes conductive structures 512a', 512b', 512c', and 512d'. The conductive component patterns 512a, 512b, 512c, and 512d can be used to manufacture corresponding conductive structures 512a', 512b', 512c', and 512d' ( Figure 5B ).

[0171] In some embodiments, conductive feature patterns 512a, 512b, 512c, 512d correspond to four M0 routing tracks in layout design 500A. In some embodiments, conductive structures 512a', 512b', 512c', 512d' correspond to four M0 routing tracks in integrated circuit 500B.

[0172] At least pattern 512a, 512b, 512c, or 512d in the conductive component pattern group 512 has a width W2 in the second direction Y. At least structure 512a', 512b', 512c', or 512d' in the conductive component group has a width W2' in the second direction Y. In some embodiments, width W2 or W2' is greater than the corresponding width W1 or W1'.

[0173] Other widths, configurations, arrangements on other layout levels, or numbers of structures or numbers of patterns in the conductive feature pattern group 512 or the conductive structure group 512 ′ are within the scope of the present disclosure.

[0174] Figure 5C is a diagram of a layout design 500C according to various embodiments of the present disclosure. Figure 5D is a top view of an integrated circuit 500D according to some embodiments.

[0175] Layout design 500C is a layout diagram of integrated circuit 500D.

[0176] Layout design 500C is Figure 1C-1D and Figure 3B A variation of the layout design 500A or portion 100C, the integrated circuit 500D is the integrated circuit 500B or the integrated circuit 200 ( Figure 2A For example, layout design 500C and integrated circuit 500D illustrate an example in which the M0 routing track has three routing tracks.

[0177] and Figure 1C Compared to the portion 100C of the layout design 100, the conductive component pattern group 514 of the layout design 500C replaces the conductive component pattern group 112, and thus similar detailed descriptions are omitted. Figure 2A Compared with the integrated circuit 200, the conductive structure group 514' of the integrated circuit 500D replaces the conductive structure group 212, and thus similar detailed description is omitted.

[0178] The conductive component pattern group 514 includes conductive component patterns 514a, 514b, and 514c. The conductive component pattern group 514 can be used to manufacture a corresponding conductive structure group 514' ( Figure 5D ). The conductive structure group 514' includes conductive structures 514a', 514b', 514c'. The conductive component patterns 514a, 514b, 514c can be used to manufacture the corresponding conductive structures 514a', 514b', 514c' ( Figure 5D ).

[0179] In some embodiments, conductive feature patterns 514a, 514b, 514c correspond to three M0 routing tracks in layout design 500C. In some embodiments, conductive structures 514a', 514b', 514c' correspond to three M0 routing tracks in integrated circuit 500D.

[0180] At least pattern 514a, 514b, or 514c in the conductive feature pattern group 514 has a width W3 in the second direction Y. At least structure 514a', 514b', or 514c' in the conductive structure group 514' has a width W3' in the second direction Y. In some embodiments, W3 or W3' is greater than the corresponding width W1 or W1' or the corresponding width W2 or W2'.

[0181] Other widths, configurations, arrangements on other layout levels, or numbers of structures or numbers of patterns in the conductive feature pattern group 514 or the conductive structure group 514 ′ are within the scope of the present disclosure.

[0182] In some embodiments, due to the reduction of at least one upper metal layer track in the conductive feature group 212, the width of one or more conductive features in the conductive feature group 212 is increased, thereby generating a layout design 500A or 500C or an integrated circuit 500B or 500D with better IR, EM, and RC metal performance compared to other methods.

[0183] Figure 6 is a circuit diagram of an integrated circuit 600 according to some embodiments. In some embodiments, the integrated circuit 600 is a 2-2 AND OR INVERT (AOI) circuit. The 2-2 AOI circuit is for illustration only, and other types of circuits, including other types of AOI circuits, are also within the scope of the present disclosure.

[0184] The integrated circuit 600 includes P-type metal oxide semiconductor (PMOS) transistors P1 , P2 , P3 , and P4 and N-type metal oxide semiconductor (NMOS) transistors N1 , N2 , N3 , and N4 .

[0185] The gate terminal of PMOS transistor P1 is configured as an input node (not labeled) configured to receive input signal A1. The gate terminal of NMOS transistor N1 is configured as an input node (not labeled) configured to receive input signal A1. In some embodiments, the gate terminal of PMOS transistor P1 is coupled to the gate terminal of NMOS transistor N1.

[0186] The gate terminal of PMOS transistor P2 is configured as an input node (not labeled) configured to receive input signal B1. The gate terminal of NMOS transistor N3 is configured as an input node (not labeled) configured to receive input signal B1. In some embodiments, the gate terminal of PMOS transistor P2 is coupled to the gate terminal of NMOS transistor N3.

[0187] The gate terminal of the PMOS transistor P3 is configured as an input node (not labeled) configured to receive the input signal A2. The gate terminal of the NMOS transistor N2 is configured as an input node (not labeled) configured to receive the input signal A2. In some embodiments, the gate terminal of the PMOS transistor P3 is coupled to the gate terminal of the NMOS transistor N2.

[0188] The gate terminal of PMOS transistor P4 is configured as an input node (not labeled) configured to receive input signal B2. The gate terminal of NMOS transistor N4 is configured as an input node (not labeled) configured to receive input signal B2. In some embodiments, the gate terminal of PMOS transistor P4 is coupled to the gate terminal of NMOS transistor N4. In some embodiments, at least input signal A1, A2, B1, or B2 is a logic low signal or a logic high signal.

[0189] The source terminal of the PMOS transistor P2 and the source terminal of the PMOS transistor P4 are coupled to a voltage source VDD. In some embodiments, the source terminal of the PMOS transistor P2 and the source terminal of the PMOS transistor P4 are coupled together.

[0190] The drain terminal of the PMOS transistor P2, the source terminal of the PMOS transistor P1, the drain terminal of the PMOS transistor P4, and the source terminal of the PMOS transistor P3 are coupled to each other.

[0191] A drain terminal of the PMOS transistor P1, a drain terminal of the PMOS transistor P3, a drain terminal of the NMOS transistor N1, and a drain terminal of the NMOS transistor N3 are coupled to each other and configured as an output node OUT1.

[0192] The source terminal of the NMOS transistor N1 and the drain terminal of the NMOS transistor N2 are coupled to each other. The source terminal of the NMOS transistor N3 and the drain terminal of the NMOS transistor N4 are coupled to each other.

[0193] The source terminal of the NMOS transistor N2 and the source terminal of the NMOS transistor N4 are both coupled to a reference voltage source VSS. In some embodiments, the source terminal of the NMOS transistor N2 and the source terminal of the NMOS transistor N4 are coupled together.

[0194] Other circuits, other types of transistors, and / or numbers of transistors are within the scope of various embodiments. For example, in some embodiments, integrated circuit 600 includes other types of AOI logic circuits, such as 2-1 AOI logic circuits. Other values ​​of at least input signals A1, A2, B1, or B2 are within the scope of various embodiments.

[0195] Figure 7A-7B is a diagram of an integrated circuit 700 according to some embodiments.

[0196] Figure 7A-7B 7 is a top view of corresponding portions 700A-700B of an integrated circuit 700, simplified for ease of illustration. Integrated circuit 700 is an embodiment of integrated circuit 600 having five M0 routing tracks (eg, a conductive feature set 712).

[0197] Portion 700A includes one or more features of integrated circuit 700 at the VBP level, OD level, POLY level, MD level, or M0 level of integrated circuit 700. Portion 700B includes one or more features of integrated circuit 700 at the BP level, BS level, VBP level, VBS level, OD level, POLY level, or MD level of integrated circuit 700.

[0198] For ease of explanation, Figure 7A-7B Some of the marked elements in Figures 7A-7B In some embodiments, the integrated circuit 700 includes Figure 7A-7B Additional elements not shown.

[0199] The integrated circuit 700 is manufactured by a corresponding layout design similar to that of the integrated circuit 700. 7A to 7B Described as integrated circuit 700, but in some embodiments, 7A to 7B Depicted is integrated circuit 700 . Figure 7A-7B Also corresponding to layout designs similar to layout designs 100, 400, 500A and 500C, the structural elements of integrated circuit 700 also correspond including alignment, length and width and structural relationships as well as the configuration and layers of integrated circuit 700, and similar detailed descriptions will not be described again for the sake of brevity.

[0200] Integrated circuit 700 is an integrated circuit 200 ( Figure 2A-2B ) or an embodiment of the integrated circuit 600. Figures 2A to 2B 7 , the power rail group 702 of the integrated circuit 700 replaces the power rail group 202 , the signal line group 703 replaces the signal line group 203 , the contact group 706 replaces the contact group 206 , the through-hole group 708 replaces the through-hole group 208 , the through-hole group 710 replaces the through-hole group 210 , and the conductive component group 712 replaces the conductive component group 212 , so similar detailed descriptions are omitted.

[0201] The power rail group 702 includes one or more power rails 702a or 702b. Power rail 702a is configured to provide a first power supply voltage of the voltage supply VDD, and power rail 702b is configured to provide a second power supply voltage of the reference voltage supply VSS. In some embodiments, power rail 702a is configured to provide the second power supply voltage of the reference voltage supply VSS, and power rail 702b is configured to provide the first power supply voltage of the voltage supply VDD.

[0202] Signal line group 703 includes at least signal line 703a. Signal line group 703 is configured to provide signal routing. In some embodiments, the signal routing provided by signal line group 703 corresponds to signal routing performed by upper layers in other approaches. Signal line 703a is configured to electrically couple the drains of NMOS transistors N1 and N3 and the drains of PMOS transistors P1 and P3, resulting in additional routing resources compared to other approaches.

[0203] Other configurations, arrangements at other layout levels, or numbers of structures in the power rail group 702 or signal line group 703 are within the scope of the present disclosure. In some embodiments, the signal line group 703 in Figures 7, 8, and 9 electrically couples a source or drain feature of a transistor with a gate feature of another transistor in Figures 7, 8, and 9. In some embodiments, the signal line group 703 in Figures 7, 8, and 9 electrically couples a gate feature of a transistor with a gate feature of another transistor in Figures 7, 8, and 9.

[0204] The contact group 706 includes one or more contacts 706a, 706b, 706c, 706d, or 706e. At least one of the contacts 706a, 706b, 706c, 706d, or 706e is similar to at least one of the contacts 206a, 206b, 206c, or 206d, and thus similar detailed description is omitted.

[0205] In some embodiments, contact 706a corresponds to the source terminals of PMOS transistors P2 and P4. In some embodiments, contact 706d corresponds to the drain terminals of PMOS transistors P1 and P3.

[0206] In some embodiments, contact 706b corresponds to the source terminal of NMOS transistor N4. In some embodiments, contact 706e corresponds to the source terminal of NMOS transistor N2. In some embodiments, contact 706c corresponds to the drain terminals of NMOS transistors N1 and N3.

[0207] Other configurations in the group of contacts 706 , arrangements on other layout levels, or numbers of contacts are within the scope of the present disclosure.

[0208] The through-hole group 708 includes one or more through-holes 708a, 708b, or 708c. At least one of the through-holes 708a, 708b, or 708c is similar to at least one of the through-holes 208a or 208b, and thus similar detailed description is omitted.

[0209] Via 708a electrically couples power rail 702a and contact 706a to each other, thereby coupling the source terminals of PMOS transistors P2 and P4 to power supply voltage VDD. Via 708b electrically couples power rail 702b and contact 706b to each other, thereby coupling the source terminal of NMOS transistor N4 to reference power supply voltage VSS. Via 708c electrically couples power rail 702b and contact 706e to each other, thereby coupling the source terminal of NMOS transistor N2 to reference power supply voltage VSS.

[0210] Other configurations in via group 708 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0211] The through-hole group 710 includes one or more through-holes 710a or 710b. At least one of the through-holes 710a or 710b is similar to at least one of the through-holes 210a or 210b, and thus similar detailed description is omitted.

[0212] Via 710a electrically couples signal line 703a and contact 706c to each other, thereby coupling the drain terminals of NMOS transistors N1 and N3 to signal line 703a. Via 710b electrically couples signal line 703a and contact 706d to each other, thereby coupling the drain terminals of PMOS transistors P1 and P3 to signal line 703a. Thus, signal line 703a and vias 710a and 710b electrically couple contacts 706c and 706d to each other, thereby coupling the drain terminals of NMOS transistors N1 and N3 and the drain terminals of PMOS transistors P1 and P3 to each other, resulting in additional wiring resources on the metal layer compared to other methods.

[0213] Other configurations, arrangements at other layout levels, or numbers of vias in the via group 710 are within the scope of the present disclosure. Other overlap locations or numbers of overlap locations between the contact group 706, the via group 710, and one or more of the signal line group 703 are within the scope of the present disclosure, and thus other electrical connections are within the scope of the present disclosure.

[0214] Conductive component group 712 includes one or more of conductive components 712a, 712b, 712c, 712d, 712e, 712f, or 712g. At least one of conductive components 712a, 712b, 712c, 712d, 712e, 712f, or 712g is similar to at least one of conductive components 212a, 212b, 212c, 212d, or 212e, and thus similar detailed descriptions are omitted. Conductive component 712a electrically couples each drain terminal of PMOS transistors P2 and P4 to the source terminals of PMOS transistors P1 and P3.

[0215] Other configurations, arrangements, or numbers of conductive features in the conductive feature group 712 at other layout levels are within the scope of the present disclosure.

[0216] Figure 8A-8B is a diagram of an integrated circuit 800 according to some embodiments.

[0217] Figure 8A-8B 8 is a top view of corresponding portions 800A-800B of integrated circuit 800, which is simplified for ease of illustration. Integrated circuit 800 is an embodiment of integrated circuit 600 having four MO routing tracks (eg, conductive feature group 812).

[0218] Portion 800A includes one or more features of integrated circuit 800 at the VBP level, OD level, POLY level, MD level, or M0 level of integrated circuit 800. Portion 800B includes one or more features of integrated circuit 800 at the BP level, BS level, VBP level, VBS level, POLY level, or MD level of integrated circuit 800.

[0219] For ease of explanation, Figure 8A-8B Some of the marked elements in Figure 8A-8B In some embodiments, the integrated circuit 800 includes Figure 8A-8B Additional elements not shown.

[0220] Integrated circuit 800 is manufactured by a corresponding layout design similar to integrated circuit 800 . Figure 8A-8B Described as integrated circuit 800, but in some embodiments, Figure 8A-8B Depicted is integrated circuit 800 . Figure 8A-8B Also corresponding to layout designs similar to layout designs 100, 400, 500A and 500C, the structural elements of integrated circuit 800 also correspond to the configuration and layers of integrated circuit 800 including alignment, length and width and structural relationships, and similar detailed descriptions will not be described again for the sake of brevity.

[0221] Integrated circuit 800 is an integrated circuit 700 ( Figure 7A-7B ) variants, similar detailed description will not be described for the sake of brevity. Figure 7A-7B Compared with the integrated circuit 700, the conductive component group 812 of the integrated circuit 800 replaces the conductive component group 712, so similar detailed description is omitted. Figure 7A-7B In further comparison to integrated circuit 700, integrated circuit 800 further includes gridline group 840. In some embodiments, gridline group 840 corresponds to M1 routing tracks that provide pin access points to other layers of integrated circuit 800. Other configurations of gridline group 840 are within the scope of the present disclosure.

[0222] Integrated circuit 800 is an integrated circuit 200 ( Figure 2A-2B ) or an embodiment of the integrated circuit 600. Figures 2A to 2B In the integrated circuit 800, the power rail group 702 replaces the power rail group 202, the signal line group 703 replaces the signal line group 203, the contact member group 706 replaces the contact member group 206, the through hole group 708 replaces the through hole group 208, the through hole group 710 replaces the through hole group 210, and the conductive component group 812 replaces the conductive component group 212, so similar detailed descriptions are omitted.

[0223] Conductive component group 812 includes one or more of conductive components 812a, 812b, 812c, 812d, 812e, or 812f. At least one of conductive components 812a, 812b, 812c, 812d, 812e, or 812f is similar to at least one of conductive components 212a, 212b, 212c, 212d, or 212e, and thus similar detailed descriptions are omitted. Conductive component group 812 corresponds to four M0 routing tracks. The number of routing tracks on other metal layers or other numbers of routing tracks is within the scope of the present disclosure.

[0224] Conductive feature 812a is similar to conductive feature 712a, and thus similar detailed description is omitted. Conductive features 812b and 812e are separated from each other in the second direction Y, thereby providing different conductive features to the upper metal layer for routing resources and pin access compared to continuous conductive features.

[0225] Conductive features 812 c and 812 f are separated from each other in the second direction Y, thereby providing different conductive features to the upper metal layer for routing resources and pin access compared to continuous conductive features. Conductive feature 812 d corresponds to output node OUT1 of integrated circuit 600 or 800 and is electrically coupled to the drain terminal of PMOS transistor P1, the drain terminal of PMOS transistor P3, the drain terminal of NMOS transistor N1, and the drain terminal of NMOS transistor N3.

[0226] Other configurations, arrangements, or numbers of conductive features in the conductive feature group 812 at other layout levels are within the scope of the present disclosure.

[0227] In some embodiments, since at least one upper metal layer track in the conductive feature group 812 is reduced compared to other approaches, the height and area of ​​the integrated circuit 800 are reduced compared to other approaches. In some embodiments, since at least one upper metal layer track in the conductive feature group 812 is reduced, the width of one or more conductive features in the conductive feature group 812 is increased compared to other approaches, thereby resulting in an integrated circuit 800 with lower IR, EM, and RC metal properties compared to other approaches.

[0228] Figure 9A-9B is a diagram of an integrated circuit 900 according to some embodiments.

[0229] Figure 9A-9B 9 is a top view of corresponding portions 900A-900B of integrated circuit 900, simplified for ease of illustration. Integrated circuit 900 is an embodiment of integrated circuit 600 having three M0 routing tracks (eg, conductive feature set 912).

[0230] Portion 900A includes one or more features of integrated circuit 900 at the VBP level, OD level, POLY level, MD level, M0 level, or Metal 1 (M1) level of integrated circuit 900. Portion 900B includes one or more features of integrated circuit 900 at the BP level, BS level, VBP level, VBS level, POLY level, or MD level of integrated circuit 900.

[0231] For ease of explanation, Figure 9A-9B Some of the marked elements in Figure 9A-9B In some embodiments, the integrated circuit 900 includes Figure 9A-9B Additional elements not shown.

[0232] Integrated circuit 900 is manufactured by a corresponding layout design similar to integrated circuit 900 . Figure 9A-9B Described as integrated circuit 900, but in some embodiments, Figure 9A-9B Depicted is integrated circuit 900 . Figure 9A-9B Also corresponding to layout designs similar to layout designs 100, 400, 500A and 500C, the structural elements of integrated circuit 900 also correspond including alignment, length and width and structural relationships as well as the configuration and layers of integrated circuit 900, and similar detailed descriptions will not be described again for the sake of brevity.

[0233] Integrated circuit 900 is an integrated circuit 700 ( Figure 7A-7B ) or 800( Figure 8A-8B ) variants, similar detailed description will not be described for the sake of brevity. 7A to 7B Compared to the integrated circuit 700 , the conductive component group 912 of the integrated circuit 900 replaces the conductive component group 712 , and the integrated circuit 900 further includes a conductive component group 920 , so similar detailed description is omitted.

[0234] Integrated circuit 900 is an integrated circuit 200 ( Figure 2A-2B ) or an embodiment of the integrated circuit 600. Figures 2A to 2B In the integrated circuit 900, the power rail group 702 replaces the power rail group 202, the signal line group 703 replaces the signal line group 203, the contact group 706 replaces the contact group 206, the through-hole group 708 replaces the through-hole group 208, the through-hole group 710 replaces the through-hole group 210, and the conductive component group 912 replaces the conductive component group 212, so similar detailed descriptions are omitted.

[0235] Conductive component group 912 includes one or more conductive components 912a, 912b, 912c, 912d, or 912e. At least one of conductive components 912a, 912b, 912c, 912d, or 912e is similar to at least one of conductive components 212a, 212b, 212c, 212d, or 212e, and thus similar detailed descriptions are omitted. Conductive component group 912 corresponds to three M0 routing tracks. Routing tracks on other metal layer numbers are within the scope of this disclosure.

[0236] The conductive features 912d and 912b are separated from each other in the second direction Y, thereby providing different conductive features to the upper metal layer for routing resources and pin access compared to continuous conductive features.

[0237] The conductive features 912e and 912c are separated from each other in the second direction Y, thereby providing different conductive features to the upper metal layer for routing resources and pin access compared to continuous conductive features.

[0238] Other configurations, arrangements, or numbers of conductive features in the conductive feature group 912 at other layout levels are within the scope of the present disclosure.

[0239] The conductive component group 920 includes one or more of conductive components 920a, 920b, 920c, 920d, or 920e. At least one of the conductive components 920a, 920b, 920c, 920d, or 920e is similar to at least one of the conductive components 212a, 212b, 212c, 212d, or 212e, and thus similar detailed description is omitted.

[0240] Conductive component group 920 extends in the second direction Y. Each conductive component of conductive component group 920 is separated from adjacent conductive components in the first direction X. Conductive component group 920 overlaps at least conductive component group 912. Conductive component group 912 corresponds to M1 routing tracks. Routing tracks on other metal layer numbers are within the scope of the present disclosure. Other configurations, arrangements, or numbers of conductive components in conductive component group 920 at other layout levels are within the scope of the present disclosure.

[0241] In some embodiments, the height and area of ​​integrated circuit 900 are reduced compared to other approaches due to the reduction of at least one upper metal layer track in conductive feature group 912. In some embodiments, the width of one or more conductive features in conductive feature group 912 is increased compared to other approaches due to the reduction of at least one upper metal layer track in conductive feature group 912, thereby resulting in integrated circuit 900 having lower IR, EM, and RC metal properties compared to other approaches.

[0242] Figure 10 is a circuit diagram of an integrated circuit 1000 according to some embodiments. In some embodiments, integrated circuit 1000 is a 2-2 NAND (NAND) logic gate (hereinafter referred to as "NAND") circuit. The 2-2 NAND circuit is for illustration only, and other types of circuits, including other types of NAND circuits, are also within the scope of the present disclosure.

[0243] Integrated circuit 1000 includes PMOS transistors P5 and P6, and NMOS transistors N5, N6, N7, and N8.

[0244] The gate terminal of the PMOS transistor P5 is configured as an input node (not labeled) configured to receive the input signal A2. The gate terminal of the NMOS transistor N6 is configured as an input node (not labeled) configured to receive the input signal A2. The gate terminal of the NMOS transistor N8 is configured as an input node (not labeled) configured to receive the input signal A2.

[0245] In some embodiments, at least two of the gate terminal of the PMOS transistor P5 , the gate terminal of the NMOS transistor N6 , and the gate terminal of the NMOS transistor N8 are coupled together.

[0246] The gate terminal of the PMOS transistor P6 is configured as an input node (not labeled) configured to receive the input signal A1. The gate terminal of the NMOS transistor N5 is configured as an input node (not labeled) configured to receive the input signal A1. The gate terminal of the NMOS transistor N7 is configured as an input node (not labeled) configured to receive the input signal A1.

[0247] In some embodiments, at least two of the gate terminal of the PMOS transistor P6 , the gate terminal of the NMOS transistor N5 , and the gate terminal of the NMOS transistor N7 are coupled together.

[0248] In some embodiments, at least the input signal A1 or A2 is a logic low signal or a logic high signal.

[0249] The source terminal of the PMOS transistor P5 and the source terminal of the PMOS transistor P6 are coupled to a voltage source VDD. In some embodiments, the source terminal of the PMOS transistor P5 and the source terminal of the PMOS transistor P6 are coupled together.

[0250] A drain terminal of the PMOS transistor P5 , a drain terminal of the PMOS transistor P6 , a drain terminal of the NMOS transistor N5 , and a drain terminal of the NMOS transistor N7 are coupled to one another and configured as an output node OUT1 .

[0251] The source terminal of the NMOS transistor N5 and the drain terminal of the NMOS transistor N6 are coupled to each other. The source terminal of the NMOS transistor N7 and the drain terminal of the NMOS transistor N8 are coupled to each other.

[0252] The source terminal of the NMOS transistor N6 and the source terminal of the NMOS transistor N8 are both coupled to the reference voltage source VSS. In some embodiments, the source terminal of the NMOS transistor N6 and the source terminal of the NMOS transistor N8 are coupled together.

[0253] Other circuits, other types of transistors, and / or numbers of transistors are within the scope of various embodiments. For example, in some embodiments, integrated circuit 1000 includes other types of NAND circuits, such as a 2-1 NAND circuit. Other values ​​of at least input signal A1 or A2 are within the scope of various embodiments.

[0254] Figures 11A-11B is a diagram of an integrated circuit 1100 according to some embodiments.

[0255] Figures 11A-11B1 is a top view of corresponding portions 1100A-1100B of integrated circuit 1100, which is simplified for ease of illustration. Integrated circuit 1100 is an embodiment of integrated circuit 1000 having five M0 routing tracks (eg, conductive feature group 1112).

[0256] Portion 1100A includes one or more features of the integrated circuit 1100 at the VBP level, OD level, POL level, MD level, M0 level, or M1 level of the integrated circuit 1100. Portion 1100B includes one or more features of the integrated circuit 1100 at the BP level, BS level, VBP level, VBS level, POLY level, or MD level of the integrated circuit 1100.

[0257] For ease of explanation, Figures 11A-11B Some of the marked components are Figures 11A-11B In some embodiments, the integrated circuit 1100 includes Figures 11A-11B Additional elements not shown.

[0258] Integrated circuit 1100 is manufactured by a corresponding layout design similar to integrated circuit 1100 . Figures 11A-11B Described as integrated circuit 1100, but in some embodiments, Figures 11A-11B Depicted is integrated circuit 1100 . Figures 11A-11B Also corresponding to layout designs similar to layout designs 100, 400, 500A and 500C, the structural elements of integrated circuit 1100 also correspond including alignment, length and width and structural relationships as well as the configuration and layers of integrated circuit 1100, and similar detailed descriptions will not be described again for the sake of brevity.

[0259] Integrated circuit 1100 is an integrated circuit 400 ( Figure 4A-4B ) or an embodiment of the integrated circuit 1000. Figures 4A to 4B In the embodiment, the power rail group 702 of the integrated circuit 1100 replaces the power rail group 202, the signal line group 1103 replaces the signal line group 203, the contact group 1106 replaces the contact group 406, and the through hole group 1108 replaces the through hole group 208 (e.g., Figure 2A-2B ), the through-hole group 1110 replaces the through-hole group 410, the conductive component group 1112 replaces the conductive component group 212, and the gate group 1116 replaces the gate group 416, so similar detailed descriptions are omitted.

[0260] Signal line group 1103 includes at least signal line 1103a. Signal line group 1103 is configured to provide routing for signals from upper layers. Signal line 1103a is configured to electrically couple the gate of PMOS transistor P5 and the gate of one of NMOS transistors N6 or N8 to the gate of the other of NMOS transistors N8 or N6, resulting in additional routing resources compared to other approaches. Other connections to other gates are within the scope of this disclosure.

[0261] Other configurations, arrangements at other layout levels, or numbers of structures in the power rail group 702 or the signal line 1103 group are within the scope of the present disclosure. In some embodiments, the signal line group 1103 in FIG. 11 is electrically coupled to the source or drain components of the transistor. FIG. 11 has Figure 10 In some embodiments, the signal line set 1103 electrically couples a source or drain component of the transistor in FIG11 with a source or drain component of another transistor in FIG11 .

[0262] Contact group 1106 includes one or more contacts 1106a, 1106b, 1106c, 1106d, or 1106e. At least one of contacts 1106a, 1106b, 1106c, 1106d, or 1106e is similar to at least one of contacts 406a, 406b, 406c, 406d, 406e, 406f, 406g, or 406h, and thus similar detailed description is omitted.

[0263] In some embodiments, contact 1106a corresponds to the source terminal of PMOS transistor P5. In some embodiments, contact 1106b corresponds to the source terminal of PMOS transistor P6. In some embodiments, contact 1106c corresponds to the source terminal of PMOS transistor P5.

[0264] In some embodiments, contact 1106d corresponds to the source terminal of NMOS transistor N6. In some embodiments, contact 1106e corresponds to the source terminal of NMOS transistor N8.

[0265] Other configurations in the group of contacts 1106 , arrangements on other layout levels, or numbers of contacts are within the scope of the present disclosure.

[0266] Via group 1108 includes one or more vias 1108a, 1108b, 1108c, 1108d, or 1108e. At least one of vias 1108a, 1108b, 1108c, 1108d, or 1108e is similar to at least one of vias 208a or 208b, and thus similar detailed description is omitted.

[0267] In some embodiments, via 1108a electrically couples power rail 702a and contact 1106a to each other, thereby coupling the source terminal of PMOS transistor P5 to power supply voltage VDD. Via 1108b electrically couples power rail 702a and contact 1106b to each other, thereby coupling the source terminal of PMOS transistor P6 to power supply voltage VDD. In some embodiments, via 1108c electrically couples power rail 702a and contact 1106c to each other, thereby coupling the source terminal of PMOS transistor P5 to power supply voltage VDD.

[0268] In some embodiments, via 1108 d electrically couples power rail 702 b and contact 1106 d to each other, thereby coupling the source terminal of NMOS transistor N6 to reference supply voltage VSS. In some embodiments, via 1108 e electrically couples power rail 702 b and contact 1106 e to each other, thereby coupling the source terminal of NMOS transistor N8 to reference supply voltage VSS.

[0269] Other configurations in via group 1108 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0270] The through-hole group 1110 includes one or more through-holes 1110a or 1110b. At least one of the through-holes 1110a or 1110b is similar to at least one of the through-holes 410a or 410b, and thus similar detailed description is omitted.

[0271] Via 1110a electrically couples signal line 1103a and gate 1116b, thereby coupling the gate terminals of PMOS transistor P5 and NMOS transistor N6 to signal line 1103a. Via 1110b electrically couples signal line 1103a and gate 1116e, thereby coupling the gate terminals of PMOS transistor P5 and NMOS transistor N8 to signal line 1103a. Thus, signal line 1103a and vias 1110a and 1110b electrically couple gates 1116b and 1116e, thereby coupling the gate terminals of PMOS transistor P5, NMOS transistor N6, and PMOS transistor N8 to each other. Compared to other methods, this results in additional wiring resources on other metal layers.

[0272] Other configurations, arrangements at other layout levels, or numbers of vias in the via group 1110 are within the scope of the present disclosure. Other overlap locations or numbers of overlap locations between one or more of the contact group 1106, the via group 1110, the signal line group 1103, and the gate group 1116, and thus other electrical connections, are within the scope of the present disclosure.

[0273] The conductive component group 1112 includes one or more conductive components 1112a, 1112b, 1112c, 1112d, 1112e, or 1112f. At least one of the conductive components 1112a, 1112b, 1112c, 1112d, 1112e, or 1112f is similar to at least one of the conductive components 212a, 212b, 212c, 212d, or 212e, and thus similar detailed description is omitted.

[0274] Other configurations, arrangements, or numbers of conductive features in the conductive feature group 1112 at other layout levels are within the scope of the present disclosure.

[0275] The gate group 1116 includes one or more gates 1116a, 1116b, 1116c, 1116d, 1116e, or 1116f. For ease of description, the gates 1116a, 1116c, 1116d, or 1116f are arranged in a Figures 11A-11B At least one of the gates 1116a, 1116b, 1116c, 1116d, 1116e, or 1116f is similar to at least one of the gates 416a, 416b, 416c, 416d, or 416e, and thus similar detailed descriptions are omitted.

[0276] In some embodiments, gate 1116b corresponds to the gate of NMOS transistor N6, and gate 1116e corresponds to the gate of NMOS transistor N8.

[0277] In some embodiments, gate 1116c corresponds to the gate of NMOS transistor N5, and gate 1116d corresponds to the gate of NMOS transistor N7.

[0278] In some embodiments, at least gate 1116b or 1116e corresponds to the gate of PMOS transistor P5. In some embodiments, at least gate 1116c or 1116d corresponds to the gate of PMOS transistor P6.

[0279] The gate 1116 b and the gate 1116 e are electrically coupled to each other through the signal line 1103 a and the vias 1110 a and 1110 b .

[0280] Signal line 1103a electrically couples gates 1116b and 1116e together, thereby using at least one smaller upper metal layer track in conductive feature group 1112, resulting in integrated circuit 1100 having at least a smaller height, smaller area, better IR, EM and RC metal performance, or other routing resources on other metal layers compared to other approaches.

[0281] Other configurations in the gate group 1116 , arrangements on other layout levels, or numbers of conductive features are within the scope of the present disclosure.

[0282] Figure 12 1 is a circuit diagram of an integrated circuit 1200 according to some embodiments. In some embodiments, the integrated circuit 1200 is a split-gate 4-2 NAND logic gate (hereinafter referred to as "NAND") circuit. The 4-2 NAND circuit is for illustration purposes only, and other types of circuits, including other types of NAND circuits, are also within the scope of the present disclosure.

[0283] Integrated circuit 1200 includes PMOS transistors P7 , P8 , P9 , and P10 , and NMOS transistors N9 , N10 , N11 , N12 , N13 , N14 , N15 , and N16 .

[0284] The gate terminal of PMOS transistor P7 is configured as an input node (not labeled) configured to receive input signal A1. The gate terminal of NMOS transistor N9 is configured as an input node (not labeled) configured to receive input signal A1. The gate terminal of NMOS transistor N13 is configured as an input node (not labeled) configured to receive input signal A1. In some embodiments, at least two of the gate terminal of PMOS transistor P7, the gate terminal of NMOS transistor N9, or the gate terminal of NMOS transistor N13 are coupled together.

[0285] The gate terminal of PMOS transistor P8 is configured as an input node (not labeled) configured to receive input signal A2. The gate terminal of NMOS transistor N10 is configured as an input node (not labeled) configured to receive input signal A2. The gate terminal of NMOS transistor N14 is configured as an input node (not labeled) configured to receive input signal A2. In some embodiments, at least two of the gate terminal of PMOS transistor P8, the gate terminal of NMOS transistor N10, or the gate terminal of NMOS transistor N14 are coupled together.

[0286] The gate terminal of PMOS transistor P9 is configured as an input node (not labeled) configured to receive input signal A3. The gate terminal of NMOS transistor N11 is configured as an input node (not labeled) configured to receive input signal A3. The gate terminal of NMOS transistor N15 is configured as an input node (not labeled) configured to receive input signal A3. In some embodiments, at least two of the gate terminal of PMOS transistor P9, the gate terminal of NMOS transistor N11, or the gate terminal of NMOS transistor N15 are coupled together.

[0287] The gate terminal of PMOS transistor P10 is configured as an input node (not labeled) configured to receive input signal A4. The gate terminal of NMOS transistor N12 is configured as an input node (not labeled) configured to receive input signal A4. The gate terminal of NMOS transistor N16 is configured as an input node (not labeled) configured to receive input signal A4. In some embodiments, at least two of the gate terminal of PMOS transistor P10, the gate terminal of NMOS transistor N12, or the gate terminal of NMOS transistor N16 are coupled together.

[0288] In some embodiments, at least the input signal A1 , A2 , A3 , or A4 is a logic low signal or a logic high signal.

[0289] The source terminals of the PMOS transistors P7, P8, P9, and P10 are coupled to a power supply VDD. In some embodiments, the source terminals of the PMOS transistors P7, P8, P9, and P10 are coupled together.

[0290] The drain terminal of the PMOS transistor P7 , the drain terminal of the PMOS transistor P8 , the drain terminal of the PMOS transistor P9 , the drain terminal of the PMOS transistor P10 , the drain terminal of the NMOS transistor N9 , and the drain terminal N13 of the NMOS transistor are coupled to each other and configured as an output node OUT1 .

[0291] The source terminal of the NMOS transistor N9 and the drain terminal of the NMOS transistor N10 are coupled to each other. The source terminal of the NMOS transistor N10 and the drain terminal of the NMOS transistor N11 are coupled to each other. The source terminal of the NMOS transistor N11 and the drain terminal of the NMOS transistor N12 are coupled to each other. The source terminal of the NMOS transistor N12 is coupled to the reference voltage source VSS.

[0292] The source terminal of the NMOS transistor N13 and the drain terminal of the NMOS transistor N14 are coupled to each other. The source terminal of the NMOS transistor N14 and the drain terminal of the NMOS transistor N15 are coupled to each other. The source terminal of the NMOS transistor N15 and the drain terminal of the NMOS transistor N16 are coupled to each other. The source terminal of the NMOS transistor N16 is coupled to the reference voltage source VSS. In some embodiments, the source terminal of the NMOS transistor N12 and the source terminal of the NMOS transistor N16 are coupled together.

[0293] Other circuits, other types of transistors, and / or numbers of transistors are within the scope of various embodiments. For example, in some embodiments, integrated circuit 1200 includes other types of NAND circuits, such as a 4-1 NAND circuit. Other values ​​of at least input signals A1, A2, A3, or A4 are within the scope of various embodiments.

[0294] Figures 13A-13B is a diagram of an integrated circuit 1300 according to some embodiments.

[0295] Figures 13A-13B 13 is a top view of corresponding portions 1300A-1300B of integrated circuit 1300, which is simplified for ease of illustration. Integrated circuit 1300 is an embodiment of integrated circuit 1200 having four M0 routing tracks (eg, conductive feature group 1312).

[0296] Portion 1300A includes one or more features of integrated circuit 1300 at the VBP level, OD level, POLY level, MD level, or M0 level of integrated circuit 1300. Portion 1300B includes one or more features of integrated circuit 1300 at the BP level, BS level, VBP level, VBS level, POLY level, or MD level of integrated circuit 1300.

[0297] For ease of explanation, Figures 13A-13B Some of the marked elements in Figures 13A-13B In some embodiments, the integrated circuit 1300 includes Figures 13A-13B Additional elements not shown.

[0298] Integrated circuit 1300 is manufactured by a corresponding layout design similar to integrated circuit 1300 . Figures 13A-13B Described as integrated circuit 1300, but in some embodiments, Figures 13A-13B Depicted is integrated circuit 1300 . Figures 13A-13B Also corresponding to layout designs similar to layout designs 100, 400, 500A and 500C, the structural elements of integrated circuit 1300 also correspond including alignment, length and width and structural relationships as well as the configuration and layers of integrated circuit 1300, and similar detailed descriptions will not be described again for the sake of brevity.

[0299] Integrated circuit 1300 is an integrated circuit 400 ( Figure 4A-4B ) or an embodiment of the integrated circuit 1200. Figure 4A-4B Compared to the integrated circuit 400, the power rail group 702 of the integrated circuit 1300 replaces the power rail group 202, the signal line group 1303 replaces the signal line group 203, the contact group 1306 replaces the contact group 406, and the through hole group 1308 replaces the through hole group 208 (in Figure 2A-2B), the via group 1310 replaces the via group 410, the conductive feature group 1312 replaces the conductive feature group 212, and the gate group 1316 replaces the gate group 416, and thus similar detailed descriptions are omitted.

[0300] Signal line group 1303 is similar to signal line group 403, so similar detailed description is omitted. Signal line group 1303 includes at least signal line 1303a. Signal line group 1303 is configured to provide routing for signals from upper layers. Signal line 1303a is configured to electrically couple the gate of PMOS transistor P9, the gate of NMOS transistor N11, and the gate of NMOS transistor N15, resulting in additional routing resources compared to other approaches. Other connections to other gates for signal line 1303a are within the scope of this disclosure.

[0301] Other configurations, arrangements at other layout levels, or numbers of structures in the power rail group 702 or the signal line 1303 group are within the scope of the present disclosure. In some embodiments, the signal line group 1303 electrically couples a source or drain feature of a transistor in FIG14 with a gate feature of another transistor in FIG13. In some embodiments, the signal line group 1303 electrically couples a source or drain feature of a transistor in FIG13 with a source or drain feature of another transistor in FIG13.

[0302] Contact group 1306 includes one or more contacts 1306a, 1306b, 1306c, 1306d, 1306e, or 1306f. At least one of contacts 1306a, 1306b, 1306c, 1306d, 1306e, or 1306f is similar to at least one of contacts 406a, 406b, 406c, 406d, 406e, 406f, 406g, or 406h, and thus similar detailed description is omitted.

[0303] In some embodiments, contact 1306a corresponds to the source terminals of PMOS transistors P10 and P9. In some embodiments, contact 1306b corresponds to the source terminals of PMOS transistors P7 and P8. In some embodiments, contact 1306b corresponds to the source terminals of PMOS transistors P7 and P8. In some embodiments, contact 1306d corresponds to the source terminals of PMOS transistors P10 and P9.

[0304] In some embodiments, contact 1306e corresponds to the source terminal of NMOS transistor N12, and contact 1306f corresponds to the source terminal of NMOS transistor N16.

[0305] Other configurations in the contact group 1306 , arrangements on other layout levels, or numbers of contacts are within the scope of the present disclosure.

[0306] Via group 1308 includes one or more vias 1308a, 1308b, 1308c, 1308d, 1308e, or 1308f. At least one of vias 1308a, 1308b, 1308c, 1308d, 1308e, or 1308f is similar to at least one of vias 208a or 208b, and thus similar detailed description is omitted.

[0307] In some embodiments, via 1308a electrically couples power rail 702a and contact 1306a to each other, thereby coupling at least the source terminal of PMOS transistor P9 or P10 to power supply voltage VDD. In some embodiments, via 1308b electrically couples power rail 702a and contact 1306b to each other, thereby coupling at least the source terminal of PMOS transistor P7 or P8 to power supply voltage VDD. In some embodiments, via 1308c electrically couples power rail 702a and contact 1306c to each other, thereby coupling at least the source terminal of PMOS transistor P7 or P8 to power supply voltage VDD. In some embodiments, via 1308d electrically couples power rail 702a and contact 1306d to each other, thereby coupling at least the source terminal of PMOS transistor P9 or P10 to power supply voltage VDD.

[0308] In some embodiments, via 1308e electrically couples power rail 702b and contact 1306e to each other, thereby coupling the source terminal of NMOS transistor N12 to reference supply voltage VSS. In some embodiments, via 1308f electrically couples power rail 702b and contact 1306f to each other, thereby coupling the source terminal of NMOS transistor N16 to reference supply voltage VSS.

[0309] Other configurations in via group 1308 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0310] The through-hole group 1310 includes one or more through-holes 1310a or 1310b. At least one of the through-holes 1310a or 1310b is similar to at least one of the through-holes 410a or 410b, and thus similar detailed description is omitted.

[0311] Via 1310a electrically couples signal line 1303a and gate 1316c to each other, thereby coupling the gate terminal of PMOS transistor P9 and the gate terminal of NMOS transistor N11 to signal line 1303a. Via 1310b electrically couples signal line 1303a and gate 1316h to each other, thereby coupling the gate terminal of PMOS transistor P9 and the gate terminal of NMOS transistor N15 to signal line 1303a. Thus, signal line 1303a and vias 1310a and 1310b electrically couple gates 1316c and 1316h to each other, thereby coupling the gate terminal of PMOS transistor P9, the gate terminal of NMOS transistor N11, and the gate terminal of NMOS transistor N15 to each other, resulting in additional wiring resources on other metal layers compared to other methods.

[0312] Other configurations, arrangements at other layout levels, or numbers of vias in the via group 1310 are within the scope of the present disclosure. Other overlap locations or numbers of overlap locations between one or more of the contact group 1306, the via group 1310, the signal line group 1303, and the gate group 1316, and thus other electrical connections, are within the scope of the present disclosure.

[0313] Conductive component group 1312 includes one or more conductive components 1312a, 1312b, 1312c, 1312d, 1312e, or 1312f. At least one of conductive components 1312a, 1312b, 1312c, 1312d, 1312e, or 1312f is similar to at least one of conductive components 212a, 212b, 212c, 212d, or 212e, and thus similar detailed description is omitted.

[0314] Other configurations in the conductive feature group 1312 , arrangements on other layout levels, or numbers of conductive features are within the scope of the present disclosure.

[0315] The gate group 1316 includes one or more gates 1316a, 1316b, 1316c, 1316d, 1316e, 1316f, 1316g, 1316i or 1316j. Figures 13A-13B 1316a, 1316b, 1316d-1316g, and 1316i-1316j are not labeled. At least one of gates 1316a, 1316b, 1316c, 1316d, 1316e, 1316f, 1316g, 1316i, or 1316j is similar to at least one of gates 416a, 416b, 416c, 416d, or 416e, and thus similar detailed descriptions are omitted.

[0316] In some embodiments, the gate 1316c corresponds to the gate of the PMOS transistor P9 of one of the NMOS transistors N11. In some embodiments, the gate 1316h corresponds to the gates of the PMOS transistor P9 and the NMOS transistor N15.

[0317] In some embodiments, gate 1316b corresponds to the gates of PMOS transistor P10 and NMOS transistor N12. In some embodiments, gate 1316i corresponds to the gates of PMOS transistor P10 and NMOS transistor N16.

[0318] In some embodiments, gate 1316d corresponds to the gates of PMOS transistor P8 and NMOS transistor N10. In some embodiments, gate 1316g corresponds to the gates of PMOS transistor P8 and NMOS transistor N14.

[0319] In some embodiments, gate 1316e corresponds to the gates of PMOS transistor P7 and NMOS transistor N9. In some embodiments, gate 1316f corresponds to the gates of PMOS transistor P7 and NMOS transistor N13.

[0320] The gate 1316c and the gate 1316h are electrically connected to each other through the signal line 1303a and the through-holes 1310a and 1310b.

[0321] Signal line 1303a electrically couples gates 1316c and 1316h together, thereby using at least one smaller upper metal layer track in conductive feature group 1312, thereby enabling integrated circuit 1300 to have at least a smaller height, a smaller area, better IR, EM and RC metal performance, or additional routing resources on other metal layers compared to other approaches.

[0322] Other configurations in gate group 1316 , arrangements on other layout levels, or numbers of conductive features are within the scope of the present disclosure.

[0323] Figures 14A-14B is a diagram of an integrated circuit 1400 according to some embodiments.

[0324] Figures 14A-14B 14 is a top view of corresponding portions 1400A-1400B of integrated circuit 1400, which is simplified for ease of illustration. Integrated circuit 1400 is an embodiment of integrated circuit 1200 having four M0 routing tracks (eg, conductive feature group 1412) and two BS tracks on the back side of integrated circuit 1400.

[0325] Portion 1400A includes one or more features of integrated circuit 1400 at the VBP level, OD level, POLY level, MD level, or M0 level of integrated circuit 1400. Portion 1400B includes one or more features of integrated circuit 1400 at the BP level, BS level, VBP level, VBS level, POLY level, or MD level of integrated circuit 1400.

[0326] For ease of explanation, Figures 14A-14B Some of the marked elements in Figures 14A-14B In some embodiments, the integrated circuit 1400 includes Figures 14A-14B Additional elements not shown.

[0327] The integrated circuit 1400 is manufactured by a corresponding layout design similar to the integrated circuit 1400. FIG. 14A to FIG. 14B Described as integrated circuit 1400, but in some embodiments, FIG. 14A to FIG. 14B Depicted is integrated circuit 1400 . Figures 14A-14B Also corresponding to layout designs similar to layout designs 100, 400, 500A and 500C, the structural elements of integrated circuit 1400 also correspond to the configuration and layers of integrated circuit 1400 including alignment, length and width and structural relationships. For the sake of brevity, similar detailed descriptions will not be described again.

[0328] Integrated circuit 1400 is an integrated circuit 400 ( Figure 4A-4B ) or an embodiment of the integrated circuit 1200.

[0329] Integrated circuit 1400 is Figures 13A-13B For the sake of brevity, similar detailed descriptions will not be given for variations of the integrated circuit 1300. Figures 13A-13B Compared with the integrated circuit 1300 , the conductive component group 1412 of the integrated circuit 1400 replaces the conductive component group 1412 , and the integrated circuit 1400 further includes a signal line group 1403 and a through-hole group 1410 , so similar detailed descriptions are omitted.

[0330] The signal line group 1403 is similar to the signal line group 403, so similar detailed descriptions are omitted. Signal line group 1403 includes at least signal line 1403a. Signal line group 1403 is configured to provide routing for signals from upper layers. Signal line 1403a is configured to electrically couple the gate of PMOS transistor P10, the gate of NMOS transistor N12, and the gate of NMOS transistor N16, resulting in additional routing resources compared to other approaches. Other connections to other gates for signal line 1403a are within the scope of this disclosure.

[0331] Other configurations, arrangements at other layout levels, or numbers of structures in the power rail group 702 or the signal line 1403 group are within the scope of the present disclosure. In some embodiments, the signal line group 1403 electrically couples a source or drain feature of a transistor in FIG14 with a gate feature of another transistor in FIG14. In some embodiments, the signal line group 1403 electrically couples a source or drain feature of a transistor in FIG14 with a source or drain feature of another transistor in FIG14.

[0332] Via group 1410 is similar to via group 410, and thus similar detailed description is omitted. Via group 1410 includes one or more vias 1410a or 1410b. At least one of vias 1410a or 1410b is similar to at least one of vias 410a or 410b, and thus similar detailed description is omitted.

[0333] Via 1410a electrically couples signal line 1403a and gate 1316b to each other, thereby coupling the gate terminal of PMOS transistor P10 and the gate terminal of NMOS transistor N12 to signal line 1403a. Via 1410b electrically couples signal line 1403a and gate 1316i to each other, thereby coupling the gate terminal of PMOS transistor P10 and the gate terminal of NMOS transistor N12 to signal line 1403a. Thus, signal line 1403a and vias 1410a and 1410b electrically couple gates 1316b and 1316i to each other, thereby coupling the gate terminal of PMOS transistor P10, the gate terminal of NMOS transistor N12, and the gate terminal of NMOS transistor N16 to each other, resulting in additional wiring resources on other metal layers compared to other methods.

[0334] Other configurations, arrangements at other layout levels, or numbers of vias in the via group 1410 are within the scope of the present disclosure. Other overlap locations or numbers of overlap locations between one or more of the contact group 1306, the via group 1310 or 1410, the signal line group 1303 or 1403, and the gate group 1316 are within the scope of the present disclosure, and thus, other electrical connections are also within the scope of the present disclosure.

[0335] Conductive component group 1412 includes one or more conductive components 1412a, 1412b, 1412c, 1412d, 1412e, 1412f, 1412g, or 1412h. At least one of conductive components 1412a, 1412b, 1412c, 1412d, 1412e, 1412f, 1412g, or 1412h is similar to at least one of conductive components 212a, 212b, 212c, 212d, or 212e, and thus similar detailed description is omitted.

[0336] Other configurations, arrangements, or numbers of conductive features in the conductive feature group 1412 at other layout levels are within the scope of the present disclosure.

[0337] Gate 1316c and gate 1316h are electrically connected to each other through signal line 1303a and vias 1310a and 1310b. Gate 1316b and gate 1316i are electrically coupled to each other through signal line 1403a and vias 1410a and 1410b.

[0338] Signal line 1303 a electrically couples gates 1316 c and 1316 h together, while signal line 1403 a electrically couples gates 1316 c and 1316 h together, thereby utilizing at least one smaller upper metal layer track in conductive feature group 1412, thereby resulting in integrated circuit 1400 having at least a smaller height, a smaller area, better IR, EM, and RC metal performance, or additional routing resources on other metal layers compared to other approaches.

[0339] Figure 15 1 is a circuit diagram of an integrated circuit 1500 according to some embodiments. In some embodiments, integrated circuit 1500 is a 3-2 NAND logic gate (hereinafter referred to as "NAND") circuit. The 3-2 NAND circuit is for illustration purposes only, and other types of circuits, including other types of NAND circuits, are also within the scope of the present disclosure.

[0340] Integrated circuit 1500 includes PMOS transistors P11 , P12 , and P13 , and NMOS transistors N17 , N18 , N19 , N20 , N21 , and N22 .

[0341] The gate terminal of PMOS transistor P11 is configured as an input node (not labeled) configured to receive input signal A1. The gate terminal of NMOS transistor N17 is configured as an input node (not labeled) configured to receive input signal A1. The gate terminal of NMOS transistor N20 is configured as an input node (not labeled) configured to receive input signal A1. In some embodiments, at least two of the gate terminal of PMOS transistor P11, the gate terminal of NMOS transistor N17, or the gate terminal of NMOS transistor N20 are coupled together.

[0342] The gate terminal of PMOS transistor P12 is configured as an input node (not labeled) configured to receive input signal A2. The gate terminal of NMOS transistor N18 is configured as an input node (not labeled) configured to receive input signal A2. The gate terminal of NMOS transistor N21 is configured as an input node (not labeled) configured to receive input signal A2. In some embodiments, at least two of the gate terminal of PMOS transistor P12, the gate terminal of NMOS transistor N18, or the gate terminal of NMOS transistor N21 are coupled together.

[0343] The gate terminal of PMOS transistor P13 is configured as an input node (not labeled) configured to receive input signal A3. The gate terminal of NMOS transistor N19 is configured as an input node (not labeled) configured to receive input signal A3. The gate terminal of NMOS transistor N22 is configured as an input node (not labeled) configured to receive input signal A3. In some embodiments, at least two of the gate terminal of PMOS transistor P13, the gate terminal of NMOS transistor N19, or the gate terminal of NMOS transistor N22 are coupled together.

[0344] In some embodiments, at least the input signal A1 , A2 , or A3 is a logic low signal or a logic high signal.

[0345] A source terminal of the PMOS transistor P13 is coupled to a voltage source VDD. In some embodiments, a source terminal of the PMOS transistor P11, a source terminal of the PMOS transistor P12, and a source terminal of the PMOS transistor P13 are coupled together.

[0346] A drain terminal of the PMOS transistor P11 , a drain terminal of the PMOS transistor P12 , a drain terminal of the PMOS transistor P13 , a drain terminal of the NMOS transistor N17 , and a drain terminal of the NMOS transistor N20 are coupled to one another and configured as an output node OUT1 .

[0347] The source terminal of the NMOS transistor N17 and the drain terminal of the NMOS transistor N18 are coupled to each other. The source terminal of the NMOS transistor N18 and the drain terminal of the NMOS transistor N19 are coupled to each other. The source terminal of the NMOS transistor N19 is coupled to the reference voltage source VSS.

[0348] The source terminal of NMOS transistor N20 and the drain terminal of NMOS transistor N21 are coupled to each other. The source terminal of NMOS transistor N21 and the drain terminal of NMOS transistor N22 are coupled to each other. The source terminal of NMOS transistor N22 is coupled to reference voltage source VSS. In some embodiments, the source terminal of NMOS transistor N19 and the source terminal of NMOS transistor N22 are coupled together.

[0349] Other circuits, other types of transistors, and / or numbers of transistors are within the scope of various embodiments. For example, in some embodiments, integrated circuit 1500 includes other types of NAND circuits, such as a 3-1 NAND circuit. Other values ​​of at least input signals A1, A2, or A3 are within the scope of various embodiments.

[0350] Figures 16A-16B is a diagram of an integrated circuit 1600 according to some embodiments.

[0351] Figures 16A-16B 16 is a top view of corresponding portions 1600A-1600B of integrated circuit 1600, simplified for ease of illustration. Integrated circuit 1600 is an embodiment of integrated circuit 1500 having three M0 routing tracks (eg, conductive feature group 1612).

[0352] Portion 1600A includes one or more features of integrated circuit 1600 at the VBP level, OD level, POLY level, MD level, or M0 level of integrated circuit 1600. Portion 1600B includes one or more features of integrated circuit 1600 at the BP level, BS level, VBP level, VBS level, POLY level, or MD level of integrated circuit 1600.

[0353] For ease of explanation, 16A to 16B Some of the marked elements in 16A to 16B In some embodiments, the integrated circuit 1600 includes 16A to 16B Additional elements not shown.

[0354] The integrated circuit 1600 is manufactured by a corresponding layout design similar to the integrated circuit 1600. 16A to 16B Described as integrated circuit 1600, but in some embodiments, 16A to 16B Depicted as integrated circuit 1600 . Figures 16A-16B Also corresponding to layout designs similar to layout designs 100, 400, 500A and 500C, the structural elements of integrated circuit 1600 also correspond including alignment, length and width and structural relationships as well as the configuration and layers of integrated circuit 1600, and similar detailed descriptions will not be described again for the sake of brevity.

[0355] Integrated circuit 1600 is an integrated circuit 400 ( Figure 4A-4B ) or an embodiment of integrated circuit 1500.

[0356] Figures 16A-16B is a diagram of an integrated circuit 1600 according to some embodiments.

[0357] Figures 16A-16B 16 is a top view of corresponding portions 1600A-1600B of integrated circuit 1600, simplified for ease of illustration. Integrated circuit 1600 is an embodiment of integrated circuit 1500 having three M0 routing tracks (eg, conductive feature group 1612).

[0358] Portion 1600A includes one or more features of integrated circuit 1600 at the VBP level, OD level, POLY level, MD level, or M0 level of integrated circuit 1600. Portion 1600B includes one or more features of integrated circuit 1600 at the BP level, BS level, VBP level, VBS level, POLY level, or MD level of integrated circuit 1600.

[0359] For ease of explanation, 16A to 16B Some of the marked elements in 16A to 16B In some embodiments, the integrated circuit 1600 includes 16A to 16B Additional elements not shown.

[0360] The integrated circuit 1600 is manufactured by a corresponding layout design similar to that of the integrated circuit 1600. 16A to 16B Described as integrated circuit 1600, but in some embodiments, 16A to 16B Depicted as integrated circuit 1600 . Figures 16A-16B Also corresponding to layout designs similar to layout designs 100, 400, 500A and 500C, the structural elements of integrated circuit 1600 also correspond including alignment, length and width and structural relationships as well as the configuration and layers of integrated circuit 1600, and similar detailed descriptions will not be described again for the sake of brevity.

[0361] Integrated circuit 1600 is an integrated circuit 400 ( Figure 4A-4B ) or an embodiment of integrated circuit 1500.

[0362] and Figure 4A-4B Compared to the integrated circuit 400, the power rail group 702 of the integrated circuit 1600 replaces the power rail group 202, the signal line group 1603 replaces the signal line group 203, the contact group 1606 replaces the contact group 406, and the through hole group 1608 replaces the through hole group 208 (in Figure 2A-2B), the via group 1610 replaces the via group 410, the conductive feature group 1612 replaces the conductive feature group 212, and the gate group 1616 replaces the gate group 416, and thus similar detailed descriptions are omitted.

[0363] Signal line group 1603 is similar to signal line group 403, so similar detailed description is omitted. Signal line group 1603 includes at least signal line 1603a. Signal line group 1603 is configured to provide routing for signals from upper layers of other methods. Signal line 1603a is configured to electrically couple the gate of PMOS transistor P12, the gate of NMOS transistor N18, and the gate of NMOS transistor N21, resulting in additional routing resources compared to other methods. Other connections to other gates for signal line 1603a are within the scope of this disclosure.

[0364] Other configurations, arrangements at other layout levels, or numbers of structures in the power rail group 702 or the signal line 1603 group are within the scope of the present disclosure. In some embodiments, the signal line group 1603 electrically couples a source or drain feature of a transistor in FIG16 with a gate feature of another transistor in FIG16. In some embodiments, the signal line group 1603 electrically couples a source or drain feature of a transistor in FIG16 with a source or drain feature of another transistor in FIG16.

[0365] Contact group 1606 includes one or more contacts 1606a, 1606b, 1606c, 1606d, 1606e, or 1606f. At least one of contacts 1606a, 1606b, 1606c, 1606d, 1606e, or 1606f is similar to at least one of contacts 406a, 406b, 406c, 406d, 406e, 406f, 406g, or 406h, and thus similar detailed description is omitted.

[0366] In some embodiments, contact 1606a corresponds to the source terminal of PMOS transistor P13. In some embodiments, contact 1606b corresponds to the source terminals of PMOS transistors P12 and P11. In some embodiments, contact 1606c corresponds to the source terminals of PMOS transistors P11 and P12. In some embodiments, contact 1606d corresponds to the source terminal of PMOS transistor P13.

[0367] In some embodiments, contact 1606e corresponds to the source terminal of NMOS transistor N19, and contact 1606f corresponds to the source terminal of NMOS transistor N22.

[0368] Other configurations in the contact group 1606 , arrangements on other layout levels, or numbers of contacts are within the scope of the present disclosure.

[0369] Via group 1608 includes one or more vias 1608a, 1608b, 1608c, 1608d, 1608e, or 1608f. At least one of vias 1608a, 1608b, 1608c, 1608d, 1608e, or 1608f is similar to at least one of vias 208a or 208b, and thus similar detailed description is omitted.

[0370] In some embodiments, via 1608a electrically couples power rail 702a and contact 1606a to each other, thereby coupling the source terminal of PMOS transistor P13 to power supply voltage VDD. In some embodiments, via 1608b electrically couples power rail 702a and contact 1606b to each other, thereby coupling at least the source terminal of PMOS transistor P12 or P11 to power supply voltage VDD. In some embodiments, via 1608c electrically couples power rail 702a and contact 1606c to each other, thereby coupling at least the source terminal of PMOS transistor P11 or P12 to power supply voltage VDD. In some embodiments, via 1608d electrically couples power rail 702a and contact 1606d to each other, thereby coupling the source terminal of PMOS transistor P13 to power supply voltage VDD.

[0371] In some embodiments, via 1608e electrically couples power rail 702b and contact 1606e to each other, thereby coupling the source terminal of NMOS transistor N19 to reference supply voltage VSS. In some embodiments, via 1608f electrically couples power rail 702b and contact 1606f to each other, thereby coupling the source terminal of NMOS transistor N22 to reference supply voltage VSS.

[0372] Other configurations in via group 1608 , arrangements on other layout levels, or numbers of vias are within the scope of the present disclosure.

[0373] The through-hole group 1610 includes one or more through-holes 1610a or 1610b. At least one of the through-holes 1610a or 1610b is similar to at least one of the through-holes 410a or 410b, and thus similar detailed description is omitted.

[0374] Via 1610a electrically couples signal line 1603a and gate 1616c to each other, thereby coupling the gate terminal of PMOS transistor P12 and the gate terminal of NMOS transistor N18 to signal line 1603a. Via 1610b electrically couples signal line 1603a and gate 1616f to each other, thereby coupling the gate terminal of PMOS transistor P12 and the gate terminal of NMOS transistor N21 to signal line 1603a. Thus, signal line 1603a and vias 1610a and 1610b electrically couple gates 1616c and 1616f to each other, thereby coupling the gate terminal of PMOS transistor P12, the gate terminal of NMOS transistor N18, and the gate terminal of NMOS transistor N21 to each other, resulting in additional wiring resources on other metal layers compared to other methods.

[0375] Other configurations, arrangements at other layout levels, or numbers of vias in the via group 1610 are within the scope of the present disclosure. Other overlap locations or numbers of overlap locations between one or more of the contact group 1606, the via group 1610, the signal line group 1603, and the gate group 1616, and thus other electrical connections, are within the scope of the present disclosure.

[0376] Conductive component group 1612 includes one or more conductive components 1612a, 1612b, 1612c, or 1612d. At least one of conductive components 1612a, 1612b, 1612c, or 1612d is similar to at least one of conductive components 212a, 212b, 212c, 212d, or 212e, and thus similar detailed description is omitted.

[0377] Conductive member 1612a electrically couples together each drain terminal of PMOS transistors P11, P12, and P13. Conductive member 1612c electrically couples together each gate terminal of NMOS transistors N19 and N22.

[0378] Other configurations in the conductive feature groups 1612 , arrangements on other layout levels, or numbers of conductive features are within the scope of the present disclosure.

[0379] The gate group 1616 includes one or more gates 1616a, 1616b, 1616c, 1616d, 1616e, 1616f, 1616g, or 1616h. Figures 16A-16B Gates 1616a, 1616b, 1616d-1616e, and 1616g-1616h are not labeled. Figures 16A-16BAt least one of gates 1616a, 1616b, 1616c, 1616d, 1616e, 1616f, 1616g, or 1616h is similar to at least one of gates 416a, 416b, 416c, 416d, or 416e, and thus similar detailed descriptions are omitted.

[0380] In some embodiments, gate 1616c corresponds to the gates of PMOS transistor P12 and NMOS transistor N18. In some embodiments, gate 1616f corresponds to the gates of PMOS transistor P12 and NMOS transistor N21.

[0381] In some embodiments, gate 1616b corresponds to the gates of PMOS transistor P13 and NMOS transistor N19. In some embodiments, gate 1616g corresponds to the gates of PMOS transistor P13 and NMOS transistor N22.

[0382] In some embodiments, gate 1616d corresponds to the gates of PMOS transistor P11 and NMOS transistor N17. In some embodiments, gate 1616e corresponds to the gates of PMOS transistor P11 and NMOS transistor N20.

[0383] The gate 1616c and the gate 1616f are electrically connected to each other through the signal line 1603a and the through-holes 1610a and 1610b.

[0384] Signal line 1603a electrically couples gates 1616c and 1616f together, thereby using at least one smaller upper metal layer track in conductive feature group 1612, resulting in integrated circuit 1600 having at least a smaller height, smaller area, better IR, EM and RC metal performance, or other routing resources on other metal layers compared to other approaches.

[0385] Other configurations in gate group 1616 , arrangements on other layout levels, or numbers of conductive features are within the scope of the present disclosure.

[0386] Figure 17 is a flow chart of a method 1700 of forming or manufacturing an integrated circuit according to some embodiments. It should be understood that Figure 17 Additional operations are performed before, during, and / or after the method 1700 depicted in FIG. Figure 17In some embodiments, method 1700 may be used to form an integrated circuit, such as 200, 400, 500B, 500D, 600-1600, or 1900B. In some embodiments, method 1700 may be used to form an integrated circuit having a similar structural relationship to one or more of layout designs 100, 300, 500A, or 500C.

[0387] In operation 1702 of method 1700, a layout design for an integrated circuit is generated. Operation 1702 is performed by a processing device (e.g., processor 2002 ( Figure 20 In some embodiments, the layout design of method 1700 includes at least one layout design 100, 300, 500A, or 500C or one or more patterns that are at least similar to features of integrated circuit 700-900, 1100, 1300-1400, or 1600. In an embodiment, the layout design of the present application is in a Pattern Database System II (GDSII) file format.

[0388] In operation 1704 of method 1700, the integrated circuit is fabricated based on the layout design. In some embodiments, operation 1704 of method 1700 includes: fabricating at least one mask based on the layout design; and fabricating the integrated circuit based on the at least one mask.

[0389] Figure 18 is a flow chart of a method 1800 for generating a layout design for an integrated circuit according to some embodiments. Figure 18 Additional operations are performed before, during, and / or after the method 1800 depicted in FIG. Figure 18 , only a brief description of other processes will be provided. In some embodiments, method 1800 is an embodiment of operation 1702 of method 1700. In some embodiments, method 1800 may be used to generate one or more layout patterns of at least layout design 100, 300, 500A, or 500C, or one or more patterns similar to integrated circuit 200, 400, 500B, 500D, 700-900, 1100, 1300-1400, or 1600. In some embodiments, method 1800 may be used to generate one or more layout patterns having structural relationships including alignment, length, and width, and configurations and layers of at least layout design 100, 300, 500A, or 500C, or at least one or more patterns similar to integrated circuit 200, 400, 500B, 500D, 700-900, 1100, 1300-1400, or 1600, for brevity. Figure 18 Similar detailed description will not be described again.

[0390] In operation 1802 of method 1800, a power rail pattern group is generated or placed on a layout design. In some embodiments, the power rail pattern group of method 1800 includes at least a portion of one or more patterns of power rail pattern group 102. In some embodiments, the power rail pattern group of method 1800 includes at least some features similar to power rail 702.

[0391] In operation 1804 of method 1800, a signal line pattern group is generated or placed on the layout design. In some embodiments, the signal line pattern group of method 1800 includes at least a portion of one or more patterns of signal line pattern group 103. In some embodiments, the signal line pattern group of method 1800 includes at least some features similar to those of signal line groups 703, 1103, 1303, 1403, or 1603.

[0392] At operation 1806 of method 1800, an active area group pattern is generated or placed on the layout design. In some embodiments, the active area group pattern of method 1800 includes at least a portion of one or more patterns of active area group pattern 104. In some embodiments, the active area group pattern of method 1800 includes at least some features similar to active area group 704.

[0393] At operation 1808 of method 1800, a contact pattern set is generated or placed on the layout design. In some embodiments, the contact pattern set of method 1800 includes at least a portion of one or more patterns of contact pattern set 106 or 306. In some embodiments, the contact pattern set of method 1800 includes at least some features similar to contact set 706, 1106, 1306, or 1606.

[0394] At operation 1810 of method 1800, a gate pattern group is generated or placed on a layout design. In some embodiments, the gate pattern group of method 1800 includes at least a portion of one or more patterns in gate pattern group 116 or 316. In some embodiments, the gate pattern group of method 1800 includes at least a portion of features similar to gate group 716, 1116, 1316, or 1616.

[0395] In operation 1812 of method 1800, a first via pattern group is generated or placed on the layout design. In some embodiments, the first via pattern group of method 1800 includes at least a portion of one or more patterns of via pattern group 108. In some embodiments, the first via pattern group of method 1800 includes at least a portion of features similar to via groups 708, 1108, 1308, or 1608.

[0396] In operation 1814 of method 1800, a second via pattern group is generated or placed on the layout design. In some embodiments, the second via pattern group of method 1800 includes at least a portion of one or more patterns of via pattern group 110 or 310. In some embodiments, the second via pattern group of method 1800 includes at least a portion of features similar to via group 710, 1110, 1310, 1410, or 1610.

[0397] At operation 1816 of method 1800, a first conductive component pattern group is generated or placed on the layout design. In some embodiments, the first conductive component pattern group of method 1800 includes at least a portion of one or more patterns in conductive component pattern groups 112, 512, or 514. In some embodiments, the first conductive component pattern group of method 1800 includes at least a portion of features similar to conductive component groups 712, 812, 912, 1112, 1312, 1412, or 1612.

[0398] Figure 19 is a functional flow chart of a method for manufacturing an IC device according to some embodiments. It should be understood that Figure 19 Additional operations may be performed before, during, and / or after the illustrated method 1900. Figure 19 Only some of the other processes are shown in and are only briefly described here.

[0399] In some embodiments, method 1900 is an embodiment of operation 1704 of method 1700. In some embodiments, method 1900 can be used to fabricate or manufacture at least integrated circuit 200, 400, 500B, 500D, 700-1600, or an integrated circuit having at least similar functionality to layout design 100, 300, 500A, or 500C. In some embodiments, other orders of operations of method 1900 are within the scope of the present disclosure. Method 1900 includes example operations, but the operations are not necessarily performed in the order shown. Operations may be added, substituted, reordered, and / or eliminated, as appropriate, consistent with the spirit and scope of the disclosed embodiments.

[0400] In operation 1902 of method 1900, a first transistor group is fabricated in a semiconductor wafer or substrate. In some embodiments, the first transistor group of method 1900 includes NMOS transistors N1-N22, Figure 15 NMOS transistors, PMOS transistors P1-P13 or Figure 15 one or more of the PMOS transistors.

[0401] In some embodiments, operation 1902 includes fabricating source and drain regions of the first transistor group in a first well. In some embodiments, the first well includes a p-type dopant. In some embodiments, the p-type dopant includes boron, aluminum, or other suitable p-type dopant. In some embodiments, the first well includes an epitaxial layer grown on a substrate. In some embodiments, the epitaxial layer is doped by adding a dopant during the epitaxial process. In some embodiments, after forming the epitaxial layer, the epitaxial layer is doped by ion implantation. In some embodiments, the first well is formed by doping the substrate. In some embodiments, the doping is performed by ion implantation. In some embodiments, the dopant concentration of the first well is between 1×10 12 atoms / cm 3 to 1×10 14 atoms / cm 3 within the range.

[0402] In some embodiments, the first well includes an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopant. In some embodiments, the n-type dopant concentration is about 1×10 12 atoms / cm 2 to about 1×10 14 atoms / cm 2 within the range.

[0403] In some embodiments, forming the source / drain features includes removing portions of the substrate to form recesses at the edges of the spacers, and then performing a filling process by filling the recesses in the substrate. In some embodiments, after removing the pad oxide layer or sacrificial oxide layer, the recesses are etched, for example, by wet etching or dry etching. In some embodiments, an etching process is performed to remove a top surface portion of the active area adjacent to the isolation region, such as the STI region. In some embodiments, the filling process is performed by an epitaxial or epitaxial (epi) process. In some embodiments, the recesses are filled using a growth process performed simultaneously with the etching process, wherein the growth rate of the etching process is greater than the etching rate of the etching process. In some embodiments, the recesses are filled using a combination of a growth process and an etching process. For example, a material layer is grown in the recess, and then an etching process is performed on the grown material to remove portions of the material. A subsequent growth process is then performed on the etched material until the desired material thickness is reached in the recess. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate.

[0404] In some embodiments, a portion of the first well is removed using an isotropic or anisotropic etching process. The etching process selectively etches the first well without etching the gate structure and any spacers. In some embodiments, the etching process is performed using reactive ion etching (RIE), wet etching, or other suitable techniques. In some embodiments, semiconductor material is deposited in the recess to form the source / drain components. In some embodiments, an epitaxial process is performed to deposit the semiconductor material in the recess. In some embodiments, the epitaxial process includes a selective epitaxial growth (SEG) process, a CVD process, molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epi process uses gaseous and / or liquid precursors that interact with the composition of the substrate. In some embodiments, the source / drain components include epitaxially grown silicon (epi Si), silicon carbide, or silicon germanium. In some cases, during the epitaxial process, the source / drain components of the IC device associated with the gate structure may be in-situ doped or undoped. If the source / drain components are not doped during the epi process, they may be doped in a subsequent process in some cases. The subsequent doping process is achieved by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, after forming the source / drain features and / or after the subsequent doping process, the source / drain features are further exposed to an annealing process.

[0405] In some embodiments, operation 1902 also includes forming contacts for the first transistor group. In some embodiments, operation 1902 also includes forming gate regions for the first transistor group. In some embodiments, the gate region is between the drain region and the source region. In some embodiments, the gate region is above the first well and the substrate. In some embodiments, fabricating the gate region of operation 1902 includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition process includes chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, fabricating the gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, fabricating the gate region includes forming a gate electrode or a dummy gate electrode. In some embodiments, fabricating the gate region includes depositing or growing at least one dielectric layer, such as a gate dielectric layer. In some embodiments, the gate region is formed using doped or undoped polysilicon (or polysilicon). In some embodiments, the gate region includes a metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0406] In operation 1904 of method 1900, a thinning process is performed on the back side of the wafer or substrate. In some embodiments, operation 1904 includes a thinning process performed on the back side of the semiconductor wafer or substrate. In some embodiments, the thinning process includes a grinding operation and a polishing operation (e.g., chemical mechanical polishing (CMP)) or other suitable process. In some embodiments, after the thinning process, a wet etching operation is performed to remove defects formed on the back side of the semiconductor wafer or substrate.

[0407] In operation 1906 of method 1900, a first set of vias is fabricated in a backside of a wafer or substrate, opposite the frontside. In some embodiments, operation 1906 includes forming a first set of self-aligned contacts (SACs) in an insulating layer over the backside of the wafer. In some embodiments, the first set of vias of method 1900 includes at least a portion of one or more of via groups 208, 708, 1108, 1308, or 1608.

[0408] In operation 1908 of method 1900, a first set of conductive regions is deposited on a backside of the wafer or substrate to form a set of power rails. In some embodiments, operation 1906 includes depositing a first set of conductive regions over at least the backside of the integrated circuit to form a set of backside power rails, the backside power rails being electrically connected to a set of first contacts of the set of transistors through a first set of vias.

[0409] In some embodiments, the power rail group of method 1900 includes at least a portion of one or more of power rail groups 202 or 702. In some embodiments, the first contact group of method 1900 includes at least a portion of one or more of contact groups 206, 406, 706, 1106, 1306, or 1606.

[0410] In operation 1910 of method 1900, a second set of vias is fabricated in the backside of the wafer or substrate. In some embodiments, operation 1910 includes forming a second set of self-aligned contacts (SACs) in an insulating layer above the backside of the wafer. In some embodiments, the second set of vias of method 1900 includes at least a portion of one or more of via groups 210 or 710. In some embodiments, the second set of vias of method 1900 includes at least a portion of one or more of via groups 410, 1110, 1310, 1410, or 1610.

[0411] In operation 1912 of method 1900 , a second set of conductive structures is deposited on the backside of the wafer or substrate to form a set of signal lines.

[0412] In some embodiments, operation 1912 includes depositing a second set of conductive regions over at least the backside of the integrated circuit, thereby forming a second set of backside signal lines electrically connected to the second set of contacts through a second set of vias. In some embodiments, the set of signal lines of method 1900 includes at least a portion of one or more of the sets of signal lines 203 or 703. In some embodiments, the second set of contacts of method 1900 includes at least a portion of one or more of the sets of contacts 206, 406, 706, 1106, 1306, or 1606.

[0413] In some embodiments, operation 1912 includes depositing a second set of conductive regions over at least a backside of the integrated circuit to form a set of backside signal lines electrically connected to the set of gates of the set of transistors through a second set of vias.

[0414] In some embodiments, the signal line group of method 1900 includes at least a portion of one or more of signal line groups 203, 1103, 1303, 1403, or 1603. In some embodiments, the signal line group of method 1900 includes at least a portion of one or more of gate groups 216, 416, 716, 1116, 1316, or 1616.

[0415] In some embodiments, operation 1912 further includes electrically connecting the signal line group to at least the second contact group of the transistor group through the second via group, or electrically connecting the signal line group to at least the gate group of the transistor group through the second via group.

[0416] In operation 1914 of method 1900 , a third conductive structure group is deposited on the first transistor group. In some embodiments, the third conductive structure group of method 1900 includes at least a portion of one or more of conductive feature groups 212 , 512 ′, 514 ′, 712 , 812 , 912 , 1112 , 1312 , 1412 , or 1612 .

[0417] In some embodiments, one or more of operations 1906, 1908, 1910, 1912, or 1914 of method 1900 include forming an opening in an insulating layer (not shown) above the substrate using a combination of photolithography and material removal processes. In some embodiments, the photolithography process includes patterning a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the photolithography process includes forming a hard mask, an anti-reflective structure, or another suitable photolithographic structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, an RIE process, laser drilling, or other suitable etching process. The opening is then filled with a conductive material, such as copper, aluminum, titanium, nickel, tungsten, or other suitable conductive material. In some embodiments, the opening is filled using CVD, PVD, sputtering, ALD, or other suitable formation processes.

[0418] In some embodiments, at least one or more operations of method 1900 are performed by Figure 21 In some embodiments, at least one method (e.g., method 1900 discussed above) is performed in whole or in part by at least one manufacturing system including system 2100. One or more operations of method 1900 are performed by IC fab 2140 ( Figure 21 ) is performed to fabricate IC device 2160. In some embodiments, one or more operations of method 1900 are performed by fabrication tool 2152 to fabricate wafer 2142.

[0419] In some embodiments, one or more operations of methods 1700, 1800, or 1900 are not performed. One or more operations of methods 1700-1800 are performed by a processing device configured to execute instructions for manufacturing an integrated circuit (e.g., integrated circuit 200, 400, 500B, 500D, 700-1600). In some embodiments, one or more operations of methods 1700-1800 are performed using the same processing device as used in a different one or more operations of methods 1700-1800. In some embodiments, a different processing device than the device used to perform the different one or more operations of methods 1700-1800 is used to perform one or more operations of methods 1700-1800. In some embodiments, other orders of operations of methods 1700, 1800, or 1900 are within the scope of the present disclosure. Methods 1700, 1800, or 1900 include example operations, but these operations are not necessarily performed in the order shown. Operations in methods 1700, 1800, or 1900 may be added, substituted, changed in order, and / or eliminated as appropriate, in accordance with the spirit and scope of the disclosed embodiments.

[0420] Figure 202 is a schematic diagram of a system 2000 for designing an IC layout design and fabricating an IC circuit, according to some embodiments. In some embodiments, system 2000 generates or places one or more IC layout designs described herein. System 2000 includes a hardware processor 2002 and a non-transitory computer-readable storage medium 2004 (e.g., memory 2004) encoded with (i.e., storing) computer program code 2006 (i.e., a set of executable instructions 2006). Storage medium 2004 is configured to interface with a fabrication machine for producing integrated circuits. Processor 2002 is electrically coupled to computer-readable storage medium 2004 via bus 2008. Processor 2002 is also electrically coupled to I / O interface 2010 via bus 2008. Network interface 2012 is also electrically coupled to processor 2002 via bus 2008. Network interface 2012 is connected to network 2014 so that processor 2002 and computer-readable storage medium 2004 can connect to external components via network 2014. The processor 2002 is configured to execute computer program code 2006 stored in a computer readable code storage medium 2004 to enable the system 2000 to perform some or all of the operations described in the method 1800 .

[0421] In some embodiments, processor 2002 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0422] In some embodiments, the computer-readable storage medium 2004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, the computer-readable storage medium 2004 includes semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a rigid disk, and / or an optical disk. In some embodiments using optical disks, the computer-readable storage medium 2004 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0423] In some embodiments, storage medium 2004 stores computer program code 2006 configured to cause system 2000 to perform method 1800. In some embodiments, storage medium 2004 also stores information required for performing method 1800 and information generated during the execution of method 1800 (e.g., layout design 2016, user interface 2018, fabrication unit 2020, and / or a set of executable instructions) to perform the operations of method 1800. In some embodiments, layout design 2016 includes at least one or more layout patterns 100, 300, 500A, or 500C, or at least features similar to integrated circuit 700-900, 1100, 1300-1400, 1600, or 1900B.

[0424] In some embodiments, storage medium 2004 stores instructions (e.g., computer program code 2006) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 2006) enable processor 2002 to generate manufacturing instructions readable by the manufacturing machine to effectively implement method 1800 in a manufacturing process.

[0425] System 2000 includes an I / O interface 2010. I / O interface 2010 is coupled to external circuitry. In some embodiments, I / O interface 2010 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for transmitting information and commands to processor 2002.

[0426] System 2000 also includes a network interface 2012 coupled to processor 2002. Network interface 2012 allows system 2000 to communicate with a network 2014, to which one or more other computer systems are connected. Network interface 2012 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-2094. In some embodiments, method 1800 is implemented in two or more systems 2000, and information such as layout designs and user interfaces is exchanged between the different systems 2000 via network 2014.

[0427] The system 2000 is configured to receive information related to a layout design via the I / O interface 2010 or the network interface 2012. The information is transmitted by the bus 2008 to the processor 2002 to determine a layout design for producing at least the integrated circuit 200, 400, 500B, 500D, 600-1600, or 1900B. The layout design is then stored in the computer-readable medium 2004 as a layout design 2016. The system 2000 is configured to receive information related to a user interface via the I / O interface 2010 or the network interface 2012. The information is stored in the computer-readable medium 2004 as a user interface 2000. The system 2000 is configured to receive information related to a fabrication unit via the I / O interface 2010 or the network interface 2012. The information is stored in the computer-readable medium 2004 as a fabrication unit 2020. In some embodiments, the fabrication unit 2020 includes fabrication units. In some embodiments, the fabrication unit 2020 corresponds to Figure 21 Mask manufacturing 2134.

[0428] In some embodiments, method 1800 is implemented as a standalone software application for execution by a processor. In some embodiments, method 1800 is implemented as a software application that is part of an additional software application. In some embodiments, method 1800 is implemented as a plug-in to a software application. In some embodiments, method 1800 is implemented as a software application that is part of an EDA tool. In some embodiments, method 1800 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout for an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer readable medium. In some embodiments, the layout is generated using a tool such as that available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool. In some embodiments, the layout is generated based on a netlist created based on a schematic design. In some embodiments, method 1800 is implemented by a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs generated by system 2000. In some embodiments, system 2000 is a manufacturing device configured to manufacture an integrated circuit. A circuit using a set of masks manufactured based on one or more layout designs of the present disclosure. In some embodiments, Figure 20 The system 2000 generates a layout design of an integrated circuit that is smaller than other methods. In some embodiments, compared to other methods, Figure 20 The system 2000 generates a layout design for an integrated circuit structure that occupies less area and provides better routing resources.

[0429] Figure 211 is a block diagram of an integrated circuit (IC) fabrication system 2100 and an associated IC fabrication flow according to at least one embodiment of the present disclosure. In some embodiments, based on a layout diagram, fabrication system 2100 is used to fabricate at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0430] exist Figure 21 In the present disclosure, an IC manufacturing system 2100 (hereinafter referred to as "system 2100") includes entities that interact with each other in the design, development, manufacturing cycle and / or services related to manufacturing IC devices 2160, such as a design room 2120, a mask room 2130, and an IC manufacturer / fab 2140. The entities in system 2100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more of the other entities. In some embodiments, one or more of the design room 2120, mask room 2130, and IC fab 2140 are owned by a single larger company. In some embodiments, one or more of the design room 2120, mask room 2130, and IC fab 2140 coexist in a common facility and use common resources.

[0431] The design office (or design team) 2120 generates an IC design layout 2122. The IC design layout 2122 includes various geometric patterns designed for the IC device 2160. The geometric patterns correspond to various components of the patterns of the metal, oxide, or semiconductor layers that make up the IC device 2160 to be manufactured. The various layers are combined to form various IC functions. For example, parts of the IC design layout 2122 include various IC functions, such as active areas, gate electrodes, source and drain electrodes, metal lines or vias for interconnecting between layers, and openings for forming pads in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 2120 implements an appropriate design process to form the IC design layout 2122. The design process includes one or more of logical design, physical design, or layout and routing. The IC design layout 2122 is presented in one or more data files having geometric pattern information. For example, the IC design layout 2122 can be expressed in a GDSII file format or a DFII file format.

[0432] 2130 includes data preparation 2132 and mask fabrication 2134. The mask chamber 2130 uses the IC design layout 2122 to fabricate one or more masks 2145, which are used to fabricate various layers of the IC device 2160 based on the IC design layout 2122. The mask chamber 2130 performs mask data preparation 2132, wherein the IC design layout 2122 is translated into a representative data file (RDF). The mask data preparation 2132 provides the RDF to the mask fabrication 2134. The mask fabrication 2134 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 2145 or a semiconductor wafer 2142. The design layout 2122 is manipulated by the mask data preparation 2132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 2140. In Figure 21 , mask data preparation 2132 and mask fabrication 2134 are shown as separate elements. In some embodiments, mask data preparation 2132 and mask fabrication 2134 may be collectively referred to as mask data preparation.

[0433] In some embodiments, mask data preparation 2132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects, etc. OPC adjusts IC design layout 2122. In some embodiments, mask data preparation 2132 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0434] In some embodiments, mask data preparation 2132 includes a mask rule checker (MRC) that checks the IC design layout, which has been processed in OPC, using a set of mask creation rules. The mask creation rules contain certain geometric and / or connectivity constraints to ensure sufficient margin to account for issues such as variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask fabrication 2134, which can undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0435] In some embodiments, mask data preparation 2132 includes lithography process checking (LPC), a process simulation that will be implemented by ICfab 2140 to manufacture the process of IC device 2160. LPC simulates the process based on the IC design layout 2122 to create a simulated manufacturing process. The processing parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to the tools used to manufacture the IC and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc. or a combination thereof. In some embodiments, after a simulated manufacturing device is created by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 2122.

[0436] It should be understood that the above description of mask data preparation 2132 has been simplified for clarity. In some embodiments, mask data preparation 2132 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. In addition, the processes applied to IC design layout 2122 during mask data preparation 2132 can be performed in a variety of different orders.

[0437] After mask data preparation 2132 and during mask fabrication 2134, a mask 2145 or a set of masks 2145 are fabricated based on the modified IC design layout 2122. In some embodiments, mask fabrication 2134 includes performing one or more photolithographic exposures based on the IC design 2122. In some embodiments, an electron beam (e-beam) or multiple e-beam mechanisms are used to form a pattern on a mask (photomask or reticle) 2145 based on the modified IC design layout 2122. Mask 2145 can be formed using various techniques. In some embodiments, mask 2145 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) already coated on a wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary form of mask 2145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 2145 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 2145, various features in the pattern formed on the mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The masks produced by mask manufacturing 2134 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0438] IC Fab 2140 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC Fab 2140 is a semiconductor foundry. For example, one fabrication facility may be used for front-end fabrication of multiple IC products (front-end of line (FEOL) fabrication), while a second fabrication facility may provide back-end fabrication of IC products for interconnection and packaging (back-end of line (BEOL) fabrication), and a third fabrication facility may provide other services for the foundry entity.

[0439] IC fab 2140 includes a wafer fabrication tool 2152 (hereinafter referred to as "fabrication tool 2152") configured to perform various fabrication operations on semiconductor wafer 2142 to fabricate IC devices 2160 according to one or more masks (e.g., mask 2145). In various embodiments, fabrication tool 2152 includes one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication devices capable of performing one or more suitable fabrication processes described herein.

[0440] IC fab 2140 uses mask 2145 manufactured by mask chamber 2130 to manufacture IC device 2160. Therefore, IC fab 2140 at least indirectly uses IC design layout 2122 to manufacture IC device 2160. In some embodiments, semiconductor wafer 2142 is formed into IC device 2160 by IC fab 2140 using mask 2145. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on IC design 2122. Semiconductor wafer 2142 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 2142 further includes one or more of various doped regions, dielectric features, multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0441] System 2100 is shown with design chamber 2120, mask chamber 2130, or IC fab 2140 as separate components or entities. However, it should be understood that one or more of design chamber 2120, mask chamber 2130, or IC fab 2140 are part of the same component or entity.

[0442] Details regarding integrated circuit (IC) manufacturing systems (e.g., system 1300 of FIG. 13 ) and the IC manufacturing processes associated therewith are found, for example, in U.S. Patent No. 9,256,709, issued on February 9, 2016, U.S. Pre-Grant Publication No. 20150278429, issued on October 1, 2015, U.S. Pre-Grant Publication No. 20140040838, issued on February 6, 2014, and U.S. Patent No. 7,260,442, issued on August 21, 2007, the entire contents of which are incorporated herein by reference.

[0443] For example, in U.S. Patent No. 9,256,709, an IC design layout is generated in a design house (or design team). The IC design layout includes various geometric patterns designed for the IC device. The geometric patterns correspond to the patterns of the metal, oxide, or semiconductor layers that make up the various components of the IC device to be manufactured. The various layers are combined to form various IC functions. For example, parts of the IC design layout include various IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines or vias for interconnecting between layers, and openings for pads formed in the semiconductor, which will be formed in the semiconductor substrate (e.g., silicon wafer) and various material layers disposed on the semiconductor substrate. The design house performs appropriate design processes to form the IC design layout. The design process may include logical design, physical design, and / or layout and routing. The IC design layout is presented in one or more data files with geometric pattern information. The mask house uses the IC design layout to manufacture one or more masks, which are used to manufacture the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, where the IC design layout is converted into a form that can be physically written by a mask writer, where the design layout prepared by the mask data preparation is modified to comply with a specific mask manufacturer and / or mask vendor and then manufactured. In this embodiment, mask data preparation and mask manufacturing are illustrated as separate elements, however, mask data preparation and mask manufacturing can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be due to diffraction, interference or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout that has been processed in OPC, which mask creation rules may contain some geometric and connectivity restrictions to ensure sufficient margins.

[0444] For example, in U.S. Pre-Grant Publication No. 20150278429, in one embodiment, an IC manufacturing system can employ maskless lithography, such as electron beam lithography or optical maskless lithography. In such a system, mask manufacturing is bypassed, and the IC design layout is modified by data preparation suitable for wafer processing using a specific maskless lithography technology. The data preparation modifies the design layout suitable for subsequent operations in the IC manufacturing system. The results of the data preparation are represented by one or more data files, such as files in a GDSII file format or a DFII file format. The one or more data files include information about geometric patterns, such as polygons representing main design patterns and / or auxiliary components. In this embodiment, the one or more data files also include auxiliary data generated by the data preparation. The auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask manufacturing performed by a mask chamber and wafer exposure performed by an IC manufacturer.

[0445] For example, in pre-authorization announcement No. 20140040838, the IC design layout is presented in one or more data files with geometric pattern information. In one example, the IC design layout is represented in the "GDS" format known in the art. In an alternative embodiment, the IC design layout can be transmitted between components in the IC manufacturing system in an alternative file format such as DFII, CIF, OASIS or any other suitable file type. The IC design layout 300 includes various geometric patterns representing components of the integrated circuit. For example, the IC design layout may include major IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines, interlayer interconnect vias, and openings for pads formed in the semiconductor, the openings to be formed in the semiconductor substrate (e.g., silicon wafer) and various material layers provided on the semiconductor substrate. The IC design layout may also include some auxiliary components, such as those used for imaging effects, processing enhancements and / or mask identification information.

[0446] For example, in U.S. Patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; a controller, coupled to the processing tool and the metrology tool, for generating a manufacturing model of the processing tool and calibrating the manufacturing model based on device data, material data, and inspection results of the mask. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs post-etch inspection or post-strip inspection and obtains post-etch inspection results or post-strip inspection results, respectively. The controller is used for run-to-run control of the processing tool, including feedforward control and feedback control. The controller receives post-etch or post-strip inspection results from the metrology tool and retrieves device and material data from the database. The controller, coupled to the manufacturing execution system, generates a manufacturing model of the processing tool and calibrates the manufacturing model based on device data, material data, and inspection results of the mask. The controller also monitors the operating conditions of the processing tool and adjusts the manufacturing model of the processing tool during processing.

[0447] One aspect of the present disclosure relates to an integrated circuit. In some embodiments, the integrated circuit includes: a first power rail extending in a first direction on a back side of a substrate; a second power rail extending in the first direction on the back side of the substrate and separated from the first power rail in a second direction different from the first direction; a signal line extending in the first direction on the back side of the substrate and between the first power rail and the second power rail; and a first active area of ​​a first transistor group, the first active area extending in the first direction and located on a first level of a front side of the substrate opposite the back side.

[0448] In the above integrated circuit, it further includes: a second active region of the second transistor group, the second active region extending in the first direction, on the first level of the front side of the substrate, and separated from the first active region in the second direction.

[0449] In the above-mentioned integrated circuit, it also includes: a first contact member, extending in the second direction, overlapping with the first active area, and located on a second level different from the first level; and a second contact member, extending in the second direction, overlapping with the second active area, located on the second level, electrically connected to the first contact member, and separated from the first contact member in the first direction.

[0450] The integrated circuit further includes: a first through-hole between the signal line and the first contact, the first through-hole electrically coupling the signal line to the first contact; and a second through-hole between the signal line and the second contact, the second through-hole electrically coupling the signal line to the second contact.

[0451] In the above-mentioned integrated circuit, it also includes: a first contact member, which extends in the second direction, overlaps with the first active area, and is located on a second level different from the first level; and a second contact member, which extends in the second direction, overlaps with the second active area, is located on the second level, and is separated from the second contact member in the first direction.

[0452] In the above integrated circuit, it also includes: a first through-hole between the first power rail and the first contact, the first through-hole electrically coupling the first power rail to the first contact; and a second through-hole between the second power rail and the second contact, the second through-hole electrically coupling the second power rail to the second contact.

[0453] The integrated circuit further includes: a gate group extending along the second direction, overlapping with the first active area, and located on a second level different from the first level, wherein each gate in the gate group is separated from adjacent gates in the gate group by a first pitch in the first direction.

[0454] The above integrated circuit also includes: a conductive structure group, which extends and overlaps along the first direction and is located on a third level different from the first level and the second level, and at least one conductive structure in the conductive structure group is separated from the adjacent conductive structure in the conductive structure group by a second pitch spacing in the second direction.

[0455] In the above integrated circuit, the first transistor group is part of an AND or inversion logic circuit.

[0456] Another aspect of the present disclosure relates to an integrated circuit. In some embodiments, the integrated circuit includes: a first power rail extending in a first direction on a back side of a substrate; a second power rail extending in the first direction on the back side of the substrate and separated from the first power rail in a second direction different from the first direction; a first conductive structure extending in the first direction and between the first and second power rails on the back side of the substrate; a first gate extending in a second direction, overlapping at least the first conductive structure, and located on a first level on a front side of the substrate opposite the back side; and a second gate extending in the second direction, overlapping at least the first conductive structure, located on a first level, and separated from the first gate in the first direction, wherein the first conductive structure electrically couples the first gate to the second gate.

[0457] In the above integrated circuit, it also includes: a first through hole between the first conductive structure and the first gate, the first through hole electrically coupling the first conductive structure to the first gate; and a second through hole between the first conductive structure and the second gate, the second through hole electrically coupling the first conductive structure to the second gate.

[0458] In the above-mentioned integrated circuit, it also includes: a second conductive structure, located on the back side of the substrate, extending along the first direction, and located between the first conductive structure and the second power rail; a third gate, extending in the second direction, overlapping at least the first conductive structure and the second conductive structure, located on the first level, and separated from the first gate in the first direction; and a fourth gate, extending in the second direction, overlapping at least the first conductive structure and the second conductive structure, located on the first level, and separated from the third gate in the first direction, wherein the second conductive structure electrically couples the third gate to the fourth gate.

[0459] In the above integrated circuit, it also includes: a third through hole between the second conductive structure and the third gate, the third through hole electrically coupling the second conductive structure to the third gate; and a fourth through hole between the second conductive structure and the fourth gate, the fourth through hole electrically coupling the second conductive structure to the fourth gate.

[0460] In the above-mentioned integrated circuit, it also includes: a first active area of ​​the first transistor group, the first active area extends in the first direction and is located on a second level different from the first level; and a second active area of ​​the second transistor group, the second active area extends in the first direction, is located on the second level, and is separated from the first active area in the second direction.

[0461] In the above-mentioned integrated circuit, it also includes: a first contact member, which extends in the second direction, overlaps with the first active area, and is located on a third level that is at least different from the second level; and a second contact member, which extends in the second direction, overlaps with the second active area, is located on the third level, and is separated from the second contact member in the first direction.

[0462] In the above integrated circuit, it also includes: a first through-hole between the first power rail and the first contact, the first through-hole electrically coupling the first power rail to the first contact; and a second through-hole between the second power rail and the second contact, the second through-hole electrically coupling the second power rail to the second contact.

[0463] In the above integrated circuit, the integrated circuit is part of a NAND logic circuit.

[0464] Another aspect of the present disclosure relates to a method for fabricating an integrated circuit. In some embodiments, the method includes fabricating a transistor group in a front side of a substrate; fabricating a first via group in a back side of the substrate opposite the front side; depositing a first conductive structure group on the back side of the substrate to form a power rail group electrically connected to a first contact group of the transistor group through the first via group; fabricating a second via group in the back side of the substrate; and depositing a second conductive structure group on the back side of the substrate to form a signal line group on the back side of the substrate.

[0465] In the above method, depositing the second conductive structure group on the back side of the substrate includes: electrically connecting the signal line group to the second contact group of the transistor group through the second via group; or electrically connecting the signal line group to at least the gate group of the transistor group through the second via group.

[0466] In the above method, the step further includes performing thinning on a back side of the substrate opposite to the front side.

[0467] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications in the present invention without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit comprising: a first power rail on the back side of the substrate and extending in a first direction, a second power rail on the back side of the substrate extending in the first direction and separated from the first power rail in a second direction different from the first direction; a signal line on the back side of the substrate and extending in the first direction and between the first power rail and the second power rail; as well as a first active area of ​​a first transistor group, the first active area extending in the first direction and being located on a first level of a front side of the substrate opposite the back side; a second active area of ​​a second transistor group, the second active area extending in the first direction, on the first level of the front side of the substrate, and separated from the first active area in the second direction; a first contact extending in the second direction, overlapping the first active region and the signal line, and located on a second level different from the first level; as well as a second contact extending in the second direction, overlapping the second active area and the signal line, located on the second level, and electrically connected to the first contact through the signal line; The first contact is completely enclosed around the first active area, and the second contact is completely enclosed around the second active area.

2. The integrated circuit according to claim 1 , further comprising: a third contact extending in the second direction, overlapping the second active region, located on the second level, and separated from the second contact in the first direction; as well as A fourth contact extends in the second direction, overlaps the first active region, is located on the second level, and is separated from the first contact in the first direction.

3. The integrated circuit of claim 1 , wherein: The second contact piece is separated from the first contact piece in the first direction.

4. The integrated circuit of claim 1 , further comprising: a first via between the signal line and the first contact, the first via electrically coupling the signal line to the first contact; and A second via is between the signal line and the second contact, the second via electrically coupling the signal line to the second contact.

5. The integrated circuit of claim 2, wherein: The first transistor group has a first conductivity type, and the second transistor group has a second conductivity type different from the first conductivity type.

6. The integrated circuit of claim 2 , further comprising: a third via between the first power rail and the third contact, the third via electrically coupling the first power rail to the third contact; and A fourth via is between the second power rail and the fourth contact, the fourth via electrically coupling the second power rail to the fourth contact.

7. The integrated circuit of claim 1 , further comprising: A gate group extends along the second direction, overlaps the first active area, and is located on a third level different from the first level. Each gate in the gate group is separated from adjacent gates in the gate group by a first pitch in the first direction.

8. The integrated circuit of claim 7, further comprising: A conductive structure group extends and overlaps along the first direction and is located on a fourth level different from the first level, the second level and the third level, and at least one conductive structure in the conductive structure group is separated from an adjacent conductive structure in the conductive structure group by a second pitch spacing in the second direction.

9. The integrated circuit according to claim 1, wherein: The first transistor group is part of an AND or inverting logic circuit.

10. An integrated circuit comprising: a first power rail on the back side of the substrate and extending in a first direction, a second power rail on the back side of the substrate extending in the first direction and separated from the first power rail in a second direction different from the first direction; a signal line on the back side of the substrate and extending in the first direction and between the first power rail and the second power rail; a first conductive structure on the back side of the substrate, the first conductive structure extending in the first direction and between the first power rail and the second power rail; a first gate extending in the second direction, overlapping at least the first conductive structure, and located on a first level of a front side of the substrate opposite to the back side; as well as a second gate extending in the second direction, overlapping at least the first conductive structure, located on the first level, and separated from the first gate in the first direction; a first active region of the first transistor group, the first active region extending in the first direction and located at a second level different from the first level; a second active region of a second transistor group, the second active region extending in the first direction, being located on the second level, and being separated from the first active region in the second direction, a first contact extending in the second direction, overlapping the first active region and the signal line, and located on a third level different from at least the second level; as well as a second contact extending in the second direction, overlapping the second active area and the signal line, located on the third level, and electrically connected to the first contact through the signal line; The first conductive structure electrically couples the first gate to the second gate, the first contact completely surrounds the first active region, and the second contact completely surrounds the second active region.

11. The integrated circuit of claim 10 , further comprising: a first via between the first conductive structure and the first gate, the first via electrically coupling the first conductive structure to the first gate; and A second via is between the first conductive structure and the second gate, wherein the second via electrically couples the first conductive structure to the second gate.

12. The integrated circuit of claim 11 , further comprising: a second conductive structure located on the back side of the substrate, extending along the first direction, and located between the first conductive structure and the second power rail; a third gate extending in the second direction, overlapping at least the first conductive structure and the second conductive structure, located on the first level, and separated from the first gate in the first direction; and a fourth gate extending in the second direction, overlapping at least the first conductive structure and the second conductive structure, located on the first level, and separated from the third gate in the first direction, The second conductive structure electrically couples the third gate to the fourth gate.

13. The integrated circuit of claim 12, further comprising: a third via between the second conductive structure and the third gate, the third via electrically coupling the second conductive structure to the third gate; and A fourth via is between the second conductive structure and the fourth gate, and the fourth via electrically couples the second conductive structure to the fourth gate.

14. The integrated circuit of claim 10, wherein: The first transistor group includes: a first transistor; a second transistor; and a third transistor; The second transistor group includes: a fourth transistor; The fifth transistor.

15. The integrated circuit of claim 14, wherein: The second contact is separated from the first contact in the first direction.

16. The integrated circuit of claim 15, further comprising: a first via between the first power rail and the first contact, the first via electrically coupling the first power rail to the first contact; and A second via is between the second power rail and the second contact, the second via electrically coupling the second power rail to the second contact.

17. The integrated circuit of claim 10, wherein: The integrated circuit is part of a NAND logic circuit.

18. A method of manufacturing an integrated circuit, the method comprising: fabricating a transistor group in the front side of the substrate; fabricating a first set of through-holes in a back side of the substrate opposite the front side; depositing a first set of conductive structures on the back side of the substrate to form a set of power rails electrically connected to a first set of contacts of the set of transistors through the first set of vias; fabricating a second set of vias in the back side of the substrate; as well as depositing a second set of conductive structures on the back side of the substrate to form a set of signal lines on the back side of the substrate; electrically connecting the set of signal lines to the second set of contacts of the set of transistors through the second set of vias, At least two contacts in the second group of contacts are electrically connected to each other through a signal line of the signal line group, and the at least two contacts in the second group of contacts completely enclose active regions of corresponding transistors of the transistor group.

19. The method according to claim 18, wherein The second through-hole group overlaps with the signal line group.

20. The method of claim 18, further comprising: Thinning is performed on a back side of the substrate opposite to the front side.

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