A method for preparing a MEMS thermoelectric device based on phononic crystals
By fabricating MEMS thermoelectric devices with phononic crystal structures on SOI substrates, the problem of imbalance between thermal conductivity and electrical conductivity has been solved, achieving efficient thermoelectric conversion and waste heat utilization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
- Filing Date
- 2020-03-04
- Publication Date
- 2026-06-02
AI Technical Summary
Existing thermoelectric devices suffer from a balance problem in terms of thermal conductivity and electrical conductivity, resulting in poor thermoelectric performance and difficulty in effectively utilizing waste heat.
The method for fabricating MEMS thermoelectric devices using phononic crystal structures involves etching thermoelectric conversion structures on SOI substrates and combining photolithography, etching, and thin film processes to fabricate suspended thermoelectric devices, thereby reducing thermal conductivity and forming phononic crystals to improve thermoelectric conversion efficiency.
It achieves efficient thermoelectric conversion of thermoelectric devices, can integrate and reduce temperature on the chip, and converts the heat emitted by the chip into electrical energy, realizing waste heat utilization.
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Figure CN113363375B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of thermoelectric device fabrication technology, and in particular to a method for fabricating MEMS thermoelectric devices based on phonon crystals. Background Technology
[0002] With the development of human society and economy, energy consumption is constantly increasing. In the combustion of traditional fossil fuels and the operation of other mechanical and electronic devices, approximately 55% or more of the energy is ultimately released into the environment as heat. Thermoelectric materials can utilize the movement of charge carriers within semiconductors to achieve the mutual conversion of thermal and electrical energy, reusing waste heat. Compared with traditional power generation technologies, it has the following advantages: no moving mechanical components, less prone to failure, no noise generation, no pollution, and can be made into small, portable devices. Thermoelectric materials with phononic crystal structures exhibit reduced thermal conductivity due to size effects and interface scattering, while electrical conductivity remains largely unaffected. Therefore, their thermoelectric devices can achieve high thermoelectric figures of merit and possess excellent thermoelectric performance. Summary of the Invention
[0003] (a) Technical problems to be solved
[0004] This disclosure provides a method for fabricating MEMS thermoelectric devices based on phononic crystals. This method reduces the thermal conductivity of the thermoelectric device by using phononic crystals to fabricate a suspended structure and realize thermoelectric conversion function.
[0005] (II) Technical Solution
[0006] A method for fabricating a MEMS thermoelectric device based on a phonon crystal includes: S1, etching a thermoelectric conversion structure 100 on the top silicon layer of an SOI substrate, the thermoelectric conversion structure 100 including a connecting portion and two ends connected to both ends of the connecting portion; S2, growing a silicon nitride film 102 on the upper surface of the structure obtained in step S1; S3, etching the silicon nitride film 102 to form a support arm and a support island, wherein the support island is disposed at the two ends, and the support arm is connected to the support island; S4, depositing a first metal 1 on the support island. S3, and etch the first metal 103 to form a metal pattern; S5, deposit the second metal 104 on the support arm, and make the second metal 104 form an ohmic contact with the top silicon through an annealing process; S6, prepare a phononic crystal at the connection of the thermoelectric conversion structure 100; S7, grow a mask layer on the upper surface of the structure obtained in step S6 and the lower surface of the SOI substrate; S8, etch the buried oxide layer 101 from the lower surface to the SOI substrate; S9, remove the buried oxide layer 101; S10, remove the mask layer on the upper surface.
[0007] Optionally, step S1 may further include doping the thermoelectric conversion structure 100 with one of the following methods: ion implantation, diffusion, or doping epitaxy, to form low-resistivity characteristics.
[0008] Optionally, step S6 includes: S61, preparing a phonon crystal pattern using a dot matrix exposure method; S62, transferring the phonon crystal pattern to the connection portion of the thermoelectric conversion structure 100 using ICP dry etching.
[0009] Optionally, gaseous HF is used to remove the buried oxygen layer 101.
[0010] Optionally, in step S8, the surface may be etched using either ICP dry etching or solution wet etching.
[0011] Optionally, the first metal 103 is a combination of Cr and Pt, and the first metal 103 is deposited on the support island by sputtering or evaporation.
[0012] Optionally, the second metal 104 is one, several, or a combination of alloys selected from Cr, Ni, Ti, Pt, Au, Al, Ag, Cu, W, Pd, and Mo, and is deposited on the support arm by sputtering or evaporation.
[0013] Optionally, if the SOI substrate thickness is greater than a preset value, the lower surface may be ground and polished before step S7 to reduce the thickness of the SOI substrate.
[0014] Optionally, silicon nitride film 102 is prepared using one of PECVD, LPCVD or ICP-CVD.
[0015] Optionally, the top silicon layer of the SOI substrate is either N-type silicon or P-type silicon, with the following crystal orientation: <100> , <110> or <111> One of them.
[0016] (III) Beneficial Effects
[0017] The fabrication method employed in this application, utilizing photolithography, etching, and thin-film processes, is effectively compatible with CMOS technology and allows for mass production. Furthermore, integrating thermoelectric devices onto the chip reduces its temperature and allows for the conversion of heat dissipated by the chip into electrical energy, thus achieving waste heat utilization. Attached Figure Description
[0018] Figure 1 The schematic diagram illustrates the steps of a method for fabricating a MEMS thermoelectric device based on a phonon crystal according to an embodiment of the present disclosure;
[0019] Figure 2A A schematic front view is shown after a thermoelectric conversion structure has been fabricated on the top silicon layer of an SOI substrate according to an embodiment of the present disclosure;
[0020] Figure 2B This illustration schematically depicts an embodiment according to the present disclosure. Figure 2A The corresponding top view;
[0021] Figure 3A This illustration schematically depicts an embodiment according to the present disclosure. Figure 2A A structural diagram showing the structure after the support arms and support islands have been fabricated.
[0022] Figure 3B This illustration schematically depicts an embodiment according to the present disclosure. Figure 3A The corresponding top view;
[0023] Figure 4A This illustration schematically depicts an embodiment according to the present disclosure. Figure 3A A structural diagram showing the structure after the first metal is fabricated.
[0024] Figure 4B This illustration schematically depicts an embodiment according to the present disclosure. Figure 4A The corresponding top view;
[0025] Figure 5A This illustration schematically depicts an embodiment according to the present disclosure. Figure 4A A structural diagram showing the structure after the second metal has been fabricated.
[0026] Figure 5B This illustration schematically depicts an embodiment according to the present disclosure. Figure 5A The corresponding top view;
[0027] Figure 6A This illustration schematically depicts an embodiment according to the present disclosure. Figure 5A A schematic diagram of the structure used to fabricate a phononic crystal;
[0028] Figure 6B This illustration schematically depicts an embodiment according to the present disclosure. Figure 6A The corresponding top view;
[0029] Figure 7 This illustration schematically depicts an embodiment according to the present disclosure. Figure 6A A schematic diagram of the structure after growing mask layers on the upper and lower surfaces of the structure shown;
[0030] Figure 8 This illustration schematically depicts an embodiment according to the present disclosure. Figure 7 A schematic diagram of the structure after the lower surface has been etched;
[0031] Figure 9A This illustration schematically depicts an embodiment according to the present disclosure. Figure 8 Front view of the structure after removing the buried oxide layer;
[0032] Figure 9B This illustration schematically depicts an embodiment according to the present disclosure. Figure 9A The corresponding main view;
[0033] Figure 10A This illustration schematically depicts an embodiment according to the present disclosure. Figure 9A The diagram shows the front view of the structure after removing the upper surface mask layer.
[0034] Figure 10B This illustration schematically depicts an embodiment according to the present disclosure. Figure 10A The corresponding top view;
[0035] Figure 11 The illustration schematically shows an optical microscope image of a thermoelectric conversion structure fabricated on the top silicon layer of an SOI substrate according to an embodiment of the present disclosure.
[0036] Figure 12 SEM images of the support arm and support island according to embodiments of the present disclosure are shown schematically.
[0037] Figure 13 The illustration schematically shows a SEM image of Cr / Pt after electron beam evaporation and pattern stripping according to an embodiment of the present disclosure;
[0038] Figure 14 An SEM image of a phonon crystal according to an embodiment of the present disclosure is shown schematically. Detailed Implementation
[0039] A method for fabricating MEMS thermoelectric devices based on phonon crystals, such as Figure 1 As shown, the method includes: S1, etching a thermoelectric conversion structure on the top silicon layer of the SOI substrate, the thermoelectric conversion structure including a connecting portion and two ends connected to both ends of the connecting portion; S2, growing a silicon nitride film on the upper surface of the structure obtained in step S1; S3, etching the silicon nitride film to form support arms and support islands, wherein the support islands are located at both ends, and the support arms are connected to the support islands; S4, depositing a first metal on the support islands and etching the first metal to form a metal pattern; S5, depositing a second metal on the support arms, and annealing the second metal to form an ohmic contact with the top silicon layer; S6, fabricating a phononic crystal on the connecting portion of the thermoelectric conversion structure; S7, growing a mask layer on the upper surface of the structure obtained in step S6 and the lower surface of the SOI substrate; S8, etching the buried oxide layer from the lower surface to the SOI substrate; S9, removing the buried oxide layer; S10, removing the mask layer on the upper surface.
[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0041] S1, a thermoelectric conversion structure 100 is etched on the top silicon layer of the SOI substrate. The thermoelectric conversion structure 100 includes a connecting portion and two ends connected to both ends of the connecting portion.
[0042] Thermoelectric conversion structure 100 is fabricated by photolithography and etching on the top silicon layer of the SOI substrate, such as... Figure 2A and Figure 2B As shown, where, Figure 2A A front view of the thermoelectric conversion structure 100 fabricated by photolithography and etching on the top silicon layer of the SOI substrate. Figure 2B for Figure 2A The corresponding top view. The thermoelectric conversion structure 100 can be doped using one of the following methods: ion implantation, diffusion, or doping epitaxy, to achieve low-resistivity characteristics. The top silicon crystal orientation of the SOI substrate is... <100> , <110> or <111> In either case, the top silicon layer is doped with either N-type or P-type materials. The donor impurity for N-type doping is a group V element, and the acceptor impurity for P-type doping is a group III element. The N-type doping concentration and the P-type doping concentration are arbitrary. The buried oxide layer 101 of the SOI substrate has an arbitrary thickness. The thermoelectric conversion structure 100 can be I-shaped, including a connecting portion and two ends connected to both ends of the connecting portion.
[0043] S2, A silicon nitride film 102 is grown on the upper surface of the structure obtained in step S1.
[0044] The upper surface of the structure obtained in step S1 is coated with a silicon nitride film 102 using methods such as PECVD, LPCVD, or ICP-CVD, which serves as an insulating or support layer. The thickness of the silicon nitride film 102 is selected based on the principle of providing sufficient support strength while keeping the thickness as thin as possible.
[0045] S3, etch the silicon nitride film 102 to form a support arm and a support island, wherein the support island is located at both ends and the support arm is connected to the support island;
[0046] The dimensions and positions are defined using photolithography or etching methods, with support islands located at both ends and support arms connected to the support islands, such as... Figure 3A and 3B As shown, where, Figure 3A Main view, Figure 4B for Figure 3A The corresponding top view.
[0047] S4, deposit the first metal 103 on the support island and etch the first metal 103 to form a metal pattern;
[0048] The first metal 103 was deposited on the supporting island, such as Figure 4A and Figure 4B As shown, where, Figure 4A This is the front view after the deposition of the first metal 103. Figure 4B for Figure 4AThe corresponding top view. The first metal 103 can be a combination of Cr and Pt, with Pt metal exhibiting excellent temperature resistance characteristics. The first metal 103 is deposited on the support island using sputtering or evaporation. The position and size of the first metal 103 are defined by photolithography. Etching can be dry or wet etching. The function of the first metal 103 is heating or temperature measurement; its thickness is typically 30-200 nm. The resistance of the metal changes linearly with temperature; by measuring the resistance value, the temperature value can be determined.
[0049] One of the support islands has a heating metal fabricated on it, and the other support island has a temperature-sensing metal fabricated on it. The heat generated by the heating metal is converted into a thermoelectric effect through the thermoelectric conversion structure 100, generating a potential difference.
[0050] S5, deposit a second metal 104 on the support arm, and make the second metal 104 form an ohmic contact with the top silicon through an annealing process;
[0051] A second metal 104 is deposited on the support arm, such as Figure 5A and Figure 5B As shown, the second metal 104 can be one, several, or a combination alloy of Cr, Ni, Ti, Pt, Au, Al, Ag, Cu, W, Pd, and Mo. The second metal 104 is deposited on the support arm by sputtering or evaporation. The etching of the second metal 104 can be done using dry or wet etching methods. The second metal 104 is used to form ohmic contacts as electrode interconnect leads, and its thickness is typically 100-1000 nm.
[0052] S6, a phononic crystal is prepared at the connection part of the thermoelectric conversion structure 100;
[0053] S61, phononic crystal patterns were prepared using a dot matrix exposure method;
[0054] S62, the phonon crystal pattern is transferred to the connection portion of the thermoelectric conversion structure 100 using ICP dry etching, such as... Figure 6A and Figure 6B As shown.
[0055] S7, grow mask layers on the upper and lower surfaces of the structure obtained in step S6;
[0056] If the SOI substrate thickness is greater than a preset value, the lower surface is further ground and polished before step S7 to thin the SOI substrate. Then, mask material 106 is grown on its upper surface and mask material 107 is grown on its lower surface, as shown below. Figure 7 As shown. Mask material 106 and mask material 107 can be dielectric layers or metal layers, and the principle for selecting the thickness is to provide good protection during subsequent etching.
[0057] S8, Etch the buried oxide layer 101 from the lower surface to the SOI substrate;
[0058] Photolithography is performed on the lower surface to etch the mask material 107, and then the substrate SOI is deeply etched down to the buried oxide layer 101 to form a suspended thin film, such as... Figure 8 As shown. The deep etching method can be either ICP dry etching or wet etching, or a combination of both.
[0059] S9, Remove the buried oxygen layer 101;
[0060] With its bottom facing upwards, the buried oxide layer 101 can be removed using gaseous HF, such as... Figure 9A and 9B As shown, where Figure 9A For the corresponding main view, Figure 9B for Figure 9A The corresponding bottom view.
[0061] S10, Remove the upper surface mask layer.
[0062] The mask material 106 on the upper surface is etched away, such as... Figure 10A and Figure 10B As shown, Figure 10B for Figure 10A The corresponding top view shows a completely suspended thermoelectric device.
[0063] In another embodiment
[0064] S210 uses SOI with a top silicon layer thickness of 150nm and a buried oxide layer thickness of 1μm as the substrate. Photoresist is used directly as a mask, and dry etching is performed on the top silicon layer to form the thermoelectric conversion structure 100. Figure 11 As shown.
[0065] The S220 uses LPCVD to deposit 380nm thick silicon nitride, followed by photolithography and ICP etching to form support arms and support islands, such as... Figure 12 As shown.
[0066] S230, using electron beam evaporation to deposit Cr / Pt (10nm / 50nm), and then stripping to obtain heated and thermometric metal patterns, such as Figure 13 As shown.
[0067] S240 utilizes magnetron sputtering to deposit Cr / Au (50nm / 250nm), and strips off the metal interconnects and bonding pads, then employs rapid annealing to obtain ohmic contacts.
[0068] S250 uses electron beam exposure to define the phononic crystal pattern, and then employs ICP dry etching to transfer the pattern onto the top silicon layer, such as... Figure 14 As shown.
[0069] For the S260, a 4μm thick silicon dioxide layer is deposited on the lower surface using PECVD. The lower surface is then photolithographically etched, using photoresist as a mask, and the silicon dioxide is dry-etched to open a window for deep silicon etching. Bosch etching is then employed to deeply etch the silicon down to the buried oxide layer.
[0070] In summary, the fabrication method employed in this application, utilizing photolithography, etching, and thin-film processes, is effectively compatible with CMOS technology and allows for mass production. Furthermore, integrating thermoelectric devices onto the chip reduces its temperature and allows for the conversion of heat dissipated by the chip into electrical energy, thus achieving waste heat utilization.
[0071] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for fabricating a MEMS thermoelectric device based on a phonon crystal, comprising: S1, a thermoelectric conversion structure (100) is etched on the top silicon layer of the SOI substrate. The thermoelectric conversion structure (100) includes a connecting portion and two ends connected to both ends of the connecting portion. S2, a silicon nitride film (102) is grown on the upper surface of the structure obtained in step S1. S3, etch the silicon nitride film (102) to form a support arm and a support island, wherein the support island is disposed at both ends and the support arm is connected to the support island; S4, deposit a first metal (103) on the support island and etch the first metal (103) to form a metal pattern; S5, deposit a second metal (104) on the support arm, and make the second metal (104) form an ohmic contact with the top silicon by an annealing process; S6, a phononic crystal is prepared at the connection of the thermoelectric conversion structure (100); S7, a mask layer is grown on the upper surface of the structure obtained in step S6 and the lower surface of the SOI substrate; S8, Etch the buried oxide layer (101) from the lower surface to the SOI substrate. S9, Remove the buried oxide layer (101) in the etched area of the SOI substrate in step S8. S10, Remove the mask layer on the upper surface of the structure obtained in step S6.
2. According to the preparation method of claim 1, step S1 further includes doping the thermoelectric conversion structure (100) with one of the following methods: ion implantation, diffusion or doping epitaxy, to form low resistance characteristics.
3. The preparation method according to claim 1, wherein step S6 comprises: S61, phononic crystal patterns were prepared using a dot matrix exposure method; S62, the phonon crystal pattern is transferred to the connection part of the thermoelectric conversion structure (100) by ICP dry etching.
4. According to the preparation method of claim 1, gaseous HF is used to remove the buried oxygen layer (101).
5. According to the preparation method of claim 1, the lower surface is etched by ICP dry etching or solution wet etching in step S8.
6. The preparation method according to claim 1, wherein the first metal (103) is a combination of Cr and Pt, and the first metal (103) is deposited on the support island by sputtering or evaporation.
7. According to the preparation method of claim 1, the second metal (104) is a combination alloy composed of one or more of Cr, Ni, Ti, Pt, Au, Al, Ag, Cu, W, Pd, and Mo, and the second metal (104) is deposited on the support arm by sputtering or evaporation.
8. According to the preparation method of claim 1, if the thickness of the SOI substrate is greater than a preset value, the lower surface is further ground and polished before step S7 to reduce the thickness of the SOI substrate.
9. The preparation method according to claim 1, wherein the silicon nitride film (102) is prepared by one of PECVD, LPCVD or ICP-CVD.
10. The preparation method according to claim 1, wherein the top silicon layer of the SOI substrate is either N-type silicon or P-type silicon, and its crystal orientation is [missing information]. <100> , <110> or <111> One of them.