Power provider

Abstract

A power provider is disclosed. The power provider includes a first power source configured to receive an input voltage and provide a first power voltage to a first output terminal, a low voltage detection circuit configured to provide a low voltage detection signal at an enable level in response to the input voltage being less than a reference low voltage and provide the low voltage detection signal at a disable level in response to the input voltage being greater than the reference low voltage, a first soft start circuit configured to connect the first input terminal to the first output terminal in response to a first control signal for the first power source changing from the disable level to the enable level, and a first boost converter configured to convert the input voltage to provide the first power voltage greater than the input voltage to the first output terminal.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0028594, filed on March 6, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. TECHNICAL FIELD

[0002] Aspects of some example embodiments of the present application relate to a power provider and a driving method thereof. BACKGROUND

[0003] With the development of information technology, display devices that provide a medium for connecting users and information are becoming more and more important. In response to this, the use of display devices such as liquid crystal display devices, organic light emitting display devices, plasma display devices, and the like has increased.

[0004] A display device generally displays an image through a combination of light emitted from a plurality of pixels. The display device can include a power provider for providing a power voltage to be supplied to the plurality of pixels.

[0005] The power provider can generate a power voltage when the display device is powered on or when an under-voltage lockout (UVLO) operation is released. For each of the above cases, the power provider needs to efficiently generate the power voltage.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it can contain information that does not constitute prior art. SUMMARY

[0007] Aspects of some example embodiments include a power provider that can be efficiently operated when a power source is turned on or a UVLO operation is released, and a driving method thereof.

[0008] A power provider according to some example embodiments of the present application can include a first power supply receiving an input voltage from a first input terminal and providing a first power voltage to a first output terminal, and a low voltage detection circuit providing a low voltage detection signal of an enable level when the input voltage is less than a reference low voltage, and providing a low voltage detection signal of a disable level when the input voltage is greater than the reference low voltage. The first power supply can include a first soft start circuit connecting the first input terminal to the first output terminal during a first period when a first control signal for the first power supply changes from the disable level to the enable level, and a first boost converter converting the input voltage to provide the first power voltage greater than the input voltage to the first output terminal after the first period. The first boost converter can stop the conversion of the input voltage when the low voltage detection signal changes from the disable level to the enable level, and the first soft start circuit can connect the first input terminal to the first output terminal during a second period when the low voltage detection signal changes from the enable level to the disable level.

[0009] According to some example embodiments, the first boost converter can convert the input voltage to provide the first power voltage greater than the input voltage to the first output terminal after the second period.

[0010] According to some example embodiments, the power provider can further include a second power supply converting an input voltage received by a second input terminal to provide a second power voltage less than the input voltage to a second output terminal during a third period between the first period and the second period, and a short circuit detection circuit stopping an operation of the second power supply when a voltage of the second output terminal is greater than a reference short circuit voltage during a fourth period between the first period and the third period.

[0011] According to some example embodiments, the second power supply can convert the input voltage to provide the second power voltage less than the input voltage to the second output terminal during at least a portion of the second period.

[0012] According to some example embodiments, the power provider can further include a register including information about a voltage level of the second power voltage, and the second power supply can determine the voltage level of the second power voltage with reference to the information provided from the register when the low voltage detection signal changes from the enable level to the disable level.

[0013] According to some example embodiments, the first soft start circuit can include a first switch having a first electrode connected to the first input terminal and a second electrode connected to the first output terminal.

[0014] According to some example embodiments, the first boost converter can include: a first inductor having one end connected to the first input terminal and another end connected to the first node; a second switch having a first electrode connected to the first node and a second electrode connected to the ground supply; and a third switch having a first electrode connected to the first node and a second electrode connected to the first output terminal.

[0015] According to some example embodiments, the second power supply can include: a fourth switch having a first electrode connected to the second input terminal and a second electrode connected to the second node; a second inductor having one end connected to the second node and another end connected to the ground supply; and a fifth switch having a first electrode connected to the second node and a second electrode connected to the second output terminal.

[0016] According to some example embodiments, the power provider can further include: a third power supply receiving an input voltage from a third input terminal and providing a third power voltage to a third output terminal, and the third power supply can include: a second soft start circuit connecting the third input terminal to the third output terminal during a fifth period when a second control signal for the third power supply changes from a disable level to an enable level; and a second boost converter converting the input voltage to provide the third power voltage greater than the input voltage to the third output terminal after the fifth period. The third power voltage can be greater than the first power voltage during a third period.

[0017] According to some example embodiments, the second boost converter can stop conversion of the input voltage when the low voltage detection signal changes from the disable level to the enable level, and the second soft start circuit can connect the third input terminal to the third output terminal during a sixth period when the low voltage detection signal changes from the enable level to the disable level.

[0018] According to some example embodiments, the second soft start circuit can include a sixth switch having a first electrode connected to the third input terminal and a second electrode connected to the third output terminal.

[0019] According to some example embodiments, the second boost converter can include: a third inductor having one end connected to the third input terminal and another end connected to a third node; a seventh switch having a first electrode connected to the third node and a second electrode connected to the ground supply; and an eighth switch having a first electrode connected to the third node and a second electrode connected to the third output terminal.

[0020] A power provider according to some example embodiments of the present invention can include a first power supply converting an input voltage received from a first input terminal to provide a first power voltage greater than the input voltage to a first output terminal, a second power supply converting an input voltage received from a second input terminal to provide a second power voltage less than the input voltage to a second output terminal, and a low voltage detection circuit providing a low voltage detection signal of an enable level when the input voltage is less than a reference low voltage and providing the low voltage detection signal of a disable level when the input voltage is greater than the reference low voltage. The first power supply and the second power supply can stop conversion of the input voltage when the low voltage detection signal changes from the disable level to the enable level, the first power supply can increase a level of the first power voltage during a first period when the low voltage detection signal changes from the enable level to the disable level, and the second power supply can decrease a level of the second power voltage during at least a portion of the first period.

[0021] According to some example embodiments, the power provider can further include a register including information on a voltage level of the second power voltage, and the second power supply can determine the voltage level of the second power voltage with reference to the information provided from the register when the low voltage detection signal changes from the enable level to the disable level.

[0022] According to some example embodiments, the power provider can further include a third power supply converting an input voltage received from a third input terminal to provide a third power voltage greater than the input voltage to a third output terminal. The third power supply can stop conversion of the input voltage when the low voltage detection signal changes from the disable level to the enable level, the third power supply can increase a level of the third power voltage during a second period when the low voltage detection signal changes from the enable level to the disable level, and the level of the third power voltage after the first period and the second period have elapsed can be greater than the level of the first power voltage.

[0023] In a driving method of a power provider according to some example embodiments of the present invention, the power provider can include a first power supply receiving an input voltage from a first input terminal and providing a first power voltage to a first output terminal, and a low voltage detection circuit providing a low voltage detection signal of an enable level when the input voltage is less than a reference low voltage and providing the low voltage detection signal of a disable level when the input voltage is greater than the reference low voltage, and the driving method can include connecting the first input terminal to the first output terminal during a first period when a first control signal for the first power supply changes from the disable level to the enable level, converting the input voltage to provide the first power voltage greater than the input voltage to the first output terminal after the first period, stopping conversion of the input voltage by the first power supply when the low voltage detection signal changes from the disable level to the enable level, and connecting the first input terminal to the first output terminal during a second period when the low voltage detection signal changes from the enable level to the disable level.

[0024] According to some example embodiments, the driving method can further include converting the input voltage by the first power converter to provide a first power voltage greater than the input voltage to the first output terminal after the second period.

[0025] According to some example embodiments, the power provider can further include a second power converter receiving the input voltage from the second input terminal and providing a second power voltage to the second output terminal, the driving method can further include converting the input voltage received from the second input terminal by the second power converter to provide a second power voltage less than the input voltage to the second output terminal during a third period between the first period and the second period, and stopping the operation of the second power converter when the voltage of the second output terminal is greater than the reference short-circuit voltage during a fourth period between the first period and the third period.

[0026] According to some example embodiments, the driving method can further include converting the input voltage by the second power converter to provide a second power voltage less than the input voltage to the second output terminal during at least a portion of the second period.

[0027] According to some example embodiments, the power provider can further include a register including information about a voltage level of the second power voltage, and the driving method can further include, when the low voltage detection signal changes from the enable level to the disable level, the second power converter determining the voltage level of the second power voltage with reference to the information provided from the register. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate aspects of some example embodiments of the present inventive concepts and together with the description serve to explain their principles.

[0029] Figure 1 is a block diagram for explaining a display apparatus according to some example embodiments of the present inventive concepts.

[0030] Figure 2 is a circuit diagram for explaining a pixel according to some example embodiments of the present inventive concepts.

[0031] Figure 3 is a graph for explaining a high-frequency driving method according to some example embodiments of the present inventive concepts.

[0032] Figure 4 is a timing diagram for explaining a data write period according to some example embodiments of the present inventive concepts.

[0033] Figure 5 is a timing diagram for explaining a data write period according to some example embodiments of the present inventive concepts.

[0034] Figure 6 is a diagram for explaining a low frequency driving method according to some example embodiments of the present application.

[0035] Figure 7 is a timing diagram for explaining a bias refresh period according to some example embodiments of the present application.

[0036] Figure 8 is another timing diagram for explaining a bias refresh period according to some example embodiments of the present application.

[0037] Figure 9 is a block diagram for explaining a power provider according to some example embodiments of the present application.

[0038] Figure 10 is a circuit diagram for explaining a first power source according to some example embodiments of the present application.

[0039] Figure 11 is a circuit diagram for explaining a second power source according to some example embodiments of the present application.

[0040] Figure 12 is a circuit diagram for explaining a third power source according to some example embodiments of the present application.

[0041] Figure 13 is a timing diagram for explaining a driving method of a power provider according to some example embodiments of the present application.

[0042] Figure 14 is a block diagram for explaining a power provider according to some example embodiments of the present application.

[0043] Figure 15 is a timing diagram for explaining a driving method of a power provider according to some example embodiments of the present application. Figure 14

[0044] Figure 16 is a block diagram for explaining a power provider according to some example embodiments of the present application.

[0045] Figure 17 is a timing diagram for explaining a driving method of a power provider according to some example embodiments of the present application. Figure 16 DETAILED DESCRIPTION

[0046] Hereinafter, aspects of some example embodiments of the present application will be described in detail with reference to the accompanying drawings, so that those skilled in the art can more easily implement the present application. The present application can be implemented in various different forms, and is not limited to the embodiments described herein.

[0047] ​​For clarity of illustration, elements of the drawings have not necessarily been drawn to scale with respect to each other, and the dimensions of the various elements are arbitrarily expanded or reduced for the sake of clarity. Thus, the foregoing description, which sets forth certain embodiments, is not intended as having limited the application to the particular form disclosed, but on the contrary, is intended to cover such alternatives, modifications, and equivalents as can be included within the spirit and scope of the application. Accordingly, the examples described herein are illustrative, and not restrictive, of the scope of the application.

[0048] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for the ease of description, and thus the present application is not necessarily limited to those shown in the drawings. In the drawings, the thickness can be exaggerated for clarity.

[0049] Hereinafter, the expression that an electrode or a line is connected to another electrode or line can indicate not only a case in which the electrode or line is "directly" connected to another electrode or line, but also a case in which the electrode or line is "indirectly" connected to another electrode or line through other components.

[0050] Figure 1 is a block diagram for explaining a display apparatus according to some example embodiments of the present application.

[0051] Referring to Figure 1 , the display apparatus 9 according to some example embodiments can include a timing controller 10, a data driver 20, a scan driver 30, an emission driver 40, a pixel unit 50, and a power provider 60.

[0052] The timing controller 10 can receive an external input signal from an external processor. The external input signal can include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), a data enable signal, an RGB data signal, etc.

[0053] The vertical synchronization signal can include a plurality of pulses. The end of a previous frame period and the beginning of a current frame period can be indicated based on a time point at which each pulse is generated. An interval between adjacent pulses in the vertical synchronization signal can correspond to one frame period. The horizontal synchronization signal can include a plurality of pulses. The end of a previous horizontal period and the beginning of a new horizontal period can be indicated based on a time point at which each pulse is generated. An interval between adjacent pulses in the horizontal synchronization signal can correspond to one horizontal period. The data enable signal can have an enable level in certain horizontal periods, and can have a disable level in the remaining horizontal periods. When the data enable signal is at the enable level, the RGB data signal can be supplied in the corresponding horizontal period. The RGB data signal can be supplied in each of the corresponding horizontal periods in units of pixels. The timing controller 10 can generate a grayscale value based on the RGB data signal to correspond to a specification of the display apparatus 9. The timing controller 10 can generate a control signal to be supplied to the data driver 20, the scan driver 30, and the emission driver 40 based on the external input signal to correspond to the specification of the display apparatus 9.

[0054] The power provider 60 can receive an input voltage Vin from a battery or the like, and convert the input voltage Vin to provide a first power voltage ELVDD, a second power voltage ELVSS, and a third power voltage AVDD. The power provider 60 can receive a first control signal ESW, and provide the first power voltage ELVDD and the second power voltage ELVSS based on the first control signal ESW. The power provider 60 can receive a second control signal ASW, and provide the third power voltage AVDD based on the second control signal ASW. The power provider 60 can receive the first control signal ESW and the second control signal ASW from at least one of the timing controller 10, the data driver 20, and an external processor. For example, the power provider 60 can be configured with a power management integrated chip (PMIC). For example, the power provider 60 can be configured as an external DC / DC IC.

[0055] The data driver 20 can generate data voltages to be provided to the data lines DL1, DL2, …, DLm using the grayscale values and the control signals received from the timing controller 10, where m is an integer greater than 0. For example, the data driver 20 can sample the grayscale values using a clock signal, and supply data voltages corresponding to the grayscale values to the data lines DL1, DL2, …, DLm in units of pixel rows (e.g., pixels connected to the same scan line).

[0056] The data driver 20 can receive the third power voltage AVDD from the power provider 60, and in some cases generate at least one of a fourth power voltage UELVDD and a fifth power voltage UELVSS using the third power voltage AVDD. For example, the data driver 20 can include a low-dropout circuit, and generate at least one of the fourth power voltage UELVDD and the fifth power voltage UELVSS by dropping the third power voltage AVDD.

[0057] For example, the data driver 20 can generate at least one of the fourth power voltage UELVDD and the fifth power voltage UELVSS in a second display mode (low-frequency driving, refer to Figure 6 ) to be described later. In this case, the power provider 60 can not provide the first power voltage ELVDD and the second power voltage ELVSS. In this case, the fourth power voltage UELVDD can be applied to the first power line ELVDDL, and the fifth power voltage UELVSS can be applied to the second power line ELVSSL (refer to Figure 2 ). Accordingly, power consumption can be reduced in the second display mode. For example, the data driver 20 can generate at least one of the fourth power voltage UELVDD and the fifth power voltage UELVSS in a first display mode (high-frequency driving, refer to Figure 3) the fourth power voltage UELVDD and the fifth power voltage UELVSS are not generated. In this case, the power provider 60 can provide the first power voltage ELVDD and the second power voltage ELVSS. In this case, the first power voltage ELVDD can be applied to the first power line ELVDDL, and the second power voltage ELVSS can be applied to the second power line ELVSSL (refer to FIG. 1). Figure 2 ) That is, power consumption can be optimized by complementarily providing power voltages through the data driver 20 and the power provider 60 according to the display mode.

[0058] The scan driver 30 can receive a clock signal, a scan start signal, and the like from the timing controller 10 to generate scan signals to be provided to the scan lines GIL1, GWNL1, GWPL1, GBL1, …, GILn, GWNLn, GWPLn, and GBLn, where n can be an integer greater than 0.

[0059] The scan driver 30 can include a plurality of sub-scan drivers. For example, a first sub-scan driver can provide scan signals for the scan lines GIL1 through GILn, a second sub-scan driver can provide scan signals for the scan lines GWNL1 through GWNLn, a third sub-scan driver can provide scan signals for the scan lines GWPL1 through GWPLn, and a fourth sub-scan driver can provide scan signals for the scan lines GBL1 through GBLn. Each of the sub-scan drivers can include a plurality of scan stages connected in the form of a shift register. For example, a scan signal can be generated by sequentially transferring an on level pulse of a scan start signal supplied to a scan start line to a next scan stage.

[0060] For another example, the first sub-scan driver and the second sub-scan driver can be integrated to provide scan signals for the scan lines GIL1 through GILn and GWNL1 through GWNLn, and the third sub-scan driver and the fourth sub-scan driver can be integrated to provide scan signals for the scan lines GWPL1 through GWPLn and GBL1 through GBLn. For example, a previous scan line (i.e., an n-1th scan line) of an nth scan line GWNLn can be connected to the same electrical node as the nth scan line GILn. Also, for example, a next scan line (i.e., an n+1th scan line) of the nth scan line GWPLn can be connected to the same electrical node as the nth scan line GBLn.

[0061] In this case, the first and second sub scan drivers can supply a scan signal of a pulse having a first polarity to the scan lines GIL1 through GILn and GWNL1 through GWNLn. Also, the third and fourth sub scan drivers can supply a scan signal of a pulse having a second polarity to the scan lines GWPL1 through GWPLn and GBL1 through GBLn. The first and second polarities can be opposite polarities.

[0062] Hereinafter, a polarity can refer to a logic level of a pulse. For example, when a pulse has a first polarity, the pulse can have a high level. At this time, the high level pulse can be referred to as an up pulse. When the up pulse is supplied to a gate electrode of an N-type transistor, the N-type transistor can be turned on. That is, the up pulse can be an on level of the N-type transistor. Here, it is assumed that a voltage of a level sufficiently lower than a voltage of the gate electrode is applied to a source electrode of the N-type transistor. For example, the N-type transistor can be an NMOS transistor.

[0063] Also, when a pulse has a second polarity, the pulse can have a low level. At this time, the low level pulse can be referred to as a down pulse. When the down pulse is supplied to a gate electrode of a P-type transistor, the P-type transistor can be turned on. That is, the down pulse can be an on level of the P-type transistor. Here, it is assumed that a voltage of a level sufficiently higher than a voltage of the gate electrode is applied to a source electrode of the P-type transistor. For example, the P-type transistor can be a PMOS transistor.

[0064] The emission driver 40 can receive a clock signal, an emission stop signal, and the like from the timing controller 10 to generate an emission signal to be provided to the emission lines EL1, EL2, …, ELn. For example, the emission driver 40 can sequentially provide an emission signal of a pulse having an off level to the emission lines EL1, EL2, …, ELn. For example, the emission driver 40 can be configured in the form of a shift register and generate the emission signal by sequentially transferring a pulse of the off level of the emission stop signal to a next emission stage under the control of the clock signal.

[0065] The pixel unit 50 can include pixels. For example, the pixel PXnm can be connected to the corresponding data line DLm, the scan lines GILn, GWNLn, GWPLn, and GBLn, and the emission line ELn.

[0066] Figure 2 is a circuit diagram for explaining a pixel according to some example embodiments of the present application.

[0067] Referring to Figure 2According to some example embodiments of the present invention, the pixel PXnm can include transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light emitting diode LD.

[0068] The transistor T1 can include a first electrode connected to a first electrode of the transistor T2, a second electrode connected to a first electrode of the transistor T3, and a gate electrode connected to a second electrode of the transistor T3. The transistor T1 can be referred to as a driving transistor.

[0069] The transistor T2 can include a first electrode connected to a first electrode of the transistor T1, a second electrode connected to a data line DLm, and a gate electrode connected to a scan line GWPLn. The transistor T2 can be referred to as a scan transistor.

[0070] The transistor T3 can include a first electrode connected to a second electrode of the transistor T1, a second electrode connected to a gate electrode of the transistor T1, and a gate electrode connected to a scan line GWNLn. The transistor T3 can be referred to as a diode-connected transistor.

[0071] The transistor T4 can include a first electrode connected to a second electrode of the storage capacitor Cst, a second electrode connected to an initialization line VINTL, and a gate electrode connected to a scan line GILn. The transistor T4 can be referred to as a gate initialization transistor.

[0072] The transistor T5 can include a first electrode connected to a first power line ELVDDL, a second electrode connected to a first electrode of the transistor T1, and a gate electrode connected to an emission line ELn. The transistor T5 can be referred to as a first emission transistor.

[0073] The transistor T6 can include a first electrode connected to a second electrode of the transistor T1, a second electrode connected to an anode of the light emitting diode LD, and a gate electrode connected to the emission line ELn. The transistor T6 can be referred to as a second emission transistor.

[0074] The transistor T7 can include a first electrode connected to an anode of the light emitting diode LD, a second electrode connected to the initialization line VINTL, and a gate electrode connected to a scan line GBLn. The transistor T7 can be referred to as an anode initialization transistor.

[0075] The storage capacitor Cst can include a first electrode connected to the first power line ELVDDL and a second electrode connected to a gate electrode of the transistor T1.

[0076] The light emitting diode LD can include an anode connected to the second electrode of the transistor T6 and a cathode connected to the second power line ELVSSL. A voltage applied to the second power line ELVSSL can be set to be lower than a voltage applied to the first power line ELVDDL. The light emitting diode LD can be an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, or the like.

[0077] The transistors T1, T2, T5, T6, and T7 can be P-type transistors. Channels of the transistors T1, T2, T5, T6, and T7 can be made of polysilicon. The polysilicon transistor can be a low temperature polysilicon (LTPS) transistor. The polysilicon transistor has a high electron mobility, and thus has a fast driving characteristic.

[0078] The transistors T3 and T4 can be N-type transistors. Channels of the transistors T3 and T4 can be composed of an oxide semiconductor. The oxide semiconductor transistor can be manufactured in a low temperature process, and has a low charge mobility compared to the polysilicon transistor. Thus, an amount of a leakage current generated in an off state of the oxide semiconductor transistor can be smaller than an amount of a leakage current generated in an off state of the polysilicon transistor.

[0079] According to some example embodiments, the transistor T7 can be composed of an N-type oxide semiconductor transistor instead of a polysilicon transistor. At this time, one of the scan lines GWNLn and GILn can be connected to a gate electrode of the transistor T7 instead of the scan line GBLn.

[0080] Figure 3 is a diagram for explaining a high frequency driving method according to some example embodiments of the present application.

[0081] When the pixel unit 50 displays a frame at the first driving frequency, the display device 9 can be denoted as being in a first display mode. Also, when the pixel unit 50 displays a frame at a second driving frequency lower than the first driving frequency, the display device 9 can be denoted as being in a second display mode.

[0082] In the first display mode, the display device 9 can display an image frame at a frequency of 20 Hz or more (e.g., 60 Hz).

[0083] The second display mode can be a low power display mode. The display device 9 can display an image frame at a frequency of less than 20 Hz (e.g., 1 Hz). For example, a case in which only time and date are displayed in a "always on mode" among a commercial mode can correspond to the second display mode.

[0084] The period 1 TP can include a plurality of frame periods 1 FP. The period 1 TP can be an arbitrary period defined for comparison of the first display mode and the second display mode. The period 1 TP can refer to the same time interval in the first display mode and the second display mode. For convenience of description, it is assumed that the frame period 1 FP has the same time interval in the first display mode and the second display mode. Accordingly, the period 1 TP can include the same number of frame periods 1 FP in the first display mode and the second display mode.

[0085] In the first display mode, each of the frame periods 1 FP can include a data write period WP and a light emission period EP. In the second display mode, each of the frame periods 1 FP can include the data write period WP and the light emission period EP. Figure 3 In the first display mode, for convenience of description, the data write period WP is positioned at the beginning of the frame period 1 FP and the light emission period EP is positioned after the data write period WP based on the first pixel row. However, in the case of other pixel rows, the data write period WP can be positioned in the middle or at the end of the frame period 1 FP.

[0086] Accordingly, the pixel PXnm can display a plurality of image frames corresponding to the number of the frame periods 1 FP during the period 1 TP based on the data voltage received in the data write period WP.

[0087] Figure 4 is a timing diagram for explaining a data write period according to some example embodiments of the present application. Figure 5 is another timing diagram for explaining a data write period according to some example embodiments of the present application.

[0088] First, an emission signal En of a cutoff level (high level) can be supplied to the emission line ELn during the data write period WP. Accordingly, the transistors T5 and T6 can be cut off during the data write period WP.

[0089] First, a first pulse of the scan signal GIn having an on level (high level) can be supplied to the scan line GILn. Accordingly, the transistor T4 can be turned on, and the gate electrode of the transistor T1 and the initialization line VINTL can be connected to each other. Accordingly, the voltage of the gate electrode of the transistor T1 can be initialized to the initialization voltage of the initialization line VINTL and can be held by the storage capacitor Cst. For example, the initialization voltage of the initialization line VINTL can be a voltage substantially lower than the voltage of the first power line ELVDDL. For example, the initialization voltage can be a voltage having the same or similar level as the voltage of the second power line ELVSSL. Accordingly, the transistor T1 can be turned on.

[0090] Next, a first pulse having an on level of the scan signals GWPn and GWNn can be supplied to the scan lines GWPLn and GWNLn, and the corresponding transistors T2 and T3 can be turned on. Accordingly, the data voltage Dm applied to the data line DLm can be written to the storage capacitor Cst through the transistors T2, T1, and T3. However, the data voltage Dm at this time can correspond to the gray value G(n-4) of the pixel four horizontal periods before. The data voltage Dm is not used for the emission of the pixel PXnm, but is used to apply an on bias voltage to the transistor T1. When the on bias voltage is applied to the transistor T1 before the desired data voltage Dm is written, the hysteresis phenomenon can be improved.

[0091] Next, a first pulse having an on level (low level) of the scan signal GBn can be supplied to the scan line GBLn, and the transistor T7 can be turned on. Accordingly, the voltage of the anode of the light emitting diode LD can be initialized.

[0092] At this time, a second pulse having an on level (high level) of the scan signal GIn can be supplied to the scan line GILn, and the above-described driving process can be performed again. That is, the on bias voltage can be applied to the transistor T1 again, and the voltage of the anode of the light emitting diode LD can be initialized.

[0093] By repeating the above-described process, when a third pulse having an on level of the scan signals GWPn and GWNn is supplied to the scan lines GWPLn and GWNLn, a data voltage Dm corresponding to the gray value Gn of the pixel PXnm can be stored in the storage capacitor Cst. At this time, the data voltage Dm written to the storage capacitor Cst can be a voltage reflecting the decrease in the threshold voltage of the transistor T1.

[0094] Finally, when the emission signal En becomes an on level (low level), the transistors T5 and T6 can be turned on. Accordingly, a driving current path connected through the first power line ELVDDL, the transistors T5, T1, and T6, the light emitting diode LD, and the second power line ELVSSL can be formed, and a driving current can flow. The amount of the driving current can correspond to the data voltage Dm stored in the storage capacitor Cst. At this time, because the driving current flows through the transistor T1, the decrease in the threshold voltage of the transistor T1 can be reflected. Accordingly, the decrease in the threshold voltage reflected in the data voltage Dm stored in the storage capacitor Cst and the decrease in the threshold voltage reflected in the driving current can cancel each other out. Thus, a driving current corresponding to the data voltage Dm can flow regardless of the threshold voltage value of the transistor T1.

[0095] The light emitting diode LD can emit light of a desired brightness according to the amount of the driving current.

[0096] According to some example embodiments, each of the scan signals is described to include three pulses, but each of the scan signals can include two pulses or four or more pulses according to some example embodiments. According to some example embodiments, each of the scan signals can be configured to include one pulse. In this case, the process of applying the on-bias voltage to the transistor Tl (refer to Figure 5 ) can be omitted.

[0097] Further, the interval between the adjacent pulses in the horizontal synchronization signal Hsync can correspond to one horizontal period. In Figure 4 , the pulses of the horizontal synchronization signal Hsync are shown at the low level. However, according to some example embodiments, the pulses of the horizontal synchronization signal Hsync can be at the high level.

[0098] Figure 6 is a timing chart for explaining the low-frequency driving method according to some example embodiments of the present application.

[0099] In the second display mode, the first frame period 1FP of the period 1TP can include the data write period WP and the light emission period EP, and the remaining frame periods 1FP of the period 1TP can include the bias refresh period BP and the light emission period EP.

[0100] The transistors T3 and T4 of the pixel PXnm can hold the off state during the remaining frame periods 1FP of the period 1TP. Thus, the storage capacitor Cst can hold the same data voltage during a plurality of image frames. For example, since the transistors T3 and T4 can be constituted of oxide semiconductor transistors, the leakage current can be minimized.

[0101] Thus, the pixel PXnm can display the same single image frame during the period 1TP based on the data voltage supplied in the data write period WP.

[0102] Figure 7 is a timing chart for explaining the bias refresh period according to some example embodiments of the present application. Figure 8 is another timing chart for explaining the bias refresh period according to some example embodiments of the present application.

[0103] Referring to Figure 7 , in the bias refresh period BP, the scan signals GIn and GWNn of the off level (low level) can be supplied. Thus, as described above, the data voltage written in the storage capacitor Cst in the bias refresh period BP can not be changed. At this time, the reference data voltage Vref can be applied to the data line DLm.

[0104] However, in the bias refresh period BP, the emission signal En having the same waveform as the waveform of the data write period WP and the scan signals GWPn and GBn can be supplied. Thus, in the plurality of frame periods 1FP of the period 1TP, since the waveform of the light emitted from the light emitting diode LD becomes similar, when driven at a low frequency, flicker is not recognized by the user.

[0105] Referring to Figures 1 to 7 The pixel PXnm described is one example of a pixel suitable for high frequency driving and low frequency driving. Aspects of some example embodiments to be described later can also be applied to a pixel having other circuits capable of high frequency driving and low frequency driving. For example, the transistors T1 to T7 of the pixel PXnm can all consist of only P-type transistors. In this case, since the scan driver 30 only needs to include a sub scan driver for P-type transistors, the configuration of the scan driver 30 can be simplified. For example, the transistors of the pixel PXnm can not include the emission transistors T5 and T6. In this case, the emission driver 40 can be unnecessary.

[0106] According to some example embodiments, the case where each of the scan signals GWPn and GBn includes three pulses has been described. However, according to some example embodiments, each of the scan signals GWPn and GBn can include two pulses or four or more pulses. According to some example embodiments, each of the scan signals GWPn and GBn can be configured to include one pulse. In this case, the process of applying an on bias voltage to the transistor T1 (refer to Figure 8 ) can be omitted.

[0107] The period 1TP in which the pixel unit 50 is driven in the first display mode can be referred to as a first period (refer to Figure 3 ). The period 1TP in which the pixel unit 50 is driven in the second display mode can be referred to as a second period (refer to Figure 6 ). In this case, the time interval of the first period can be the same as the time interval of the second period. That is, the first period and the second period can include the same number of frame periods 1FP.

[0108] The plurality of scan stages can supply the scan signal at the on level at the first cycle during the first period. For example, referring to Figure 3 and Figure 5 , the scan signal at the on level can be supplied in proportion to the number of data write periods WP in the first period. The plurality of scan stages can supply the scan signal at the on level at the second cycle during the second period. For example, referring to Figure 6 and Figure 8, the scan signal of the on level can be supplied in proportion to the number of data write periods WP in the second period. The number of data write periods WP included in the second period can be less than the number of data write periods WP included in the first period. Accordingly, the first period can be shorter than the second period.

[0109] Figure 9 is a block diagram for explaining a power provider according to some example embodiments of the present invention.

[0110] Referring to Figure 9 , the power provider 60 according to some example embodiments of the present invention can include a first power supply 61, a second power supply 62, a third power supply 63, a low voltage detection circuit 64, and a short circuit detection circuit 65.

[0111] The low voltage detection circuit 64 can provide a low voltage detection signal UVLO of an enable level when the input voltage Vin is less than a reference low voltage, and provide a low voltage detection signal UVLO of a disable level when the input voltage Vin is greater than the reference low voltage.

[0112] When the first power supply 61 receives the low voltage detection signal UVLO of the enable level, the first power supply 61 can stop an operation of converting the input voltage Vin into the first power voltage ELVDD. Similarly, when the second power supply 62 receives the low voltage detection signal UVLO of the enable level, the second power supply 62 can stop an operation of converting the input voltage Vin into the second power voltage ELVSS. Similarly, when the third power supply 63 receives the low voltage detection signal UVLO of the enable level, the third power supply 63 can stop an operation of converting the input voltage Vin into the third power voltage AVDD.

[0113] The first power supply 61 and the second power supply 62 can receive a first control signal ESW. The third power supply 63 can receive a second control signal ASW.

[0114] When the voltage of the second output terminal of the second power supply 62 is greater than a reference short circuit voltage, the short circuit detection circuit 65 can stop an operation of the second power supply 62. For example, when the first power supply 61 terminates a soft start operation, a first soft start signal SST1 of an enable level can be provided. When the short circuit detection circuit 65 receives the first soft start signal SST1 of the enable level, the second power voltage ELVSS can be compared with the reference short circuit voltage. When the second power voltage ELVSS is greater than the reference short circuit voltage, the short circuit detection circuit 65 can provide a short circuit detection signal SSD of a disable level. The short circuit detection signal SSD of the disable level can indicate a fault situation in which the first power line ELVDDL and the second power line ELVSSL are short-circuited. The second power supply 62 receiving the short circuit detection signal SSD of the disable level can not convert the input voltage Vin into the second power voltage ELVSS.

[0115] When the second power voltage ELVSS is less than the reference short-circuit voltage, the short-circuit detection circuit 65 can provide the short-circuit detection signal SSD at the enable level. The short-circuit detection signal SSD at the enable level can refer to a normal case in which the first power line ELVDDL and the second power line ELVSSL are not short-circuited. The second power supply 62 receiving the short-circuit detection signal SSD at the enable level can convert the input voltage Vin into the second power voltage ELVSS.

[0116] Figure 10 is a circuit diagram for explaining a first power supply according to some example embodiments of the present application.

[0117] Referring to Figure 10 , the first power supply 61 according to some example embodiments of the present application can include a first soft-start circuit STC1 and a first boost converter BST1.

[0118] The first power supply 61 can receive the input voltage Vin from the first input terminal IT1 and provide the first power voltage ELVDD to the first output terminal OT1.

[0119] The first soft-start circuit STC1 can include a soft-start controller 613 and a first switch SW1. The first switch SW1 can include a first electrode connected to the first input terminal IT1 and a second electrode connected to the first output terminal OT1.

[0120] The soft-start controller 613 can provide a control signal SSC1 for the first switch SW1 based on the first control signal ESW and the low voltage detection signal UVLO. For example, the soft-start controller 613 can provide the control signal SSC1 at the on level during the soft-start operation, and the first switch SW1 can be turned on. The soft-start controller 613 can provide the control signal SSC1 at the off level when the soft-start operation is completed, and the first switch SW1 can be turned off.

[0121] In addition, the soft-start controller 613 can generate the first soft-start signal SST1 at the enable level when the soft-start operation is completed. When the soft-start operation is not completed, the soft-start controller 613 can generate the first soft-start signal SST1 at the disable level.

[0122] The first boost converter BST1 can include a first inductor L1, a second switch SW2, and a third switch SW3. In addition, the first boost converter BST1 can include a carrier signal generator 611, a first power controller 612, a first comparator CP1, a first error amplifier EA1, and first feedback resistors FB11 and FB12 for controlling the second switch SW2 and the third switch SW3.

[0123] The first inductor L1 can include one end connected to the first input terminal IT1 and the other end connected to the first node N1. The second switch SW2 can include a first electrode connected to the first node N1 and a second electrode connected to the ground power source. The third switch SW3 can include a first electrode connected to the first node N1 and a second electrode connected to the first output terminal OT1. According to some example embodiments, the third switch SW3 can be replaced with a diode having an anode connected to the first node N1 and a cathode connected to the first output terminal OT1.

[0124] The first feedback resistors FB11 and FB12 can be connected in series between the first output terminal OT1 and the ground power source. The inverting terminal of the first error amplifier EA1 can be connected between the first feedback resistors FB11 and FB12 to receive the first feedback voltage FBV1. The non-inverting terminal of the first error amplifier EA1 can receive the first reference voltage Vref1 from the first power controller 612.

[0125] The first power controller 612 can determine the first reference voltage Vref1 based on the first control signal ESW, the low voltage detection signal UVLO, and the first soft start signal SST1. When the first reference voltage Vref1 is greater than the first feedback voltage FBV1, the first error amplifier EA1 can increase the magnitude of the first error signal EAS1 in a positive direction. When the first reference voltage Vref1 is less than the first feedback voltage FBV1, the first error amplifier EA1 can increase the magnitude of the first error signal EAS1 in a negative direction. According to some example embodiments, when the first reference voltage Vref1 is less than the first feedback voltage FBV1, the first error amplifier EA1 can provide the first error signal EAS1 having a minimum magnitude.

[0126] The carrier signal generator 611 can provide a first carrier signal CS1. The first carrier signal CS1 can be a signal in which a triangular wave is periodically repeated. The carrier signal generator 611 can employ a conventional configuration for PWM (Pulse Width Modulation) driving.

[0127] The inverting terminal of the first comparator CP1 can receive the first carrier signal CS1, and the non-inverting terminal of the first comparator CP1 can receive the first error signal EAS1. The first comparator CP1 can output a pulse when the first error signal EAS1 is greater than the first carrier signal CS1, and can not output a pulse when the first error signal EAS1 is less than the first carrier signal CS1. The output signal of the first comparator CP1 can be referred to as a first PWM signal PWM1, and the pulse width with respect to the period of the pulse can be referred to as a duty ratio. That is, the duty ratio can increase as the pulse width increases.

[0128] In response to a pulse of the first PWM signal PWM1, the second switch SW2 can be turned on, and the third switch SW3 can be turned off. That is, the longer the pulse width (on-duty period), the longer the period in which the second switch SW2 is turned on. In this case, the current flows from the input voltage Vin to the ground power through the first inductor L1, and energy can be stored in the first inductor L1.

[0129] On the other hand, during an off-duty period in which no pulse is generated, the second switch SW2 can be turned off, and the third switch SW3 can be turned on. In this case, the input voltage Vin and the current flowing from the first inductor L1 can be added, so that a first power voltage ELVDD greater than the input voltage Vin can be applied to the first output terminal OT1. As the duty ratio increases, the first power voltage ELVDD can be boosted more.

[0130] According to some example embodiments, the first soft start circuit STC1 can further include an additional switch, a first electrode of the additional switch being connected to a second electrode of the third switch SW3, and a second electrode of the additional switch being connected to the first output terminal OT1. The first soft start circuit STC1 can operate the additional switch complementarily to the first switch SW1. For example, during the soft start operation, the first switch SW1 can be in an on state, and the additional switch can be in an off state. In addition, when the soft start operation is completed, the first switch SW1 can be in an off state, and the additional switch can be in an on state. When the additional switch is provided, the first boost converter BST1 can be separated from the first output terminal OT1 during the soft start operation.

[0131] Figure 11 is a circuit diagram for explaining a second power supply according to some example embodiments of the present application.

[0132] The second power supply 62 can receive an input voltage Vin from a second input terminal IT2, and provide a second power voltage ELVSS to a second output terminal OT2. For example, the second power supply 62 can be a buck-boost converter.

[0133] The second power supply 62 can include a second inductor L2, a fourth switch SW4, and a fifth switch SW5. In addition, the second power supply 62 can include a carrier signal generator 621, a second power controller 622, a second comparator CP2, a second error amplifier EA2, and second feedback resistors FB21 and FB22 for controlling the fourth switch SW4 and the fifth switch SW5.

[0134] The fourth switch SW4 can include a first electrode connected to the second input terminal IT2 and a second electrode connected to the second node N2. The second inductor L2 can include one end connected to the second node N2 and the other end connected to the ground supply. The fifth switch SW5 can include a first electrode connected to the second node N2 and a second electrode connected to the second output terminal OT2. According to some example embodiments, the fifth switch SW5 can be replaced with a diode having an anode connected to the second output terminal OT2 and a cathode connected to the second node N2.

[0135] The second feedback resistors FB21 and FB22 can be connected in series between the second output terminal OT2 and the ground supply. The non-inverting terminal of the second error amplifier EA2 can be connected between the second feedback resistors FB21 and FB22 to receive the second feedback voltage FBV2. The inverting terminal of the second error amplifier EA2 can receive the second reference voltage Vref2 from the second power controller 622.

[0136] The second power controller 622 can determine the second reference voltage Vref2 based on the first control signal ESW, the low voltage detection signal UVLO, and the short circuit detection signal SSD. When the second reference voltage Vref2 is less than the second feedback voltage FBV2, the second error amplifier EA2 can increase the magnitude of the second error signal EAS2 in a positive direction. When the second reference voltage Vref2 is greater than the second feedback voltage FBV2, the second error amplifier EA2 can increase the magnitude of the second error signal EAS2 in a negative direction. According to some example embodiments, when the second reference voltage Vref2 is greater than the second feedback voltage FBV2, the second error amplifier EA2 can provide the second error signal EAS2 with a minimum magnitude.

[0137] The carrier signal generator 621 can provide a second carrier signal CS2. The second carrier signal CS2 can be a signal in which a triangular wave periodically repeats. The carrier signal generator 621 can employ a conventional configuration for PWM driving.

[0138] The inverting terminal of the second comparator CP2 can receive the second carrier signal CS2, and the non-inverting terminal of the second comparator CP2 can receive the second error signal EAS2. The second comparator CP2 can output a pulse when the second error signal EAS2 is greater than the second carrier signal CS2, and can not output a pulse when the second error signal EAS2 is less than the second carrier signal CS2. The output signal of the second comparator CP2 can be referred to as a second PWM signal PWM2, and the pulse width with respect to the period of the pulse can be referred to as a duty ratio. That is, the duty ratio can increase as the pulse width increases.

[0139] In response to a pulse of the second PWM signal PWM2, the fourth switch SW4 can be turned on, and the fifth switch SW5 can be turned off. That is, the longer the pulse width (on duty period), the longer the period in which the fourth switch SW4 is turned on. In this case, current flows from the input voltage Vin to the ground supply through the second inductor L2, and energy can be stored in the second inductor L2.

[0140] On the other hand, during an off duty period in which no pulse is generated, the fourth switch SW4 can be turned off, and the fifth switch SW5 can be turned on. In this case, because the second inductor L2 maintains current flowing to the ground supply, the second power voltage ELVSS of the second output terminal OT2 becomes less than the input voltage Vin. As the duty ratio increases, the second power voltage ELVSS can further decrease.

[0141] Figure 12 is a circuit diagram for explaining a third power supply according to some example embodiments of the present application.

[0142] Referring to Figure 12 The third power supply 63 according to some example embodiments of the present application can include a second soft start circuit STC2 and a second boost converter BST2.

[0143] The third power supply 63 can receive an input voltage Vin from a third input terminal IT3, and provide a third power voltage AVDD to a third output terminal OT3.

[0144] The second soft start circuit STC2 can include a soft start controller 633 and a sixth switch SW6. The sixth switch SW6 can include a first electrode connected to the third input terminal IT3 and a second electrode connected to the third output terminal OT3.

[0145] The soft start controller 633 can provide a control signal SSC3 for the sixth switch SW6 based on a second control signal ASW and a low voltage detection signal UVLO. For example, the soft start controller 633 can provide the control signal SSC3 at an on level during a soft start operation, and the sixth switch SW6 can be turned on. The soft start controller 633 can provide the control signal SSC3 at an off level when the soft start operation is completed, and the sixth switch SW6 can be turned off.

[0146] In addition, when the soft start operation is completed, the soft start controller 633 can generate the second soft start signal SST2 at an enable level. When the soft start operation is not completed, the soft start controller 633 can generate the second soft start signal SST2 at a disable level.

[0147] The second boost converter BST2 can include a third inductor L3, a seventh switch SW7, and an eighth switch SW8. In addition, the second boost converter BST2 can include a carrier signal generator 631, a third power controller 632, a third comparator CP3, a third error amplifier EA3, and third feedback resistors FB31 and FB32 for controlling the seventh switch SW7 and the eighth switch SW8.

[0148] The third inductor L3 can include one end connected to the third input terminal IT3 and the other end connected to the third node N3. The seventh switch SW7 can include a first electrode connected to the third node N3 and a second electrode connected to the ground power supply. The eighth switch SW8 can include a first electrode connected to the third node N3 and a second electrode connected to the third output terminal OT3. According to some example embodiments, the eighth switch SW8 can be replaced with a diode having an anode connected to the third node N3 and a cathode connected to the third output terminal OT3.

[0149] The third feedback resistors FB31 and FB32 can be connected in series between the third output terminal OT3 and the ground power supply. An inverting terminal of the third error amplifier EA3 can be connected between the third feedback resistors FB31 and FB32 to receive the third feedback voltage FBV3. A non-inverting terminal of the third error amplifier EA3 can receive the third reference voltage Vref3 from the third power controller 632.

[0150] The third power controller 632 can determine the third reference voltage Vref3 based on the second control signal ASW, the low voltage detection signal UVLO, and the second soft start signal SST2. When the third reference voltage Vref3 is greater than the third feedback voltage FBV3, the third error amplifier EA3 can increase the magnitude of the third error signal EAS3 in a positive direction. When the third reference voltage Vref3 is less than the third feedback voltage FBV3, the third error amplifier EA3 can increase the magnitude of the third error signal EAS3 in a negative direction. According to some example embodiments, when the third reference voltage Vref3 is less than the third feedback voltage FBV3, the third error amplifier EA3 can provide the third error signal EAS3 having a minimum magnitude.

[0151] The carrier signal generator 631 can provide a third carrier signal CS3. The third carrier signal CS3 can be a signal in which a triangular wave is periodically repeated. The carrier signal generator 631 can employ a conventional configuration for PWM driving.

[0152] The inverting terminal of the third comparator CP3 can receive the third carrier signal CS3, and the non-inverting terminal of the third comparator CP3 can receive the third error signal EAS3. The third comparator CP3 can output a pulse when the third error signal EAS3 is greater than the third carrier signal CS3, and can not output a pulse when the third error signal EAS3 is less than the third carrier signal CS3. The output signal of the third comparator CP3 can be referred to as a third PWM signal PWM3, and the pulse width with respect to the period of the pulse can be referred to as a duty cycle. That is, the duty cycle can increase as the pulse width increases.

[0153] In response to the pulse of the third PWM signal PWM3, the seventh switch SW7 can be turned on, and the eighth switch SW8 can be turned off. That is, the longer the pulse width (on-duty period), the longer the period in which the seventh switch SW7 is turned on. In this case, the current flows from the input voltage Vin to the ground power through the third inductor L3, and energy can be stored in the third inductor L3.

[0154] On the other hand, during an off-duty period in which no pulse is generated, the seventh switch SW7 can be turned off, and the eighth switch SW8 can be turned on. In this case, the input voltage Vin and the current flowing from the third inductor L3 can be added, so that a third power voltage AVDD greater than the input voltage Vin can be applied to the third output terminal OT3. As the duty cycle increases, the third power voltage AVDD can be boosted more.

[0155] According to some example embodiments, the second soft start circuit STC2 can further include an additional switch, a first electrode of the additional switch being connected to a second electrode of the eighth switch SW8, and a second electrode of the additional switch being connected to the third output terminal OT3. The second soft start circuit STC2 can operate the additional switch complementarily with the sixth switch SW6. For example, during the soft start operation, the sixth switch SW6 can be in an on state, and the additional switch can be in an off state. In addition, when the soft start operation is completed, the sixth switch SW6 can be in an off state, and the additional switch can be in an on state. When the additional switch is provided, the second boost converter BST2 can be separated from the third output terminal OT3 during the soft start operation.

[0156] Figure 13 is a timing diagram for explaining a driving method of a power provider according to some example embodiments of the present invention.

[0157] Before a time point t1, the display device 9 can be in a power-off state. At this time, the first control signal ESW and the second control signal ASW can be a disable level (logic low level).

[0158] At the time point t1, the display device 9 can be powered on. At this time, the second control signal ASW can change from the disable level to the enable level (logic high level). In this case, the second soft start circuit STC2 can connect the third input terminal IT3 to the third output terminal OT3 during the fifth period t1 to t2. That is, the sixth switch SW6 can be turned on during the fifth period t1 to t2. Accordingly, the third output terminal OT3 can be charged with the input voltage Vin. At the time point t2 at which the soft start operation is completed, the sixth switch SW6 can be turned off.

[0159] After the fifth period t1 to t2, the second boost converter BST2 can convert the input voltage Vin to provide the third power voltage AVDD greater than the input voltage Vin to the third output terminal OT3. At this time, the third power voltage AVDD can be boosted to a default level (e.g., a set or predetermined default level) AV1.

[0160] After the third power voltage AVDD is boosted to the default level AV1, the second control signal ASW can be a level control ASWC. The level control ASWC of the second control signal ASW can be a method of changing the level of the second control signal ASW a plurality of times at a plurality of intervals (e.g., a set or predetermined plurality of intervals) to transmit information about a voltage level to which the third power voltage AVDD will be reached to the third power controller 632.

[0161] Accordingly, at the time point t4, the third power voltage AVDD can be converted to a use level AV2 under the control of the third power controller 632.

[0162] At the time point t3, the first control signal ESW can change from the disable level to the enable level. In this case, the first soft start circuit STC1 can connect the first input terminal IT1 to the first output terminal OT1 during the first period t3 to t4. That is, the first switch SW1 can be turned on during the first period t3 to t4. Accordingly, the first output terminal OT1 can be charged with the input voltage Vin. At the time point t4 at which the soft start operation is completed, the first switch SW1 can be turned off.

[0163] After the first period t3 to t4, the first boost converter BST1 can convert the input voltage Vin to provide the first power voltage ELVDD greater than the input voltage Vin to the first output terminal OT1. During the first period t3 to t4, the first control signal ESW can be a level control ESWC. In this case, it is assumed that the level control ESWC of the first control signal ESW is used for the second power voltage ELVSS. Accordingly, the first power voltage ELVDD, which is irrelevant to the level control ESWC, can be boosted to a default level (e.g., a set or predetermined default level) ED1.

[0164] At the time point t4, the short-circuit detection circuit 65 can receive the first soft-start signal SST1 of the enable level from the soft-start controller 613. During the fourth period t4 to t5, the short-circuit detection circuit 65 can detect whether the second output terminal OT2 is short-circuited. During the fourth period t4 to t5, when the voltage of the second output terminal OT2 is greater than the reference short-circuit voltage, the short-circuit detection circuit 65 can stop the operation of the second power supply 62. Hereinafter, a normal case in which the second power line ELVSSL is not short-circuited is assumed. Therefore, at the time point t5, the second power controller 622 can receive the short-circuit detection signal SSD of the enable level output from the short-circuit detection circuit 65.

[0165] During the third period t5 to t6, the second power supply 62 can convert the input voltage Vin received by the second input terminal IT2 to provide the second power voltage ELVSS less than the input voltage Vin to the second output terminal OT2. The second power controller 622 can control the ESWC to lower the second power voltage ELVSS to the use level ES1 based on the level of the first control signal ESW previously received.

[0166] Therefore, the time point t6 can be a time point when the first power voltage ELVDD, the second power voltage ELVSS, and the third power voltage AVDD are completely converted to the target levels. The display device 9 can display an image using the pixels from the time point t6. The first power voltage ELVDD can be greater than the second power voltage ELVSS. Further, the third power voltage AVDD can be greater than the first power voltage ELVDD.

[0167] It is assumed that the low-voltage detection signal UVLO changes from the disable level (logic low level) to the enable level (logic high level) at the time point t7. That is, at the time point t7, a temporary failure case in which the input voltage Vin is less than the reference low voltage is assumed. Therefore, at the time point t8, the first boost converter BST1, the second power supply 62, and the second boost converter BST2 can stop the operation of converting the input voltage Vin. Therefore, at the time point t8, the first power voltage ELVDD, the second power voltage ELVSS, and the third power voltage AVDD can be the ground voltage level.

[0168] It is assumed that the low-voltage detection signal UVLO changes from the enable level to the disable level at the time point t9. That is, at the time point t9, a recovered normal case in which the input voltage Vin is greater than the reference low voltage is assumed.

[0169] In this case, the first soft start circuit STC1 can connect the first input terminal IT1 to the first output terminal OT1 during the second period t9 to tl 1. After the second period t9 to tl 1, the first boost converter BST1 can convert the input voltage Vin to provide the first power voltage ELVDD greater than the input voltage Vin to the first output terminal OT1.

[0170] Similarly, the second soft start circuit STC2 can connect the third input terminal IT3 to the third output terminal OT3 during the sixth period t9 to tl 0. After the sixth period t9 to tl 0, the second boost converter BST2 can convert the input voltage Vin to provide the third power voltage AVDD greater than the input voltage Vin to the third output terminal OT3. In this case, because the level control ASWC of the second control signal ASW has not been provided after the time point t8, the third power voltage AVDD can be boosted to the default level AV1.

[0171] During the period tl 1 to tl 2, the short circuit detection circuit 65 can detect whether the second output terminal OT2 is short-circuited. Because the operation of the short circuit detection circuit 65 during the period tl 1 to tl 2 is the same as that during the fourth period t4 to t5, the repeated description is omitted.

[0172] During the period tl 2 to tl 3, the second power supply 62 can convert the input voltage Vin received by the second input terminal IT2 to provide the second power voltage ELVSS less than the input voltage Vin to the second output terminal OT2. In this case, because the level control ESWC of the first control signal ESW has not been provided after the time point t8, the second power voltage ELVSS can be lowered to the default level ES2.

[0173] If the first boost converter BST1 directly boosts the first power voltage ELVDD from the ground voltage level to the default level ED1 without the help of the first soft start circuit STC1, a very large inrush current can be generated in the battery providing the input voltage Vin. The same problem can also occur in the third power supply 63. According to some example embodiments, even when the low voltage detection signal UVLO changes from the enable level to the disable level, because the soft start circuits STC1 and STC2 are operated, the inrush current in the battery providing the input voltage Vin can be reduced.

[0174] Figure 14 is a block diagram for explaining a power provider according to some example embodiments of the present application. Figure 15 is a timing chart for explaining a driving method of the power provider of Figure 14 .

[0175] Figure 14 60' power supply with Figure 9 The difference in the power supply 60 is that the short-circuit detection circuit 65' receives the low voltage detection signal UVLO.

[0176] According to some example embodiments, when the low voltage detection signal UVLO changes from an enabled level to a disabled level, the short circuit detection circuit 65' can output an enabled level short circuit detection signal SSD. That is, the short circuit detection circuit 65' can output an enabled level short circuit detection signal SSD at time point t9 without a separate short circuit detection process.

[0177] Therefore, the second power supply 62 can convert the input voltage Vin during at least a portion of the second time period t9 to t13' to provide a second power voltage ELVSS, which is less than the input voltage Vin, to the second output terminal OT2.

[0178] According to some example embodiments, when the low voltage detection signal UVLO changes from an enabled level to a disabled level, the unnecessary short-circuit detection process can be omitted. Since a short circuit is a physical state, a short-circuit check during the fourth time period t4 to t5 after the display device 9 is powered on can be sufficient. According to some example embodiments, the short-circuit detection process is omitted, allowing pixels to begin displaying an image as quickly as 10 ms.

[0179] Figure 16 This is a block diagram used to explain a power provider according to some example embodiments of the present invention. Figure 17 It is used for explanation Figure 16 Timing diagram of the driving method for the power supply.

[0180] Figure 16 The power supply unit 60” and Figure 14 The difference between the power supply 60' and the power supply 60' is that the power supply 60" also includes a register 66.

[0181] Register 66 may include information about the voltage level of the second power voltage ELVSS. For example, register 66 may control ESWC to store information about the voltage level of the second power voltage ELVSS based on the level of the first control signal ESW. Although the level of the low voltage detection signal UVLO changes during time period t8 to t9, register 66 may retain information about the voltage level of the second power voltage ELVSS.

[0182] When the low voltage detection signal UVLO changes from the enable level to the disable level, the second power supply 62 can determine the voltage level of the second power voltage ELVSS with reference to the information provided by the register 66. Thus, the second power voltage ELVSS can reach the use level ES1 at the time point t13" when the transition is completed.

[0183] According to some example embodiments, the register 66 can include information on the voltage level of the first power voltage ELVDD or the third power voltage AVDD. Similarly, when the low voltage detection signal UVLO changes from the enable level to the disable level, the third power supply 63 can determine the voltage level of the third power voltage AVDD with reference to the information provided by the register 66. Thus, the third power voltage AVDD can reach the use level AV2 at the time point when the transition is completed.

[0184] According to some example embodiments, when the low voltage detection signal UVLO changes from the enable level to the disable level, the second power voltage ELVSS can directly reach the use level ES1 without passing through the default level ES2. Thus, the display quality (brightness, etc.) of the pixels can be maintained before and after the level change of the low voltage detection signal UVLO.

[0185] In addition, according to some example embodiments, when the low voltage detection signal UVLO changes from the enable level to the disable level, the third power voltage AVDD can directly reach the use level AV2 without passing through the default level AV1. Thus, an increase in current consumption can be prevented or mitigated, and logic malfunction of the data driver 20 can be prevented or mitigated before and after the level change of the low voltage detection signal UVLO.

[0186] The power provider according to the present application and the driving method thereof can be effectively operated when the power is turned on or the UVLO operation is released.

[0187] The detailed description of the application heretofore referred to the drawings and above described is only for the purpose of illustrating the application. It will be understood that the application disclosed is for the purpose of illustration only and is not intended to limit the scope of the application. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments are possible without departing from the scope of the application. Accordingly, the true scope of the application should be determined by the technical idea of the appended claims and equivalents thereof.

Claims

1. A power provider comprising: a first power supply configured to receive an input voltage from a first input terminal and to provide a first power voltage to a first output terminal; and a low voltage detection circuit configured to provide a low voltage detection signal at an enable level in response to the input voltage being less than a reference low voltage and to provide the low voltage detection signal at a disable level in response to the input voltage being greater than the reference low voltage, wherein the first power supply includes a first soft start circuit configured to connect the first input terminal to the first output terminal during a first period in response to a first control signal for the first power supply changing from a disable level to an enable level such that the first output terminal outputs the input voltage and a first boost converter configured to convert the input voltage to provide the first power voltage greater than the input voltage to the first output terminal in a period subsequent to and adjacent to the first period, wherein the first boost converter is configured to stop conversion of the input voltage in response to the low voltage detection signal changing from the disable level to the enable level, and wherein the first soft start circuit is configured to connect the first input terminal to the first output terminal during a second period in response to the low voltage detection signal changing from the enable level to the disable level such that the first output terminal outputs the input voltage. the first boost converter is configured to convert the input voltage to provide the first power voltage greater than the input voltage to the first output terminal in a period subsequent to the second period.

2. The power provider of claim 1, wherein, 3. The power provider of claim 2, further comprising: a second power supply configured to convert the input voltage received by a second input terminal to provide a second power voltage less than the input voltage to a second output terminal during a third period between the first period and the second period; and a short circuit detection circuit configured to stop operation of the second power supply in response to a voltage of the second output terminal being greater than a reference short circuit voltage during a fourth period between the first period and the third period. the second power supply is configured to convert the input voltage to provide the second power voltage less than the input voltage to the second output terminal during at least a portion of the second period.

5. The power provider of claim 3, further comprising:

4. The power provider of claim 3, wherein, a register including information regarding a voltage level of the second power voltage, wherein the second power supply is configured to determine the voltage level of the second power voltage with reference to the information provided from the register in response to the low voltage detection signal changing from the enable level to the disable level. the first soft start circuit includes a first switch having a first electrode connected to the first input terminal and a second electrode connected to the first output terminal. the first boost converter includes:

6. The power provider of claim 3, wherein, ​ 7. The power provider of claim 6, wherein, ​ a first inductor having one end connected to the first input terminal and another end connected to a first node; a second switch having a first electrode connected to the first node and a second electrode connected to a ground supply; and a third switch having a first electrode connected to the first node and a second electrode connected to the first output terminal.

8. The power provider of claim 7, wherein, the second power supply includes: a fourth switch having a first electrode connected to the second input terminal and a second electrode connected to a second node; a second inductor having one end connected to the second node and another end connected to the ground supply; and a fifth switch having a first electrode connected to the second node and a second electrode connected to the second output terminal.

9. The power provider of claim 8, further comprising: a third power supply configured to receive the input voltage from a third input terminal and to provide a third power voltage to a third output terminal, wherein the third power supply includes a second soft-start circuit configured to connect the third input terminal to the third output terminal during a fifth time period in response to a second control signal for the third power supply changing from a disable level to an enable level, and a second boost converter configured to convert the input voltage to provide the third power voltage greater than the input voltage to the third output terminal after the fifth time period, and wherein the third power voltage is greater than the first power voltage during the third time period.

10. The power provider of claim 9, wherein, the second boost converter is configured to stop conversion of the input voltage in response to the low voltage detection signal changing from the disable level to the enable level, wherein the second soft-start circuit is configured to connect the third input terminal to the third output terminal during a sixth time period in response to the low voltage detection signal changing from the enable level to the disable level, wherein the second soft-start circuit includes a sixth switch having a first electrode connected to the third input terminal and a second electrode connected to the third output terminal, and wherein the second boost converter includes: a third inductor having one end connected to the third input terminal and another end connected to a third node; a seventh switch having a first electrode connected to the third node and a second electrode connected to the ground supply; and an eighth switch having a first electrode connected to the third node and a second electrode connected to the third output terminal.

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