Processes input / output storage instructions

Abstract

A data processing system (210) and method for processing input / output storage instructions (30) includes a system nest (18) coupled to at least one input / output bus (22) via an input / output bus controller (20). The data processing system (210) further includes at least a data processing unit (216) comprising a kernel (12), system firmware (10), and an asynchronous kernel-nest interface (14). The data processing unit (216) is coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load data from and / or store data to at least one external device (214) coupled to the input / output bus (22). The data processing unit (216) is configured to complete the input / output storage instruction (30) before execution of the input / output storage instruction (30) in the system nest (18) is completed. The asynchronous kernel-nest interface (14) includes an input / output status array (44) having a plurality of input / output status buffers (24).

Description

Technical Field

[0001] The present invention relates generally to data processing systems, and more particularly to methods, computer program products, and data processing systems for processing input / output storage instructions to multiple external devices. Background Art

[0002] A computing environment may include one or more types of input / output devices, including different types of adapters. One type of adapter is a Peripheral Component Interconnect (PCI) or Peripheral Component Interconnect Express (PCIe) adapter. The adapter includes one or more address spaces for transferring data between the adapter and the system attached to the adapter.

[0003] In some systems, a portion of the address space of a central processing unit (CPU) coupled to the adapter is mapped into the adapter's address space so that CPU instructions that access memory can directly manipulate data in the adapter's address space.

[0004] Communication with an adapter (eg, a PCI or PCIe adapter) may be facilitated by control instructions specifically designed to transfer data to and from the adapter and for communication.

[0005] In the prior art, a storage instruction for storing data in an adapter includes, for example, obtaining a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction including, for example, an opcode field identifying a store to adapter instruction. A first field identifies a first location including data to be stored in the adapter. A second field identifies a second location, the contents of which include a function handle identifying the adapter, the name of an address space within the adapter where the data will be stored, and an offset within the address space. The machine instruction is executed, and the execution includes using the function handle to obtain a function table entry associated with the adapter. At least one of the information in the function table entry and the offset is used to obtain the data address of the adapter. The data is stored from the first location in a specific location in the address space identified by the name of the address space, the specific location being identified by the data address of the adapter.

[0006] An existing feature in large multi-processor systems is the ability to quiesce all processors in a target region. The purpose of the quiesce function is to temporarily stop or change the state of a processor or group of processors to perform, for example, a system update or backup. In some instances, the quiesce interrupt only applies to a subset of the system resources. In such cases, the system can be divided into different zones. For a quiesce operation that applies to one zone (the target zone), processors outside the target zone are allowed to continue running, although new transitions may be blocked. Typically, at least one system controller or other mechanism broadcasts the quiesce to all physical processors in the system, a process collects the quiesce state information, and indicates to the requesting processor when all processors have started, or ignores (filters out) the quiesce request.

[0007] A quiesce controller may be communicatively coupled to a processor in a multi-processor system, and a quiesce state machine configured to receive a quiesce request. The computer system is configured to perform a method comprising: receiving, at the quiesce controller, a quiesce request from a requesting processor, the requesting processor being one of a plurality of processors in the multi-processor system; and determining, based on a state of the quiesce state machine, that the quiesce request was not accepted. The method further comprises, based on the quiesce request not being accepted, generating a rejection message configured to indicate that the quiesce request has been rejected; retaining the rejection message until a quiesce command is broadcast to the multi-processor system, the quiesce command being based on a different quiesce request; and, based on the quiesce controller detecting the broadcast of the quiesce command, sending the rejection message to the requesting processor. Summary of the Invention

[0008] A data processing system for processing input / output storage instructions is provided, comprising a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system further comprises at least a data processing unit, which includes a core, system firmware, and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregate buffer. The system nest is configured to asynchronously load data from and / or store data to at least one external device communicatively coupled to the input / output bus. The asynchronous core-nest interface comprises an input / output status array having a plurality of input / output status buffers, and array management and access logic.

[0009] The data processing system is configured to execute: (i) an operating system running on the data processing system issues an input / output storage instruction, which specifies at least an input / output function with an offset to an address, data to be transferred and / or a pointer to the data to be transferred, and a length of the data; (ii) a data processing unit is configured to identify the input / output function by the address specified in the input / output storage instruction; (iii) the data processing unit is configured to verify whether access to the input / output function is allowed at the address space and at the level of a client instance running on the data processing system; (iv) the data processing unit is configured to verify whether access to the input / output function is allowed at the address space and at the level of a client instance running on the data processing system; The data processing unit is configured to complete the input / output storage instruction before the execution of the input / output storage instruction in the system nest is completed; (v) the system firmware is configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output storage instruction; (vi) the array management and access logic collects the completion of the storage instruction and updates the input / output status buffer based on the received completion message; and (vii) the data processing unit delays the execution of the storage instruction until the input / output status buffer is available to store information about the completion of the pending storage instruction.

[0010] Advantageously, multiple outstanding asynchronous store instructions can be allowed to execute simultaneously to reduce the number of cycles per instruction for repeated asynchronous store instructions. An order is defined between asynchronous store instructions and synchronous load / store instructions. Support for multiple outstanding asynchronous store instructions is based on bookkeeping of dependencies between multiple status messages and responses using status entries.

[0011] A data processing system according to a first embodiment of the present invention includes instructions for loading from and storing to at least one external device of the data processing system via an input / output bus. Asynchronous instructions are completed before data is stored in the external device, while synchronous instructions are completed after data is stored in the external device. Within the embodiments described herein, PCI can be used interchangeably with any other input / output technology, and thus embodiments of the present invention are not limited to PCI.

[0012] Embodiments of the present invention describe the execution of input / output storage instructions in a strictly in-order manner observable from an architectural boundary, while the actual execution within the hardware of a data processing unit (CPU) may be out-of-order.

[0013] According to an embodiment of the present invention, PCI storage instructions can be executed through asynchronous execution and asynchronous state processing of PCIe storage effects.Asynchronous reliable execution is based on a reliable forwarding mechanism in the micro-architecture of the data processing system of the present invention.

[0014] Existing PCI store and store block commands are typically synchronous until the PCI store data has been transferred to the PCIe interface and completion is returned to the processing unit.

[0015] The PCI standard only requires asynchronous transmission of PCI information commands, which is usually achieved by aggregating the asynchronously transmitted data through the memory queue in the processor.

[0016] Advantageously, according to embodiments of the present invention, improvements in cycles per instruction may be achieved by replacing synchronous PCI instructions with reliable asynchronous send processing of input / output store instructions.

[0017] As an alternative or in addition to the data to be transferred, a storage instruction according to an embodiment of the present invention may also specify a pointer to the main memory, from which the data should be retrieved, rather than directly containing the data.

[0018] The client instance level may also mean that a single client or host may be running on the data processing system.

[0019] The offset address of the input / output function itself can be a virtual, physical, or logical address. Virtual and logical addresses are usually converted into physical addresses by a memory management unit (MMU), and then the physical address can be used to identify which function and offset it refers to.

[0020] Physical address in this context means "the lowest address in the address translation hierarchy accessible from within the guest / OS".

[0021] Advantageously, the I / O status buffers can collect return status from the system nest and / or from the I / O bus controller, particularly completion messages from the system nest. These I / O status buffers can collect return status, thereby acting as asynchronous system message buffers supporting asynchronous transfer processes. Advantageously, for faster response times, the I / O status buffers can be integrated directly into the asynchronous core-nest interface.

[0022] According to an advantageous embodiment of the data processing system of the present invention, the data processing unit can delay the execution of asynchronous and / or synchronous store instructions until an input / output status buffer is available to store information regarding the completion of the pending store instructions. Thus, the process of sequencing multiple store instructions to multiple input / output devices can be handled in an efficient manner, providing the ability to save processing time.

[0023] According to an advantageous embodiment of the data processing system according to the present invention, the input / output status buffer can collect message statuses, in particular completion statuses, from the system nest and / or from the input / output bus controller. In this way, information about the completion status of different storage instructions can be processed in an orderly and efficient manner.

[0024] According to an advantageous embodiment of the data processing system of the present invention, the message status and / or the completion status can be numbered by an input / output status buffer index. The numbering makes it possible to process the messages, in particular the completion status, in an orderly and efficient manner for further processing of other storage instructions.

[0025] According to an advantageous embodiment of the data processing system of the present invention, the aggregation buffer can be communicatively coupled to the asynchronous core-nested interface via an asynchronous bus. Thus, the aggregation buffer can continuously process data sent directly by the asynchronous core-nested interface until all data to be transmitted to the external device is stored in the aggregation buffer. In this manner, an asynchronous transmission mechanism for transmitting data from the asynchronous core-nested interface can be advantageously supported.

[0026] According to an advantageous embodiment of the data processing system of the present invention, if the length of the source data exceeds 8 bytes, the data can be transferred to the aggregation buffer by the input / output storage instruction via an asynchronous transfer mechanism with an early completion message in multiple packets. Otherwise, the data can be transferred in a single packet. This asynchronous transfer mechanism is advantageous because the sending device is free for reuse in an earlier state.

[0027] According to an advantageous embodiment of the data processing system of the present invention, the system firmware may include asynchronous I / O driver code for processing I / O storage instructions. Thus, an asynchronous transfer mechanism may be used to transfer data from the data processing unit to an external device.

[0028] According to an advantageous embodiment of the data processing system of the present invention, the kernel may include asynchronous setup code for handling memory requirements for state information of the asynchronous input / output driver code. The asynchronous setup code may further facilitate asynchronous transfer mechanisms through the aggregate buffer to the system nesting and input / output bus controllers.

[0029] According to an advantageous embodiment of the data processing system of the present invention, the asynchronous core-nested interface may include an asynchronous core-nested interface forwarding component for forwarding locally completed data. This component may be implemented in hardware within the asynchronous core-nested interface. Thus, an advantageous asynchronous transfer mode for sending data in packets to the aggregation buffer may be supported.

[0030] According to an advantageous embodiment of the data processing system of the present invention, the aggregation buffer may include early completion logic for transmitting a free for reuse message after sending a request. This enables early continuation of the processing of data transmitted via the aggregation buffer to the system nesting and input / output bus controller.

[0031] According to an advantageous embodiment of the data processing system of the present invention, the system firmware may include array management logic that allocates / frees input / output status buffers in the input / output status array and / or initiates the start of a new store instruction. Thus, free status buffers are available for further store instructions. This allows for orderly processing of store instructions in an efficient and time-saving manner.

[0032] According to an advantageous embodiment of the data processing system of the present invention, the system message may include one of the following: a hierarchical physical destination address; an SMT (Simultaneous Multi-Threading) thread or aggregate buffer identifier; a data length; an input / output bus address; or an input / output status buffer index. Thus, an advantageous transfer of relevant information through the data processing system is ensured.

[0033] Furthermore, a method for processing an input / output storage instruction for at least one external device of a data processing system is provided. The data processing system includes a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system also includes at least one data processing unit, the data processing unit including a core, system firmware, and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The external device is communicatively coupled to the input / output bus. The asynchronous core-nest interface includes an input / output status array having a plurality of input / output status buffers, and array management and access logic.

[0034] The method includes: (i) an operating system running on a data processing system issues an input / output storage instruction that specifies at least an input / output function with an offset to an address, data to be transferred and / or a pointer to the data to be transferred, and a length of the data; (ii) a data processing unit is configured to identify the input / output function by the address specified in the input / output storage instruction; (iii) the data processing unit is configured to verify whether access to the input / output function is allowed at the address space and client instance level, the client running on the data processing system; (iv) the data processing unit is configured to complete the input / output storage instruction before execution of the input / output storage instruction in the system nest is completed; (v) the system firmware is configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during asynchronous execution of the input / output storage instruction; (vi) the array management and access logic collects completions of the storage instructions and updates an input / output status buffer based on the received completion messages; and (vii) the data processing unit delays execution of the storage instruction until the input / output status buffer is available to store information about the completion of the pending storage instruction.

[0035] Advantageously, multiple outstanding asynchronous store instructions can be allowed to execute simultaneously to reduce the number of cycles per instruction for repeated asynchronous store instructions. Ordering is defined between asynchronous store instructions and synchronous load / store instructions. Support for multiple outstanding asynchronous store instructions is based on bookkeeping of multiple status messages and correlation of responses with status items.

[0036] A method according to another embodiment of the present invention includes loading and storing instructions from and to external devices of a data processing system via an input / output bus. Asynchronous instructions are executed before data is stored in the external device, while synchronous instructions are executed after data is stored in the external device. Within the embodiments described herein, PCI will be interchangeably used with any other input / output technology, and thus embodiments of the present invention are not limited to PCI.

[0037] Embodiments of the method of the present invention describe the execution of input / output storage instructions in a strictly in-order manner as observed from above the architectural boundary, while the actual execution may be out-of-order within the hardware of the data processing unit (CPU).

[0038] According to an embodiment of the method of the present invention, PCI storage instructions can be executed through asynchronous execution and asynchronous state processing of PCIe storage effects.Asynchronous reliable execution is based on a reliable forwarding mechanism in the micro-architecture of the data processing system of the present invention.

[0039] Existing PCI store and store block commands are typically synchronous until the PCI store data has been transferred to the PCIe interface and completion is returned to the processing unit.

[0040] The PCI standard only requires asynchronous transmission of PCI information, which is usually achieved by aggregating the asynchronously transmitted data through a storage queue in the processor.

[0041] Advantageously, according to embodiments of the method of the present invention, improvements in cycles per instruction may be achieved by replacing synchronous PCI instructions with reliable asynchronous send processing of input / output storage instructions.

[0042] As an alternative or in addition to the data to be transferred, a storage instruction according to an embodiment of the present invention may also specify a pointer to the main memory from which the data should be retrieved, rather than directly containing the data.

[0043] The client instance level may also mean that a single client or host may be running on the data processing system.

[0044] The offset address of the input / output function itself can be a virtual, physical, or logical address. Virtual and logical addresses are usually converted into physical addresses by a memory management unit (MMU), and then the physical address can be used to identify which function and offset it refers to.

[0045] Physical address in this context means "the lowest address in the address translation hierarchy accessible from within the guest / OS".

[0046] According to an advantageous embodiment of the method of the present invention, the data processing unit can delay the execution of asynchronous and / or synchronous store instructions until an input / output status buffer is available to store information about the completion of the pending store instructions. As a result, the process of sequencing multiple store instructions to multiple input / output devices can be handled in an efficient manner, providing the ability to save processing time.

[0047] According to an advantageous embodiment of the method according to the present invention, an I / O status buffer can collect message statuses, in particular completion statuses, from the system nest and / or from the I / O bus controller, wherein the message statuses and / or completion statuses are numbered by an I / O status buffer index. This allows information about the completion statuses of different memory instructions to be processed in an orderly and efficient manner. The numbering enables the orderly and efficient processing of messages, and in particular completion statuses, for further processing of other memory instructions.

[0048] According to an advantageous embodiment of the method of the present invention, system firmware may include array management logic that allocates / frees I / O status buffers in the I / O status array and / or initiates the start of a new store instruction. Thus, free status buffers are available for future store instructions. This allows for orderly processing of store instructions in an efficient and time-saving manner.

[0049] According to an advantageous embodiment, the method may further comprise: (i) the operating system issues an input / output storage instruction; (ii) the system firmware (10) allocates a free input / output status buffer index; if no free input / output status buffer index is available, waiting for a free input / output status buffer index; (iii) the system firmware injects the storage instruction into the asynchronous send engine; if blocked by another storage instruction, waiting until the storage instruction is completed; (iv) depending on the length of the data: if the length of the data exceeds 8 bytes, the system firmware software repeatedly issues a system message to send the data packet to the aggregate buffer until all data of the storage block has been forwarded to the aggregate buffer, and the system firmware software waits until the system message has sent the data; otherwise, the system firmware issues a system message to send the data to the aggregate buffer; further independent of the length of the data, (v) the system firmware issues a system message to the aggregate buffer to asynchronously forward the data as a single nested message to the input / output bus controller, while waiting for the aggregate buffer to send a completion message; vi) the aggregation buffer injects the nest message into the system nest, wherein the aggregation buffer is free for reuse immediately after the send operation, thereby signaling back to the system firmware; the aggregation buffer then sends a free for reuse message; (vii) the system nest forwards the message to the target location; (viii) the input / output bus controller receives the message and forwards the data in the data frame to the input / output bus; (ix) the input / output bus controller sends a completion message to the system nest; (x) the system nest forwards the completion message to the initiating aggregation buffer; (xi) the aggregation buffer forwards the completion to the asynchronous kernel-nest interface; (xii) the asynchronous kernel-nest interface stores the completion status in the input / output status buffer for input / output status buffer indexing and signals the completion of the operation to the system firmware; (xiii) the system firmware updates the input / output status buffer tracking via the input / output status buffer indexing; and (xiv) the system firmware asynchronously signals the defect to the operating system in the event of an error.

[0050] Only step (ii) is dependent on the length of the data and is different for data lengths exceeding 8 bytes than for data lengths not exceeding 8 bytes.

[0051] According to an embodiment of the method of the present invention, data is transferred to the aggregation buffer in slices until all data of a memory block is forwarded to the aggregation buffer, wherein the system firmware waits until the data has been sent by the asynchronous core-nesting interface.

[0052] Thus, if the data is smaller than eight bytes, the process of filling the aggregation buffer with the data packets in the form of fragments can be skipped, and the data transmission process to the external device can be completed in a single step.

[0053] According to an advantageous embodiment of the method of the present invention, if the length of the source data exceeds 8 bytes, the data can be transferred to the aggregation buffer in multiple packets by the input / output storage instruction via an asynchronous transfer mechanism with early completion messages. This asynchronous transfer mechanism is advantageous because the sending device is free for reuse in the early state.

[0054] According to an advantageous embodiment of the method of the present invention, the system firmware can use asynchronous input / output driver code to process input / output storage instructions. Thus, data can be transferred from the data processing unit to the external device using an asynchronous transfer mechanism.

[0055] According to an advantageous embodiment of the method of the present invention, the kernel can use asynchronous setup code to handle memory requirements for state information of the asynchronous input / output driver code. The asynchronous setup code can further facilitate asynchronous transfer mechanisms through the aggregate buffer to the system nesting and input / output bus controllers.

[0056] Advantageously, the asynchronous core-nested interface can forward locally completed data using an asynchronous core-nested interface forwarding component. Thus, an advantageous asynchronous transfer mode for sending data in packets to an aggregation buffer can be supported.

[0057] Advantageously, the aggregation buffer can use early completion logic for transmitting a free for reuse message after a send request. This enables early continuation of the process of transferring data via the aggregation buffer to the system nest and input / output bus controller.

[0058] Advantageously, the I / O status buffers can collect return status from the system nest and / or from the I / O bus controller, in particular completion messages from the system nest. These I / O status buffers can collect return status, thereby acting as asynchronous system message buffers supporting asynchronous transfer processes.

[0059] According to an advantageous embodiment of the method of the present invention, the system message may include one of the following: a hierarchical physical target address; a sourcing SMT thread or aggregate buffer identifier; a length of the data; an input / output bus address; or an input / output status buffer index. Thus, an advantageous transfer of relevant information through the data processing system is ensured.

[0060] Furthermore, an advantageous computer program product is provided for processing input / output storage instructions to at least one external device of a data processing system. The data processing system includes a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system further includes at least one data processing unit, the data processing unit including a core, system firmware, and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The external device is communicatively coupled to the input / output bus. The asynchronous core-nest interface includes an input / output status array having a plurality of input / output status buffers, and array management and access logic.

[0061] The computer program product comprises a computer-readable storage medium having program instructions embodied therewith, the program instructions being executable by the computer system to cause the computer system to perform a method, the method comprising: (i) an operating system running on the data processing system issuing the input / output storage instruction, which specifies at least an input / output function having an offset through an address, data to be transferred and / or a pointer to the data to be transferred, and a length of the data; (ii) the data processing unit being configured to identify the input / output function by the address specified in the input / output storage instruction; (iii) the data processing unit being configured to verify whether access to the input / output function is allowed at the address space and at the client instance level; said input / output function, said client executing on said data processing system; (iv) said data processing unit being configured to complete said input / output storage instruction before said system nested execution of said input / output storage instruction is completed; (v) said system firmware being configured to notify said operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by said data processing unit during asynchronous execution of said input / output storage instruction; (vi) said array management and access logic registering completion of said storage instruction and updating said input / output status buffer based on the received completion message; and (vii) said data processing unit delaying execution of said storage instruction until said input / output status buffer is available to store information regarding completion of pending storage instructions.

[0062] Furthermore, a data processing system for executing a data processing program is proposed, wherein the data processing system comprises computer-readable program instructions for executing the above method. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The invention, together with the foregoing and other objects and advantages, will be best understood from the following detailed description of the embodiments to which the invention is not limited.

[0064] Figure 1A block diagram illustrating a data processing system for processing an input / output storage instruction for an external device according to an embodiment of the present invention is shown.

[0065] Figure 2 A message sequence chart illustrating a method for processing an input / output storage instruction for an external device according to an embodiment of the present invention.

[0066] Figure 3 A first part of a flowchart for processing an input / output storage instruction for an external device according to an embodiment of the present invention is shown.

[0067] Figure 4 A second part of the flowchart for processing an input / output storage instruction for an external device according to an embodiment of the present invention is shown.

[0068] Figure 5 An exemplary embodiment of a data processing system for carrying out the method according to the invention is shown. DETAILED DESCRIPTION

[0069] In the accompanying drawings, the same elements are represented by the same reference numerals. The accompanying drawings are only schematic representations and are not intended to describe specific parameters of the present invention. In addition, the accompanying drawings are intended to describe only typical embodiments of the present invention and are therefore not to be considered as limiting the scope of the present invention.

[0070] The illustrative embodiments described herein provide a data processing system and method for handling input / output store instructions. The data processing system includes a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system also includes at least one data processing unit, the data processing unit including a core, system firmware, and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregate buffer. The system nest is configured to asynchronously load data from and / or store data to an external device communicatively coupled to the input / output bus. The asynchronous core-nest interface includes an input / output status array having a plurality of input / output status buffers, and array management and access logic.

[0071] Illustrative embodiments may be used in a method comprising: (i) an operating system running on a data processing system specifies an input / output function with at least an offset by an address, data to be transferred and / or a pointer to the data to be transferred, and a length of the data; (ii) a data processing unit is configured to identify the input / output function by an address specified in an input / output store instruction; (iii) the data processing unit is configured to verify whether access to the input / output function is permitted at an address space and at a client instance level, the client running on the data processing system; (iv) the data processing unit is configured to complete the input / output store instruction before completing execution of the input / output store instruction in the system nest; (v) system firmware is configured to notify the operating system by interrupting, sending data of the failed asynchronous execution, if an error is detected by the data processing unit during asynchronous execution of the input / output store instruction; (vi) array management and access logic collects completions of the store instructions and updates an input / output status buffer based on the received completion messages; and (vii) the data processing unit delays execution of the store instruction until the input / output status buffer is available to store information about the completion of the pending store instruction.

[0072] Alternatively or additionally, for the data to be transferred, the storage instruction according to an embodiment of the present invention may also specify a pointer pointing to , which should be used to extract the data from the main memory instead of directly containing the data.

[0073] The client instance level may also mean that a single client or host may be running on the data processing system.

[0074] The offset of the input / output function itself can be a virtual, physical, or logical address. Virtual and logical addresses are usually converted into physical addresses by the memory management unit (MMU), and then the physical address can be used to identify which function and offset it refers to.

[0075] A physical address in the context of this specification means "the lowest address in the address translation hierarchy accessible from within the guest / OS."

[0076] Figure 1 A block diagram of a data processing system 210 for processing input / output storage instructions 30 to at least one external device 214 according to an embodiment of the present invention is shown. The data processing system 210 includes a system nest 18 communicatively coupled to an input / output bus 22 via an input / output bus controller 20, a data processing unit 216 including a kernel 12, system firmware 10, and an asynchronous kernel-nest interface 14. The input / output bus controller 20 may also be coupled to multiple external devices 214 via multiple input / output buses 22.

[0077] The data processing unit 216 is communicatively coupled to the system nest 18 via the aggregate buffer 16. The system nest 18 is configured to asynchronously load data from and / or store data to external devices 214 communicatively coupled to the input / output bus 22 through a buffer input / output bus controller interface 28 and an input / output bus controller 20 that are part of the system nest 18.

[0078] Aggregation buffer 16 is communicatively coupled to asynchronous kernel-nest interface 14. System firmware 10 includes asynchronous I / O driver code 32 for processing I / O store instructions 30. Kernel 12 includes asynchronous setup code 34 for processing memory requests for status information from asynchronous I / O driver code 32. Asynchronous kernel-nest interface 14 includes asynchronous kernel-nest interface forwarding component 36 for forwarding locally completed data. Aggregation buffer 16 includes early completion logic 26 for transmitting a "free for reuse" message after a request is sent. Aggregation buffer 16 is coupled to asynchronous kernel-nest interface 14 via asynchronous bus 38. Asynchronous kernel-nest interface 14 includes an I / O status array 44 having a plurality of I / O status buffers 24, and array management and access logic 46. I / O status buffers 24 collect return status from system nest 18 and / or from I / O bus controller 20, particularly completion messages from system nest 18. I / O status buffers 24 are directly integrated into asynchronous kernel-nest interface 14. A message 48 (eg, a completion message sent to one of the input / output status buffers 24 ) may be received by the system nest 18 with the identification of the array item.

[0079] According to an embodiment of the method of the present invention, an operating system running on data processing system 210 issues an I / O store instruction 30 that specifies at least an I / O function by an offset to an address, data to be transferred and / or a pointer to the data to be transferred, and the length of the data. Data processing unit 216 is thus configured to identify the I / O function by the address specified in I / O store instruction 30. Data processing unit 216 is configured to verify that access to the I / O function is permitted at the address space and at the level of the client instance running on data processing system 210. Data processing unit 216 is configured to complete I / O store instruction 30 before execution of I / O store instruction 30 is completed in system nest 18. System firmware 10 is configured to notify the operating system by interrupting and sending data indicating the failed asynchronous execution if an error is detected by data processing unit 216 during asynchronous execution of I / O store instruction 30.

[0080] The array management and access logic 46 collects completions of the store instructions 30 and, based on the received completion messages, updates the input / output status buffer 24. The data processing unit 216 delays execution of the store instructions 30 until the input / output status buffer 24 is available to store information about the completions of the pending store instructions 30. Specifically, the data processing unit 216 delays execution of asynchronous and / or synchronous store instructions 30 until the input / output status buffer 24 is available to store information about the completions of the pending store instructions 30.

[0081] The I / O status buffer 24 collects message statuses, particularly completion statuses, from the system nest 18 and / or from the I / O bus controller 20. The message statuses and / or completion statuses are preferably numbered by an I / O status buffer index.

[0082] System firmware 10 includes array management logic 42 that allocates / frees input / output status buffers 24 in an input / output status array 44 and / or initiates the start of a new store instruction 30 .

[0083] Input / output storage instructions 30 are located in the data processing system 210 on the user interface 40 side of the architectural boundary that separates the system hardware / firmware 50 from the user side 40 .

[0084] Thus, if the source data is longer than 8 bytes, the data may be transferred by the I / O store instruction 30 to the aggregation buffer 16 in multiple packets via an asynchronous transfer mechanism with an early completion message, otherwise, the data may be transferred in one packet.

[0085] A system message according to an embodiment of a data processing system of the present invention includes one of: a hierarchical physical target address; a SMT thread or aggregate buffer identifier; a length of data; an input / output bus address; or an input / output status buffer index.

[0086] The queuing and ordering semantics for handling store instructions 30 to multiple external devices 214 can advantageously be implemented as described below. For a separate SMT thread and I / O function relationship, all traditional I / O load / store operations can be ordered relative to a single thread of the processor unit 216. New I / O store instructions are completely out of order with respect to each other. New I / O store instructions are ordered relative to traditional I / O instructions. All I / O instructions for different I / O functions are not ordered relative to each other.

[0087] Figure 2 A message sequence chart illustrating a method for processing an input / output storage instruction 30 for an external device 214 according to an embodiment of the present invention.

[0088] like Figure 2 As shown, the method begins with the operating system issuing an I / O store instruction 30. In step S101, the system firmware 10 allocates a free I / O status buffer index. If no free I / O status buffer index is available, the system firmware 10 waits. In step S103, the system firmware 10 checks whether the store instruction can be injected into the asynchronous send engine. If this is possible, the process continues. If this is not possible, the store instruction is delayed until the store instruction causing the delay completes.

[0089] Next, as shown in steps S100 and S104, if the data length exceeds 8 bytes, the system firmware 10 repeatedly issues a system message to send the data packet to the aggregation buffer 16 until all data in the store block has been forwarded to the aggregation buffer 16. Meanwhile, the system firmware 10 waits until the data has been sent via the system message. In steps S102 and S106, a local completion message is sent back to the system firmware 10.

[0090] Then in step S108 , the system firmware 10 issues a system message to the aggregation buffer 16 to asynchronously forward the data to the input / output bus controller 20 in the form of a single nested message, while waiting for the aggregation buffer 16 to send a completion message.

[0091] Next, in step S110, the aggregation buffer 16 injects the nest message into the system nest 18, wherein the aggregation buffer 16 becomes free for reuse immediately after the send operation, signaling back to the system firmware 10. The aggregation buffer 16 then sends a free for reuse message.

[0092] In step S112 , the system nest 18 forwards the message to the target location, followed by step S114 , the I / O bus controller 20 receives the message and forwards the data in the data frame to the I / O bus, and then in step S116 , the I / O bus controller 20 sends a completion message to the system nest 18 .

[0093] Next, at step S118, the system nest 18 forwards the completion message to the originating aggregation buffer 16. Subsequently, at step S120, the aggregation buffer 16 forwards the completion message to the asynchronous core-nest interface 14. Then, at step S122, the asynchronous core-nest interface 14 stores the state of the corresponding input / output status buffer index in the input / output buffer 24 and sends a signal to the system firmware 10 notifying the system firmware 10 of the completion of the operation. Finally, at step S123, the system firmware 10 updates the input / output status buffer 24 tracking with the input / output status buffer index. The input / output status buffer 24 is now free again.

[0094] In the event that an error occurs during data transfer, system firmware 10 asynchronously sends a signal informing the operating system of the defect.

[0095] In case the data to be transmitted is less than 8 bytes, the repeated filling of the aggregation buffer 16 is skipped.

[0096] Figure 3 The first part of the flowchart for processing the input / output storage instruction 30 for the external device 214 according to an embodiment of the present invention is shown. Figure 4 The second part of the flow chart is shown.

[0097] At step S200, the system firmware of the data processing unit begins. At step S202, the system firmware receives a legacy I / O storage block instruction via a message. At step S208, a check is performed to determine whether there are any outstanding new storage instructions 30, with or without an asynchronous response. If this is the case, the system waits until there are no more outstanding asynchronous responses from the kernel-nested interface 14. If this is not the case, the process immediately continues to step S212, where the kernel-nested interface 14 sends a legacy I / O storage instruction 30 in the form of a message. Then, at step S214, the system waits until it receives a legacy response message, at step S216. Then, at step S218, the legacy storage instruction 30 is completed with a message, and at step 220, the system firmware 10 ends the process.

[0098] In parallel, at step S204, the system firmware 10 receives a new I / O storage instruction 30 via a message. At step S222, it is checked whether a free status slot, i.e., the I / O status buffer 24, is available. If so, the slot is marked as used at step S224, and the storage process then continues to Figure 4 The connection point A shown in the second part of the flow chart shown in . If this is not the case, then in step S226 it is waited until the core-nest interface 14 has a free slot available.

[0099] In step S206, an asynchronous execution completion message may be received, and then in step S228, the slot tracking is updated with the corresponding input / output status buffer index. Then, in step S230, the system firmware 10 ends the process.

[0100] Figure 4 The second part of the flow chart starting at connection point A is shown in FIG. First, in step S304, a check is made to see if more than 8 bytes are to be transferred. If so, then in step S306, the item is sent. In step S308, the system firmware waits until a local completion message is sent in step S310, returning to step S304. If less than 8 bytes remain in the check in step S304, the flow continues in step S312, where the kernel-nested interface sends an asynchronous input / output message, followed by a wait in step S314 for a buffer response in step S316. Then, in step S318, a finish store block instruction is executed, and the flow ends with the system firmware ending in step S320.

[0101] In step S328, the asynchronous core-nested interface logic starts an outbound processing loop, then receives an aggregation buffer completion message in step S322, forwards the data message to the aggregation buffer in step S324, and then sends a completion message back to the system firmware in step S326. In step S330, an asynchronous input / output send message is received and then forwarded to the aggregation buffer.

[0102] At step S338, the aggregation buffer logic begins an outbound processing loop, subsequently receiving data at step S334 and aggregating the data in the aggregation buffer at step S336. The aggregation buffer also receives input / output send messages at step S340, and subsequently forwards the data in the aggregation buffer using the input / output send messages at step S242. Next, at step S344, a response message from the aggregation buffer is sent to the system firmware via the kernel-nested interface.

[0103] Now refer to Figure 5 , a schematic diagram of an example of a data processing system 210 is shown. Data processing system 210 is only one example of a suitable data processing system and is not intended to suggest any limitation as to the scope of use or functionality of the embodiments of the present invention described herein. Regardless, data processing system 210 is capable of implementing and / or performing any of the functions described above.

[0104] Among data processing system 210 is computer system / server 212, which is operable with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use with computer system / server 212 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the foregoing, among others.

[0105] Computer system / server 212 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Generally speaking, program modules can include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. Computer system / server 212 can be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located in both local and remote computer system storage media, including memory storage devices.

[0106] like Figure 5 As shown, computer system / server 212 in data processing system 210 is shown in the form of a general-purpose computing device. Components of computer system / server 212 may include, but are not limited to, one or more processors or processing units 216, system memory 228, and bus 218 that couples various system components, including system memory 228, to processor 216.

[0107] Bus 218 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0108] Computer system / server 212 typically includes a variety of computer system readable media. Such media can be any available media that can be accessed by computer system / server 212 and includes both volatile and nonvolatile media, removable and non-removable media.

[0109] System memory 228 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 230 and / or cache memory 232. Computer system / server 212 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 234 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, commonly referred to as a "hard drive"). Although not shown, a magnetic disk drive for reading and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk such as a CD-ROM, DVD-ROM, or other optical media may be provided. In such instances, each may be connected to bus 218 via one or more data media interfaces. As will be further depicted and described below, memory 228 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the present invention.

[0110] A program / utility 240 having a set (at least one) of program modules 242, as well as an operating system, one or more application programs, other program modules, and program data, may be stored in memory 228 by way of example and not limitation. Each of the operating system, one or more application programs, other program modules, and program data, or some combination thereof, may include an embodiment of a networked environment. The program modules 242 generally perform the functions and / or methods of the embodiments of the present invention described herein.

[0111] Computer system / server 212 can also communicate with one or more external devices 214, such as a keyboard, pointing device, and display 224; one or more devices that enable a user to interact with computer system / server 212; and / or any device that enables computer system / server 212 to communicate with one or more other computing devices (e.g., a network card, modem, etc.). Such communication can occur via input / output (I / O) interface 222. Furthermore, computer system / server 212 can communicate with one or more networks, such as a local area network (LAN), a general-purpose wide area network (WAN), and / or a public network (e.g., the Internet), via network adapter 220. As shown, network adapter 220 communicates with other components of computer system / server 212 via bus 218. It should be understood that, although not shown, other hardware and / or software components may be used in conjunction with computer system / server 212. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archiving storage systems.

[0112] The present invention may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform aspects of the present invention.

[0113] A computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device (such as a punched card or a raised structure in a groove with instructions recorded thereon), and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (such as a light pulse by a fiber optic cable), or an electrical signal transmitted by a wire.

[0114] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0115] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, and conventional procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits (including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs)) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuits to perform various aspects of the present invention.

[0116] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowchart and / or block diagram, and combinations of blocks in the flowchart and / or block diagram, can be implemented by computer-readable program instructions.

[0117] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions, through execution by the processor of the computer or other programmable data processing device, create a device for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can instruct the computer, programmable data processing device, and / or other device to function in a specific manner, so that the computer-readable storage medium having the instructions stored therein comprises an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0118] Computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other apparatus, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0119] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to different embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the function marked in the box may not occur in the order marked in the figure. For example, depending on the function involved, the two boxes shown in succession can actually be performed substantially simultaneously, or these boxes can sometimes be performed in the opposite order. It will also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be realized by a system based on dedicated hardware that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0120] The description of various embodiments of the present invention has been provided for illustrative purposes, but the above description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0121] Reference numerals

[0122] 10 System FW

[0123] 12 cores

[0124] 14 Asynchronous Kernel - Nested IF

[0125] 16 Aggregation Buffer

[0126] 18 System Nesting

[0127] 20 I / O bus controllers

[0128] 22 I / O buses

[0129] 24 I / O status buffer

[0130] 26 Early completion logic

[0131] 28 Buffer-IO bus controller IF

[0132] 30 I / O storage instructions

[0133] 32 Asynchronous IO driver code

[0134] 34 I / O setting code

[0135] 36 Asynchronous forwarding

[0136] 38 Asynchronous Bus

[0137] 40 User IF

[0138] 42 Array Management Logic

[0139] 44 I / O status array

[0140] 46 Array Management and Access Logic

[0141] 48 Message with the ID of the array item

[0142] 50 System HW / FW

[0143] 210 Data Processing System

[0144] 212 Computer Systems / Servers

[0145] 214 External Devices

[0146] 216 CPU / data processing unit

[0147] 218 Input and Output Bus

[0148] 220 Network Adapter

[0149] 222 Input and Output Interface

[0150] 224 Display

[0151] 228 Memory

[0152] 230 RAM

[0153] 232 Cache memory

[0154] 234 Storage System

[0155] 240 Programs / Utilities

[0156] 242 program modules

Claims

1. A data processing system for processing input / output storage instructions, comprising: The system nest is communicatively coupled to at least one input / output bus via an input / output bus controller, further comprising: a data processing unit comprising a kernel, system firmware, and an asynchronous kernel-nesting interface; wherein the data processing unit is communicatively coupled to the system nest via an aggregation buffer; wherein the system nest is configured to asynchronously load data from and / or store data to at least one external device communicatively coupled to the input / output bus, The asynchronous core-nested interface includes an input / output status array having multiple input / output status buffers, array management and access logic, And among them, (i) an operating system running on the data processing system, issuing the input / output storage instruction, which specifies at least an input / output function having an offset to an address, data to be transferred and / or a pointer to the data to be transferred, and a length of the data; (ii) the data processing unit is configured to identify the input / output function by the address specified in the input / output storage instruction; (iii) the data processing unit is configured to verify whether access to the input / output function is allowed at an address space and at a client instance level, the client running on the data processing system; (iv) the data processing unit is configured to complete the input / output storage instruction before execution of the input / output storage instruction in the system nest is completed; (v) the system firmware is configured to issue a system message to send data packets to the aggregation buffer until all data of a storage block has been forwarded to the aggregation buffer; (vi) the system firmware is configured to issue a system message to the aggregation buffer to asynchronously forward the data to the input / output bus controller in a single nested message while waiting for the aggregation buffer to send a completion message; (vii) the data processing unit is configured to receive a reusable message from the aggregation buffer after sending a message to the system nest, so as to be able to continue sending data to the system nest and the input / output bus controller through the aggregation buffer as early as possible; (viii) the system nest is configured to forward the message to a target location; (ix) the input / output bus controller is configured to receive the message, forward the data in the data frame to the input / output bus, and send a completion message to the system nest; (x) the system nest is configured to forward the completion message to the aggregation buffer; (xi) the aggregation buffer is configured to forward the completion message to the asynchronous kernel-nesting interface; (xii) the asynchronous core-nest interface is configured to store state in the input / output buffer and to signal operation completion to the system firmware; (xiii) the system firmware is configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output storage instruction; (xiv) The data processing unit delays execution of the store instruction until an input / output status buffer is available to store information about completion of the pending store instruction.

2. The data processing system according to claim 1, further comprising: Execution of asynchronous and / or synchronous store instructions is delayed until the input / output status buffer is available to store information regarding completion of pending store instructions.

3. The data processing system according to claim 1 or 2, wherein: The system nest is communicatively coupled to the data processing unit via the aggregation buffer, and message status and / or completion status are collected from the system nest. 4 . The data processing system according to claim 3 , wherein the message status and / or the completion status are numbered by an input / output status buffer index.

5. The data processing system of claim 3, wherein the aggregation buffer is communicatively coupled to an asynchronous core-nesting interface of the data processing unit via an asynchronous bus. The data processing system according to claim 3 , wherein: If the length of the data exceeds 8 bytes, the data is transferred to the aggregation buffer in multiple data packets by the input / output storage instruction via an asynchronous transfer mechanism with an early completion message; otherwise, the data is transferred in one data packet.

7. The data processing system of claim 1, wherein the system firmware includes asynchronous I / O driver code for processing the I / O storage instruction.

8. The data processing system of claim 7, the kernel comprising asynchronous setup code for handling memory requirements for status information of the asynchronous input / output driver code. 9 . The data processing system according to claim 5 , wherein the asynchronous kernel-nested interface comprises an asynchronous kernel-nested interface forwarding component for forwarding locally completed data.

10. The data processing system of claim 3, the aggregation buffer comprising early completion logic for transmitting a free for reuse message after sending a request.

11. The data processing system according to claim 1 , wherein the system firmware comprises array management logic, and the array management logic allocates / releases an input / output status buffer in the input / output status array and / or initiates the start of a new storage instruction.

12. The data processing system according to claim 1, wherein the system message used in the system comprises one of the following: - Hierarchical physical target address, - provides an SMT thread or aggregate buffer identifier, - the length of the data, - Input / Output bus address, - Input / output status buffer index.

13. A method for processing an input / output storage instruction for at least one external device of a data processing system, the data processing system comprising: a system nested in communication coupled to at least one input / output bus via an input / output bus controller, and further comprising at least a data processing unit, the data processing unit comprising a kernel, system firmware and an asynchronous kernel-nested interface, wherein the data processing unit is communicatively coupled to the system nest via an aggregate buffer, wherein the system nest is configured to asynchronously load data from and / or store data to at least one external device communicatively coupled to the input / output bus, wherein the asynchronous core-nest interface includes an input / output status array having a plurality of input / output status buffers, array management and access logic, The method includes: (i) an operating system running on the data processing system, issuing the input / output storage instruction, which specifies at least an input / output function having an offset to an address, data to be transferred and / or a pointer to the data to be transferred, and a length of the data; (ii) the data processing unit identifies the input / output function by the address specified in the input / output storage instruction; (iii) the data processing unit verifies whether access to the input / output function is allowed at the address space and at the client instance level, the client running on the data processing system; (iv) the data processing unit completes the input / output storage instruction before execution of the input / output storage instruction in the system nest is completed; (v) the system firmware issues a system message to send data packets to the aggregation buffer until all data of the storage block has been forwarded to the aggregation buffer; (vi) the system firmware issues a system message to the aggregation buffer to asynchronously forward the data to the input / output bus controller in the form of a single nested message, while waiting for the aggregation buffer to send a completion message; (vii) after sending a message to the system nest, the data processing unit receives a reusable message from the aggregation buffer so as to be able to continue sending data to the system nest and the input / output bus controller through the aggregation buffer as soon as possible; (viii) the system nesting forwards the message to the target location; (ix) the input / output bus controller receives the message, forwards the data in the data frame to the input / output bus, and sends a completion message to the system nest; (x) the system nesting forwards the completion message to the aggregation buffer; (xi) the aggregation buffer forwards the completion message to the asynchronous kernel-nesting interface; (xii) the asynchronous core-nested interface stores state in the input / output buffer and signals the system firmware that the operation is complete; (xiii) the system firmware is configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output storage instruction; (xiv) The data processing unit delays execution of the store instruction until an input / output status buffer is available to store information about completion of the pending store instruction.

14. The method according to claim 13, further comprising: Execution of asynchronous and / or synchronous store instructions is delayed until the input / output status buffer is available to store information regarding completion of pending store instructions.

15. The method according to claim 13 or 14, further comprising: Message status and / or completion status are collected, wherein the message status and / or the completion status are numbered by an input / output status buffer index.

16. The method according to claim 15, wherein If the length of the data exceeds 8 bytes, the data is transferred by the input / output store instruction to the aggregation buffer in multiple data packets via an asynchronous transfer mechanism with an early completion message.

17. The method according to claim 16, wherein The aggregation buffer uses early completion logic for transmitting free for reuse messages after a send request.

18. The method according to claim 13, wherein The system message used in the method includes one of the following: - Hierarchical physical target address, - provides an SMT thread or aggregate buffer identifier, - the length of the data, - Input / Output bus address, - Input / output status buffer index.

19. A computer program product comprising program instructions, wherein the program instructions are executable by a computer system to cause the computer system to perform the method according to any one of claims 13 to 18.

20. A data processing system for executing a data processing program, the data processing system comprising computer-readable program instructions for performing the method according to any one of claims 13 to 18.

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