Report control information error

Abstract

This application is directed to reporting control information errors. The status of a memory array can be monitored during operation. After detecting an error (e.g., in received control information), the memory device can enter a first state (e.g., a locked state) and can indicate to the host device the detected error, the status of the memory array before the error was detected, and / or at least a portion of the control signal carrying the received control information. The host device can diagnose the cause of the error based on receiving the indication of the error and / or the copy of the control signal. After identifying and / or resolving the cause of the error, the host device can transmit one or more commands (e.g., unlock the memory device and return the memory array to the original state) based on receiving the original state from the memory device.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 067412, filed Dec. 19, 2019, by Richter et al. and titled "REPORTING CONTROL INFORMATION ERRORS", which claims priority to U.S. Patent Application No. 16 / 719,896, filed Dec. 18, 2019, by Richter et al. and titled "REPORTING CONTROL INFORMATION ERRORS" and to U.S. Provisional Patent Application No. 62 / 781,989, filed Dec. 19, 2018, by Richter et al. and titled "REPORTING CONTROL INFORMATION ERRORS", all of which are assigned to the assignee hereof and are hereby incorporated by reference in their entireties.

[0003] The technical field relates to reporting control information errors. BACKGROUND OF THE DISCLOSURE

[0004] The following generally relates to operating a memory array and, more particularly, to reporting control information errors.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, commonly labeled as logic "1" or logic "0". In other systems, more than two states can be stored. To access the stored information, components of an electronic device can read or sense at least one of the stored states in the memory device. To store information, components of an electronic device can write or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memories (e.g., FeRAM, PCM, RRAM) can maintain their stored logical states for a long time, even in the absence of an external power supply. Volatile memory devices (e.g., DRAM) may lose their stored states over time unless periodically refreshed by an external power supply.

[0007] Control information for operating or accessing a memory device can be transmitted between an external controller and the memory device. In some cases, the control information received at the memory device is corrupted. There is a desire to improve techniques for managing such situations. Summary of the Invention

[0008] Describes a method. The method may include receiving, from a host device, control information for operating a memory array, the control information including a first command; detecting an error in the control information; at least partially based on detecting the error, suppressing execution of the first command; at least partially based on detecting the error, entering a state that restricts access to the memory array; and at least partially based on entering the state that restricts access to the memory array, transmitting a first indication that the error has been detected in the control information to the host device.

[0009] Describes a method. The method may include determining, by a host device, control information for operating a memory array of a memory device; transmitting a control signal including the control information to the memory device; receiving, from the memory device, an indication that a corrupted version of the control signal has been received at the memory device and a state of the memory array before the corrupted version of the control signal was received at the memory device; and at least partially based on receiving the state of the memory array, transmitting one or more commands for restoring the state of the memory array.

[0010] Describe a device. The device may include a memory array including a plurality of memory banks; a receiver coupled to the memory array and configured to receive control signaling including control information for accessing the memory array; circuitry coupled to the receiver and configured to detect an error in the control information and signal an indication of the detected error, wherein the memory array is configured to enter an access-limited state based at least in part on an output of the circuitry; a first register coupled to the circuitry and configured to store a state of the memory array based at least in part on the output of the circuitry; and a transmitter coupled to the first register and configured to transmit the content of the first register and an indication of an error detected in control information corresponding to the content of the first register to a host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Describe aspects of an exemplary system that supports reporting errors in control information as disclosed herein.

[0012] Figure 2 Describe aspects of an exemplary memory device that supports reporting errors in control information as disclosed herein.

[0013] Figure 3 Describe aspects of an exemplary system that supports reporting errors in control information as disclosed herein.

[0014] Figure 4 Describe aspects of an exemplary memory device that supports reporting errors in control information as disclosed herein.

[0015] Figure 5 Describe an exemplary timing diagram for reporting errors in control information as disclosed herein.

[0016] Figure 6 Describe aspects of an exemplary memory device that supports reporting errors in control information as disclosed herein.

[0017] Figure 7 Describe an exemplary flowchart for reporting errors in control information as disclosed herein.

[0018] Figure 8 Describe an exemplary processing flow for reporting errors in control information as disclosed herein.

[0019] Figure 9 and 10 Describe a block diagram representing aspects of a controller that supports reporting errors in control information as disclosed herein.

[0020] Figure 11 and 12A flowchart illustrating one or more methods for reporting control information errors as disclosed herein. DETAILED DESCRIPTION

[0021] Electronic transmissions containing control information (which may be referred to herein as control signaling) and data (which may be referred to herein as control signaling data signaling) may be transferred within a memory system. Control information contained in the control signaling may include commands, addresses, or error detection / correction information, or a combination thereof. In some cases, errors such as those attributable to transmission, reception, signal lane, and / or timing errors may be detected in the control information.

[0022] In some cases, after an error is detected in the received information (e.g., in the control information), the device receiving the control information (e.g., the memory device) may discard the control information, such as by refraining from executing the command in the control information, and indicate to the device transmitting the control information (e.g., the host device) that an error has been detected in the received control information. However, receiving an indication that an error has occurred at the memory device may not indicate to the host device what type of error has occurred or what caused the error, among other information. That is, the memory device may be able to detect an error but may not be certain, or may not be able to determine, the cause or nature of the error.

[0023] To enable the host device to better diagnose the cause, nature, or both of errors in the transmitted control information, the receiving device may provide the host device with additional information (e.g., regarding the cause and nature of the error detected in the control information). For example, the receiving device may transmit at least a non - complete but at least a portion of the stored copy of the received control signal containing the corrupted control information to the host device. And the host device may then use the information of the received control signal (e.g., the copy) to determine the cause of the error, such as by comparing the received control signal with the transmitted control signal. In some cases, by allowing the host device to diagnose the cause or nature of the error, the host device may be able to take measures to correct or avoid errors in subsequent communications (e.g., by updating the modulation scheme or avoiding a damaged signal path). In some instances, an instruction register and accompanying logic components may be included in the memory device to store the failed control signal.

[0024] In some cases, the memory device may enter a locked state until the host device identifies and / or resolves the cause of the error. Entering the locked state may include refraining from executing the received command and shutting down all memory banks at the memory device. By entering the locked state, the memory device may preserve the information stored in the memory array at the memory device. However, after entering the locked state, the memory device may not be able to return to its previous state without the assistance of another device (e.g., the host device).

[0025] To support the locked state of the memory device, the memory device may store (e.g., continuously store) the state of the memory array during normal operation (e.g., non-locked operation) and may transmit the state of the memory array stored before / at the time of detecting an error in the received control information to the host device. For example, the memory device may store (e.g., continuously store) the memory address of the most recently accessed row in each memory bank and the state of each memory bank (e.g., whether the memory bank is open or closed) based on the latest data in the memory array. In some instances, a register bank and accompanying logic components may be included in the memory device to store the memory address and bank state of the memory array (which may be collectively referred to as "memory state" or "memory state information").

[0026] The following further describes the features of the present disclosure introduced above in the context of the Figure 1-2 memory system referenced. Specific examples of the memory device, timing diagrams, flowcharts, and processing flows for reporting control information errors with reference to the Figure 3-8 are then described. These and other features of the present disclosure are further illustrated by and described with reference to device diagrams, system diagrams, and flowcharts related to reporting control information errors as described with reference to the Figure 9-12 device diagrams, system diagrams, and flowcharts described.

[0027] Figure 1 Aspects of an exemplary system that supports reporting control information errors as disclosed herein are illustrated. System 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 that couple the external memory controller 105 to the memory device 110. System 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0028] System 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. The memory device 110 may be a component of a system configured to store data for one or more other components of System 100. In some instances, System 100 is configured for two-way wireless communication with other systems or devices using a base station or access point. In some instances, System 100 is capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0029] At least some portions of system 100 may be examples of host devices. Such host devices may be examples of devices that use memory to execute processing programs, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, Internet-connected devices, some other stationary or portable electronic device, etc. In some cases, the host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as the host or host device. In some instances, system 100 may be a graphics card. The host device may include multiple drivers and multiple channels that link the host device to the memory device.

[0030] In some cases, the memory device 110 may be an independent device or component configured to communicate with other components of system 100 and provide physical memory addresses or other spaces that can be used or referenced by system 100. In some instances, the memory device 110 may be configured to cooperate with at least one or more different types of system 100. Signaling between the components of system 100 and the memory device 110 can be used to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packages of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and other factors.

[0031] The memory device 110 may be configured to store data for the components of system 100. In some cases, the memory device 110 may act as a slave device of system 100 (e.g., respond to and execute commands provided by system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. In some cases, the access command may be a command that causes the memory device to store data or read data from one or more memory cells. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support the desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0032] System 100 may additionally include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may be coupled or electronically communicated with each other using a bus 140.

[0033] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, processor 120 may be an instance of a CPU, a GPU, a GPGPU, or a system on a chip (SoC), among other instances.

[0034] In some cases, processor 120 may be incorporated into or part of external memory controller 105. In some cases, processor 120 may be a GPU. Processor 120 may perform various aspects of configuring bus transmission lines (e.g., data bus transmission lines) as described herein. For example, processor 120 may divide a data bus into two groups of transmission lines: a first group that transmits control signals and a second group that transmits data signals.

[0035] BIOS component 125 may be a software component including BIOS operating as firmware that may initialize and run various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0036] Peripheral component 130 may be any input device or output device, or an interface to such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a peripheral component interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components that are understood by those skilled in the art to be peripheral devices.

[0037] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0038] Input device 145 may represent a device or signal that is external to system 100 and can provide information, signals, or data to system 100 or its components. This can include a user interface or an interface with or between other devices. In some cases, input device 145 can be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or can be managed by I / O controller 135.

[0039] Output device 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output device 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output device 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0040] The components of system 100 may be composed of general or special purpose circuits designed to perform their functions. This may include output driver circuitry and various other circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements configured to implement the functions described herein.

[0041] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, each of which is configured to store at least one bit of digital data. Figure 2 Features of memory array 170 and / or memory cells are further described.

[0042] Memory array 170 may be an example of a two-dimensional (2D) memory cell array or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, a level, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high stacked memory dies, three high stacked memory dies, four high stacked memory dies, five high stacked memory dies, six high stacked memory dies, seven high stacked memory dies, eight high stacked memory dies). This can increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn can reduce production costs, increase performance of the memory array, or both. In some 3D memory devices, different stacks can share at least one common access line, such that some stacks can share at least one of a word line, a digit line, and / or a plate line.

[0043] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with the external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or control signals (e.g., commands, addresses, and / or error detection information) from the external memory controller 105. For example, the memory device 110 may receive a write command or a read command, wherein the write command instructs the memory device 110 to store certain data on behalf of a component of the system 100 (e.g., the processor 120) and the read command instructs the memory device 110 to provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, an encoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, and the like.

[0044] A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 may be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 to control the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0045] The external memory controller 105 may be configured to enable the transfer of information, data, commands, and / or addresses between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the operating details of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 satisfies. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0046] In some cases, the external memory controller 105 or other components of the system 100 or its functions described herein may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functions described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120).

[0047] Components of system 100 may exchange information with memory device 110 using a plurality of channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to function as part of a channel. In some cases, a pin or pad of a terminal may be part of a signal path of channel 115.

[0048] Additional signal paths may be coupled to the terminals of the channels to route signals within the components of the system 100. For example, the memory device 110 may include signal paths (e.g., signal paths internal to the memory device 110 or its components, such as signal paths internal to the memory die 160) that route signals from the terminals of the channel 115 to various components of the memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170). The signal paths may be implemented using one or more types of transmit lines, including differential transmit lines and single-ended transmit lines.

[0049] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting a specific type of information. In some cases, channel 115 may be an aggregate channel and may therefore include multiple individual channels. For example, data channel 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc. Signals transmitted via the channel may use double data rate (DDR) signaling. For example, some symbols of the signal may be recorded on the rising edge of the clock signal, and other symbols of the signal may be recorded on the falling edge of the clock signal. Signals transmitted via the channel may use single data rate (SDR) signaling. For example, for each clock cycle, one symbol of the signal may be recorded.

[0050] In some cases, the channel 115 may include one or more command and address (C / A) channels 186. The C / A channel 186 may be configured to transmit commands between the external memory controller 105 and the memory device 110, including control information associated with the command (e.g., address information). For example, the C / A channel 186 may include a read command regarding the address of the desired data. In some cases, the C / A channel 186 may register on a rising clock signal edge and / or a falling clock signal edge. In some cases, the C / A channel 186 may include multiple (e.g., eight or nine) signal paths.

[0051] In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channel 188 may be configured to transmit one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to adjust (e.g., oscillate) between a high state and a low state, and coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal) and the signal path of the CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. The CK channel 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations of the memory device 110 or other system-wide operations of the memory device 110. The clock signal CK may therefore be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0052] In some cases, the channel 115 may include one or more data (DQ) channels 190. For example, the channel 115 may include data channels 190-1 to 190-n. Each data channel may be associated with or include one or more transmission lines. The data channels 190 may be configured to communicate data and / or control information between the external memory controller 105 and the memory device 110. For example, the data channels 190 may communicate information to be written to the memory device 110 (e.g., bidirectionally) or information to be read from the memory device 110.

[0053] In some cases, channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths.

[0054] In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference (e.g., a timing reference for both read and write operations) that is typically used for access operations of the memory device 110. Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t signal and WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0055] In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels may be configured to convey error detection signals, such as checksums, to improve system reliability. EDC channels may include any number of signal paths.

[0056] Channel 115 may couple external memory controller 105 with memory device 110 using a variety of different architectures. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0057] Different types of signals may be transmitted on channel 115. In some cases, a control signal including both a command and a memory address is referred to as a C / A signal. In one example, a C / A signal including an activate ("ACT") command and a row address may indicate to a memory device to activate a row of memory cells in preparation for or in conjunction with another memory operation (e.g., a read or write operation). Activating a memory cell may refer to energizing a word line corresponding to the memory cell. When an ACT command is transmitted to the memory device, the ACT command may include or be followed by a certain number of address bits indicating a group that is the target of an upcoming read or write operation and a row within the group to be activated. Thus, the transmitted ACT command may include or be followed by a group and row address associated with an upcoming memory operation. When the ACT command includes a row address, the ACT command may be referred to as a row command. An external controller may transmit an ACT command whenever a new row in a group is targeted for a read or write operation.

[0058] A precharge ("PRE") command may indicate to the memory device that a memory bank is to be turned off. Turning off a memory bank may include removing applied voltages from word lines in the memory bank and turning off any rows turned on by a previous ACT command. An external controller may issue a PRE command after an ACT command has been used to turn on a row in a memory bank, e.g., to effectuate turning on of a different row in the same memory bank.

[0059] A read ("RD") command may indicate to a memory device that one or more memory cells are to undergo a read operation so that the information stored therein (e.g., as represented by a logic state) may be transferred to an external controller. Reading a memory cell may refer to a process of applying a voltage across a memory cell to cause the memory cell to discharge onto a digital line for sensing. When a read command is transmitted to a memory device, the read command may include or be followed by a bank address and a column address of a memory cell that is the target of the read operation. When a read command includes a column address, the read command may be referred to as a column command. In some cases, the read command may also indicate the number of memory cells to be read, starting at an initial address point. The number of memory cells to be read in response to a read command may be referred to as a read burst length.

[0060] A write ("WR") command may indicate to a memory device that one or more memory cells are to undergo a write operation so that information from an external controller may be stored in one of the memory banks of the memory device. Writing a memory cell may refer to a process of applying a voltage across a memory cell so that the memory cell is charged to a state indicating a logical one or zero. When a write command is transmitted to a memory device, the write command may include or be followed by a bank address and a column address of a memory cell that is the target of the write operation. When a write command includes a column address, the write command may be referred to as a column command. In some cases, the write command may also indicate the number of memory cells to be written, starting at an initial address point. The number of memory cells to be written in response to a write command may be referred to as a write burst length.

[0061] Signals communicated over the channel 115 (and its associated transmission lines) may be modulated using a variety of different modulation schemes. In some cases, signals communicated between the external memory controller 105 and the memory device 110 may be modulated using a binary symbol (or binary level) modulation scheme. A binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, NRZ, unipolar encoding, bipolar encoding, Manchester encoding, PAM with two symbols (e.g., PAM2), and the like.

[0062] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals transmitted between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal (e.g., a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0063] As discussed herein, signaling including control information ("control signaling") and data ("data signaling") may be transmitted within a memory system, such as between a host device 105 and a memory device 110. The control information included in the control signaling may include commands, addresses, and / or error detection / correction information. In some cases, errors due to, for example, transmission, reception, signal lanes, and / or timing errors may be detected in the control information. In some cases, after receiving an error in the control information, the device receiving the control information ("memory device") may discard the control information, such as refraining from executing the command in the control information, and indicating to the device transmitting the control information ("host device") that an error was detected in the received control information. However, receiving an indication that an error occurred at the memory device may not indicate to the host device what type of error occurred or what caused the error. That is, the memory device may be able to detect an error but may not be certain, or may not be able to determine the cause or nature of the error. In addition, the memory device may not be able to determine which command the host actually transmitted or intended to transmit to the memory device.

[0064] To enable the host device to diagnose the cause and / or nature of the error in the transmitted control information, the receiving device may provide the host device with additional information about the cause and nature of the error detected in the control information. For example, the receiving device may transmit a stored copy of at least a portion, if not a complete copy, of at least a portion of a received control signal that includes damaged control information to the host device. And the host device may then use the partial or complete stored copy of the received control signal to determine the cause of the error, for example, by comparing the received control signal against the transmitted control signal. By allowing the host device to diagnose the cause or nature of the error, the host device may be able to take measures to correct or avoid the error in subsequent communications (e.g., by updating the modulation scheme or avoiding damaged signal paths). In some examples, the instruction register and accompanying logic components may be included in a memory device to store the failed control signal.

[0065] In some cases, the memory device may enter a locked state until the host device identifies and / or resolves the cause of the error. Entering the locked state may include refraining from executing received commands and shutting down all memory banks at the memory device. By entering the locked state, the memory device may save information stored in the memory array at the memory device until the cause of the error has been resolved. However, after entering the locked state, the memory device may not be able to return to its previous state without the assistance of another device (e.g., a host device).

[0066] To support the locked state of the memory device and to enable the memory device to fully recover from errors, the memory device may continuously store the state of the memory array during normal operation (e.g., non-locked operation) and may transmit the state of the memory array stored before / when the error was detected in the received control information to the host device. For example, the memory device may continuously store the memory address of the most recently accessed row in the memory group and the state of each memory group (e.g., whether the memory group is turned on or off) based on the latest data of each memory group in the memory array. In some examples, a register set and accompanying logic components may be included in the memory device to store the memory address (e.g., row address) and group state of the memory array (which may be collectively referred to as "memory state" or "memory state information").

[0067] Figure 2 Aspects of an exemplary memory device that supports reporting of control information errors as disclosed herein are described.

[0068] The memory device 200 may be a reference Figure 1 1. An example of a memory die 160 is described in detail. In some cases, the memory device 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory device 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic (e.g., logic 0 and logic 1) at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic (e.g., logic 00, logic 01, logic 10, or logic 11) at a time.

[0069] Memory cell 205 may store a charge representing a programmable state in a capacitor. In a dynamic random access memory (DRAM) architecture, a memory cell such as memory cell 205 may include a capacitor including a dielectric material that stores a charge representing a programmable state. In other memory architectures, other storage devices and components are possible. For example, a nonlinear dielectric material may be used.

[0070] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210 and / or digit line 215. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, and digit lines, or the like, are interchangeable and do not affect understanding or operation. Activating or selecting word line 210 or digit line 215 may include applying a voltage to the corresponding line.

[0071] The memory device 200 may include access lines (e.g., word lines 210 and digit lines 215) arranged in a grid-like pattern. Memory cells 205 may be located at the intersections of the word lines 210 and digit lines 215. By biasing the word lines 210 and digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at their intersections. The memory device 200 may include a number of memory banks, at least some of which (if not all) may have unique addresses and may include a large number of rows and columns.

[0072] Access to the memory cells 205 in the memory group may be controlled by the row decoder 220 or the column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the word line 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 260 and may activate the digit line 215 based on the received column address. For example, the memory device 200 may include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Therefore, by activating the word line 210 and the digit line 215, such as WL_1 and DL_3, the memory cell 205 at the intersection thereof may be accessed. The intersection of the word line 210 and the digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 205.

[0073] Memory cell 205 may include a logic storage component, such as capacitor 230 and switch component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switch component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 is ground, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switch component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes (e.g., stops) electronic communication between two components.

[0074] Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switch component 235. Capacitor 230 may be in electronic communication with digit line 215 using switch component 235. For example, when switch component 235 is deactivated, capacitor 230 may be isolated from digit line 215, and when switch component 235 is activated, capacitor 230 may be coupled to digit line 215. In some cases, switch component 235 may be or include a transistor, and its operation may be controlled by applying a voltage to a transistor gate, wherein a voltage difference between the transistor gate and the transistor source may be greater than or less than a threshold voltage of the transistor. In some cases, switch component 235 may be or include a p-type transistor or an n-type transistor. Word line 210 may be in electronic communication with a gate of switch component 235, and switch component 235 may be activated / deactivated based on a voltage applied to word line 210.

[0075] The word line 210 may be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of a switching element 235 of the memory cell 205 and may be configured to control the switching element 235 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205 and the memory cell 205 may not include a switching element.

[0076] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing component 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during a portion of an access operation. For example, the word line 210 and the switching component 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0077] The sensing component 245 may be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205, and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be small. Therefore, the sensing component 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205. The sense amplifier may detect a small change in the charge of the digit line 215 during a read operation, and may generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output a signal (e.g., release charge) to its corresponding digit line 215. The signal may cause the voltage of the digit line 215 to change. The sensing component 245 may be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 250 (e.g., a reference voltage). The sensing component 245 may determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digital line 215 has a higher voltage than the reference signal 250, then the sensing component 245 can determine that the stored state of the memory cell 205 is a logic 1, and if the digital line 215 has a lower voltage than the reference signal 250, then the sensing component 245 can determine that the stored state of the memory cell 205 is a logic 0.

[0078] The sensing component 245 may include various transistors or amplifiers to detect and amplify the difference in the signal. In some cases, the sensing component 245 may be part of another component (e.g., column decoder 225, row decoder 220). In some cases, the sensing component 245 may be in electronic communication with the row decoder 220 or the column decoder 225.

[0079] As one example, the detected logic state of the memory cell 205 as determined by the sense component 245 may be output by the column decoder 225 as an output 255. The output 255 may communicate the detected logic state to one or more intermediate components (e.g., a local memory controller) for transmission over one or more channels (e.g., for transmission on one or more transmission lines). Thus, the detected logic state of the memory cell 205 may be communicated to a device or component external to the memory device 200. For example, the detected logic state may be communicated via one or more transmission lines (e.g., to the external memory controller 105).

[0080] The local memory controller 260 may control the operation of the memory cell 205 via various components (eg, the row decoder 220, the column decoder 225, and the sensing component 245). The local memory controller 260 may be a reference Figure 1105 . In some cases, one or more of the row decoder 220, column decoder 225, and sense component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be configured to receive data from the external memory controller 105 (or reference 105). Figure 1 The device memory controller 155 described herein receives commands and / or data, translates the commands and / or data into information that can be used by the memory device 200, performs one or more operations on the memory device 200, and communicates data from the memory device 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 260 can generate row signals and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory device 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein can be adjusted or changed and can be different for the various operations discussed in operating the memory device 200.

[0081] In some cases, the local memory controller 260 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory device 200. The write operation may be used for data received from an external device. During the write operation, the memory cells 205 of the memory device 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify the target memory cell 205 to which the write operation will be performed. The local memory controller 260 may identify the target word line 210 and the target digit line 215 (e.g., the address of the target memory cell 205) that are in electronic communication with the target memory cell 205. The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. Local memory controller 260 may apply a first signal (eg, voltage) to digit line 215 to store a first state (eg, charge) in capacitor 230 of memory cell 205 during a write operation, and the first state (eg, charge) may indicate a desired logic state.

[0082] In some cases, the local memory controller 260 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory device 200. The read operation may be used for data requested by or intended for an external device. During a read operation, a logical state stored in a memory cell 205 of the memory device 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify a target memory cell 205 on which a read operation is to be performed. The local memory controller 260 may identify a target word line 210 and a target digit line 215 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205.

[0083] The local memory controller 260 may be configured to store memory state information (e.g., the most recently accessed row address and memory bank status of each memory bank) during operation of the memory device 200. In some cases, the local memory controller 260 may be configured to cause the memory device 200 to enter a locked state after detecting an error in the received control information. The local memory controller 260 may also be configured to cause the memory device to store a copy of all or a portion of the control signal after detecting an error in the control information received in the control signal. In addition, the local memory controller 260 may cause the memory device 200 to transmit at least a portion or a complete copy of the memory state information and / or the failure control signal to an external device, such as a host device, after detecting an error or in response to a request from an external device.

[0084] The target memory cell 205 may transmit a signal to the sensing component 245 in response to biasing the access line. The sensing component 245 may amplify the signal. The local memory controller 260 may activate (or "fire") the sensing component 245 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 to the reference signal 250. Based on the comparison, the sensing component 245 may determine the logic state stored on the memory cell 205. As part of the read operation, the local memory controller 260 may transmit the logic state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller 155).

[0085] In some memory architectures, accessing the memory cell 205 may degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. The local memory controller 260 may perform a rewrite operation or a refresh operation to restore the memory cell to its original logic state. The local memory controller 260 may rewrite the logic state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered part of the read operation.

[0086] Figure 3 Aspects of an exemplary system that supports reporting control information errors as disclosed herein are described.

[0087] System 300 may be a reference Figure 1 300 may include a host device 305, a memory device 310, and a transmission line 315. In some cases, the host device 305 may be a reference Figure 1 The described examples of external memory controller 105 (also referred to as external controller, host device controller or host) or processor 120 (e.g., GPU, GPGPU, CPU). In some cases, memory device 310 may be referenced Figure 1 and 2 Examples of memory device 110, memory die 160, device memory controller 155, local memory controller 165, or memory device 200 are depicted.

[0088] The host device 305 may be configured to transmit control and data information to the memory device 310. As discussed herein, the host device 305 may also be configured to receive an indication from the memory device 310 that the memory device 310 failed to properly decode the control information received from the host device 305 (e.g., based on a failed CRC operation). After receiving the indication, the host device 305 (and other devices) may be configured to identify and resolve the error that caused the control information transmission failure (e.g., based on additional information received from the memory device 310). The host device 305 may be further configured to return the memory device 310 to a state previously identified by the memory device 310 after identifying and resolving the error. In some cases, the host device 305 may include a host transceiver 320 and a host pin 335.

[0089] Host transceiver 320 may be configured to transmit signaling conveying control and / or data information to memory device 310 and receive signaling conveying control and / or data information from memory device 310. Host transceiver 320 may include host pins 335 and / or may be in electronic communication with host pins 335.

[0090] The host pins 335 may be configured to provide an interface between the host transceiver 320 and the transmission line 315. That is, the host pins 335 may cause internal signals at the host device 305 to be transmitted to other devices. In some cases, a pin located at the host device 305 (e.g., a controller pin 1a ("CP_1a")) may correspond to a pin located at the memory device 310 (e.g., a memory device pin 1a ("MDP_1a")). In some cases, the host pins 335 may be referred to as nodes, pads, terminals, transmission line interfaces, interface components, or connection points. In some cases, the host pins 335 may be made of a conductive material capable of transmitting current or voltage into and out of the transmission line 315 and the host device 305. In some cases, the host pins 335 include an error pin 350. The error pin 350 may be configured to transmit between the host device 305 and the memory device 310 an indication that the memory device 310 failed to successfully decode the received control information (e.g., based on a CRC or parity error).

[0091] Memory device 310 may be configured to process control and data information received from host device 305 and to provide data information to host device 305. Memory device 310 may store information in memory cells of one or more memory banks (e.g., memory banks 0 to x). Memory cells may be arranged in rows and columns in memory banks, for example, as shown in FIG. Figure 2 described.

[0092] Memory device 310 may be further configured to detect errors in control information received from host device 305. Upon detecting an error, memory device 310 may indicate to host device 305 that an error occurred at memory device 310 (e.g., while processing control information received from host device 305). Memory device 310 may be configured to transmit additional information to host device 305 upon detecting an error, the additional information including address and group status information and / or at least a portion or a complete copy of the received control signal carrying corrupted control information. In some cases, memory device 310 may include memory transceiver 340 and memory pins 345.

[0093] Memory transceiver 340 may be configured to receive control and / or data information from host device 305. Memory transceiver 340 may also be configured to transmit control and / or data information to host device 305.

[0094] Memory pins 345 may be configured to provide an interface between transmit and receive components of memory device 310 and transmit line 315. In some cases, a pin located at memory device 310 (e.g., device pin 1a (“MDP_1a”)) may correspond to a pin located at host device 305 (e.g., controller pin 1a (“CP_1a”)). In some cases, memory pins 345 may be referred to as nodes, pads, terminals, transmit line interfaces, interface components, or connection points. In some cases, memory pins 345 may be made of a conductive material capable of transmitting current or voltage into and out of transmit line 315 and memory device 310. In some cases, memory pins 345 include error pins 355. Error pins 355 may be configured to transmit between host device 305 and memory device 310 an indication that memory device 310 failed to successfully decode received control information (e.g., based on a CRC or parity error). In some cases, memory device 310 may include error pins in addition to error pins 355.

[0095] Transmission line 315 can be configured to electronically connect host device 305 and memory device 310. As shown in system 300, transmission line 315 can originate at one component (e.g., host device 305) and terminate at another component (e.g., memory device 310) that may or may not be within the same device. Transmission line 315 can be a conductive wire or trace. In some cases, transmission line 315 provides a one-to-one mapping between host pin 335 and memory pin 345. In some cases, transmission line 315 includes a transmission line between a channel (e.g., reference Figure 1 For example, transmit lines 1a-M may be included in a control channel (eg, C / A channel 185) and transmit lines 1b-N may be included in a data channel (eg, DQ channel 190-1).

[0096] The C / A bus 325 can be configured to transmit C / A signaling between the host device 305 and the memory device 310. In some cases, the C / A bus 325 includes a subset of the host pins 335 (e.g., CP_1a to CP_M), a subset of the memory pins 345 (e.g., MDP_1a to MDP_M), and a subset of the transmission lines 315 (e.g., TL_1a to TL_M). In other cases, the C / A bus 325 is defined as including a subset of the transmission lines 315 and is equivalent to a channel, such as reference 1. Figure 1In some cases, the C / A bus 325 may also be configured to include an error pin 350 and an error pin 355. In some cases, the host device 305 may include error pins in addition to the error pin 350. In other cases, the memory device error pins including at least the error pin 350 and the host device error pins including at least the error pin 355 may not be included in the bus or may be included in different buses (e.g., an error correction / detection bus).

[0097] Data bus 330 can be configured to transmit data signaling between host device 305 and memory device 310. In some cases, data bus 330 includes a subset of host pins 335 (e.g., CP_1b to CP_N), a subset of memory pins 345 (e.g., MDP_1b to MDP_N), and a subset of transmission lines 315 (e.g., TL_1b to TL_N). In some cases, the data signal transmitted on data bus 330 corresponds to the C / A signal transmitted on C / A bus 325, for example, instructions for processing the data information transmitted in the data signal can be included in the previous C / A signal.

[0098] Figure 4 Aspects of an exemplary memory device that supports reporting of control information errors as disclosed herein are described.

[0099] The memory device 400 may be configured to detect errors in control information received from the host device and report the detected errors to the host device. In addition to reporting the detected errors to the host device, the memory device 400 may be further configured to store and transmit memory array state information (e.g., row address and group status) to the host device. The memory device 400 may also be further configured to store and transmit to the host device a version (e.g., a copy) of all or a portion of the control signal conveying the damaged control information.

[0100] The memory device 400 may be a reference Figures 1 to 3 4. The memory device 400 may include a command input 403, an address input 406, a clock input 409, a command decoder 412, a command checker 415, a first command line 418, a second command line 421, a third command line 424, a fourth command line 427, a command link 430, an error detection latch 433, a command logic 436, and an address logic 439. The memory device 400 may also include a register file 442, an instruction register 445, a memory status output 454, a first command decoder logic 457, a second command decoder logic 460, a third command decoder logic 463, a fourth command decoder logic 466, a command output 469, and an address output 472.

[0101] Command input 403 may be configured to transmit commands embedded in received control signaling / information to other components in memory device 400. In some cases, a portion of a transmitted control signal representing a command is transmitted on command input 403. In some cases, a receiver at memory device 400 (e.g., memory transceiver 340) outputs a received version of the portion of a transmitted control signal representing a command on command input 403. Address input 406 may similarly be configured to transmit an address corresponding to a command embedded in control signaling / information to a component in memory device 400. Command input 403 and address input 406 together may be configured to provide command and address signaling / information to a component in memory device 400. In some cases, command input 403 and / or address input 406 may be further configured to transmit error detection information (e.g., CRC and / or parity bits) to a component in memory device 400. Clock input 409 may be configured to transmit a timing signal (e.g., a clock) to a component in memory device 400.

[0102] Command decoder 412 may be configured to receive command information via command input 403 and determine a command corresponding to the received control information. For example, command decoder 412 may determine that after decoding the received command information, the received command information corresponds to an ACT, PRE, RD, or WR command.

[0103] The first command line 418, the second command line 421, the third command line 424, and the fourth command line 427 may be configured to transmit a command to a memory array within the memory device 400. In some cases, after identifying a command corresponding to the received control information, the command decoder 412 may output the determined command on a specific command line. For example, the command decoder 412 may output an ACT command on the first command line 418, a PRE command on the second command line 421, an RD command on the third command line 424, and a WR command on the fourth command line 427.

[0104] The first command decoder logic 457, the second command decoder logic 460, the third command decoder logic 463, and the fourth command decoder logic 466 may be configured to forward or block signals on the first command line 418, the second command line 421, the third command line 424, and the fourth command line 427 from being sent to a memory array in the memory device 400. For example, the first command decoder logic 457 may be configured to block the signal on the first command line 418 from being delivered to the memory array if the output of the error detection latch 433 indicates that an error has been detected to the first command decoder logic 457.

[0105] The command checker 415 may be configured to detect errors in the received control information. In some cases, the command checker 415 may use error detection techniques to determine that an error exists in the received control information. For example, the command checker 415 may check whether the CRC and / or parity bits included in the control information are consistent with the received control information. The command checker 415 may be further configured to output to other components in the memory device 400 whether an error has been detected in the received control information. For example, the command checker 415 may be configured to output a specific voltage (e.g., a high voltage) when an error is detected in the received control information.

[0106] The error detection latch 433 may be configured to store the output of the command checker 415. The error detection latch 433 may be further configured to signal the output of the command checker to other components in the memory device 400. In some cases, the error detection latch 433 is coupled to the clock input 409 and repeatedly stores the output of the command checker 415 each time a rising edge of a signal transmitted on the clock input 409 is registered at the error detection latch 433. After the error detection latch 433 stores the output of the command checker 415, the error detection latch 433 may also signal the output of the command checker 415 to other components in the memory device 400. In this way, the error detection latch 433 may delay the signaling of the output of the command checker 415 to other components in the memory device 400.

[0107] The command logic 436 may be configured to block the timing signal transmitted on the clock input 409 from being delivered to other components in the memory device 400 until the command checker 415 detects an error. For example, the command logic 436 may be an AND gate, where a first input of the AND gate is connected to the clock input 409 and a second input of the AND gate is connected to the command checker 415. The AND gate may be configured to output a low voltage as long as the output of the command checker 415 is a low voltage (e.g., when no error is detected) and may be configured to output a high voltage when the timing signal transmitted on the clock input 409 and the output of the command checker are high voltages (e.g., when an error is detected). The address logic 439 may be similarly configured to block the timing signal transmitted on the clock input 409 from being delivered to other components in the memory device 400 until the command checker 415 detects an error.

[0108] The register file 442 may be configured to store the current state of the memory array included in the memory device 400. In some cases, the register file 442 may be configured to store, for each memory bank in the memory array, the latest row address accessed in the memory bank and the state of the memory bank (e.g., whether the memory bank is turned on or off). In some cases, the contents of the register file 442 may be updated based on the output of the command decoder 412. For example, the register file 442 may be configured to update the latest row address accessed in the memory bank after determining that the command decoder 412 has output an ACT command. The register file 442 may be further configured to set a flag indicating that the memory bank identified by the ACT command is turned on after determining that the command decoder 412 has output an ACT command. In another example, the register file 442 may be configured to reset a flag indicating that the memory bank is turned off after determining that the command decoder 412 has output a PRE command identified by the memory bank. This relationship between the register file 442 and the command decoder 412, the first command line 418, and / or the second command line may be represented by the command link 430. In some cases, the command link is a physical connection (eg, a conductive trace).

[0109] Register file 442 may be further configured to signal at least a portion of the contents of register file 442 to a host device via memory status output 454, e.g., after an error is detected by command checker 415. In some cases, memory status output 454 is coupled to a data transmission line used to transfer data between memory device 400 and a host device. In some examples, the contents of register file 442 are transmitted to the host device using a more reliable transmission scheme (e.g., a transmission scheme associated with a low bit error rate, such as SDR) than a transmission scheme (e.g., DDR) used to transmit data between memory device 400 and the host device.

[0110] Instruction register 445 may be configured to store a version of the control signal (e.g., all or a portion of the control signal) transmitted on command input 403 and address input 406 after an error is detected in the control information embedded in the control signal. The instruction register may be further configured to transmit all or a portion of the stored version of the control signal to the host device after an error is detected. In some cases, instruction register 445 may include command latch 448 and address latch 451.

[0111] The command latch 448 may be configured to store a command signal transmitted on the command input 403 when a trigger is received (e.g., when the command latch 448 detects a rising edge at the enable input). As discussed above, the command logic 436 may block input of a timing signal transmitted on the clock input 409 until an error is detected at the command checker 415, wherein the output of the command logic may trigger storage of the command signal when an error is detected at the command checker 415. The address latch 451 may similarly be configured to store an address signal transmitted on the address input 406 when a trigger is received.

[0112] The command latch 448 may be further configured to signal the stored command signal to the host device via the command output 469 after the command checker 415 detects an error. In some cases, the command output 469 is coupled to a data transmission line used to transmit data between the memory device 400 and the host device. In some examples, the contents of the instruction register 445 are transmitted to the host device using a more reliable transmission scheme (e.g., a transmission scheme associated with a low bit error rate, such as PAM 2) than the transmission scheme used to transmit data between the memory device 400 and the host device (e.g., PAM4). The address latch 451 may be similarly configured to signal the stored address signal to the host device via the address output 472 after the command checker 415 detects an error. In some cases, the memory device 400 signals a single one of the stored command signal or the address signal to the host device (e.g., to save energy, reduce bandwidth, after an error is detected in a single one of the signals, etc.).

[0113] Figure 5 An exemplary timing diagram for reporting control information errors as disclosed herein is illustrated.

[0114] Timing diagram 500 may include clock signal 505, command signal 510, and error signal 520. The signals depicted by timing diagram 500 may represent aspects of a training procedure for determining a duration between transmitting a corrupted command signal from a host device and receiving an error indication from a memory device.

[0115] Clock signal 505 may represent one or more timing signals provided to components of a host device and / or a memory device, where the timing signals may be used to synchronize the timing of operations at the components. In some cases, clock signal 505 represents a reference Figure 4 The voltage of clock input 409 is depicted as varying over time.

[0116] Command signal 510 may represent one or more commands sent from a host device to a memory device. In some cases, command signal 510 represents a reference Figure 4The host device may be configured to transmit the training command 515 to determine the duration between transmitting the failure command and receiving an indication (e.g., error indication 525) of improperly receiving the command at the memory device. This duration may be represented by a reporting time interval 530. Unlike a damaged command received at the memory device, the memory device may be configured to not enter a locked state after receiving the training command 515.

[0117] The error signal 520 may represent that one or more error signals are transmitted from the memory device to the host device. In some cases, the error signal 520 is transmitted on a dedicated error line. In other cases, the error signal 520 is transmitted on one or more data lines or control lines. An error indication 525 may be included in the error signal 520. The memory device may be configured to transmit the error indication 525 after determining that a training command 515 and / or a damaged command has been received from the host device. By transmitting the error indication 525, the memory device may report to the host device that a command was incorrectly received at the memory device, for example due to a transmission error, a reception error, and / or a decoding error. When the host device receives the error indication 525 after transmitting the training command 515, the host device may determine the reporting time interval 530 as the time between transmitting the training command 515 and receiving the error indication 525.

[0118] In subsequent transmissions of control information, the host device may use the reporting time interval 530 to identify which command transmitted corresponds to which error indication. For example, the host device may receive an error indication from the memory device. The host device may then identify commands transmitted within a duration equal to the reporting time interval 530 before receiving the error indication. After identifying the command, the host device may determine that an error was detected in the command at the memory device. And after determining that an error was detected in the command, the host device may diagnose what caused the error to occur in the command (e.g., transmission error, timing error, signal lane error, reception error, decoding error, interference, etc.).

[0119] As described above, the error indication 525 may be indicated to the host device in a variety of different ways. For example, the memory device may transmit a specific voltage (e.g., a high voltage or a low voltage) to the host device on a dedicated error pin at the memory device, and the host device may determine that an error has occurred based on detecting the specific voltage on a corresponding error pin at the host. In another example, the memory device may transmit a specific voltage pattern to the host device on an existing transmission line (e.g., a data and / or control line) when an error is detected, and the host device may determine that an error has occurred based on detecting the specific voltage pattern on the repurposed transmission line. Similarly, in another example, the memory device may transmit a specific voltage sequence (or "pattern sequence") on an existing transmission line when an error is detected, and the host device may determine that an error has occurred based on detecting the pattern sequence. In another example, the memory device may indicate an error to the host by transmitting data to the host device along with an inverted checksum.

[0120] Figure 6 Aspects of an exemplary memory device that supports reporting of control information errors as disclosed herein are described.

[0121] The memory device 600 may be configured to refrain from entering the locked state after detecting an error in a command until one or more lock timers are inactive. By waiting before entering the locked state, the memory device 600 may enable commands successfully received before an error is detected to be properly executed.

[0122] The memory device 600 may be a reference Figures 1 to 4 Examples of memory device 110, memory device 200, memory device 310, and / or memory device 400 are described. Memory device 600 can include a command decoder 605, a command line 610, an error line 615, a first logic component 620, a RAS lock timer 625, a WR lock timer 630, a RD lock timer 635, and a second logic component 640.

[0123] Command decoder 605 may be configured to decode and / or detect errors in received commands. As part of memory device 600 entering a locked state, command decoder 605 may be further configured to transmit a command that causes all memory banks in memory device 600 to be precharged (a "PREALL command") after an error is detected in a received command. Command decoder 605 may be a reference Figure 4 Examples of command decoder 412 and / or command checker 415 are described.

[0124] Command line 610 may be configured to communicate a PREALL command to a memory array in memory device 600. In some cases, command decoder 605 may signal an indication of a PREALL command on command line 610 after detecting an error in a received command. Error line 615 may be configured to communicate an error indication to a memory array in memory device 600. In some cases, command decoder 605 may signal an error indication on error line 615 after detecting an error in a received command.

[0125] The first logic component 620 can be configured to forward signals transmitted on the command line to the memory array when all inputs of the first logic component 620 are activated (e.g., when the command decoder 605 indicates a PREALL command on the command line 610 and transmits an error indication on the error line 615). The first logic component 620 can also be configured to block the transmission of signals on the command line 610 when the inputs of the first logic component 620 are not activated. In some cases, the first logic component 620 includes an AND gate.

[0126] The RAS lock timer 625 can be configured to protect the operation of the ACT command by preventing the memory device 600 from entering a locked state before the execution of the ACT command is completed. For example, the RAS lock timer 625 can be initiated after receiving an indication from the command decoder 605 that the command decoder 605 has decoded the ACT command. After receiving the indication from the command decoder 605, the RAS lock timer 625 can be configured to start a timer, wherein the timer can be active for a duration covering the complete execution of the ACT command until a subsequent corresponding PRE command is transmitted. As long as the RAS lock timer 625 is active, the second logic component 640 can be configured to generate an output that causes the first logic component 620 to block the signal on the command line 610 from being forwarded to the memory array.

[0127] The WR lock timer 630 may similarly be configured to protect the operation of a WR command by preventing the memory device 600 from entering a locked state before the execution of the WR command is complete. For example, the WR lock timer 630 may be initiated after the WR command is received at the command decoder 605 and may be configured to be active for a duration that encompasses the complete execution of the WR command. As long as the WR lock timer 630 is active, the second logic component 640 may be configured to generate an output that causes the first logic component 620 to block the signal on the command line 610 from being forwarded to the memory array.

[0128] The RD lock timer 635 can similarly be configured to protect the operation of the RD command by preventing the memory device 600 from entering a locked state before the execution of the RD command is completed. For example, the RD lock timer 635 can be initiated after the RD command is received at the command decoder 605 and can be configured to be active for a duration covering the complete execution of the RD command. As long as the RD lock timer 635 is active, the second logic component 640 can be configured to generate an output that causes the first logic component 620 to block the signal on the command line 610 from being forwarded to the memory array.

[0129] By having multiple lock timers corresponding to particular commands, the memory device can reduce the latency associated with detecting command errors and entering a locked state. Other lock timers can be similarly implemented at the memory device 600. In some cases, instead of having individual lock timers for different commands, the memory device 600 can include a single lock timer that is activated for a duration that covers the longest execution of the memory operation.

[0130] Figure 7 An exemplary flow chart for reporting control information errors as disclosed herein is illustrated. Flowchart 700 may illustrate aspects of a method of entering and exiting a locked state after a memory device detects an error and reports to a host device that an error was detected in received control information. The memory device may be a reference Figures 1 to 4 6. The host device may be a reference to an example of the memory device 200, the memory device 310, the memory device 400, and / or the memory device 600 described in Figure 1 and 3 Examples of external memory controller 105, processor 120, and / or host device 305 are described.

[0131] At 705, the memory device may receive control information from the host device. In some cases, the memory device may receive a control signal including the control information at a transceiver. The control information may include commands, addresses, and / or error detection information.

[0132] At 710, after receiving the control information, the memory device may determine whether there is an error in the received control information. In some cases, the memory device uses the CRC bits included in the control information to determine whether there is an error. For example, the memory device may generate a CRC bit (or checksum) based on the control information and then compare the generated CRC bit with the received CRC bit. If the generated CRC bit matches the received CRC bit, the memory device may determine that there is no error in the received control information (i.e., the control information is successfully received, or no error occurs during the communication of the control information). Otherwise, if the generated CRC bit does not match the received CRC bit, the memory device may determine that there is an error in the received control information. Similarly, the memory device may use the parity bit included in the control information to determine whether there is an error. For example, the memory device may determine whether the received control information has an odd parity or an even parity based on the value of the parity bit. If the value of the parity bit indicates that the received control information has an even parity and the memory device determines that the received control information has an even parity, the memory device may determine that there is no error in the received control information. Otherwise, if the value of the parity bit indicates that the received control information has even parity and the memory device determines that the received control information has odd parity, or vice versa, the memory device may determine that there is an error in the received control information.

[0133] If an error is detected in the received control information, the memory device may perform the operations discussed at 715-730.

[0134] At 715, the memory device may set a lock bit that is configured to cause a component at the memory device to enter a limited state. For example, the lock bit may prevent the memory array from executing the failure command and any subsequent commands received at the memory device. In some cases, setting the lock bit includes storing a logical 1 at the lock bit. In some cases, the memory device may also store at least some (e.g., a copy) of the received control signals that carry corrupted control information.

[0135] At 720, the memory device may alert the host device that an error has occurred during reception / decoding of the received control information. For example, the memory device may transmit an indication that an error has occurred on a dedicated pin or by signaling a specific voltage pattern or sequence pattern on a pin also used for data and / or control signaling between the memory device and the host device. In another example, the memory device may alert the host by transmitting the data to the host device along with an inverted checksum.

[0136] In some cases, alerting the host device may include transmitting to the host the state of the memory array before / at the time of the control information detecting the error. Additionally or alternatively, alerting the host device may include transmitting to the host a copy of all or a portion of the received control signal conveying the damaged control information.

[0137] At 725, the memory device may shut down the memory bank located at the memory device based on detecting the error. In some cases, the memory device waits until one or more lock timers expire / are in a deactivated state before shutting down the memory bank.

[0138] At 730, the memory device may enter a self-refresh mode during which the memory banks are periodically refreshed to maintain states stored at memory cells in the memory banks and avoid loss of data content if the host device analyzes a failure.

[0139] If no errors are detected in the received control information, the memory device may perform the operations discussed at 735 .

[0140] At 735, the memory device may determine whether the memory device is currently in a locked state, for example, based on previously identifying a command error. In some cases, the memory device may determine that the memory device is in a locked state based on identifying that a lock bit is set.

[0141] If the memory device is currently in a locked state when the error-free control information is received, the memory device may perform the operations discussed at 740-745.

[0142] At 740, the memory device may reset the lock bit. In some cases, resetting the lock bit includes storing a logic 0 at the lock bit. In some cases, the memory device may reset the lock bit based on determining that the received control information includes an unlock command. In some cases, the memory device may reset the lock bit if an unlock command is received in the control information.

[0143] At 745, the memory device may exit the self-refresh / lock mode (ie, enter an unlocked or normal mode) based on resetting the lock bit. After returning to normal operation, the memory device may continue to process and execute control information received from the host device.

[0144] If the memory device is currently in an unlocked state when the error-free control information is received, the memory device may perform the operations discussed at 750-785.

[0145] At 750, the memory device may determine whether the received control information includes an ACT command. In some cases, the memory device may indicate that an ACT command was decoded (e.g., via a dedicated command line, such as a reference line) based on a command decoder at the memory device. Figure 4 The first command line 418 described above determines that an ACT command has been received.

[0146] If an ACT command is received in the control information, the memory device may perform the operations discussed at 755 , 760 , and 785 .

[0147] At 755, after determining that an ACT command is received in the control information, the memory device may turn on the row of memory cells in the memory bank indicated by the address received in the control information.

[0148] At 760, after turning on a memory row in a memory bank, the memory device may store a row address corresponding to the row of memory cells in a register file (eg, reference 760). Figure 3 In some cases, opening a row of memory cells, storing a row address, and updating the state of a memory group may be performed simultaneously or in a different order.

[0149] If an ACT command is not received in the control information, the memory device may perform the operations discussed at 765 .

[0150] At 765, the memory device may determine whether a PRE command was received in the control information. In some cases, the memory device may indicate that a PRE command was decoded (e.g., via a dedicated command line, such as a reference line) based on a command decoder at the memory device. Figure 4 The second command line 421) described determines that a PRE command is received.

[0151] If a PRE command is not received in the control information, the memory device may perform the operations discussed at 770 , 775 , and 785 .

[0152] At 770, after determining that a PRE command is received in the control information, the memory device may turn off a row of memory cells in the memory bank indicated by the address received in the control information.

[0153] After closing the row of memory cells, the memory device may update the state of the memory bank indicated by the address being closed in the register file at 775. In some cases, closing the row of memory cells and updating the state of the memory bank may be performed simultaneously or in a different order.

[0154] If a PRE command is not received in the control information, the memory device may perform the operations discussed at 780 and 785 .

[0155] At 780, the memory device may determine that a command other than an action ACT or PRE command is included in the error-free control information, such as a WR command, an RD command, etc. Therefore, the memory device may execute the received command.

[0156] At 785, the memory device may reset the lock timer associated with the received error-free command to prevent the memory device from prematurely shutting down the memory bank when an error is detected in subsequently received control information, such as with reference to Figure 6 For example, if the memory device receives an ACT command, the memory device may reset and trigger the start of operation of the RAS lock timer so that the memory device will not enter the locked state before the RAS lock timer expires. The memory device may similarly reset and trigger the WR lock timer, the RD lock timer, or any other lock timer based on receiving a corresponding command in the control information.

[0157] Figure 8 An exemplary process flow for reporting control information errors as disclosed herein is described. Process flow 800 may be performed by a host device 805 and a memory device 810, which may be a host device 805 and a memory device 810 as described herein. Figures 1-4 Examples of the host device 105 or 305 and memory device 110, 200, 310, or 400 described herein. In some examples, the memory device 810 can report to the host device 805 when an error occurs at the memory device 810 and information (e.g., received control signals) that enables the host device 805 to diagnose what caused the error. In some examples, the memory device 810 can also report the state of the memory array before / when the error occurred, so that the host device 805 returns the memory array to the reported state after diagnosing the error.

[0158] At 815, host device 805 may transmit control signaling to memory device 810 and memory device 810. The control signaling may include control information for operating a memory array at memory device 810, wherein the control information may include commands and / or memory addresses. In some cases, the control information may also include error detection / correction information (e.g., parity and / or cyclic redundancy check (CRC) bits) that enables a receiving device to detect and / or repair errors in the received control information. In some cases, before transmitting the control signaling, host device 805 may determine the control information for operating a memory array at memory device 810. For example, host device 805 may generate control information for memory device 810 in response to receiving a request from a user application to access information stored in memory.

[0159] The memory device 810 may receive and process control signaling from the host device 805. In some cases, the memory device 810 may decode control information embedded in the received control signaling to identify a command and / or a memory address. The memory device 810 may then execute the identified command at the identified memory address of the memory array at the memory device 810, for example, the memory device may read a memory page starting at the identified memory address. The memory device 810 may also perform error detection on the control information using the error detection information and determine whether the received control signal is damaged (e.g., during transmission or reception). In some cases, if an error is detected, the memory device 810 may refrain from executing the identified command and may indicate to the host device that an error was received.

[0160] At 820, the memory device 810 may process the control information embedded in the control signaling. Processing the control information may include storing the received memory address (e.g., row or column address) in a register file. Processing the control information may also include storing the state of the memory bank in the memory array at the memory device 810. For example, the memory device 810 may receive control information including an ACT command and a row address identifying one or more memory cells in the memory bank. In some cases, the row address may correspond to a memory page. After successfully decoding the control information, the memory device 810 may execute the ACT command on the one or more memory cells, causing the one or more memory cells to pass to the corresponding digital line (e.g., by activating the corresponding word line). In addition, the memory device 810 may store the row address in the register file and may also set a flag indicating that the memory bank including the one or more memory cells is turned on. The memory device 810 may repeat this processing procedure for subsequent commands and memory addresses received. In some examples, the memory device 810 stores recently accessed memory addresses in memory groups and sets a flag for each memory group in the memory array that indicates the state of the memory group (eg, on or off).

[0161] In some cases, the memory device 810 stores only the row address in the register file. In some cases, when the corresponding ACT command is received, the memory device 810 stores only the row address in the register file. In some examples, the memory device 810 may update the state of the memory group after receiving the PRE command for the memory group, for example, a flag indicating that the memory group is closed may be set. By storing the latest memory address accessed in the memory group and the current state of the memory group, the memory device 810 continuously monitors the state of the memory array, for example, it can always know which memory pages in which memory groups are opened and closed.

[0162] At 825, the host device 805 may transmit control signaling to the memory device 810. The control signaling may include commands, memory addresses, and / or error detection / correction information. In some cases, the control signal including the command, memory address, and error detection / correction information may be damaged before or during the transmission (e.g., due to interference, transmission errors, timing errors, or signal lane errors, or any combination thereof). The memory device 810 may receive and process the control signaling from the host device 805. In some cases, the memory device 810 receives the control signal incorrectly or receives a damaged control signal.

[0163] At 830, after incorrectly receiving the control signal or receiving a damaged control signal, the memory device may decode the control information within the control signal and may check whether the control information has errors. To check whether the control information has errors, the memory device 810 may use one or more error detection techniques. For example, the memory device 810 may use CRC bits included in the control information, such as by calculating a checksum from the command and memory address bits and comparing the calculated checksum to the CRC bits, to determine whether the command and / or memory address was received correctly. In another example, the memory device 810 may check the parity bits included in the control information to determine whether the command and / or memory address was received correctly, such as by determining whether the command and / or memory address has an even parity or an odd parity and comparing the determined parity to the received parity bits.

[0164] In some cases, memory device 810 detects errors in received control information of a control signal based on performing error detection. In some examples, an error detection component within memory device 810 can generate an output (e.g., a high output voltage) based on detecting an error. The error detection component can also signal the output to one or more other components within memory device 810.

[0165] At 835, after detecting an error in the control information contained in the received control signal (which may also be referred to as a "corrupted" or "failed" control signal), the memory device 810 may store the received control signal, or a version of the received control signal, in an instruction register at the memory device 810. In some examples, the memory device 810 may store a copy of all received control signals (e.g., commands, addresses, and error detection / correction information) in the instruction register. In other examples, the memory device 810 may store a portion of the received control signal (e.g., the command and memory portion or only the command portion) in the instruction register. In some cases, the memory device 810 stores the received control signal in the instruction register based on receiving an output signal from the error detection component indicating that an error was detected in the control signal. By storing the corrupted control signal, the memory device 810 can save a copy of the received control signal that can be requested by the host device 805 and used by it to diagnose what caused the control signal to fail (e.g., interference, transmission error, reception error, timing error, and / or signal lane error). Memory device 810 may also refrain from executing commands received in the failed control signal based on detecting an error in the control information.

[0166] At 840, the memory device 810 may transmit an indication to the host device 805 that an error was identified when decoding the control information. In some cases, the indication does not identify an error that has occurred, but instead identifies that an error did occur at the memory device 810. In some cases, the memory device 810 transmits the indication on a dedicated pin at the memory device 810, and the host device receives the indication on the dedicated pin. In another example, the memory device transmits the indication on a pin used for other functions at the memory device 810, such as a data or control pin. When using data or control pins, the memory device 810 may transmit a specific pattern on the pins (e.g., by applying a specific voltage to one or more of the pins), and the host device 805 may determine that an error has occurred at the memory device 810 based on receiving and identifying the specific pattern. In another example, the memory device 810 may transmit the indication by transmitting a pattern sequence (e.g., a series of continuous high and / or low voltages) on one or more pins, and the host device 805 may determine that an error has occurred at the memory device 810 based on receiving and identifying the pattern sequence.

[0167] At 845 , after identifying that an error has occurred at the memory device 810 , the host device 805 requests the damaged control signals stored at the memory device 810 and / or the status of the memory banks at the memory device 810 .

[0168] At 850, the memory device 810 may transmit the damaged control signal or a version of the damaged control signal (e.g., a copy or portion of the received control signal) to the host device 805. In some cases, after detecting the error, the memory device 810 transmits all or a portion of the damaged control signal back to the host device 805, e.g., by rerouting the received signal to a transmitter at the memory device 810, without storing the damaged control signal and without receiving a request from the host device 805. For example, the memory device 810 may transmit the damaged control signal back to the host device 805 in response to the indication of the error transmitted at 840. In other cases, the memory device 810 transmits the damaged control signal stored at the memory device 810 after receiving a request from the host device 805 to read the damaged control signal stored at the memory device 810. The host device 805 may use the copy (e.g., a partial or complete copy) of the damaged control signal received from the memory device 810 to diagnose what originally caused the error in the damaged control signal.

[0169] In some cases, memory device 810 may transmit the corrupted control signal over the data transmission line to host device 805. In some cases, memory device 810 may transmit the corrupted control signal using a more reliable / robust transmission scheme than used to transmit data to host device 805. For example, memory device 810 may transmit the corrupted control signal using a lower order modulation scheme (e.g., PAM2) or at a lower data rate.

[0170] At 855, the memory device 810 may transmit the memory group information to the host device 805. Similar to the above, the memory device 810 may transmit the memory group information with or without receiving a request from the host device 805. In some cases, the memory device 810 transmits the memory group information to the host device 805 in response to the error indication at 840. In other cases, the memory device 810 transmits the memory group information to the host device 805 after receiving a request for the memory group information from the host device 805 at 845. The host device 805 may use the memory group information to determine a state of the memory array at the memory device 810 before or when an error in the control information is identified at the memory device 810.

[0171] At 860, the memory device 810 may enter a locked state based on detecting an error in the control information. In some cases, the memory device 810 may enter a locked state based on receiving a signal from an error detection component within the memory device 810. While in the locked state, the memory device 810 may restrict access to the memory array. For example, the memory device 810 may refrain from executing a fail command and any subsequent commands received at the memory device 810. The memory device 810 may also shut down one or more (e.g., all) memory banks in the memory array. The memory device 810 may also precharge one or more (e.g., all) memory banks in the memory array. The memory device 810 may also perform a self-refresh operation on the shut down memory banks in the memory array.

[0172] In some cases, the memory device 810 may wait to enter a locked state. For example, the memory device 810 may wait for a valid memory operation performed on the memory array to complete before entering a partially or fully locked state, for example, the memory device 810 may wait for a read or write operation to complete before entering a locked state. In some cases, when the memory device 810 waits to enter a locked state, the memory device 810 includes one or more lock timers, for example, the memory device 810 may include a first lock timer for an ACT operation ("RAS lock timer"), a second lock timer for an RD operation ("RD lock timer"), and / or a third lock timer for a WR operation ("WR lock timer"). The memory device 810 may start a RAS lock timer when an ACT command is received. In some cases, the RAS lock timer is a countdown timer and counts down from a value associated with the time between executing an ACT command and a corresponding PRE command. After the RAS lock timer reaches zero, the memory device 810 may, for example, generate an output indicating that the ACT to PRE timing has expired based on the RAS lock timer, so that the memory device 810 can enter a locked state. After the RAS lock timer reaches zero, the value of the RAS lock timer can be reset to the starting value and all memory banks in the memory array can be precharged.In some cases, an analog timer can be configured to lock one or more of the timers.

[0173] The memory device 810 may similarly start RD and WR timers upon receiving an RD or WR command, wherein the RD lock timer may count down from a value associated with the time between executing the RD command and the corresponding PRE command, and the WR lock timer may count down from a value associated with the time between executing the WR command and the corresponding PRE command. In some cases, multiple RAS, RD, and WR lock timers will be activated simultaneously, and the memory device 810 will not enter the locked state until all active lock timers reach zero.

[0174] At 865, the host device 805 may diagnose the cause of the error in the control information that the memory device 810 did not successfully receive. As described herein above, the host device 805 may diagnose the cause of the error using the damaged control signal received at 850 (which may be a copy of all or a portion of the actual damaged control signal received at the memory device 810). For example, the host device 805 may compare the damaged control signal received from the memory device 810 with the control signal actually provided to the transmitter at the host device 805. The host device 805 may then identify a transmission error, a timing error, a signal lane error, a reception error, or any combination thereof. The transmission error may occur due to interference within the host device 805. The timing error may occur when the timing of the transmitter at the host device 805 and the receiver at the memory device 810 loses synchronization. The signal lane error may occur when there is a defect in the transmission line. The reception error may occur due to interference within the memory device 810. In some cases, diagnosing the error may include retransmitting the original control information to determine whether the same error is caused, such as to rule out errors caused by interference.

[0175] At 870, the host device 805 may determine the state of the memory array at the memory device 810 before or at the time of identifying the error in the control information. As described herein above, the host device may identify the state of the memory array using the memory bank information received at 855. For example, the host device 805 may receive the last memory address (e.g., row address) accessed in each memory bank of the memory array, and receive the state of each memory bank (e.g., whether the memory bank was open or closed before or at the time of the error). The host device 805 may use this information to restore the state of the memory array to the state identified before / at the time of the error. That is, the host device 805 may use this information to determine which memory pages in which memory banks are open and closed when the error is identified, and may direct the memory device 810 to open the memory pages that were open before / at the time of the error and close the memory pages that were closed before / at the time of the error. In some cases, the host device 805 determines the state of the memory array when a fail command is received at the memory device 810. In other cases, the host device 805 determines the state of the memory array when a fail command is detected at the memory device 810.

[0176] At 875, after the cause of the error has been diagnosed or otherwise resolved, the host device 805 may transmit an unlock command to the memory device 810. In some cases, the unlock command includes information to return the memory array at the memory device 810 to a previous state. In some cases, the unlock command is followed by additional commands to return the memory array to a previous state. The memory device 810 may receive the unlock command and / or the additional recovery command and may exit the locked state.

[0177] At 880, the memory device 810 may exit the locked state, for example, based on receiving an unlock command from the host device 805. Exiting the locked state may include returning a memory bank of the memory to an open or closed state identified before / at the time of detecting the error in the control information. After exiting the locked state, the memory device 810 may resume processing and execution of commands received from the host device 805.

[0178] At 885, host device 805 may modify transmit parameters based on diagnosing the cause of the error in the transmitted control information. Modifying the transmit parameters may include optimizing transmit timing, using a different modulation scheme, using a different coding scheme, reducing the data rate, or any combination thereof. In some cases, host device 805 may also modify receive parameters of memory device 810, such as receive timing.

[0179] At 890, host device 805 may resume transmitting control signaling to memory device 810 in accordance with the modified transmission parameters. In some cases, host device 805 may resend the failed control information in accordance with the modified transmission parameters. Memory device 810 may receive control signaling in accordance with the modified transmission parameters and / or modified reception parameters and may execute the successfully received commands.

[0180] It should be noted that the operations performed by the host device 805 and the memory device 810 discussed above may be omitted, combined, or rearranged. To name a few examples, the memory device 810 may enter a locked state before transmitting an error indication. The memory device 810 may store a damaged control signal after indicating that an error has occurred. Or the memory device 810 may transmit an error indication, a damaged control signal, and / or memory bank information in a single transmission. Other variations are possible without loss of operation.

[0181] Figure 9 A block diagram representing aspects of a controller at a memory device that supports reporting control information errors as disclosed herein is illustrated.

[0182] The memory device controller 900 may be referenced Figure 1 and 2Depicted are examples of device memory controller 155, local memory controller 165-a, or local memory controller 260. Memory device controller 900 may include bias component 910, timing component 915, decoding component 920, error detection component 925, command execution component 930, and memory status component 935.

[0183] In some cases, decoding component 920 may be configured to receive control information for operating a memory array in a memory device. Error detection component 925 may be configured to detect errors in the control information ("corrupted control information"). Command execution component 930 may be configured to refrain from executing a command received in the control information based on the error detected by error detection component 925. Refraining from executing the command may include refraining from signaling the decoded command to the memory array.

[0184] The bias component 910 can be configured to apply a voltage throughout the memory device controller 900. The timing component 915 can be configured to provide a timing signal (or clock signal) to components within the memory device controller 900.

[0185] The memory state component 935 may be configured to cause the memory device to enter a state (a "locked state") that restricts access to a memory array in the memory device based on the error detected by the error detection component 925. Causing the memory device to enter the locked state may include signaling an error indicator to a component in the memory device (e.g., by transmitting a high voltage on an error signal path coupled to the component in the memory device). Causing the memory device to enter the locked state may include causing the decode component 920 to refrain from executing subsequent commands and causing the memory array to shut down one or more memory banks and enter a self-refresh mode. The bias component 910 in conjunction with the transmitter may be configured to cause the memory device to enter the locked state based on the memory state component 935, transmitting an indication that the error detection component 925 detected an error in the received control information.

[0186] The memory state component 935 may be further configured to monitor the state of the memory array during normal operation (e.g., before an error is detected in the received control information). After an error is detected, the memory state component 935 may be configured to identify the state of the memory array (the "original state"), and in conjunction with the bias component and transmitter, may be configured to transmit the identified memory array state to the host device. The memory state component 935 may be further configured to refrain from storing the memory address or state of the memory bank indicated in the damaged control information.

[0187] The bias component 910 in combination with the transmitter can be configured to transmit an indication by applying a voltage to a dedicated pin to indicate the detection of an error in the control information, by applying a voltage pattern to multiple pins to indicate the detection of an error in the control information, or by applying a voltage sequence with specific timing and duration to indicate the detection of an error in the control information.

[0188] The decoding component 920 may be further configured to receive one or more commands that restore the memory array to the original state. After decoding the command for restoring the memory array, the memory state component 935 may be configured to cause the memory device to exit the locked state, and the command execution component 930 may be configured to restore the memory array to the original state by executing the received one or more commands.

[0189] Decoding component 920 may be further configured to receive a request for the original state of the memory array and, in conjunction with command execution component 930 and biasing component 910, may be configured to transmit the original state of the memory array to the requesting device.

[0190] In some cases, the decoding component 920 may receive and successfully decode control information from the memory array before receiving the damaged control information. The memory state component 935 may be configured to store the memory address contained in the successfully decoded control information and set a flag indicating the state of the memory group contained in the successfully decoded control information. The command execution component 930 may be configured to execute the successfully decoded control information. After an error is detected in the damaged control information, the memory state component 935 in conjunction with the bias component 910 and the transmitter may be configured to transmit the memory address and the flag indicating the memory group of the successfully decoded control information to the host device.

[0191] After indicating the error to the host device, the decoding component 920 may be further configured to receive a command to exit the locked state (“unlock command”) from the host device, and the memory state component 935 may be configured to cause the memory device to exit the locked state based on the decoding component 920 receiving the unlock command.

[0192] In some cases, after detecting an error in received control information, the memory status component 935 waits for ongoing memory operations to complete before signaling an indication of the error detected in the control information to components in the memory device.

[0193] In some cases, the error detection component 925 in conjunction with the timing component 915 and other logic components can be configured to store all or a portion of the received control signal after an error is detected in the control information contained in the control signal. The error detection component 925 and the bias component 910 can be further configured to transmit all or a portion of the stored control signal to the host device, for example, in response to receiving a request from the host device. In some cases, the stored control signal is transmitted on the data channel using a lower data rate than the data is transmitted on the data channel, for example, to increase the reliability of the control signal transmission.

[0194] Figure 10 A block diagram representing aspects of a controller at a host device that supports reporting control information errors as disclosed herein is illustrated.

[0195] The host device controller 1000 may be used as a reference Figure 1 An example of an external memory controller 105 is depicted. The host device controller 1000 can include a bias component 1010, a timing component 1015, an encoding component 1020, an error diagnostic component 1025, and a memory status component 1030.

[0196] The bias component 1010 can be configured to apply a voltage throughout the host device controller 1000. The timing component 1015 can be configured to provide a timing signal (or clock signal) to components within the host device controller 1000.

[0197] The encoding component 1020 may be configured to determine and encode control information for operating a memory array of a memory device. The encoding component 1020 in combination with the bias component 1010 may be configured to transmit a control signal including the control information to a host device. The error diagnostic component 1025 may be configured to receive from the memory device an indication that a damaged version of the transmitted control signal was received at the memory device. The error diagnostic component 1025 may be further configured to receive a state of the memory array before the damaged version of the control signal was received at the memory device ("original state"). The memory state component 1030 in combination with the bias component 1010 may be configured to transmit one or more commands for restoring the original state of the memory array based on receiving the original state of the memory array.

[0198] The error diagnostic component 1025 can be further configured to receive at least a portion of the corrupted version of the control signal from the memory device. The error diagnostic component 1025 can compare the control signal transmitted to the memory device with the corrupted version of the control signal and identify an error (e.g., a transmission, reception, interference, signal lane, or decoding error) that caused the corrupted version of the control signal. The error diagnostic component 1025 in conjunction with the bias component 1010 and the transmitter can be configured to transmit a command to the memory device that directs the memory device to exit the locked state based on the diagnostic error.

[0199] The bias component 1010 can be configured to modify parameters for transmitting control signaling to the memory device based on the error being identified by the error diagnostic component 1025. The bias component 1010 can be further configured to perform subsequent control signaling using the modified transmission parameters.

[0200] In some cases, the memory state component 1030 may be configured to transmit a request for the original state of the memory array to the memory device. For each memory bank in the memory array, the most recently accessed memory cell row and the state of the memory bank (e.g., open or closed) may be received. In some examples, the memory state component 1030 receives a row address in the memory bank and a flag indicating that the memory bank is open from the memory device. The memory state component 1030 may be further configured to determine the original state of the memory array based on the memory state information received from the memory device, and when restoring the original state of the memory array, the memory state component 1030 may transmit a command to the memory device to open the memory cell row corresponding to the row address in the memory bank.

[0201] Figure 11 Flowchart illustrating one or more methods for reporting control information errors as disclosed herein. Method 1100 may illustrate aspects of a memory device entering a locked state after identifying an error in received control information and indicating, by the memory device, to a host device that an error was identified in the received control information.

[0202] At block 1105, the method may include receiving control information for operating a memory array from a host device, the control information including a first command, such as reference Figures 1 to 8 In some examples, the operation of block 1105 may be performed by reference to Figure 1 , 2 , 3 and 9 are performed or facilitated by the memory controller described.

[0203] At block 1110, the method may include detecting an error in the control information, such as reference Figures 1 to 8 In some examples, the operations of block 1110 may be performed by reference to Figure 1 ,2 , 3 and 9 are performed or facilitated by the memory controller described.

[0204] At block 1115, the method may include refraining from executing the first command based at least in part on detecting the error, as described in reference to Figures 1 to 8 In some examples, the operation of block 1115 may be performed by reference to Figure 1 , 2 , 3 and 9 are performed or facilitated by the memory controller described.

[0205] At block 1120, the method may include entering a state that restricts access to the memory array based at least in part on detecting an error, as described with reference to Figures 1 to 8 In some examples, the operations of block 1120 may be performed by reference to Figure 1 , 2 , 3 and 9 are performed or facilitated by the memory controller described.

[0206] At block 1125, the method may include transmitting to the host device a first indication that an error was detected in the control information based at least in part on entering a state that restricts access to the memory array, as described with reference to Figures 1 to 8 In some examples, the operation of block 1125 may be performed by reference to Figure 1 , 2 , 3 and 9 are performed or facilitated by the memory controller described.

[0207] In some examples, an apparatus as described herein may perform one or more methods, such as method 1100. The apparatus may include features, means, or instructions (e.g., instructions executable by a processor stored by a non-transitory computer-readable medium) for: receiving control information for operating a memory array from a host device, the control information including a first command; detecting an error in the control information; refraining from executing the first command based at least in part on detecting the error; entering a state that restricts access to the memory array based at least in part on detecting the error; and transmitting a first indication of the detection of the error in the control information to the host device based at least in part on entering the state that restricts access to the memory array.

[0208] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: monitoring the memory array prior to detecting the error; identifying a first state of the memory array based at least in part on detecting the error in the control information; and transmitting the first state of the memory array to the host device based at least in part on identifying the first state of the memory array.

[0209] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: receiving one or more commands from the host device to restore the memory array based at least in part on transmitting the first state of the memory array to the host device; exiting the state that restricts access to the memory array based at least in part on the one or more commands; and restoring the memory array to the first state based at least in part on the one or more commands.

[0210] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for receiving a request for the first state of the memory array from the host device based at least in part on transmitting the first indication, wherein the first state of the memory array is transmitted to the host device based at least in part on receiving the request.

[0211] Some examples of the methods, apparatuses, and non-transitory computer-readable media described herein may additionally include operations, features, devices, or instructions for: receiving, prior to receiving the control information, second control information for operating the memory array from the host device, wherein the second control information includes a second command and a second memory address indicating a second memory bank; successfully decoding the second control information; and executing the second command based at least in part on successfully decoding the second control information. In some examples of the methods, apparatuses, and non-transitory computer-readable media described herein, monitoring the state of the memory array includes storing the second memory address based at least in part on successfully decoding the second control information; and setting a second flag based at least in part on successfully decoding the second control information, wherein the second flag indicates that the second memory bank is turned on.

[0212] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, transmitting the first state of the memory array includes transmitting the second memory address and the second flag to the host device based at least in part on detecting the error in the control information.

[0213] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, the control information includes a first memory address of an identified first memory group, and monitoring the state of the memory array includes refraining from storing the first memory address or setting a first flag indicating a state of the first memory group based at least in part on detecting the error in the control information.

[0214] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: receiving from the host device a second command to exit the state in which access to the memory array is restricted; and exiting the state in which access to the memory array is restricted based at least in part on successfully decoding the second command.

[0215] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, entering the state in which access to the memory array is restricted includes refraining from executing subsequent commands; shutting down one or more memory banks at the memory array; or performing one or more self-refresh operations on the one or more memory banks; or any combination thereof.

[0216] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: based at least in part on detecting the error in the control information, waiting for a memory operation to complete; and after the memory operation is completed, signaling a second indication that the error was detected in the control information, wherein the state of restricting access to the memory array is entered after the memory operation is completed. In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, the memory operation includes activating a first plurality of memory cells of the memory array, reading a second plurality of memory cells, or writing a third plurality of memory cells, or any combination thereof.

[0217] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, the control information is received in a control signal, and the methods, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: storing at least a portion of the control signal based at least in part on detecting the error in the control information; and transmitting at least the portion of the control signal to the host device based at least in part on entering the state that restricts access to the memory array.

[0218] Some examples of methods, apparatuses, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: receiving a request for at least the portion of the control signal from the host device based at least in part on transmitting the first indication that the error was detected in the control information; and transmitting at least the portion of the control signal to the host device based at least in part on receiving the request. In some examples of methods, apparatuses, and non-transitory computer-readable media described herein, at least the portion of the control signal is transmitted at a data rate that is lower than a data rate used to transmit data to the host device.

[0219] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, transmitting the first indication of detecting the error includes applying a voltage to a pin for indicating error detection in control information; applying multiple voltages to multiple pins for transmitting data to the host device, wherein the multiple voltages are applied to the multiple pins according to a pattern indicating the error detection in control information; or transmitting a pattern sequence to the host device on at least one of the multiple pins.

[0220] Figure 12 A flow chart illustrating one or more methods for reporting control information errors as disclosed herein. The method 1200 may illustrate aspects of restoring, by a host device, a current state of a memory array to a previous state identified before an error was identified in control information received at the memory device, and determining, by the host device, a cause of an error identified in a control information transmission.

[0221] At block 1205, the method may include determining, by a host device, control information for operating a memory array of a memory device, such as reference Figures 1 to 8 In some examples, the operations of block 1205 may be performed by reference to Figure 1 , 2 , 3 and 10 are performed or facilitated by the memory controller described.

[0222] At block 1210, the method may include transmitting a control signal including the control information to the memory device, as described with reference to Figures 1 to 8 In some examples, the operations of block 1210 may be performed by reference to Figure 1 , 2 , 3 and 10 are performed or facilitated by the memory controller described.

[0223] At block 1215, the method may include receiving from a memory device an indication that a corrupted version of a control signal was received at the memory device and a state of the memory array before the corrupted version of the control signal was received at the memory device, as described with reference to Figures 1 to 8 In some examples, the operation of block 1215 may be performed by reference to Figure 1 , 2 , 3 and 10 are performed or facilitated by the memory controller described.

[0224] At block 1220, the method may include transmitting one or more commands for restoring the state of the memory array based at least in part on receiving the state of the memory array, as described with reference to FIG. Figures 1 to 8 In some examples, the operations of block 1220 may be performed by reference to Figure 1 , 2 , 3 and 10 are performed or facilitated by the memory controller described.

[0225] In some examples, an apparatus as described herein may perform one or more methods, such as method 1200. The apparatus may include features, means, or instructions (e.g., instructions executable by a processor stored by a non-transitory computer-readable medium) for: determining, by a host device, control information for operating a memory array of a memory device; transmitting a control signal including the control information to the memory device; receiving from the memory device an indication that a corrupted version of the control signal was received at the memory device and a state of the memory array before the corrupted version of the control signal was received at the memory device; and transmitting one or more commands for restoring the state of the memory array based at least in part on receiving the state of the memory array.

[0226] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: receiving at least a portion of the corrupted version of the control signal from the memory device; comparing the control signal transmitted to the memory device with at least the portion of the corrupted version of the control signal received from the memory device; identifying an error that caused the corrupted version of the control signal based at least in part on the comparison, wherein identifying the error includes identifying a transmission error, a timing error, a signal lane error, or any combination thereof; and transmitting a command to the memory device to exit a state that restricts access to the memory device based at least in part on identifying the error.

[0227] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: modifying parameters for transmitting control signaling to the memory device based at least in part on identifying the error; and transmitting a second signal including the control information to the memory device based on the modified parameters for transmitting the control signaling.

[0228] In some examples of methods, apparatuses, and non-transitory computer-readable media described herein, the control information includes a first command and a first memory address indicating a first memory bank. Some examples of methods, apparatuses, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: transmitting a request for the state of the memory array prior to receiving the damaged version of the control signal to the memory device based at least in part on receiving the indication that the damaged version of the control signal was received at the memory device. In some examples of methods, apparatuses, and non-transitory computer-readable media described herein, receiving the state of the memory array includes receiving from the memory device a second memory address identifying a plurality of memory cells in a second memory bank and a flag indicating that the second memory bank was on prior to receiving the damaged version of the control signal.

[0229] Some examples of methods, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for determining, based at least in part on the second memory address and the flag, the state of the memory array when the damaged version of the control signal is received. In some examples of methods, apparatus, and non-transitory computer-readable media described herein, transmitting the one or more commands for restoring the state of the memory array includes transmitting a second command to the memory device to turn on the plurality of memory cells in the second memory group based at least in part on the second memory address and the flag.

[0230] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more of the methods described may be combined.

[0231] In some examples, an apparatus or device may perform aspects of the functionality described herein using general or special purpose hardware. For example, the apparatus or device may include a memory array including a plurality of memory banks; a receiver coupled to the memory array and configured to receive control signaling including control information for accessing the memory array; a circuit coupled to the receiver and configured to detect an error in the control information and signal an indication of the detected error, wherein the memory array is configured to enter an access restricted state based at least in part on an output of the circuit; a first register coupled to the circuit and configured to store a state of the memory array based at least in part on the output of the circuit; and a transmitter coupled to the first register and configured to transmit the contents of the first register and an indication of an error detected in the control information corresponding to the contents of the first register to a host device.

[0232] In some examples, the apparatus or device includes a component configured to cause the memory array to enter the access restricted state based at least in part on the output of the circuit.

[0233] In some examples, the device or apparatus includes a decoder coupled to the receiver and the memory array, the decoder configured to decode received control information and signal the decoded control information to the memory array; a clock coupled to the first register and configured to provide a timing signal for the device; and a logic component configured to block an output of the clock based on the output of the circuit configured to detect an error, wherein an input of the logic component is coupled to the clock and the decoder, and an output of the logic component is coupled to the first register.

[0234] In some examples, the apparatus or device includes a decoder coupled to the receiver and the memory array, the decoder configured to decode received control information and signal the decoded control information to the memory array; a latch configured to store the output of the circuit configured to detect errors; a clock coupled to the latch and configured to provide a timing signal, wherein the latch is further configured to signal the output of the circuit based at least in part on the output of the clock; and a logic component configured to block the decoder output from the memory array based at least in part on the output of the latch.

[0235] In some examples, the apparatus or device includes a second register configured to store at least a portion of the first control signal of the control signaling based at least in part on the output of the circuit configured to detect an error in the control information.

[0236] In some examples, the apparatus or device includes a decoder coupled to the first register and the memory array, the decoder configured to decode received control information and signal the decoded control information to the memory array, wherein the first register is further configured to store a memory address or a state of a memory bank or both based at least in part on an output of the decoder.

[0237] In some examples, the apparatus or device includes a control line coupled to the receiver and configured to carry control signaling; a data line coupled to the transmitter and configured to carry contents of a first register; a plurality of pins coupled to the transmitter and the data line, the plurality of pins configured to signal data to an external device via the data lines; and a pin coupled to the transmitter and configured to signal an indication of a detected error in the control information to the external device.

[0238] In some examples, the apparatus or device includes a decoder coupled to the memory array and configured to decode control information based at least in part on receiving control signaling; a timer coupled to the decoder and configured to track the timing of memory commands successfully decoded by the decoder; and a logic component configured to block the decoder output to the memory array, wherein the logic component is configured to signal the output of the decoder based at least in part on the output of the timer.

[0239] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signaling as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have various bit widths.

[0240] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected or coupled) may be open circuits or closed circuits based on the operation of the device containing the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some cases, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0241] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals cannot currently be communicated between components through conductive paths, to a closed circuit relationship between components, in which signals can be communicated between components through conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0242] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. When a controller isolates two components, the controller implements the following change: a signal is prevented from flowing between the components using a conductive path that previously permitted the signal to flow.

[0243] The term "layer" as used herein refers to a layer or slice of a geometric structure. Each layer can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer can be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. A layer can contain different elements, components, and / or materials. In some cases, a layer can be composed of two or more sublayers. In some drawings, two dimensions in a three-dimensional layer are depicted for illustrative purposes. However, those skilled in the art will recognize that a layer is three-dimensional in nature.

[0244] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0245] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material such as a metal. The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0246] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0247] In the drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0248] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0249] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0250] The techniques described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function may be stored as one or more instructions or codes on a computer-readable medium or transmitted by a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination of these. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Also, as used herein, included in the claims, the "or" used in the list of items (e.g., a list of items starting with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0251] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media may be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory media that can be used to carry or store the desired program code device in the form of an instruction or data structure and can be accessed by a general or special-purpose computer or a general or special-purpose processor. And, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave is used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0252] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, which includes: receiving control information for operating a memory array from a host device, the control information including a first command; detecting an error in the control information; at least partially based on detecting the error, suppressing execution of the first command; at least partially based on detecting the error, restricting access to the memory array; and at least partially based on restricting access to the memory array, transmitting a first indication that the error has been detected in the control information to the host device.

2. The method according to claim 1, which further includes: monitoring the memory array before or when the error is detected; at least partially based on detecting the error in the control information, identifying a first state of the memory array; and at least partially based on identifying the first state of the memory array, transmitting the first state of the memory array to the host device.

3. The method according to claim 2, which further includes: at least partially based on transmitting the first state of the memory array to the host device, receiving one or more commands from the host device for restoring the memory array; at least partially based on the one or more commands, restoring access to the memory array; and at least partially based on the one or more commands, restoring the memory array to the first state.

4. The method according to claim 2, which further includes: at least partially based on transmitting the first indication, receiving a request for the first state of the memory array from the host device, wherein the first state of the memory array is transmitted to the host device at least partially based on receiving the request.

5. The method according to claim 2, which further includes: before receiving the control information, receiving second control information for operating the memory array from the host device, wherein the second control information includes a second command and a second memory address indicating a second memory bank; successfully decoding the second control information, wherein monitoring the first state of the memory array includes: at least partially based on successfully decoding the second control information, storing the second memory address; and at least partially based on successfully decoding the second control information, setting a second flag, wherein the second flag indicates that the second memory bank is enabled; and at least partially based on successfully decoding the second control information, executing the second command.

6. The method according to claim 5, wherein transmitting the first state of the memory array includes: at least partially based on detecting the error in the control information, transmitting the second memory address and the second flag to the host device.

7. The method according to claim 2, wherein the control information includes a first memory address of a first memory bank identified, wherein monitoring the first state of the memory array includes: At least partially based on detecting the error in the control information, inhibit storing the first memory address or set a first flag indicating the state of the first memory bank.

8. The method according to claim 1, further comprising: receiving, from the host device, a second command to resume access to the memory array; and at least partially based on successfully decoding the second command, resume the state of access to the memory array.

9. The method according to claim 1, wherein restricting access to the memory array comprises: inhibiting execution of subsequent commands; closing one or more memory banks at the memory array; or performing one or more self-refresh operations on the one or more memory banks; or any combination thereof.

10. The method according to claim 1, further comprising: at least partially based on detecting the error in the control information, wait for a memory operation to complete; and after the memory operation is completed, send a second indication that the error has been detected in the control information, wherein access to the memory array is restricted after the memory operation is completed.

11. The method according to claim 1, wherein receiving the control information comprises receiving the control information in a control signal, the method further comprising: at least partially based on detecting the error in the control information, store at least a portion of the control signal; and at least partially based on restricting access to the memory array, transmit at least the portion of the control signal to the host device.

12. The method according to claim 11, further comprising: at least partially based on transmitting the first indication that the error has been detected in the control information, receive a request for at least the portion of the control signal from the host device; and at least partially based on receiving the request, transmit at least the portion of the control signal to the host device.

13. The method according to claim 11, wherein at least the portion of the control signal is transmitted at a data rate lower than the data rate for transmitting data to the host device.

14. The method according to claim 1, wherein transmitting the first indication of detecting the error comprises: applying a voltage for indicating error detection in the control information to a pin; applying a plurality of voltages for transmitting data to the host device to a plurality of pins, wherein the plurality of voltages are applied to the plurality of pins according to a pattern indicating the error detection in the control information; or transmitting a pattern sequence to the host device on at least one of the plurality of pins.

15. The method according to claim 1, wherein restricting access to the memory array comprises: inhibiting execution of subsequent commands; closing one or more memory banks at the memory array; and performing one or more self-refresh operations on the one or more memory banks.

16. A method, which comprises: determining, by a host device, control information for operating a memory array of a memory device; transmitting a control signal including the control information to the memory device; Receive an indication of a corrupted version of the control signal received at the memory device and an indication of the state of the memory array, where the state of the memory array is prior to receiving the corrupted version of the control signal at the memory device and prior to access being restricted at the memory device; and At least partially based on receiving the state of the memory array, transmit one or more commands for restoring the state of the memory array.

17. The method according to claim 16, further comprising: Receive at least a portion of the corrupted version of the control signal from the memory device; Compare the control signal transmitted to the memory device with at least the portion of the corrupted version of the control signal received from the memory device; Identify an error causing the corrupted version of the control signal at least partially based on the comparison, where identifying the error includes identifying a transmission error, a timing error, a signal lane error, or any combination thereof; and At least partially based on identifying the error, transmit a command to restore the state of access to the memory device to the memory device.

18. The method according to claim 17, further comprising: Modify parameters for transmitting control signaling to the memory device at least partially based on identifying the error; and Transmit a second signal including the control information to the memory device according to the modified parameters for transmitting the control signaling.

19. The method according to claim 16, where the control information includes a first command and a first memory address indicating a first memory bank, the method further comprising: At least partially based on receiving the indication of the corrupted version of the control signal received at the memory device, transmit a request for the state of the memory array prior to or at the time of receiving the corrupted version of the control signal to the memory device, where receiving the state of the memory array includes: Receive from the memory device a second memory address identifying a plurality of memory cells in a second memory bank and a flag indicating that the second memory bank was open prior to receiving the corrupted version of the control signal.

20. The method according to claim 19, further comprising: Determine the state of the memory array when the corrupted version of the control signal was received at least partially based on the second memory address and the flag, where transmitting the one or more commands for restoring the state of the memory array includes: Transmit a second command to turn on the plurality of memory cells in the second memory bank to the memory device at least partially based on the second memory address and the flag.

21. An apparatus, which comprises: A memory array including a plurality of memory banks; A receiver coupled to the memory array and configured to receive control signaling including control information for accessing the memory array; A circuit, coupled to the receiver and configured to detect an error in the control information and signal an indication of the detected error, wherein the memory array is configured to restrict access to the memory array at least in part based on the output of the circuit; A first register, coupled to the circuit and configured to store a state of the memory array at least in part based on the output of the circuit; and A transmitter, coupled to the first register and configured to transmit the content of the first register and an indication of an error detected in the control information corresponding to the content of the first register to a host device.

22. The apparatus according to claim 21, further comprising: A component configured to cause the memory array to restrict access to the memory array at least in part based on the output of the circuit.

23. The apparatus according to claim 21, further comprising: A decoder, coupled to the receiver and the memory array, the decoder configured to decode received control information and signal the decoded control information to the memory array; A clock, coupled to the first register and configured to provide a timing signal for the apparatus; and A logic component configured to block an output of the clock based on the output of the circuit configured to detect an error, wherein an input of the logic component is coupled to the clock and the decoder, and an output of the logic component is coupled to the first register.

24. The apparatus according to claim 21, further comprising: A decoder, coupled to the receiver and the memory array, the decoder configured to decode received control information and signal the decoded control information to the memory array; A latch configured to store the output of the circuit configured to detect an error; A clock, coupled to the latch and configured to provide a timing signal, wherein the latch is further configured to signal the output of the circuit at least in part based on the output of the clock; and A logic component configured to block the decoder from outputting to the memory array at least in part based on the output of the latch.

25. The apparatus according to claim 21, further comprising: A second register configured to store at least a portion of a first control signal of the control signaling at least in part based on the output of the circuit configured to detect an error in the control information.

26. The apparatus according to claim 21, further comprising: A decoder, coupled to the first register and the memory array, the decoder configured to decode received control information and signal the decoded control information to the memory array, wherein the first register is further configured to store a memory address or a state of a memory bank or both at least in part based on the output of the decoder.

27. An apparatus, which comprises: A memory array; and A controller, coupled to the memory array, wherein the controller is operable to: Receive control information for operating the memory array from a host device, the control information including a first command; Detect an error in the control information; At least partially based on detecting the error, inhibit execution of the first command; At least partially based on detecting the error, restrict access to the memory array; and At least partially based on restricting access to the memory array, transmit a first indication that the error has been detected in the control information to the host device.

28. The apparatus of claim 27, wherein the controller is operable to: Receive a second command to resume access to the memory array; and At least partially based on successfully decoding the second command, resume access to the memory array.

29. The apparatus of claim 27, wherein to restrict access to the memory array, the controller is operable to: Inhibit execution of subsequent commands; Turn off one or more memory banks at the memory array; and Perform one or more self-refresh operations on the one or more memory banks at the memory array.

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