DC offset cancellation circuit for single frequency continuous wave radar with zero intermediate frequency receiver structure

Abstract

The invention discloses a DC offset cancellation circuit of a single-frequency continuous wave radar with a zero intermediate frequency receiver structure, comprising a mixer intermediate frequency port, an adjustable DC offset circuit, a differential amplifier, an anti-aliasing filter and an analog-to-digital converter; the mixer intermediate frequency port is used to access a first voltage source voltage divider circuit signal and output it to the differential amplifier; the adjustable DC offset circuit is used to access a second voltage source voltage divider circuit signal and suppress power supply voltage ripple and system noise, and output it to the differential amplifier; the output to the differential amplifier is used to perform DC offset cancellation on two voltage source voltage divider circuit signals, and output them to the anti-aliasing filter; the anti-aliasing filter is used to filter out signals outside a frequency band of interest, retain part of the useful DC offset, and output it to the analog-to-digital converter; the analog-to-digital converter is used to convert analog signals into digital electrical signals and output them.

Description

Technical Field

[0001] The invention belongs to the technical field of single-frequency continuous wave Doppler radar, and in particular relates to a DC offset cancellation circuit of a single-frequency continuous wave radar with a zero intermediate frequency receiver structure. Background Art

[0002] The zero intermediate frequency receiver has the advantage of simple structure and greatly reduces the local oscillator phase noise due to distance correlation. However, the self-mixing of the zero intermediate frequency receiver will generate DC offset interference. The local oscillator leakage self-mixing is caused by the hardware defects of the component. The leaked local oscillator signal passes through the low noise amplifier or the RF bandpass filter or the receiving antenna end and the local oscillator signal, which will introduce a large DC offset in the baseband signal at the intermediate frequency port. Moreover, radar targets that do not move relative to the radar receiver are considered to be clutter noise, which will also cause local oscillator leakage in the system. In addition, interference self-mixing is another cause of DC offset interference. Because the isolation performance of each port of the mixer is not good, the strong interference signal entering the low noise amplifier leaks to the local oscillator port, which will self-mix with the strong interference signal passing through the RF port, thereby generating a large DC offset. In summary, there are two sources of DC offset: hardware and environment. The hardware DC offset is independent of the environment and will not change after the system is assembled. The environmental DC offset is caused by radar clutter. Any movement will change the radar environment, and the environmental DC offset will change accordingly. These DC signals will be superimposed on the baseband signal and interfere with the baseband signal, which is called DC offset. The DC offset is usually larger than the noise of the RF front end, and the signal-to-noise ratio deteriorates. At the same time, excessive DC offset can saturate the amplifier behind the mixer, and fail to amplify useful signals, or even burn the chip. The DC component of the single-frequency Doppler radar signal of the zero-IF receiver will continue to change with the change of the radar detection space and target. When the target is at different positions or distances, the system will produce different DC offsets. This part of the useful DC offset is necessary for accurate phase demodulation. The DC offset compensation circuit of the single-frequency continuous wave radar removes useless DC offsets and retains useful DC offsets.

[0003] Therefore, how to perform DC offset compensation in zero-IF receiver radar is crucial. Alexander M. Vergara of the University of Hawaii at Manoa proposed a digitally controlled voltage feedback circuit design that uses a digital-to-analog converter (DAC) to provide a compensation signal for the DC component when used for differential amplification with the input baseband. Estimate and eliminate the total DC offset of the radar IQ two-way to avoid amplifier saturation. The system requires a digital acquisition system (DAQ) to amplify small time-varying signals, a 16-bit DAC and DSP digital acquisition system, which pays a high hardware cost. Byung-Kwon Park of the University of Hawaii at Manoa proposed a circuit design for two-stage DC offset. The first stage includes a 16-bit analog-to-digital converter (ADC1) and a 16-bit digital-to-analog converter (DAC). This stage obtains an estimated value of the DC offset and provides a reference level for the second stage. The second stage removes the DC offset through differential amplification and sends the remaining time-varying signal to a second 16-bit ADC (ADC2) for quantization. This system avoids the problem of DC offset causing saturation of baseband amplifiers and analog-to-digital converters, but each radar IQ channel requires two baseband amplifiers, two 16-bit ADCs and one 16-bit DAC, a comparator, and a DC controller. The system is complex and has a high hardware cost. Zhejiang University (patent number, CN 110133642 A) proposed a DC offset compensation method for radar sensors. This method only targets the signal processing field of DC offset. This method cannot avoid the hardware problem of excessive DC offset causing saturation of baseband amplifiers and analog-to-digital converters.

[0004] The radar's zero intermediate frequency receiver mixes the echo signal with the carrier signal of the same frequency and converts the signal directly to the baseband. The conversion process does not pass through the intermediate frequency, the system structure is simple, and there is no image frequency interference. However, due to system hardware problems, there will be "local oscillator leakage" and "interference self-mixing", which will inevitably cause DC offset problems. Excessive DC offset will cause the baseband amplifier or analog-to-digital converter to saturate, and cannot amplify useful signals, and may even burn the chip. Summary of the invention

[0005] In view of this, the main purpose of the present invention is to provide a DC offset cancellation circuit for a single-frequency continuous wave radar with a zero intermediate frequency receiver structure.

[0006] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0007] An embodiment of the present invention provides a DC offset cancellation circuit for a single-frequency continuous wave radar with a zero intermediate frequency receiver structure, comprising an intermediate frequency port of a mixer, an adjustable DC offset circuit, a differential amplifier, an anti-aliasing filter and an analog-to-digital converter;

[0008] The mixer intermediate frequency port is used to access the first voltage source voltage divider circuit signal and output it to the differential amplifier;

[0009] The adjustable DC offset circuit is used to access the signal of the second voltage source voltage divider circuit and suppress the power supply voltage ripple and system noise, and output it to the differential amplifier;

[0010] The output is sent to a differential amplifier for performing DC offset on the signals of the two voltage source voltage divider circuits, and is output to an anti-aliasing filter;

[0011] The anti-aliasing filter is used to filter out signals outside the frequency band of interest, retain part of the useful DC offset, and output it to the analog-to-digital converter;

[0012] The analog-to-digital converter is used to convert analog signals into digital electrical signals and output them.

[0013] In the above scheme, the adjustable DC offset circuit includes a comparator, a 42nd resistor R42, a 46th point group R46, a 47th resistor R47, a 48th resistor R48, a 50th resistor R50, and a 51st resistor R51. The 6th terminal of the comparator is connected to OP_+5V through the 46th resistor R46 after passing through the 47th resistor R47, and is connected to the analog ground AGND through the 50th resistor R50. The 5th terminal is connected to the analog ground AGND through the 51st resistor R51, the 4th terminal is connected to OP_-5V, the 7th terminal is output through the 48th resistor R48, and the 8th terminal is connected to OP_+5V. The 6th terminal and the 7th terminal of the comparator are connected to the 42nd resistor R42, and one side of the 48th resistor R48 is also connected to the third interface J3.

[0014] In the above scheme, the adjustable DC offset circuit filters the input power VCC_IN of the linear power supply LT3045 circuit through a π-type filter circuit, and suppresses power supply voltage ripple and system noise through the linear power supply LT3045 circuit network.

[0015] In the above scheme, the π-type filter circuit includes a forty-seventh polarity capacitor C47, a fourth inductor L4, and a fiftieth capacitor C50. The positive end of the forty-seventh polarity capacitor C47 is connected to the input power supply VCC_IN, and the negative end is connected to the power ground GND. One end of the fourth inductor L4 is connected to the input power supply VCC_IN, and the other end is respectively connected to the fiftieth capacitor C50 and the output power supply T_+5V. The other end of the fiftieth capacitor C50 is connected to the power ground GND.

[0016] In the above scheme, the linear power supply LT3045 circuit includes an LT3045 chip, a twenty-fifth polarity capacitor C25, a twenty-seventh capacitor C27, a twenty-eighth capacitor C28, a thirty-second capacitor C32, a thirty-third capacitor C33, a fortieth capacitor C40, a thirty-second resistor R32, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-eighth resistor R38, a thirty-ninth resistor R39, and a fortieth resistor R40. The first terminal of the LT3045 chip is connected to the output power supply T_+5V in the π-type filter circuit through the thirty-second resistor R32, the second, third, and fourth terminals are connected to the first terminal in common, and the fifth terminal is connected to the first terminal through the thirty-third resistor R33. The LT3045 The 25th polarity capacitor C25, the 27th capacitor C27, and the 28th capacitor C28 are connected in parallel between the 1st end of the chip and the 32nd resistor R32, and the 25th polarity capacitor C25, the 27th capacitor C27, and the 28th capacitor C28 are grounded in common, the 9th end is grounded, the 6th end is connected to the 9th end via the 40th resistor R40, the 40th capacitor C40 and the 38th resistor R38 are connected in parallel between the 8th end and the 9th end in sequence, the 39th resistor R39 is connected in parallel between the 7th end and the 9th end, the 12th end outputs the output power supply OP_+5V to the adjustable DC offset circuit, the 34th resistor R34 is connected in parallel between the 7th end and the 12th end, and the 32nd capacitor C32 and the 33rd capacitor C33 are connected in parallel between the 12th end and the 9th end in sequence.

[0017] Compared with the prior art, the present invention does not require complex hardware system design, but can eliminate useless DC offsets caused by hardware and environment, suppress power supply voltage ripple, and mainly avoid the problem of DC offset leading to saturation of baseband amplifiers and analog-to-digital converters, or even chip burning; retain the useful DC offset generated by the target, which is a prerequisite for subsequent radar signal processing and accurate acquisition of target object motion information. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to disclose a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0019] Figure 1 A principle block diagram of a DC offset cancellation circuit of a single-frequency continuous wave radar with a zero intermediate frequency receiver structure is provided in an embodiment of the present invention.

[0020] Figure 2 An embodiment of the present invention provides a circuit diagram of an adjustable DC offset circuit in a DC offset cancellation circuit of a single-frequency continuous wave radar with a zero intermediate frequency receiver structure.

[0021] Figure 3A circuit diagram of a π-type filter circuit in a DC offset cancellation circuit of a single-frequency continuous wave radar with a zero intermediate frequency receiver structure is provided in an embodiment of the present invention.

[0022] Figure 4 A circuit diagram of a linear power supply LT3045 circuit in a DC offset cancellation circuit of a single-frequency continuous wave radar with a zero intermediate frequency receiver structure is provided in an embodiment of the present invention.

[0023] Figure 5 Simulate the π-type filter circuit in the Mulitsim simulation software.

[0024] Figure 6 This is the Bode diagram of the π-type filter circuit in the Mulitsim simulation software.

[0025] Figure 7 A comparison diagram of radar signals incorporating the circuit design of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limitations on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0028] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0029] The embodiment of the present invention provides a DC offset cancellation circuit for a single-frequency continuous wave radar with a zero intermediate frequency receiver structure, such as Figure 1As shown, it includes a mixer intermediate frequency port 12, an adjustable DC offset circuit 13, a differential amplifier 14, an anti-aliasing filter 15 and an analog-to-digital converter 16;

[0030] The mixer intermediate frequency port 12 is used to receive the first voltage source voltage divider circuit signal and output it to the differential amplifier 14;

[0031] The adjustable DC offset circuit 13 is used to access the signal of the second voltage source voltage divider circuit and suppress the power supply voltage ripple and system noise, and output it to the differential amplifier 14;

[0032] The output is sent to the differential amplifier 14, which is used to cancel the DC offset of the two-way voltage source voltage divider circuit signal, remove the useless DC offset, and output to the anti-aliasing filter 15;

[0033] The anti-aliasing filter 15 is used to filter out signals outside the frequency band of interest and retain part of the useful DC offset to prevent signal frequency aliasing, and output to the analog-to-digital converter 16;

[0034] The analog-to-digital converter 16 is used to convert analog signals into digital electrical signals and output them.

[0035] like Figure 2 As shown, the adjustable DC offset circuit 13 includes a comparator, a 42nd resistor R42, a 46th resistor R46, a 47th resistor R47, a 48th resistor R48, a 50th resistor R50, and a 51st resistor R51. The 6th terminal of the comparator is connected to OP_+5V through the 46th resistor R46 after passing through the 47th resistor R47, and is connected to the analog ground AGND through the 50th resistor R50. The 5th terminal is connected to the analog ground AGND through the 51st resistor R51, the 4th terminal is connected to OP_-5V, the 7th terminal is output through the 48th resistor R48, and the 8th terminal is connected to OP_+5V. The 6th terminal and the 7th terminal of the comparator are connected to the 42nd resistor R42, and one side of the 48th resistor R48 is also connected to the third interface J3.

[0036] The power supply of the adjustable DC offset circuit 13 includes OP_+5V and OP_-5V. The power supply voltage ripple has a relatively large impact on the adjustable DC offset circuit. In particular, the power supply voltage ripple of OP_+5V connected to the forty-sixth resistor R46 will be amplified by the amplifier. Excessive power supply voltage ripple will affect the effect of DC offset cancellation. The power supply voltage ripple will be superimposed on the original DC offset, causing the signal voltage to exceed the operating voltage of the baseband amplifier and the digital-to-analog converter, affecting the removal of useless DC offset and retaining useful DC offset. The present invention first filters the input power supply VCC_IN through a suitable π-type filter circuit, and then uses the linear power supply LT3045 circuit network to suppress the power supply voltage ripple and system noise, thereby ensuring the normal operation of the entire DC offset cancellation circuit, removing useless DC offsets, and retaining useful DC offsets.

[0037] like Figure 3 As shown, the π-type filter circuit with a cut-off frequency of 2.5kHz includes a forty-seventh polarity capacitor C47, a fourth inductor L4, and a fiftieth capacitor C50. The positive polarity end of the forty-seventh polarity capacitor C47 is connected to the input power supply VCC_IN, and the negative polarity end is connected to the power ground GND. One end of the fourth inductor L4 is connected to the input power supply VCC_IN, and the other end is respectively connected to the fiftieth capacitor C50 and the output power supply T_+5V. The other end of the fiftieth capacitor C50 is connected to the power ground GND.

[0038] like Figure 4As shown, the linear power supply LT3045 circuit includes an LT3045 chip, a twenty-fifth polarity capacitor C25, a twenty-seventh capacitor C27, a twenty-eighth capacitor C28, a thirty-second capacitor C32, a thirty-third capacitor C33, a fortieth capacitor C40, a thirty-second resistor R32, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-eighth resistor R38, a thirty-ninth resistor R39, and a fortieth resistor R40. The first terminal of the LT3045 chip is connected to the output power supply T_+5V in the π-type filter circuit through the thirty-second resistor R32, the second, third, and fourth terminals are connected to the first terminal in common, and the fifth terminal is connected to the first terminal through the thirty-third resistor R33. The LT3045 The 25th polarity capacitor C25, the 27th capacitor C27, and the 28th capacitor C28 are connected in parallel between the 1st end of the chip and the 32nd resistor R32, and the 25th polarity capacitor C25, the 27th capacitor C27, and the 28th capacitor C28 are grounded in common, the 9th end is grounded, the 6th end is connected to the 9th end via the 40th resistor R40, the 40th capacitor C40 and the 38th resistor R38 are connected in parallel between the 8th end and the 9th end in sequence, the 39th resistor R39 is connected in parallel between the 7th end and the 9th end, the 12th end outputs the output power OP_+5V to the adjustable DC offset circuit 13, the 34th resistor R34 is connected in parallel between the 7th end and the 12th end, and the 32nd capacitor C32 and the 33rd capacitor C33 are connected in parallel between the 12th end and the 9th end in sequence.

[0039] The linear power supply LT3045 circuit is connected Figure 3 The output power T_+5V in the π-type filter circuit outputs the ultra-low noise power OP_+5V. The output power OP_+5V of the linear power supply LT3045 circuit network is given to Figure 2 The forty-sixth resistor R46 in the adjustable DC offset circuit 13 is connected to provide a divided voltage and Figure 2 The positive power supply terminal of the comparator U3B is connected to provide driving power.

[0040] The present invention has three unique features: first, Figure 3 As shown, a suitable π-type filter circuit is used to filter the input power supply, filter out switching noise and other noise, and suppress Figure 2 The power ripple of the DC offset circuit can be adjusted to ensure the normal operation of the entire DC offset compensation circuit, remove useless DC offsets, and retain useful DC offsets. Figure 5 As shown, a suitable π-type filter circuit is simulated and selected in the Mulitsim simulation software, such as Figure 6 The Bode plot shows that the amplitude of this π-type filter circuit at 2.453kHz is -2.763dB.

[0041] Second, the LT3045 linear power supply chip from Analog Devices (ADI) is used. The LT3045 is an ultra-low noise, ultra-high power supply ripple suppression (PSRR), low dropout voltage linear regulator. The LT3045 uses a unique design, generating ultra-low noise of 2nV / √Hz at 10kHz, and has very good PSRR performance at low and high frequencies, which can effectively suppress power supply voltage ripple and system noise, and help to extract useful signals from radar echoes later.

[0042] Third, the differential amplifier 14 has a high input impedance and a low output impedance. When the input impedance is very high, it is equivalent to an open circuit in the front stage circuit, and its output voltage is not affected by the impedance of the rear stage circuit, and has a certain isolation function; when the output impedance is very low, it is equivalent to a constant voltage source for the rear stage circuit, that is, the output voltage is not affected by the impedance of the rear stage circuit. Therefore, the voltage follower is often used as an intermediate stage to "isolate" the influence between the front and rear stage circuits, also known as a buffer stage, which allows it to play the role of impedance matching in the circuit, so that the rear stage circuit of the amplifier circuit can work better.

[0043] like Figure 7 As shown, the waveform without the circuit design of the present invention shows that the signal voltage range is from 2.83V to 4.41V, the peak-to-peak voltage is 1.58V, and the signal waveform is clipped because the maximum signal voltage exceeds the operating voltage range of the baseband amplifier and the analog-to-digital converter, causing signal distortion. The waveform with the circuit design of the present invention shows that the signal voltage range is from 0.70V to 2.60V, the peak-to-peak voltage is 1.90V, the radar signal is DC offset, some harmful DC components are removed, and useful DC components are retained. The radar signal voltage is within the operating voltage range of the baseband amplifier and the analog-to-digital converter (between 0V and 3.3V), which mainly avoids the saturation of the baseband amplifier and the analog-to-digital converter caused by the DC offset, ensuring that the signal is pure and undistorted.

[0044] In summary, the present invention designs a simple circuit for DC offset compensation from the hardware perspective, which does not require complex hardware system design. However, the present invention has two functions: first, it eliminates the useless DC offset caused by hardware and environment, mainly avoiding the problem of DC offset causing saturation of baseband amplifier and analog-to-digital converter, or even chip burning. Second, it retains the useful DC offset generated by the target, which is the prerequisite for subsequent radar signal processing to accurately obtain the target object motion information.

[0045] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A DC offset cancellation circuit for a single-frequency continuous wave radar with a zero intermediate frequency receiver structure, characterized in that: Includes mixer intermediate frequency port, adjustable DC offset circuit, differential amplifier, anti-aliasing filter and analog-to-digital converter; The mixer intermediate frequency port is used to access the first voltage source voltage divider circuit signal and output it to the differential amplifier; The adjustable DC offset circuit is used to access the signal of the second voltage source voltage divider circuit and suppress the power supply voltage ripple and system noise, and output to the differential amplifier; the power supply of the adjustable DC offset circuit includes OP_+5V and OP_-5V; The output is sent to a differential amplifier for performing DC offset on the signals of the two voltage source voltage divider circuits, and is output to an anti-aliasing filter; The anti-aliasing filter is used to filter out signals outside the frequency band of interest, retain part of the useful DC offset, and output it to the analog-to-digital converter; The analog-to-digital converter is used to convert the analog signal into a digital electrical signal and output it; The adjustable DC offset circuit includes a comparator, a 42nd resistor R42, a 46th point group R46, a 47th resistor R47, a 48th resistor R48, a 50th resistor R50, and a 51st resistor R51. The 6th terminal of the comparator is connected to OP_+5V through the 47th resistor R47 and then to the 46th resistor R46, and is connected to the analog ground AGND through the 50th resistor R50. The 5th terminal is connected to the analog ground AGND through the 51st resistor R51, the 4th terminal is connected to OP_-5V, the 7th terminal is output through the 48th resistor R48, and the 8th terminal is connected to OP_+5V. The 6th terminal and the 7th terminal of the comparator are connected to the 42nd resistor R42, and one side of the 48th resistor R48 is also connected to the third interface J3. The adjustable DC offset circuit filters the input power VCC_IN of the linear power supply LT3045 circuit through a π-type filter circuit, and suppresses power supply voltage ripple and system noise through the linear power supply LT3045 circuit network; The π-type filter circuit includes a 47th polarity capacitor C47, a fourth inductor L4, and a 50th capacitor C50. The positive end of the 47th polarity capacitor C47 is connected to the input power supply VCC_IN, and the negative end is connected to the power ground GND. One end of the fourth inductor L4 is connected to the input power supply VCC_IN, and the other end is respectively connected to the 50th capacitor C50 and the output power supply T_+5V. The other end of the 50th capacitor C50 is connected to the power ground GND. The linear power supply LT3045 circuit is connected to the output power supply T_+5V in the π-type filter circuit to output an ultra-low noise power supply OP_+5V; The output power supply OP_+5V of the linear power supply LT3045 circuit network is respectively connected to the forty-sixth resistor R46 in the adjustable DC offset circuit to provide a divided voltage and is connected to the positive power supply terminal of the comparator U3B to provide a driving power supply.

2. The DC offset cancellation circuit of the single-frequency continuous wave radar with a zero intermediate frequency receiver structure according to claim 1, characterized in that: The linear power supply LT3045 circuit includes an LT3045 chip, a twenty-fifth polarity capacitor C25, a twenty-seventh capacitor C27, a twenty-eighth capacitor C28, a thirty-second capacitor C32, a thirty-third capacitor C33, a fortieth capacitor C40, a thirty-second resistor R32, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-eighth resistor R38, a thirty-ninth resistor R39, and a fortieth resistor R40. The first end of the LT3045 chip is connected to the output power supply T_+5V in the π-type filter circuit through the thirty-second resistor R32, the second, third, and fourth ends are connected to the first end, the fifth end is connected to the first end through the thirty-third resistor R33, and the first end and the thirty-second resistor R34 are connected to the output power supply T_+5V in the π-type filter circuit. The 25th polarity capacitor C25, the 27th capacitor C27, and the 28th capacitor C28 are connected in parallel between the resistor R32, and the 25th polarity capacitor C25, the 27th capacitor C27, and the 28th capacitor C28 are grounded in common, the 9th terminal is grounded, the 6th terminal is connected to the 9th terminal via the 40th resistor R40, the 40th capacitor C40 and the 38th resistor R38 are connected in parallel between the 8th terminal and the 9th terminal, the 39th resistor R39 is connected in parallel between the 7th terminal and the 9th terminal, the 12th terminal outputs the power supply OP_+5V to the adjustable DC offset circuit, the 34th resistor R34 is connected in parallel between the 7th terminal and the 12th terminal, and the 32nd capacitor C32 and the 33rd capacitor C33 are connected in parallel between the 12th terminal and the 9th terminal.

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