Storage circuit and writing method

Abstract

The memory circuit includes a memory array and a control circuit. A first column of the memory array includes a selection line, a first bit line and a second bit line, a first subset of memory cells coupled to the selection line and the first bit line of the array, and a second subset of memory cells coupled to the selection line and the second bit line. The control circuit is configured to simultaneously activate each of the selection line and the first bit line, and during a period of simultaneously activating the selection line and the first bit line, activate a first plurality of word lines, each word line of the first plurality of word lines being coupled to a memory cell of the first subset of memory cells. Embodiments of the present invention also relate to a method of writing data to a memory array.

Description

Technical Field

[0001] Embodiments of the present invention relate to a storage circuit and a writing method. Background Art

[0002] In some applications, an integrated circuit (IC) includes storage circuitry that stores data in nonvolatile memory (NVM), where the data is not lost when the IC is powered off. Types of NVM cells include three-terminal devices in which a dielectric layer between a gate and each of two source / drain (S / D) terminals has one or more characteristics that can be changed in response to an applied voltage, such that a detectable change in characteristics is used to represent a stored logic state. In some cases, the dielectric layer includes a ferroelectric material, and the device is referred to as a ferroelectric random access memory (FRAM or FeRAM) cell. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a storage circuit is provided, comprising: a memory array, comprising a first column, the first column comprising: a selection line; a first bit line and a second bit line; a first subset of memory cells, coupled to the selection line and the first bit line; and a second subset of memory cells, coupled to the selection line and the second bit line; and a control circuit, configured to: simultaneously activate each of the selection line and the first bit line, and in a period of simultaneously activating the selection line and the first bit line, activate a first plurality of word lines, wherein each of the first plurality of word lines is coupled to memory cells of the first subset of memory cells.

[0004] According to another aspect of an embodiment of the present invention, a method for writing data to a memory array is provided, the method comprising: programming a first subset of memory cells in a first column of the memory array to a first logic level simultaneously by activating a first selection line of the first column and a first bit line of the first column; and programming a second subset of memory cells in the first column to the first logic level simultaneously by activating a first selection line and a second bit line of the first column, wherein each memory cell of the memory array is a three-terminal memory cell.

[0005] According to another aspect of an embodiment of the present invention, a method for writing data to a memory array is provided, the method comprising: identifying a first data pattern corresponding to a first subset of memory cells, the first subset of memory cells being arranged in a first line extending along a first array dimension and being located at a first position along a second array dimension; identifying a second subset of memory cells corresponding to the first data pattern, the second subset of memory cells being arranged in a second line extending along the first array dimension and being located at a second position along the second array dimension; and simultaneously programming the first subset of memory cells and the second subset of memory cells to a first logic level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the size of each component may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A-Figure 1D is a schematic diagram of a memory circuit according to some embodiments.

[0008] Figure 1E and Figure 1F is a schematic diagram of operating parameters of a memory circuit according to some embodiments.

[0009] Figure 2 is a schematic diagram of a memory cell according to some embodiments.

[0010] Figure 3 is a flow chart of a method of writing data to a memory array according to some embodiments.

[0011] Figure 4 is a flow chart of a method of writing data to a memory array according to some embodiments.

[0012] Figure 5 is a flow chart of a method of writing data to a memory array according to some embodiments.

[0013] Figure 6A-6E is a schematic diagram of a memory array according to some embodiments.

[0014] Figure 7A-7H is a schematic diagram of a memory array according to some embodiments.

[0015] Fig. 8A and Figure 8B is a schematic diagram of a memory array according to some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. In order to simplify the present invention, specific examples of components, numerical values, operations, materials, arrangements, etc. are described below. Of course, these are only examples and are not intended to be limited. Other components, numerical values, operations, materials, arrangements, etc. can be expected. For example, in the following description, the formation of a first component above or on a second component can include an embodiment in which the first component and the second component are directly contacted to form, and can also include an embodiment in which additional components are formed between the first component and the second component, so that the first and second components may not be in direct contact. In addition, the present invention can repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "under," "below," "beneath," "over," "above," etc. may be used herein to describe the relationship of one element or component to another element or component illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] In various embodiments, a memory circuit including a three-terminal memory cell can simultaneously write data to multiple cells in a single column, thereby implementing a column write scheme and algorithm in which data is written to multiple rows and columns simultaneously. Such a memory circuit can have an increased write bandwidth compared to an approach that does not simultaneously write data to multiple cells in a single column, thereby reducing the overall write time without exacerbating write disturb events.

[0019] Figure 1A-Figure 1D is a schematic diagram of a memory circuit 100 according to some embodiments. Figure 1A Memory circuit 100 is generally depicted, and Figure 1B-Figure 1D 1 and 2 each depict a non-limiting example of a programming operation on the memory circuit 100 .

[0020] The memory circuit 100 includes a memory array 110 coupled to a word line driver 120 and a read / write interface 130, and a control circuit 140 coupled to the word line driver 120 and the read / write interface 130. The memory circuit 100 is configured to be able to perform some or all of the methods, for example, as described below with reference to Figure 3-Figure 5 One or more of methods 300, 400, or 500 are discussed, as described below, where data is written simultaneously to multiple cells in a single column.

[0021] For the purpose of illustration, the memory circuit 100 is simplified. In various embodiments, the memory circuit 100 includes Figure 1A-Figure 1D Various elements may be included in addition to those shown in FIG. 1 , or may be otherwise arranged to perform the operations discussed below.

[0022] Two or more circuit elements are considered to be coupled based on one or more direct signal connections and / or one or more indirect signal connections, wherein the one or more indirect signal connections include one or more logic devices, such as inverters or logic gates, between the two or more circuit elements. In some embodiments, the signal communication between the two or more coupled circuit elements can be improved by one or more logic devices, for example, inverted or made individual.

[0023] Memory array 110 includes memory cells 112 arranged in columns C0-C3 and rows R0-R5. Figure 1A-Figure 1D Memory cells 112 are schematically illustrated in FIG. 1 such that two subsets of memory cells in each of columns C0-C3 are respectively aligned vertically. In various embodiments, some or all of the memory cells 112 in columns C0-C3 are physically arranged in lines extending in a first direction (i.e., vertically or horizontally), and some or all of the memory cells 112 in rows R0-R5 are physically arranged in lines extending in a second direction (i.e., horizontally or vertically).

[0024] exist Figure 1A – Figure 1D The number of rows and columns of memory cells 112 depicted in are non-limiting examples for illustration. In various embodiments, memory array 110 includes more than six rows R0-R5 and / or more than four columns C0-C3. In some embodiments, memory array 110 includes a number of rows ranging from 64 to 1024. In some embodiments, memory array 110 includes a number of rows ranging from 128 to 512. In some embodiments, memory array 110 includes a number of columns ranging from eight to 256. In some embodiments, memory array 110 includes a number of columns ranging from 36 to 96.

[0025] exist Figure 1A-Figure 1D In the depicted embodiment, the memory array 110 includes rows R0-R5 and columns C0-C3 arranged along row and column dimensions (not labeled), respectively. In some embodiments, the memory array 110 has a three-dimensional (3D) arrangement, also referred to as a stacked arrangement, which includes one or more vertically spaced elements. Figure 1A-Figure 1D The array layers (not shown) are arranged in row and column dimensions in a single layer, so that the memory array 110 is not Figure 1A-Figure 1D Includes rows and columns in addition to those shown.

[0026] The memory cell 112 is a three-terminal device including one or more dielectric layers ( Figure 2 ). As described below, one or more dielectric layers include one or more dielectric materials, such as ferroelectric materials, having properties that are controllable in response to an applied voltage so that the changing property states can be used as representations of stored logic levels (i.e., logic high and logic low). In some embodiments, memory cell 112 is an NVM cell, such as a FRAM cell. In some embodiments, memory cell 112 includes the following: Figure 2 A memory cell 200 is discussed.

[0027] In a programming operation, a given memory cell 112 is configured to be programmed to a predictable state in response to receiving a first voltage at the gate and a second voltage at both S / D terminals, and to remain in a predictable state in response to receiving a reference voltage or a ground voltage on the gate and S / D terminals. In the following discussion, a given memory cell 112 is described as being fully selected in a first scenario and unselected in a second scenario. Based on the three-terminal arrangement discussed below and the configuration of the memory array 110, for example, in response to programming activity on other memory cells 112, a given memory cell 112 is capable of receiving various combinations of a first voltage, a second voltage, and a reference voltage that are different from the voltages of the first scenario and the second scenario. In the following discussion, a given memory cell 112 is described as being partially selected by receiving one of a combination other than the combination of the first scenario and the second scenario.

[0028] A given memory cell 112 can remain in a predictable state in response to some partial selection scenarios, and can be placed in an unpredictable state in response to other partial selection scenarios. As described below, by controlling write operations to avoid placing memory cells 112 in unpredictable states under partial selection scenarios, multiple memory cells 112 in a single column can be programmed simultaneously, thereby improving the efficiency of write operations compared to methods that do not write data to multiple cells in a single column simultaneously.

[0029] Each memory cell 112 of rows R0-R5 includes a gate coupled to a corresponding word line WL0-WL5 configured to carry a respective word line voltage VW0-VW5, and each memory cell 112 of columns C0-C3 includes an S / D terminal coupled to a corresponding select line SL0-SL3, which is configured to carry a respective select line voltage VS0-VS3. In each column C0-C3, the memory cells 112 at alternating positions include an S / D terminal coupled to a corresponding bit line BL0-BL3 or a corresponding bit line BL1-BL4, which is configured to carry a respective bit line voltage VB0-VB3, and the corresponding bit line BL1-BL4 is configured to carry a respective bit line voltage VB1-VB4. Each word line WL0-WL5 is coupled to a word line driver 120, and the select lines S0-S3 and the bit lines BL0-BL4 are coupled to a read / write interface 130.

[0030] Columns C0-C3 thus each include a first subset of memory cells 112 of first bit lines coupled to corresponding select lines S0-S3 and bit lines BL0-BL4, and a second subset of memory cells 112 of second bit lines coupled to corresponding select lines SL0-SL3 and bit lines BL0-BL4, such that each of the bit lines BL1-BL3 is shared by corresponding pairs of adjacent columns C0 / C1, C1 / C2 or C2 / C3.

[0031] exist Figure 1A-Figure 1D , memory cells 112 at alternating positions coupled to respective bit lines BL0-BL3 are also coupled to word lines in alternation of word lines WL0-WL5 (i.e., word lines WL1, WL3, and WL5), and memory cells 112 at alternating positions coupled to respective bit lines BL1-BL4 are also coupled to alternating word lines in word lines WL0-WL5, i.e., word lines WL0, WL2, and WL4. In a given one of columns C0-C3, a first subset of memory cells 112 are thereby coupled to odd word lines WL0-WL5, and a second subset of memory cells 112 are thereby coupled to even word lines WL0-WL5.

[0032] In some embodiments, the memory circuit 100 includes Figure 1A-Figure 1DArrangements other than those shown are such that first and second subsets of a given memory cell 112 in columns C0-C3 are coupled to word line groupings other than the odd / even groupings of word lines WL0-WL5. In a non-limiting example, the first and second subsets of memory cells 112 are coupled to respective first and second groups of word lines WL0-WL5, and each group includes adjacent pairs of word lines WL0-WL5 separated by adjacent pairs of word lines WL0-WL5 included in the other group, such that each group includes odd word lines WL0-WL5 and even word lines WL0-WL5.

[0033] exist Figure 1A-Figure 1D In the embodiment depicted in FIG, the position of each of the 24 memory cells 112 corresponds to the intersection of one of the four columns C0-C3 and the six rows R0-R5, so that a given memory cell 112 can be identified by its corresponding column and row, for example, the rightmost and bottommost memory cell 112 corresponds to position C3 / R0.

[0034] The word line driver 120 is configured to generate word line voltages VW0-VW5 on respective word lines WL0-WL5 based on one or more control signals (not shown) received from the control circuit 140 or from one or more circuits (not shown) external to the memory circuit 100. The word line driver 120 is configured to drive each of the word line voltages VW0-VW5 (generally referred to as word line voltages VWx) to a reference voltage level (e.g., a ground voltage level) or to one or more other voltage levels to activate the corresponding word line WL0-WL5 during read and write operations. During a read or write operation, activating a given word line WL0-WL5 results in one or more target memory cells 112 coupled to the given word line WL0-WL5 being fully selected, and other memory cells 112 coupled to the given word line WL0-WL5 being partially selected, as discussed further below.

[0035] The read / write interface 130 is an electronic circuit that is configured to generate select line voltages VS0-VS3 on corresponding select lines SL0-SL3 and bit line voltages VB0-VB4 on corresponding bit lines BL0-BL4 based on one or more control signals (not shown) received from the control circuit 140 or from one or more circuits (not shown) external to the memory circuit 100. The read / write interface 130 is configured to drive each of the select line voltages VS0-VS3 (generally referred to as the select line voltage VSx) and each of the bit line voltages VB0-VB4 (generally referred to as the bit line voltage BLx) in the manner discussed above with respect to the word line voltages VW0-VW5, thereby activating the corresponding select lines SL0-SL3 and bit lines BL0-BL4 during read and write operations. During read and write operations, a given select line SL0-SL3 or bit line BL0-BL4 is activated so that one or more target memory cells 112 coupled to the given select line SL0-SL3 or bit line BL0-BL4 are fully selected, and other memory cells 112 coupled to the given select line SL0-SL3 or bit line BL0-BL4 will be partially selected, as further discussed below.

[0036] The read and write interface 130 is also configured to perform one or more additional read operations based on one or a combination of the select lines SL0-SL3 or the bit lines BL0-BL4, for example, measuring one or more currents, voltages, or voltage differences in which a state of the selected memory cell 112 is detected, which indicates a stored logic high level or a logic low level.

[0037] According to embodiments discussed below, control circuitry 140 is an electronic circuit configured to control the operation of memory circuitry 100 by generating one or more control signals received by wordline driver 120 and read / write interface 130. In various embodiments, control circuitry 140 includes hardware processor 142 and non-transitory computer-readable storage medium 144. Storage medium 144 is encoded with (i.e., stores) computer program code (i.e., a set of executable instructions), among other things. The instructions executed by hardware processor 142 (at least partially) represent memory circuitry operating means that implement, for example, the following with respect to Figure 3 Method 300 of discussion, the following Figure 4 Method 400 discussed below and / or with respect to Figure 5 A portion or all of method 500 is discussed (hereinafter, the process and / or method described).

[0038] The processor 142 is electrically coupled to the computer-readable storage medium 144anI / O interface and a network (details not shown) via a bus. The network interface is connected to a network (not shown) so that the processor 142 and the computer-readable storage medium 144 can be connected to external elements via the network. The processor 142 is configured to execute computer program code encoded in the computer-readable storage medium 144 so that the control circuit 140 and the storage circuit 100 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 142 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0039] In one or more embodiments, the computer-readable storage medium 144 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, the computer-readable storage medium 144 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 704 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0040] In one or more embodiments, the storage medium 144 stores computer program code configured to cause the control circuit 140 to generate control signals that can be used to perform some or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 144 also stores some or all of the information that facilitates the performance of the processes and / or methods mentioned. In one or more embodiments, the storage medium 144 stores one or more data sets, such as a plurality of data patterns, which are discussed below with respect to the processes and / or methods mentioned.

[0041] Each memory cell 112 is configured to be programmed to a first state corresponding to a logic high level in a first write operation in response to receiving a word line voltage VWx having a first gate voltage level at a gate and receiving each of a select line voltage VSx and a bit line voltage VBx having a first S / D voltage level at a corresponding S / D terminal. The memory cell 112 is configured to be programmed to a second state corresponding to a logic low level in a second write operation in response to receiving a word line voltage VWx having a second gate voltage level and receiving each of a select line voltage VSx and a bit line voltage VBx having a second S / D voltage level. In various embodiments, the first gate voltage level and the second gate voltage level have opposite polarities and / or the first S / D voltage level and the second S / D voltage level have opposite polarities. In various embodiments, the first gate voltage level and the second gate voltage level have the same magnitude and / or the first S / D voltage level and the second S / D voltage level have the same magnitude.

[0042] Thus, each memory cell 112 is configured to be programmed in the first write operation and the second write operation in response to being fully selected, i.e., receiving each of the word line voltage VWx, the select line voltage VSx, and the bit line voltage VBx. The memory cell 112 is also configured to remain in a predictable state (not programmed) in response to four non-programmed partial selection combinations, and to be placed in an unpredictable state in response to the fifth partial selection combination. As described below, in various embodiments, the write operation includes each memory cell 112 being fully selected or receiving one of the four non-programmed partial selection combinations without receiving the fifth partial selection combination, thereby avoiding being placed in an unpredictable state.

[0043] As described below, each of the four non-programmed combinations of word line voltage VWx, select line voltage VSx, and bit line voltage VBx and a fifth combination in which a given memory cell 112 is in an unpredictable state corresponds to a write disturbance event, wherein one or more memory cells 112 other than the given memory cell 112 are programmed in the first write operation or the second write operation.

[0044] In the first non-programming combination, a given memory cell 112 receives a word line voltage VWx having a first gate voltage level or a second gate voltage level while receiving each of a select line voltage VSx and a bit line voltage VBx having a ground voltage level or a reference voltage level at each S / D terminal. Figure 1A-Figure 1D In the illustrated embodiment, a first non-programming combination occurs when memory cells 112 in the same row R0-R5 as a given memory cell 112 are fully selected in either the first write operation or the second write operation.

[0045] like Figure 1BAs shown in the first non-limiting example, in the first write operation or the second write operation, the memory cell 112 is fully selected at the position C1 / R1 so that the word line voltage VW1 on the word line WL1 has a first gate voltage level or a second gate voltage level (collectively represented as Vg), the selection line voltage VSx other than the selection line voltage VS1 on the selection line SL1 has a ground voltage level (represented as 0V), and the bit line voltage VBx other than the bit line voltage VB1 on the bit line BL1 has a ground voltage level of 0V, so that each memory cell 112 at the positions C0 / R1, C2 / R1 and C3 / R1 receives the first non-programmed combination.

[0046] In the second non-programming combination, a given memory cell 112 receives each of the select line voltage VSx and the bit line voltage VBx having the first S / D voltage level or the second S / D voltage level, while receiving the word line voltage VWx having the ground voltage level or the reference voltage level at the gate. Figure 1A-Figure 1D In the illustrated embodiment, the second non-programmed combination occurs when all memory cells 112 in the same column C0-C3 as the given memory cell 112 and a subset of the memory cells 112 in columns C0-C3 are selected in either the first write operation or the second write operation.

[0047] exist Figure 1B In the first non-limiting example shown, the selection line voltage VS1 having a first S / D voltage level or a second S / D voltage level (collectively represented as Vsd) on the selection line SL1, the bit line voltage VB1 having a corresponding first S / D voltage level or a second S / D voltage level Vsd on the bit line BL1, and other word line voltages VWx other than the word line voltage VW1 having a ground voltage level 0V on the word line WL1 cause the memory cells 112 at positions C1 / R3 and C1 / R5 to receive a second non-programmed combination.

[0048] In the third non-programming combination, a given memory cell 112 receives a selection line voltage VSx having a first S / D voltage level or a second S / D voltage level, while receiving each of bit line voltages VBx and VWx having a ground voltage level or a reference voltage level. Figure 1A-Figure 1D In the illustrated embodiment, a third non-programmed combination occurs when all memory cells 112 in the same column C0-C3 as a given memory cell 112 and a different subset of memory cells 112 in columns C0-C3 are selected in either the first write operation or the second write operation.

[0049] exist Figure 1BIn the first non-limiting example shown, a selection line voltage VS1 having a first S / D voltage level or a second S / D voltage level Vsd on the selection line SL1, a bit line voltage VBx other than a bit line voltage VB1 having a ground voltage level of 0V on the bit line BL1, and a word line voltage VWx other than a word line voltage VW1 having a ground voltage level of 0V on the word line WL1 cause the memory cells 112 at positions C1 / R0, C1 / R2, and C1 / R4 to receive a third non-programmed combination.

[0050] In the fourth non-programming combination, a given memory cell 112 receives a bit line voltage VBx having a first S / D voltage level or a second S / D voltage level, and simultaneously receives a selection line voltage VSx and a word line voltage VWx having a ground voltage level or a reference voltage level. Figure 1A-Figure 1D In the illustrated embodiment, the fourth non-programmed combination occurs when memory cells 112 in columns C0-C3 that are adjacent to the column of a given memory cell 112 and share bit lines BL1-BL3 with the given memory cell 112 are fully selected in either the first write operation or the second write operation.

[0051] exist Figure 1B In the first non-limiting example shown, a bit line voltage VB1 having a first S / D voltage level or a second S / D voltage level Vsd on the bit line BL1, a selection line voltage VSx other than a selection line voltage VS1 having a ground voltage level 0V on the selection line SL1, and a word line voltage VWx other than a word line voltage VW1 having a ground voltage level 0V on the word line WL1 cause the memory cells 112 at positions C0 / R0, C0 / R2, and C0 / R4 to receive a fourth non-programmed combination.

[0052] In a fifth combination, a given memory cell 112 is capable of being in an unpredictable state in response to receiving a partially programmed combination of a word line voltage VWx having a first gate voltage level or a second gate voltage level and a bit line voltage VBx having a corresponding one of a first S / D voltage level or a second S / D voltage level while receiving a select line voltage VSx having a ground voltage level or a reference voltage level.

[0053] exist Figure 1A-Figure 1D In the illustrated embodiment, a fifth non-programmed combination occurs when two or more memory cells 112 in the same column C0-C3 as a given memory cell 112 are simultaneously programmed by complete selection in the first write operation or the second write operation and the two or more memory cells 112 include at least one memory cell 112 in each of the first subset and the second subset of memory cells 112 in the same column C0-C3.

[0054] exist Figure 1CIn the second non-limiting example shown, each memory cell 112 at positions C1 / R1 and C1 / R2 is fully selected simultaneously in the first write operation or the second write operation so that each of the word line voltages VW1 on the word line WL1 and VW2 on the word line WL2 has a first gate voltage level or a second gate voltage level Vg, each of the bit line voltages VB1 on the bit line BL1 and the bit line voltages VB2 on the bit line BL2 has a corresponding first S / D voltage level or a second S / D voltage level Vsd, and the selection line voltages VSx other than the selection line voltage VS1 on the selection line SL1 have a ground voltage level of 0V, so that each of the memory cells 112 at positions C0 / R2 and C2 / R1 receives the fifth combination, thereby possibly placing each memory cell 112 at positions C0 / R2 and C2 / R1 in an unpredictable state.

[0055] The memory circuit 100 is configured to be able to program two or more memory cells 112 at the same time by performing a first write operation and a second write operation on two or more memory cells 112 in the same column C0-C3, each of the two or more memory cells 112 being included in the same subset of the memory cells 112 in the same column C0-C3. Because each of the two or more memory cells 112 is included in the same subset of the memory cells 112, other memory cells 112 other than the two or more memory cells 112 avoid receiving the fifth combination, and other memory cells other than the two or more memory cells 112 are partially grounded and selected by receiving one of the first to fourth non-programming combinations, or other memory cells other than the two or more memory cells 112 are not selected by receiving each of the word line voltage VWx, the selection line voltage VSx, and the bit line voltage VBx having a ground voltage.

[0056] exist Figure 1DIn the third non-limiting example shown in , each memory cell 112 at positions C1 / R1 and C1 / R3 in the first write operation or the second write operation is programmed simultaneously by fully selecting the word line voltage VW1 on the word line WL1 and VW3 on the word line WL3, so that each of the word line voltages VW1 on the word line WL1 and VW3 on the word line WL3 has the first gate voltage level or the second gate voltage level Vg, the selection line voltage VS1 on the selection line SL1 has the corresponding first S / D voltage level or the second S / D voltage level, the bit line voltage VB1 on the bit line BL1 has the corresponding first or second S / D voltage level Vsd, and each voltage other than the word line voltages VW1 and VW3, the selection line voltage VS1 and the bit line voltage VB1 has the ground voltage level. Each memory cell 112 at the position C1 / R1C1 / R3 is programmed simultaneously in the first write operation or the second write operation, resulting in each memory cell 112 at the position C0 / R1, C2 / R1, C3 / R1, C0 / R3, C2 / R3 and C3 / R3 receiving a first non-programmed combination, the memory cell 112 at the position C1 / R5 receiving a second programmed combination, each memory cell 112 at the position C1 / R0, C1 / R2 and C1 / R4 receiving a third non-programmed combination, and each memory cell 112 at the position C0 / R0, C0 / R2 and C0 / R4 receiving a fourth non-programmed combination. Thus, all other memory cells 112 in the memory array 110 receive each of the word line voltage VWx, the selection line voltage VSx and the bit line voltage VBx having a ground voltage level 0V.

[0057] Figure 1E and Figure 1F is based on Figure 1D Schematic diagram of memory circuit operating parameters of some embodiments corresponding to a third non-limiting example of the operation of the memory circuit 100 shown in FIG. Figure 1E is a timing diagram corresponding to a first write operation, in which the memory cells 112 at the locations C1 / R1 and C1 / R3 are programmed to a first state corresponding to a logic high level. Figure 1F is a timing diagram corresponding to a second write operation, in which the memory cells 112 at the locations C1 / R1 and C1 / R3 are simultaneously programmed to a second state corresponding to a logic low level.

[0058] like Figure 1EAs shown in FIG. 1 , the first write operation includes each of the selection line voltage VS1 and the bit line voltage VB1 transitioning from the ground voltage level 0V to the first S / D voltage level (not labeled) equal to -Vsd in a first period (not labeled), followed by the selection line voltage VS1 and the bit line voltage VB1 transitioning from the first S / D voltage level -Vsd to the ground voltage level 0V. In the first period, each of the selection line voltage VS1 and the bit line voltage VB1 has the first S / D voltage level -Vsd, and each of the word line voltages VW1 and VW3 transitions from the ground voltage level 0V to the first gate voltage level equal to +Vg in a second period (not labeled), followed by the selection line voltage VS1 and the bit line voltage VB1 transitioning from the first gate voltage level +Vg to the ground voltage level 0V.

[0059] like Figure 1F As shown in , the second write operation includes each of the selection line voltage VS1 and the bit line voltage VB1 transitioning from the ground voltage level 0V to the second S / D voltage level equal to +Vsd in a third period (not labeled), followed by each of the selection line voltage VS1 and the bit line voltage VB1 transitioning from the second S / D voltage level +Vsd to the ground voltage level 0V. During the third period in which each of the selection line voltage VS1 and the bit line voltage VB1 has the second S / D voltage level +Vsd, each of the word line voltages VW1 and VW3 transitions from the ground voltage level 0V to the second gate voltage level equal to -Vg in a fourth period (not labeled), followed by each of the word line voltages VW1 and VW3 transitioning from the second gate voltage level -Vg to the ground voltage level 0V.

[0060] Figure 1E and Figure 1F The voltage levels and timing relationships shown in are non-limiting examples provided for illustration purposes. In various embodiments, one or more of the first or second S / D voltages -Vsd or +Vsd, the first or second gate voltage levels +Vg or -Vg, or the ground voltage level 0V have Figure 1E In various embodiments, one or more of the first to fourth time periods have a duration relative to other time periods in the first to fourth time periods, rather than Figure 1E and Figure 1F The duration shown.

[0061] Figure 1B-1F The operations shown in are non-limiting examples provided for illustration purposes. In various embodiments, the programming operation includes Figure 1B One or more memory cells 112 other than those included in FIG. 1E are programmed according to various embodiments discussed below.

[0062] like Figure 1B-Figure 1FAs shown, by being configured to program multiple cells in a single column simultaneously in a first write operation and a second write operation, the memory circuit 100 enables a column write scheme, for example, according to one or both of the methods 300 or 400 and discussed below and, for example, according to an algorithm of the method 500 discussed below, in which data is written to multiple rows and columns simultaneously. Compared to methods that do not write data to multiple cells in a single column simultaneously, such a memory circuit can have an increased write bandwidth, thereby reducing the total write time without exacerbating write disturb events.

[0063] Figure 2 2 is a schematic diagram of a memory cell 200 according to some embodiments. The memory cell 200 is also referred to as an NVM cell 200 or a FRAM cell 200 in some embodiments and can be used as described above with respect to Figure 1A-1F One or more examples of the memory cell 112 are discussed. The memory cell 200 includes a substrate 200B, an S / D structure 200SD located in the substrate 200B, a dielectric layer 200D covering the substrate 200B, and a gate electrode 200G covering the dielectric layer 200D and the substrate 200B.

[0064] The gate electrode 200G corresponds to the gate of the memory cell 112, is coupled to the word line WLx, and is thereby configured to receive the word line voltage VWx; the first S / D structure 200SD corresponds to the first S / D terminal of the memory cell 112, is coupled to the selection line SLx, and is thereby configured to receive the selection line voltage VSx; and the second S / D structure 200SD corresponds to the second S / D terminal of the memory cell 112, is coupled to the bit line BLx, and is thereby configured to receive the bit line voltage VBx, each with reference to Figure 1A-1F Discussed.

[0065] The dielectric layer 200D includes one or more dielectric materials configured to electrically isolate the gate electrode 200G from the substrate 200B and the S / D structure 200SD. The one or more dielectric materials include at least one ferroelectric material, such as lead zirconate titanate (PZT), and the at least one ferroelectric material is capable of changing in response to a word line voltage VWx received at the gate electrode 200G, a select line voltage VSx received at the first S / D structure 200SD, and a bit line voltage VBx received at the second S / D structure 200SD. In some embodiments, the at least one ferroelectric material is capable of changing based on a dipole aligned in response to receiving a voltage, such that a first dipole alignment corresponds to a memory cell 200 programmed to a logic high level, and a second dipole alignment corresponds to a memory cell 200 programmed to a logic low level.

[0066] By including memory cell 200 as one or more instances of memory cell 112 , memory circuit 100 can achieve the advantages discussed above.

[0067] Figure 3 is a flow chart of a method 300 for writing data to a memory array according to some embodiments. The method 300 may be used with a memory circuit, such as described above with respect to Figure 1A-1F A memory circuit 100 is discussed.

[0068] Figure 3 The order in which the operations of method 300 are described is for illustration only; the operations of method 300 can be performed simultaneously or in parallel. Figure 3 In some embodiments, Figure 3 Performed before, between, during and / or after the indicated operations Figure 3 In some embodiments, the operations of method 300 are a subset of a method of operating an IC (e.g., a processor, logic, memory, or signal processing circuit, etc.). In various embodiments, one or more operations of method 300 are described below with respect to Figure 4 and Figure 5 A subset of method 400 or method 500 is discussed.

[0069] At operation 310, each of the select lines and bit lines of a column of memory cells are simultaneously activated. The column of memory cells includes a select line and a first bit line and a second bit line, and the simultaneous activation of each of the select lines and bit lines includes activating each of the select lines and the first bit lines coupled to a first subset of memory cells and a second subset of memory cells coupled to the select line and the second bit line.

[0070] In some embodiments, one of the first subset or the second subset of memory cells is disposed in memory cells of even numbered rows of the memory array and the other of the first subset or the second subset of memory cells is disposed in memory cells of odd numbered rows of the memory array.

[0071] In some embodiments, simultaneously activating each of the select lines and bit lines of the memory cells in columns includes simultaneously activating the select lines SL0-SL4 and a corresponding one of the bit lines BL0-BL3 or BL1-BL4 of the memory array 110 of the corresponding columns C0-C3 discussed above with respect to the storage circuit 100 and FIG. 1 .

[0072] Each of the select lines and bit lines of the memory cells in the column that are simultaneously activated includes the memory cells as three-terminal memory cells, for example, Figure 1A-1F In some embodiments, the memory cell is a NVM cell, such as a FRAM cell. In some embodiments, the memory cell is a memory cell as described above with respect to Figure 2 A memory cell 200 is discussed.

[0073] In some embodiments, simultaneously activating each of the select line and the bit line comprises driving each of the select line and the bit line to an S / D voltage level having a first polarity. In some embodiments, simultaneously activating each of the select line and the bit line comprises driving the second bit line to a reference voltage level, such as a ground voltage level.

[0074] In various embodiments, simultaneously activating each of the select line and the bit line is part of programming the first subset of memory cells to a logic high level in a first write operation or part of programming the first subset of memory cells to a logic low level in a second write operation.

[0075] In some embodiments, the column is a first column of a plurality of columns of memory cells, and simultaneously activating each of the select lines and the bit lines of the column of memory cells includes simultaneously activating the select lines and the bit lines of a plurality of columns of the plurality of columns.

[0076] At operation 320, during a period of simultaneously activating the select lines and the bit lines, a first plurality of word lines are activated, each word line in the first plurality of word lines being coupled to memory cells of the column of memory cells. Activating the first plurality of word lines includes activating a first plurality of word lines coupled to a first subset of memory cells, and a second plurality of word lines coupled to a second subset of memory cells.

[0077] In various embodiments, activating the first plurality of word lines includes activating memory cells of the first plurality of word lines corresponding to some or all of the odd rows of the first column of memory cells or some or all of the even rows of the first column of memory cells.

[0078] In some embodiments, activating the first plurality of word lines includes activating the above-described memory circuit 100 and Figure 1A-1F Two or more word lines WL0-WL5 are discussed.

[0079] In some embodiments, activating the first plurality of word lines comprises driving each of the first plurality of word lines to a gate voltage level having a second polarity opposite to the first polarity. In some embodiments, activating the first plurality of word lines comprises driving each of the first plurality of word lines to a gate voltage level having the same magnitude as the S / D voltage level.

[0080] In some embodiments, activating the plurality of word lines includes driving each word line of the second plurality of word lines to a reference voltage level.

[0081] In various embodiments, activating the first plurality of word lines is part of programming the first subset of memory cells to a logic high level in a first write operation or part of programming the first subset of memory cells to a logic low level in a second write operation.

[0082] In some embodiments, the column is a first column of a plurality of columns of memory cells, and activating the first plurality of word lines includes coupling each word line of the first plurality of word lines to each column of memory cells of the plurality of columns.

[0083] By performing some or all of the operations of method 300 , multiple cells in a single column may be programmed simultaneously in a write operation, thereby achieving the benefits discussed above with respect to memory circuit 100 .

[0084] Figure 4 4 is a flow chart of a method 400 for writing data to a memory array according to some embodiments. The method 400 may be used with a memory circuit, such as the one described above with respect to Figure 1A-1F A memory circuit 100 is discussed.

[0085] exist Figure 4 The order in which the operations of method 400 are described is for illustration only; the operations of method 400 can be performed in the same order as described in Figure 4 In some embodiments, the Figure 4 Performed before, between, during and / or after the indicated operations Figure 4 In some embodiments, the operations of method 400 are a subset of a method of operating an IC (e.g., a processor, logic, memory, or signal processing circuit, etc.). In some embodiments, the operations of method 500 are a subset of a method of performing memory array testing.

[0086] According to various embodiments, a memory array includes memory cells in rows and columns, and data can be written to the memory array by programming the memory cells in rows or in columns. Programming a given row includes sequentially performing a first write operation and a second write operation once so as to program a total of two subsets of the memory cells to a high logic level or a low logic level. Programming a given column includes sequentially performing a first write operation and a second write operation twice, as described above with respect to Figure 1A-Figure 3 As discussed, once on each of the two subsets, a total of four subsets of memory cells are programmed to a high logic level or a low logic level. Therefore, in the case where the number of rows programmed in a programming operation is greater than twice the number of columns programmed in a programming operation, fewer write operations are required to program the memory cells by column than to program the memory cells by row. Therefore, in this case, programming the memory cells by column is more efficient than programming the memory cells by row.

[0087] In some embodiments, at operation 410, it is determined that the number of rows of the memory array being programmed in the programming operation is greater than twice the number of columns of the memory array being programmed in the programming operation. In some embodiments, the programming operation includes the entire memory array, and determining that the number of rows is greater than twice the number of columns includes determining that the total number of rows in the memory array is greater than twice the total number of columns of the memory array. In some embodiments, determining that the number of rows is greater than twice the number of columns is a configuration memory circuit (e.g., as described above with respect to Figure 1A-1F Part of the memory circuit 100 discussed.

[0088] In some embodiments, the programming operation includes a portion of the memory array, eg, a partial write operation, and determining that the number of rows is greater than twice the number of columns includes determining that a subset of the total number of rows in the memory array is greater than twice a subset of the total number of columns in the memory array.

[0089] In some embodiments, the above description of the memory circuit 100 and Figure 1A-1F As discussed, determining that the number of rows is greater than twice the number of columns includes determining that a subset or total number of rows R0 - R5 is greater than twice a subset or total number of columns C0 - C3 .

[0090] At operation 420, a first subset of memory cells in a first column of the memory array is simultaneously programmed to a first logic level by activating a first select line of the first column and a first bit line of the first column. Simultaneously programming a first subset of memory cells in a first column of the memory array includes performing the above-described Figure 3 Operations 310 and 320 of method 300 are discussed.

[0091] In various embodiments, programming the memory cells (eg, a first subset of memory cells) to a first logic level includes the first logic level being a logic high and the second logic level being a logic low, or includes the first logic level being a logic low and the second logic level being a logic high.

[0092] In some embodiments, the above description of the memory circuit 100 and Figure 1A-1F As discussed, activating a first select line of a first column and a first bit line of the first column includes simultaneously activating select lines SL0 - SL4 and a corresponding one of bit lines BL0 - BL3 or BL1 - BL4 of a corresponding column C0 - C3 of the memory array 110 .

[0093] In some embodiments, simultaneously programming a first subset of memory cells to a first logic level by activating a first select line and a first bit line comprises driving the first select line and the first bit line to a first S / D voltage level having a first polarity. In some embodiments, simultaneously programming a first subset of memory cells to a first logic level comprises driving a first subset of word lines to a first gate voltage level having a second polarity.

[0094] At operation 430, in some embodiments, a second subset of memory cells in the first column are simultaneously programmed to the first logic level by activating the first select line and the second bit line of the first column. Simultaneously programming the second subset of memory cells in the first column of the memory array includes performing the above-described Figure 3 Operations 310 and 320 of method 300 are discussed.

[0095] In some embodiments, the above description of the memory circuit 100 and Figure 1A-1F As discussed, activating the first select line of the first column and the second bit line of the first column includes simultaneously activating select lines SL0 - SL4 and a corresponding one of bit lines BL0 - BL3 or BL1 - BL4 of a corresponding column C0 - C3 of the memory array 110 .

[0096] In some embodiments, simultaneously programming a second subset of memory cells to a first logic level by activating a first select line and a second bit line comprises driving the first select line and the second bit line to a first S / D voltage level having a first polarity. In some embodiments, simultaneously programming a second subset of memory cells to a first logic level comprises driving a second subset of word lines to a first gate voltage level having a second polarity.

[0097] At operation 440, in some embodiments, a third subset of memory cells in the first column are simultaneously programmed to a second logic level by activating the first select line and the first bit line. Simultaneously programming the third subset of memory cells in the first column of the memory array includes performing the above-described Figure 3 Operations 310 and 320 of method 300 are discussed.

[0098] In some embodiments, the above description of the memory circuit 100 and Figure 1A-1F As discussed, activating a first select line of a first column and a first bit line of the first column includes simultaneously activating select lines SL0 - SL4 and a corresponding one of bit lines BL0 - BL3 or BL1 - BL4 of a corresponding column C0 - C3 of the memory array 110 .

[0099] In some embodiments, simultaneously programming a third subset of memory cells to a second logic level by activating the first select line and the first bit line comprises driving the first select line and the first bit line to a second S / D voltage level having a second polarity. In some embodiments, simultaneously programming a third subset of memory cells to a second logic level comprises driving a third subset of word lines to a second gate voltage level having a first polarity.

[0100] At operation 450, in some embodiments, a fourth subset of memory cells in the first column are simultaneously programmed to a second logic level by activating the first select line and the second bit line. Simultaneously programming the fourth subset of memory cells in the first column of the memory array includes performing the above-described Figure 3 Operations 310 and 320 of method 300 are discussed.

[0101] In some embodiments, the above description of the memory circuit 100 and Figure 1A-1F As discussed, activating the first select line of the first column and the second bit line of the first column includes simultaneously activating select lines SL0 - SL4 and a corresponding one of bit lines BL0 - BL3 or BL1 - BL4 of a corresponding column C0 - C3 of the memory array 110 .

[0102] In some embodiments, simultaneously programming a fourth subset of memory cells to a second logic level by activating the first select line and the second bit line includes driving the first select line and the second bit line to a second S / D voltage level having a second polarity. In some embodiments, simultaneously programming a fourth subset of memory cells to a second logic level includes driving a fourth subset of word lines to a second gate voltage level having a first polarity.

[0103] In some embodiments, operations 420-450 are performed sequentially in any order, thereby programming each memory cell in the first column to a logic high level or a logic low level, or thereby programming a portion of the memory cells in the first column to one of a logic high level or a logic low level corresponding to a programming operation.

[0104] At operation 460, in some embodiments, each of the fifth, sixth, seventh, and eighth subsets of memory cells in the second column of the memory array is simultaneously programmed. Simultaneously programming each of the fifth, sixth, seventh, and eighth subsets of memory cells in the second column of the memory array includes simultaneously programming the fifth subset of memory cells in the second column of the memory array to a first logic level by activating a second select line of the second column and a third bit line of the second column, simultaneously programming the sixth subset of memory cells in the second column to a first logic level by activating the second select line and a fourth bit line of the second column, simultaneously programming the seventh subset of memory cells in the second column to a second logic level by activating the second select line and the third bit line, and simultaneously programming the eighth subset of memory cells in the second column to a second logic level by activating the second select line and the fourth bit line.

[0105] Simultaneously programming each of the fifth through eighth subsets of memory cells in the second column of the memory array includes performing the steps described above with respect to Figure 3Operations 310 and 320 of method 300 are discussed, such that the memory cells of the second column of the memory array are programmed in the manner discussed above with respect to operations 420-450.

[0106] At operation 470, in some embodiments, operation 460 is repeated for all columns of the memory array included in the programming operation. By repeating operation 460 for all columns, each memory cell in the memory array included in the programming operation, i.e., part or all of the memory cells in the memory array, is programmed to one of a logic high level or a logic low level.

[0107] In some embodiments, the memory array includes multiple layers of columns and rows, and repeating operation 460 includes repeating operation 460 on each of the multiple layers included in the programming operation.

[0108] By executing some or all of the operations of method 400, multiple cells in some or all of the columns of the memory array are programmed simultaneously in the first write operation and the second write operation, thereby achieving the benefits discussed above with respect to the memory circuit 100. In the case where the number of rows in the memory array programmed in the programming operation is greater than twice the number of columns programmed in the programming operation, the execution of method 400 results in fewer programming operations than a method that does not program multiple cells in the columns simultaneously, thereby reducing the total programming time.

[0109] Figure 5 is a flow chart of a method 500 for writing data to a memory array according to some embodiments. The method 500 may be used with a memory circuit, such as the one described above with respect to Figure 1A-1F A memory circuit 100 is discussed.

[0110] exist Figure 5 The order in which the operations of method 500 are described is for illustration only; the operations of method 500 can be performed simultaneously or in a sequential manner. Figure 5 In some embodiments, Figure 5 The operation shown in Figure 3 Performed before, between, during and / or after the indicated operations Figure 5 In some embodiments, the operations of method 500 are a subset of a method of operating an IC (e.g., a processor, logic, memory, or signal processing circuit, etc.). In some embodiments, the operations of method 500 are a subset of a method of performing memory array testing.

[0111] Figure 6A-6E is a schematic diagram of a memory array 600, Figure 7A-7H is a schematic diagram of a memory array 700, and Fig. 8A and Figure 8B8 is a schematic diagram of a memory array 800 according to some embodiments. In an embodiment including eight columns (not labeled) and six rows (not labeled), each of the memory arrays 600, 700, and 800 can be used as described above with respect to the memory circuits 100 and Figure 1A-1F The memory array 110 is discussed.

[0112] Figure 6A-6E , Figure 7A-7H , Fig. 8A and Figure 8B A non-limiting example corresponding to the operations of method 500 described below is depicted. Figure 6A-6E , Figure 7A-7H , Fig. 8A and Figure 8B In the , a logic high level is represented as "1" and a logic low level is represented as "0".

[0113] By performing some or all of the operations discussed below, method 500 includes executing an algorithm in which a plurality of cells in a single column are simultaneously programmed in a write operation based on identifying a subset of memory cells having a matching data pattern, and the identified subset of memory cells are simultaneously programmed in a program operation. The matching data pattern is obtained by accessing a memory device (e.g., as described above with respect to Figure 1A-Figure 1D The storage medium 144 discussed above is identified by the memory device being configured to store a plurality of data patterns included in a programming operation.

[0114] At operation 505, in some embodiments, in a storage device (eg, Figure 1A-Figure 1D In various embodiments, receiving the plurality of data patterns includes receiving the plurality of data patterns at the storage medium 144 discussed above. Fig. 6E , Figure 7H or Figure 8B The high and low logic levels in rows and columns are shown in one of the FIG.

[0115] At operation 510, in some embodiments, a plurality of data patterns are stored in a memory device. In various embodiments, storing the plurality of data patterns in the memory device includes storing the plurality of data patterns in the memory device in a memory circuit that includes a memory array or in a circuit external to the memory circuit that includes a memory array. In some embodiments, storing the plurality of data patterns in the memory device includes storing the plurality of data patterns in the memory device as described above with respect to memory circuit 100 and Figure 1A-1F In the storage medium 144 discussed.

[0116] The plurality of data patterns correspond to data configured to be written to a portion or all of the memory array in a programming operation. The plurality of data patterns correspond to an array, such as the entire memory array, such that each of the plurality of data patterns corresponds to one of the columns or rows of the array. In various embodiments, the respective relationship of each data pattern to one of the columns or rows is predetermined or determinable as part of retrieving the one or more data patterns from the memory device.

[0117] The memory device is configured to have an access time significantly faster than an access time included in a programming operation so that accessing multiple data patterns does not significantly affect the overall length of the programming operation. In some embodiments, the memory device includes an SRAM or DRAM structure.

[0118] At operation 520, a first data pattern is identified corresponding to a first subset of memory cells arranged in a first line extending in a first array dimension and located at a first position along a second array dimension. Identifying the first data pattern includes identifying a logic high pattern extending in the first line or a logic low pattern extending in the first line.

[0119] In some embodiments, the first line corresponds to a first column of memory cells, e.g., extending vertically, the first position corresponds to a first position in a row of memory cells, e.g., extending horizontally, and the first data pattern corresponds to a first subset of memory cells in the first column, e.g., coupled to the above-described Figure 1A-1F A first subset of memory cells 112 of first bit lines BL0 - BL4 of respective columns C0 - C3 is discussed.

[0120] In some embodiments, the first line corresponds to a first row of memory cells, the first position corresponds to a first position within a column of memory cells, and the first data pattern corresponds to a subset of memory cells in a word line of a first plurality of word lines, e.g., coupled to the memory cell described above with respect to Figure 1A-1F A first subset of memory cells 112 of each of columns C0 - C3 is discussed with respect to odd word lines WL1 , WL3 , and WL5 or even word lines WL0 , WL2 , and WL4 .

[0121] In some embodiments, the first line corresponds to Figure 6A-6E As shown in the top row of FIG, identifying the first data pattern includes identifying Fig. 6A The corresponding modes shown as low logic levels or in Figure 6C In some embodiments, the first line corresponds to Figure 7A-7H , identifying the first data pattern includes identifying Fig. 7A or Figure 7B In some embodiments, the first line corresponds to Fig. 8A and Figure 8B As shown in the leftmost column of , identifying the first data pattern includes identifying Fig. 8A The corresponding modes of low logic levels are shown.

[0122] In some embodiments, identifying the first data pattern based on the first line corresponding to one of the first column or the first row is based on a predetermined association of the data pattern with the column or row. In some embodiments, identifying the first data pattern based on the first line corresponding to one of the first column or the first row includes selecting a type corresponding to the column or row based on evaluating multiple data patterns.

[0123] In some embodiments, evaluating the plurality of data patterns includes comparing the number of programming operations based on each corresponding type. In some embodiments, evaluating the plurality of data patterns includes comparing the number of columns and rows, for example, determining that the number of rows of the memory array being programmed in the programming operation is greater than twice the number of columns of the memory array being programmed in the programming operation.

[0124] In some embodiments, identifying a first data pattern corresponding to a first subset of memory cells includes accessing a memory device, such as described below with respect to Figure 1A-Figure 1D 3 The storage medium 144 discussed above.

[0125] At operation 530, a second subset of memory cells corresponding to the first data pattern is identified, the second subset of memory cells being arranged in a second line extending along the first array dimension and located at a second position along the second array dimension. Identifying the second subset of memory cells corresponding to the first data pattern includes matching the second data pattern with the first data pattern, the second data pattern being associated with the second subset of memory cells.

[0126] In some embodiments, the second subset is a subset of a plurality of subsets, and identifying the second subset of memory cells corresponding to the first data pattern includes identifying a plurality of subsets corresponding to the first pattern, each subset of the plurality of subsets extending over the first array dimension and located at a corresponding position along the second array dimension.

[0127] In some embodiments, the second line corresponds to a second column of memory cells, and the second position corresponds to a second position in the row of memory cells. In some embodiments, the second column is one of a plurality of columns, and identifying a second subset of memory cells corresponding to the first data pattern includes identifying a subset of memory cells for each of the plurality of columns corresponding to the first data pattern. In some embodiments, identifying a subset of memory cells for each of the plurality of columns corresponding to the first data pattern includes identifying an entire subset of memory cells for each of the plurality of columns corresponding to the first data pattern included in the programming operation.

[0128] In some embodiments, identifying the second subset of memory cells corresponding to the first data pattern includes identifying Figure 1A-1F A first subset of memory cells 112 of columns C0-C3 is discussed.

[0129] In some embodiments, the second line corresponds to a second row of memory cells, the second position corresponds to a second position within a column of memory cells, and identifying the second subset of memory cells corresponding to the first data pattern includes the second row being one of the first plurality of rows. In some embodiments, the second row is one of the first plurality of rows, and identifying the second subset of memory cells corresponding to the first data pattern includes identifying a subset of memory cells for each of the first plurality of rows corresponding to the first data pattern. In some embodiments, identifying the subset of memory cells for each of the first plurality of rows corresponding to the first data pattern includes identifying the entire subset of memory cells for each of the plurality of rows corresponding to the first data pattern included in the programming operation.

[0130] In some embodiments, identifying a second subset of memory cells corresponding to the first data pattern comprises identifying Figure 1A-1F The memory cells 112 of the odd rows R1, R3 and R5 or the even rows R0, R2 and R4 are discussed.

[0131] In some embodiments, identifying the second subset of memory cells corresponding to the first data pattern includes accessing the memory device, for example, as described below with respect to Figure 1A-Figure 1D Storage medium 144 is discussed.

[0132] In some embodiments, identifying the second subset of memory cells corresponding to the first data pattern includes failing to identify the second subset of memory cells corresponding to the first data pattern.

[0133] In some embodiments, identifying the second subset of memory cells includes identifying Fig. 6A or Figure 6C In some embodiments, identifying the second subset of memory cells includes failing to identify the third and fifth rows of memory cells. Fig. 7A Additional rows or identification shown Figure 7B In some embodiments, identifying the second subset of memory cells includes identifying Fig. 8A The second to eighth columns shown in .

[0134] At operation 540, the first subset and the second subset of memory cells are simultaneously programmed to the first logic level or the second logic level. In various embodiments, programming the memory cells, such as the first subset and the second subset of memory cells, to the first logic level or the second logic level includes: the first logic level is a logic high level and the second logic level is a logic low level, or includes the first logic level is a logic low level and the second logic level is a logic high level.

[0135] In some embodiments, the second subset is a subset of the plurality of subsets identified in operation 530, and simultaneously programming the first subset and the second subset of memory cells to the first logic level includes simultaneously programming the plurality of subsets to the first logic level.

[0136] Programming the first and second subsets of memory cells simultaneously includes activating a select line and a first bit line for each column of memory cells included in the first and second subsets of memory cells and activating each word line of the first plurality of word lines.

[0137] In some embodiments, simultaneously programming the first subset and the second subset of memory cells to the first logic level comprises performing the Figure 3 Operations 310 and 320 of method 300 are discussed.

[0138] In some embodiments, wherein the second subset of memory cells is not identified as corresponding to the first data pattern, simultaneously programming the first subset and the second subset of memory cells includes programming the first subset of memory cells without programming the second subset of memory cells.

[0139] In some embodiments, simultaneously programming the first subset and the second subset of memory cells includes simultaneously programming Fig. 6A or Figure 6C In some embodiments, simultaneously programming the first subset and the second subset of memory cells includes simultaneously programming Fig. 7A The top row in the Figure 7B In some embodiments, simultaneously programming the first subset and the second subset of memory cells includes simultaneously programming Fig. 8A The leftmost column to the eighth column shown in .

[0140] At operation 550, in some embodiments, some or all of operations 520-540 are repeated until all memory cells of the memory array being programmed in the programming operation have been programmed to the first logic level or the second logic level.

[0141] Repeating operation 520 includes the first data pattern being a first data pattern different from the first data pattern previously identified by performing operation 520 or the first subset of memory cells being one or two of the first subset of memory cells different from the first subset of memory cells previously identified by performing operation 520. Thus, repeating operations 530 and 540 are based on a unique combination of the first data pattern and the first subset of memory cells.

[0142] In some embodiments, the first subset of memory cells corresponds to a column, and repeating some or all of operations 520-540 includes performing operations 520-540 sequentially, e.g., by column number, based on the first subset of memory cells in each column from the first column to the last column. In some embodiments, performing operations 520-540 based on the first subset of memory cells in each column from the first column to the last column includes bypassing a given column if all memory cells in the given column have been previously programmed.

[0143] In some embodiments, the first subset of memory cells corresponds to columns, and for a given column, repeating some or all of operations 520-540 includes performing operations 520-540 for each of four combinations of programming memory cells to logic high and low levels, and programming the first and second subsets of memory cells for a given column (e.g., odd and even rows).

[0144] In some embodiments, the first subset of memory cells corresponds to a row, and repeating some or all of operations 520-540 includes performing operations 520-540 sequentially, e.g., by row number, based on the first subset of memory cells in each of the first to last rows. In some embodiments, performing operations 520-540 based on the first subset of memory cells in each of the first to last rows includes bypassing a given row if all memory cells in the given row have been previously programmed.

[0145] In some embodiments, the first subset of memory cells corresponds to rows, and for a given column, repeating some or all of operations 520-540 includes performing operations 520-540 for each of two combinations of programming memory cells to logic high and logic low.

[0146] In some embodiments, repeating some or all of operations 520-540 includes programming memory array 600 by performing each of operations 520-540 based on a first subset of memory cells corresponding to a row, as in Figure 6A-6E shown. Fig. 6A Operations 520-540 are depicted being performed to program a first plurality of subsets of memory cells of a first plurality of rows to logic low levels. Figure 6BDepicted is performing operations 520-540 to program a first plurality of subsets of memory cells of a second plurality of rows to logic low levels. Figure 6C Depicted is performing operations 520-540 to program a second plurality of subsets of memory cells of the first plurality of rows to logic high levels. Fig.6D Operations 520-540 are depicted being performed to program a second plurality of subsets of memory cells of a second plurality of rows to logic high levels. Fig. 6E 6. Depicts memory array 600 after performing a programming operation by repeating some or all of operations 520-540 to match the memory array 600 stored in the memory device (eg, Figure 1A-Figure 1D Multiple data patterns in the storage medium 144 discussed.

[0147] In some embodiments, repeating some or all of operations 520-540 includes programming memory array 800 by performing each of operations 520-540 based on a first subset of memory cells corresponding to a column, such as Fig. 8A and Figure 8B shown. Fig. 8A Depicted is performing operations 520-540 to program a first plurality of subsets of memory cells of each column to a logic low level. Figure 6B Depicted performing operations 520-540 to program a second plurality of subsets of memory cells of each column to a logic high level, thereby completing a programming operation on the memory array 800 by repeating some or all of operations 520-540 to match the memory cells stored in the memory device (e.g., as described above with respect to Figure 1A-Figure 1D Multiple data patterns in the storage medium 144 discussed.

[0148] In some embodiments, at least a portion of the grounding is performed using the above description of the memory circuit 100 and Figure 1A-1F The control circuit 140 is discussed to at least partially perform some or all of the repetitive operations 520 - 540 .

[0149] In some embodiments, the memory array includes multiple layers of columns and rows, and repeating some or all of operations 520-540 includes repeating some or all of operations 520-540 on each of the multiple layers included in the programming operation.

[0150] By performing some or all of the operations of method 500, an algorithm is executed in which multiple cells in a single column are programmed simultaneously in a write operation, thereby achieving the advantages discussed above with respect to memory circuit 100. By identifying a subset of memory cells having a matching data pattern, and programming the identified subset of memory cells simultaneously in a programming operation, execution of method 500 results in fewer programming operations, thereby reducing the overall programming time, compared to methods that do not simultaneously program a subset of memory cells having a matching data pattern.

[0151] In some embodiments, a memory circuit includes: a memory array including a first column, the first column including a select line, a first bit line, and a second bit line, a first subset of memory cells coupled to the select line and the first bit line, and a second subset of memory cells coupled to the select line and the second bit line, and a control circuit, the control circuit being configured to simultaneously activate each of the select line and the first bit line, and during a period of time when the select line and the first bit line are simultaneously activated, activate a first plurality of word lines, wherein each word line of the first plurality of word lines is coupled to a memory cell of the first subset of memory cells. In some embodiments, the control circuit is configured to cause the second bit line to have a reference voltage level during a period when the select line and the first bit line are simultaneously activated. In some embodiments, each word line of the second plurality of word lines is coupled to a memory cell of the second subset of memory cells, and the control circuit is configured to cause the second plurality of word lines to have a reference voltage level during a period when the select line and the first bit line are simultaneously activated. In some embodiments, one of the first subset or the second subset of memory cells is disposed in memory cells of even rows of the memory array, and the other of the first subset or the second subset of memory cells is disposed in memory cells of odd rows of the memory array. In some embodiments, the control circuit is configured to simultaneously activate each of the select line and the first bit line by driving each of the select line and the bit line to an S / D voltage level having a first polarity, and to activate the first plurality of word lines by driving each of the first plurality of word lines to a gate voltage level having a second polarity opposite to the first polarity. In some embodiments, the S / D voltage level and the gate voltage level have the same magnitude. In some embodiments, each memory cell of the first subset and the second subset of memory cells comprises a FRAM cell.

[0152] In some embodiments, a method of writing data to a memory array includes programming a first subset of memory cells in a first column of the memory array to a first logic level simultaneously by activating a first select line of the first column and a first bit line of the first column, and programming a second subset of memory cells in the first column to the first logic level simultaneously by activating a first select line and a second bit line of the first column, wherein each memory cell of the memory array is a three-terminal memory cell. In some embodiments, the method includes programming a third subset of memory cells in the first column to a second logic level simultaneously by activating the first select line and the first bit line, and programming a fourth subset of memory cells in the first column to a second logic level simultaneously by activating the first select line and the second bit line. In some embodiments, each of activating the first select line and the first bit line and activating the first select line and the second bit line includes driving the first select line and the first bit line or the second bit line to a first S / D voltage level having a first polarity when the first subset or the second subset of memory cells is programmed to the first logic level, and driving the first select line and the first bit line or the second bit line to a second S / D voltage level having a second polarity when the third subset or the fourth subset of memory cells is programmed to the second logic level. In some embodiments, simultaneously programming a first subset of memory cells to a first logic level, and simultaneously programming a second subset of memory cells to a first logic level each comprises simultaneously driving a corresponding subset of word lines to a first gate voltage level having a second polarity, and simultaneously programming a third subset of memory cells to a second logic level and simultaneously programming a fourth subset of memory cells to a second logic level each comprises simultaneously driving a corresponding subset of word lines to a second gate voltage level having a first polarity. In some embodiments, the method comprises simultaneously programming a fifth subset of memory cells in a second column of the memory array to a first logic level by activating a second select line for the second column and a third bit line for the second column, simultaneously programming a sixth subset of memory cells in the second column to a first logic level by activating a second select line and a fourth bit line for the second column, simultaneously programming a seventh subset of memory cells in the second column to a second logic level by activating a second select line and a third bit line for the second column, and simultaneously programming an eighth subset of memory cells in the second column to a second logic level by activating a second select line and a fourth bit line for the second column. In some embodiments, each three-terminal memory cell of the memory array comprises a FRAM cell. In some embodiments, the method is part of a programming operation and includes, prior to simultaneously programming a first subset of memory cells and simultaneously programming a second subset of memory cells, determining that a number of rows of the memory array being programmed in the programming operation is greater than twice a number of columns of the memory array being programmed in the programming operation.

[0153] In some embodiments, a method of writing data to a memory array includes identifying a first data pattern corresponding to a first subset of memory cells arranged in a first line extending along a first array dimension and located at a first position along a second array dimension, identifying a second subset of memory cells corresponding to the first data pattern, the second subset of memory cells arranged in a second line extending along the first array dimension and located at a second position along the second array dimension, and simultaneously programming the first subset and the second subset of memory cells to a first logic level. In some embodiments, the first line and the second line correspond to a first column and a second column of memory cells, respectively, each of the first and second positions corresponds to a position within the row of memory cells, and simultaneously programming the first subset and the second subset of memory cells to the first logic level includes activating a select line and a first bit line in each of the first column and the second column. In some embodiments, the method includes: identifying a second data pattern of a third subset of memory cells corresponding to the first column of memory cells, identifying a fourth subset of memory cells corresponding to the second data pattern, the fourth subset of memory cells being included in a third column of memory cells at a third position in the row of memory cells, and simultaneously programming the third subset and the fourth subset of memory cells to a first logic level, simultaneously programming the third subset and the fourth subset of memory cells to the first logic level includes activating a select line and a second bit line in the first column. In some embodiments, the first line and the second line correspond to a first row and a second row of memory cells, respectively, each of the first position and the second position corresponds to a position within the column of memory cells, and simultaneously programming the first subset and the second subset of memory cells to the first logic level includes activating a select line and a first bit line of the column. In some embodiments, the method includes: identifying a second data pattern corresponding to a third subset of memory cells of a third row of memory cells located at a third position within the column, identifying a fourth subset of memory cells corresponding to the second data pattern, the fourth subset of memory cells being included in a fourth row of memory cells located at a fourth position within the column, and simultaneously programming the third subset and the fourth subset of memory cells to a first logic level, wherein simultaneously programming the third subset and the fourth subset of memory cells to the first logic level includes activating a select line and a second bit line in the column. In some embodiments, each of identifying the first data pattern corresponding to the first subset of memory cells and identifying the second data pattern corresponding to the first subset of memory cells includes accessing a memory device having stored write data including the first data pattern.

[0154] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present invention. It should be understood by those skilled in the art that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present invention.

Claims

1. A storage circuit, comprising: A memory array includes a first column, wherein the first column includes: Select the line; A first bit line and a second bit line; a first subset of memory cells coupled to the select line and the first bit line; and a second subset of memory cells coupled to the select line and the second bit line, wherein one of the first subset of memory cells or the second subset of memory cells is disposed in memory cells of even rows of the memory array, and the other of the first subset of memory cells or the second subset of memory cells is disposed in memory cells of odd rows of the memory array, and each memory cell of the first subset of memory cells and the second subset of memory cells is a ferroelectric random access memory cell; and The control circuit is configured as follows: activating each of the select line and the first bit line simultaneously, and During a period in which the select line and the first bit line are simultaneously activated, a first plurality of word lines are activated, wherein each word line of the first plurality of word lines is coupled to memory cells of a first subset of the memory cells.

2. The storage circuit according to claim 1, wherein: The control circuit is configured to cause the second bit line to have a reference voltage level during a period in which the selection line and the first bit line are simultaneously activated.

3. The storage circuit according to claim 1, wherein: Each word line of the second plurality of word lines is coupled to memory cells of a second subset of the memory cells, and The control circuit is configured to cause the second plurality of word lines to have a reference voltage level during a period in which the selection line and the first bit line are simultaneously activated.

4. The memory circuit according to claim 1, wherein: The ferroelectric random access memory cell includes one or more dielectric layers between a gate and each of two source / drains.

5. The memory circuit according to claim 1, wherein: The control circuit is configured to: simultaneously activating each of the select line and the first bit line by driving each of the select line and the bit line to a source / drain voltage level having a first polarity; and The first plurality of word lines are activated by driving each word line of the first plurality of word lines to a gate voltage level having a second polarity opposite the first polarity.

6. The memory circuit according to claim 5, wherein: The source / drain voltage level and the gate voltage level have the same magnitude.

7. The memory circuit according to claim 1, wherein: The first subset of memory cells and the second subset of memory cells are located at alternating positions in the first column.

8. A method for writing data into a memory array, the method comprising: simultaneously programming a first subset of memory cells in a first column of the memory array to a first logic level by activating a first select line of a first column of the memory array and a first bit line of the first column; simultaneously programming a second subset of memory cells in the first column to the first logic level by activating the first select line and a second bit line of the first column; simultaneously programming a third subset of memory cells in the first column to a second logic level by activating the first select line and the first bit line; and simultaneously programming a fourth subset of memory cells in the first column to the second logic level by activating the first select line and the second bit line, Wherein, each memory cell of the memory array is a three-terminal ferroelectric random access memory cell.

9. The method according to claim 8, wherein: The three-terminal ferroelectric random access memory cell includes one or more dielectric layers between a gate and each of two source / drains.

10. The method according to claim 8, wherein: Each of the activating the first selection line and the first bit line and the activating the first selection line and the second bit line includes: driving the first select line and the first bit line or the second bit line to a first source / drain voltage level having a first polarity when the first subset of the memory cells or the second subset of the memory cells are programmed to the first logic level; and When the third subset of the memory cells or the fourth subset of the memory cells are programmed to the second logic level, the first select line and the first bit line or the second bit line are driven to a second source / drain voltage level having a second polarity.

11. The method according to claim 10, wherein: The simultaneously programming the first subset of the memory cells to the first logic level and the simultaneously programming the second subset of the memory cells to the first logic level each include simultaneously driving a corresponding subset of word lines to a first gate voltage level having the second polarity, and The simultaneously programming the third subset of the memory cells to the second logic level and the simultaneously programming the fourth subset of the memory cells to the second logic level each include simultaneously driving a corresponding subset of word lines to a second gate voltage level having the first polarity.

12. The method according to claim 8, further comprising: simultaneously programming a fifth subset of memory cells in a second column of the memory array to the first logic level by activating a second select line of a second column of the memory array and a third bit line of the second column; simultaneously programming a sixth subset of memory cells in the second column to the first logic level by activating the second select line and a fourth bit line of the second column; simultaneously programming a seventh subset of memory cells in the second column to the second logic level by activating the second select line and the third bit line; as well as An eighth subset of memory cells in the second column are simultaneously programmed to the second logic level by activating the second select line and the fourth bit line.

13. The method according to claim 8, wherein: The first subset of memory cells and the second subset of memory cells are located at alternating positions in the first column.

14. The method according to claim 8, wherein: The method is part of a programming operation, and The method also includes, prior to simultaneously programming the first subset of the memory cells and simultaneously programming the second subset of the memory cells, determining that a number of rows of the memory array programmed in the programming operation is greater than twice a number of columns of the memory array programmed in the programming operation.

15. A method for writing data into a memory array, the method comprising: identifying a first data pattern corresponding to a first subset of memory cells, each memory cell of the first subset of memory cells being a ferroelectric random access memory cell and the first subset of memory cells being arranged in a first line extending along a first array dimension and being located at a first position along a second array dimension; identifying a second subset of memory cells corresponding to the first data pattern, each memory cell of the second subset of memory cells being a ferroelectric random access memory cell, and the second subset of memory cells being arranged in a second line extending along the first array dimension and being located at a second position along the second array dimension; as well as simultaneously programming a first subset of the memory cells and a second subset of the memory cells to a first logic level; wherein the first line and the second line correspond to a first column of memory cells and a second column of memory cells, respectively, each of the first position and the second position corresponds to a position within a row of memory cells, and the simultaneously programming the first subset of memory cells and the second subset of memory cells to the first logic level comprises activating a select line and a first bit line in each of the first column and the second column; or The first line and the second line correspond to a first row and a second row of memory cells, respectively, each of the first position and the second position corresponds to a position in a column of memory cells, and simultaneously programming the first subset of the memory cells and the second subset of the memory cells to the first logic level includes activating a selection line and a first bit line of the column.

16. The method according to claim 15, wherein: The ferroelectric random access memory cell includes one or more dielectric layers between a gate and each of two source / drains.

17. The method of claim 15, wherein the first line and the second line correspond to a first column of memory cells and a second column of memory cells, respectively, the method further comprising: identifying a second data pattern corresponding to a third subset of memory cells of the memory cells of the first column; identifying a fourth subset of memory cells corresponding to the second data pattern, the fourth subset of memory cells being included in a third column of memory cells located at a third position within the row of memory cells; as well as Simultaneously programming the third subset of the memory cells and the fourth subset of the memory cells to the first logic level includes activating the select line and the second bit line in the first column.

18. The method according to claim 15, wherein: The first logic level is a logic high level.

19. The method of claim 15, wherein the first line and the second line correspond to a first row and a second row of memory cells, respectively, the method further comprising: identifying a second data pattern corresponding to a third subset of the memory cells of the memory cells of a third row of memory cells located at a third position within the column; identifying a fourth subset of memory cells corresponding to the second data pattern, the fourth subset of memory cells being included in a fourth row of memory cells at a fourth position within the column; as well as Concurrently programming a third subset of the memory cells and a fourth subset of the memory cells to the first logic level includes activating the select line and a second bit line in the column.

20. The method according to claim 15, wherein: The identifying the first data pattern corresponding to a first subset of the memory cells and the identifying the second subset of the memory cells corresponding to the first data pattern each include accessing a storage device having stored write data including the first data pattern.

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