Semiconductor structure and manufacturing method

Abstract

This disclosure relates to semiconductor structures and methods for manufacturing the same. By bonding a pre-formed mold (e.g., a fine / thin post) for defining via openings and a first fan-out layer to an adhesive layer on a substrate, and by removing the mold for defining the via openings to define a first via opening in the first fan-out layer, then removing a portion of the adhesive layer through plasma etching to expose a substrate pad to define a second via opening, and finally filling the first and second via openings with conductive material to form vias that electrically connect the first fan-out layer and the substrate, the stability of the semiconductor structure is improved, which is beneficial for improving product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor structures and their manufacturing methods. Background Technology

[0002] Semiconductor wafer manufacturing capabilities improve year after year, and semiconductor substrate manufacturing capabilities must keep pace to meet the requirements of chip-substrate interfacing. FOCoS (Fan-Out Chip on Substrate) is currently the main method for combining Fan-Out and Substrate. FOSub (Fan-Out Substrate) is another method for combining Fan-Out and Substrate, which uses an adhesive film to bond the Fan-Out (RDL layer) and Substrate, and then uses vias to connect the electrical channels between the Fan-Out and Substrate.

[0003] In current FOSub (Fan Out Substrate) processes, after the fan-out structure is fixed to the substrate with an adhesive film, vias are then created. However, this is limited by the current capabilities of laser processing (minimum aperture and maximum depth), making it impossible to fabricate small apertures or achieve the required depth in a single pass. If plasma etching is used, side etching can occur, resulting in abnormal via walls. Furthermore, the quality of the via fabrication affects the electrical connection between the redistribution layer and the substrate, impacting the stability of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides semiconductor structures and methods for manufacturing them.

[0005] In a first aspect, this disclosure provides a semiconductor structure comprising: a substrate having a pad; an adhesive layer disposed on the substrate; a first redistribution layer disposed on the adhesive layer; and at least one via, the via including a second via and a first via disposed from bottom to top, the first via extending from the first redistribution layer to the adhesive layer, and the second via extending from the adhesive layer to the pad of the substrate.

[0006] In some alternative implementations, the lower end faces of each first through hole are located at the same horizontal position.

[0007] In some alternative implementations, the heights of the second vias are different.

[0008] In some alternative implementations, the first via includes a first seed layer, a second seed layer, and a conductive post.

[0009] In some alternative implementations, the second via includes a second seed layer and a conductive post.

[0010] In some alternative implementations, the diameter of the lower opening of the first through hole is larger than the diameter of the second through hole.

[0011] In some alternative implementations, the second via gradually expands and then gradually contracts in the direction toward the substrate.

[0012] In some alternative embodiments, the semiconductor structure further includes: a second adhesive layer disposed on the first redistribution layer; a second redistribution layer disposed on the second adhesive layer; and a third via electrically connecting the first redistribution layer and the second redistribution layer.

[0013] In some alternative implementations, the semiconductor structure further includes: electronic components electrically connected to the first and / or second wiring layers; and an underfill material to fill the gap between the electronic components and the second wiring layer.

[0014] In a second aspect, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising: providing a carrier including a via opening mold, a release layer, a first seed layer, and a first redistribution layer; bonding the carrier to a substrate by an adhesive layer, the substrate having a pad; removing the via opening mold and the release layer to define a first via opening extending from the first redistribution layer to the adhesive layer; removing a portion of the adhesive layer to expose the pad to define a second via opening extending from the adhesive layer to the substrate; and sequentially forming a second seed layer and a conductive pillar in the first via opening and the second via opening to form a via electrically connecting the first redistribution layer and the substrate.

[0015] In some alternative embodiments, the carrier is formed by the following steps: providing a wafer; etching the wafer to form a via opening mold; sequentially forming a release layer, a first seed layer, and a first redistribution layer on the via opening mold; etching a portion of the first seed layer to expose the tip of the release layer, thereby forming a carrier comprising the via opening mold, the release layer, the first seed layer, and the first redistribution layer arranged sequentially.

[0016] In some alternative embodiments, the method further includes: providing a second wiring layer; bonding the second wiring layer to the first wiring layer via a second adhesive layer; and forming a third via on the second wiring layer to electrically connect the first wiring layer and the second wiring layer.

[0017] To address the limitations of current laser processing capabilities (minimum aperture and maximum depth) in via opening, which prevents the fabrication of small apertures and the achievement of the required depth in a single pass, and to mitigate the issues of side etching and abnormal hole walls caused by plasma etching, this disclosure provides a semiconductor structure and manufacturing method that combines a pre-formed mold (e.g., a fine / thin post) for defining via openings with a first fan-out layer on an adhesive layer on a substrate. The mold is then removed to define a first via opening on the first fan-out layer. Plasma etching is then used to remove a portion of the adhesive layer, exposing a substrate pad, to define a second via opening. Finally, conductive material is filled into both the first and second via openings to form vias that electrically connect the first fan-out layer and the substrate. This improves the stability of the semiconductor structure and increases product yield. In addition, by removing part of the adhesive layer through plasma etching to expose the substrate pads, the second via opening is defined. This facilitates contact between the bottom of the via and the pads with inconsistent thicknesses, avoiding various electrical connection problems caused by inconsistent pad thicknesses on the substrate. Attached Figure Description

[0018] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0019] Figures 1-10 These are first to tenth structural schematic diagrams of an embodiment of the semiconductor structure according to the present disclosure;

[0020] Figures 11A to 11H This is a schematic diagram of the manufacturing process of the semiconductor structure according to the present disclosure.

[0021] Symbol explanation:

[0022] 1-Substrate, 2-Adhesive layer, 21-Particle, 3-First redistribution layer, 4-Through hole, 41-First through hole, 411-First seed layer, 412-Second seed layer, 413-Conductive pillar, 42-Second through hole, 5-Second adhesive layer, 6-Second redistribution, 7-Third through hole, 8-Electronic component, 9-Carrier, 91-Wafer, 92-Through hole opening mold, 93-Release layer, 10-Bottom filler, 11-Wire, 12-Multilayer redistribution layer. Detailed Implementation

[0023] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0024] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0025] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] Please refer to Figures 1-10 , Figures 1-10 A first to a tenth structural schematic diagram of an embodiment of a semiconductor structure according to the present disclosure are shown.

[0027] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor structure may include: a substrate 1, an adhesive layer 2, a first redistribution layer 3, and at least one via 4. The substrate 1 has a pad. The adhesive layer 2 is disposed on the substrate 1. The first redistribution layer 3 is disposed on the adhesive layer 2. The via 4 includes a second via 42 and a first via 41 disposed from bottom to top. The first via 41 extends from the first redistribution layer 3 to the adhesive layer 2, and the second via 42 extends from the adhesive layer 2 to the pad of the substrate 1.

[0028] Substrate 1 may include organic and / or inorganic materials. Organic materials may include, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin / prepreg), ABF (Ajinomoto Build-up Film), etc. Inorganic materials may include, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. Substrate 1 may also be a PCB (Printed Circuit Board).

[0029] Adhesive layer 2 can be a structural layer that serves to bond structures together.

[0030] The first wiring layer 3 can include various conductors, vias, buried vias, or blind vias to achieve circuit connections. It should be noted that there are no specific limitations on the size or orientation of the vias, buried vias, or blind vias. If vias, buried vias, or blind vias are provided, they can be filled with conductive materials such as metals or metal alloys, or contain conductive materials such as metals or metal alloys. Here, the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0031] The via 4 enables electrical connection between the substrate 1 and the first redistribution layer 3.

[0032] In some alternative implementations, such as Figure 1 As shown, the lower end faces of each first through hole 41 can be located at the same horizontal position.

[0033] Here, since the first through hole 41 is defined by a pre-formed mold for defining the opening of the through hole 4, the mold may have at least one thin column of the same height, so the height of each defined first through hole 41 is the same, and the lower end face of each first through hole 41 may be located at the same horizontal position.

[0034] In some alternative implementations, such as Figure 1 As shown, the height of each second through hole 42 can be different.

[0035] Here, since the pad thickness of the substrate 1 is inconsistent, part of the adhesive layer 2 is removed by plasma etching to expose the pad of the substrate 1. The height of the defined second via 42 can be different to expose pads with inconsistent thickness.

[0036] In some alternative implementations, such as Figure 1 As shown, the first via 41 may include a first seed layer 411, a second seed layer 412, and a conductive post 413.

[0037] Here, the first via 41 is defined in the first redistribution layer 3, which is pre-formed and includes a first seed layer 411 during the pre-formation process.

[0038] In some alternative implementations, such as Figure 1 As shown, the second via 42 may include a second seed layer 412 and a conductive post 413.

[0039] In some alternative implementations, such as Figure 10 As shown, the diameter of the lower opening of the first through hole 41 can be larger than the diameter of the second through hole 42.

[0040] In some alternative implementations, such as Figure 10 As shown, the second via 42 can gradually expand and then gradually contract in the direction toward the substrate 1.

[0041] In some alternative implementations, such as Figure 2 As shown, the semiconductor structure may further include a second adhesive layer 5. The second adhesive layer 5 may be disposed on the first redistribution layer 3. The second redistribution layer 6 may be disposed on the second adhesive layer 5. The third via 7 may electrically connect the first redistribution layer 3 and the second redistribution layer 6.

[0042] In some alternative implementations, such as Figure 5 As shown, the semiconductor structure may further include electronic components 8 and underfill material 10. Electronic components 8 may be electrically connected to the first rewiring layer 3 and / or the second rewiring layer 6. Underfill material 10 may fill the gap between electronic components 8 and the second rewiring layer 6.

[0043] In some alternative implementations, such as Figure 6 As shown, the semiconductor structure may also include a wire 11. Electrical connections can be formed by bonding the two ends of the wire 11 to the electronic component 8 and the second wiring layer 6, respectively.

[0044] In some alternative implementations, such as Figure 3 As shown, the first rewiring layer 3 can be a multi-layer rewiring layer 12.

[0045] In some alternative implementations, such as Figure 4 As shown, substrate 1 can be a redistribution layer.

[0046] In some alternative implementations, such as Figure 7As shown, the adhesive layer 2 may also include particles 21. The particles may be, for example, fillers to enhance structural strength.

[0047] In some alternative implementations, such as Figure 8 As shown, the conductive post 413 can be partially filled; for example, a through hole can be provided in the center of the conductive post 413. This can save costs and avoid the problem of voids that easily occur when fully filled, which can affect the electrical performance.

[0048] In some alternative implementations, such as Figure 9 As shown, the upper aperture D of via 4 can be between 10 micrometers and 20 micrometers, the lower aperture d of via 4 can be between 3 micrometers and 10 micrometers, and the ratio of the upper aperture D to the lower aperture d of via 4 is between 0.65 and 1. The thickness t1 of the first redistribution layer 3 can be between 3 micrometers and 10 micrometers, the thickness t2 of the adhesive layer 2 can be between 10 micrometers and 40 micrometers, the distance A from the adhesive layer 2 to the substrate 1 can be between 20 micrometers and 60 micrometers, the thickness h of the pad can be between 5 micrometers and 20 micrometers, the height p of the first via 41 in the adhesive layer 2 is between 5 micrometers and 30 micrometers, and the height k of the second via 42 is between 5 micrometers and 20 micrometers. The sidewall angle θ of the via 4 is between 30 degrees and 80 degrees, and the ratio between the sum of the thickness t1 of the first redistribution layer 3 and the thickness t2 of the adhesive layer 2 and the upper opening diameter D of the via 4 is between 0.65 and 5.

[0049] The semiconductor structure provided in this disclosure improves the stability of the semiconductor structure and improves product yield by bonding a pre-formed mold (e.g., fine / thin post) for defining via openings 4 and a first redistribution layer 3 (Fan-Out) to an adhesive layer 2 on a substrate 1. A first via opening 41 is defined on the first redistribution layer 3 by removing the via opening mold 92. A portion of the adhesive layer 2 is then removed by plasma etching to expose the pads on the substrate 1, defining a second via opening 42. Finally, conductive material is filled into the first and second via openings 41 and 42 to form vias 4 that electrically connect the first redistribution layer 3 and the substrate 1. This improves product yield. Furthermore, removing a portion of the adhesive layer 2 by plasma etching to expose the pads on the substrate 1 and define the second via opening 42 facilitates contact between the bottom of the via opening 4 and pads of inconsistent thickness, avoiding various electrical connection problems caused by inconsistent pad thickness on the substrate 1.

[0050] Figures 11A to 11H This is a schematic diagram of the manufacturing process of the semiconductor structure according to the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure.

[0051] Please refer to Figure 11D A carrier 9 is provided, which may include a through-hole opening mold 92, a release layer 93, a first seed layer 411, and a first rewiring layer 3.

[0052] In some alternative implementations, please refer to Figures 11A-11D The carrier 9 can be formed by the following steps: providing a wafer 91 ( Figure 11A ). Etch wafer 91 to form via opening mold 92 ( ). Figure 11B A release layer 93, a first seed layer 411, and a first rewiring layer 3 are sequentially formed on the through-hole opening mold 92. Figure 11C The first seed layer 411 is etched to expose the tip of the release layer 93, forming a carrier 9 for the via opening mold 92, the release layer 93, the first seed layer 411, and the first redistribution layer 3. Figure 11D ).

[0053] Please refer to Figure 11E The carrier 9 is bonded to the substrate 1 by the adhesive layer 2, and the substrate 1 has a pad.

[0054] Please refer to Figure 11F Remove the via opening mold 92 and the release layer 93 to define the first via opening extending from the first redistribution layer 3 to the adhesive layer 2. Remove a portion of the adhesive layer 2 to expose the gasket to define the second via opening extending from the adhesive layer 2 to the substrate 1.

[0055] Please refer to Figure 11G A second seed layer 412 and a conductive pillar 413 are sequentially formed in the first and second via openings to form a via 4 that electrically connects the first redistribution layer 3 and the substrate 1.

[0056] In some alternative implementations, please refer to Figure 11H The method may further include: providing a second rewiring layer 6; bonding the second rewiring layer 6 to the first rewiring layer 3 via a second adhesive layer 5; and forming a third via 7 in the second rewiring layer 6 to electrically connect the first rewiring layer 3 and the second rewiring layer 6.

[0057] The method in this embodiment can achieve similar technical effects to the semiconductor packaging structure in the previous embodiments, and will not be described again here.

[0058] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor structure, comprising: The substrate has a pad; An adhesive layer is disposed on the substrate; The first wiring layer is disposed on the adhesive layer; At least one via is provided, the via including a second via and a first via disposed from bottom to top, the first via extending from the first redistribution layer to the adhesive layer, the second via extending from the adhesive layer to the pad of the substrate, the lower end faces of each of the first vias being located at the same horizontal position, wherein the first via includes a first seed layer, a second seed layer and a conductive pillar.

2. The semiconductor structure according to claim 1, wherein, The heights of the second through holes are different.

3. The semiconductor structure according to claim 1 or 2, wherein, The second via includes the second seed layer and the conductive post.

4. The semiconductor structure according to claim 1 or 2, wherein, The second via gradually expands and then gradually contracts in the direction toward the substrate.

5. The semiconductor structure according to claim 1 or 2, wherein, The semiconductor structure also includes: The second adhesive layer is disposed on the first rewiring layer; A second wiring layer is disposed on the second adhesive layer; The third via electrically connects the first and second wiring layers.

6. The semiconductor structure according to claim 5, wherein, The semiconductor structure also includes: Electronic components, electrically connected to the first and / or second wiring layers; Bottom filler material fills the gap between the electronic component and the second rewiring layer.

7. A method for manufacturing a semiconductor structure, comprising: A carrier is provided, the carrier comprising a through-hole opening mold, a release layer, a first seed layer, and a first rewiring layer; The carrier is bonded to the substrate by an adhesive layer, wherein the substrate has a gasket; Remove the via opening mold and the release layer to define a first via opening extending from the first redistribution layer to the adhesive layer; Remove a portion of the adhesive layer to expose the gasket, thereby defining a second via opening extending from the adhesive layer to the substrate; A second seed layer and a conductive pillar are sequentially formed in the first and second via openings to form a via that electrically connects the first redistribution layer and the substrate.

8. The method according to claim 7, wherein, The carrier is formed through the following steps: Provide wafers; The wafer is etched to form the via opening mold; The release layer, the first seed layer, and the first rewiring layer are sequentially formed on the through hole opening mold; A portion of the first seed layer is etched to expose the tip of the release layer, thereby forming a carrier of the via opening mold, the release layer, the first seed layer, and the first redistribution layer arranged sequentially.

9. The method according to claim 7 or 8, wherein, The method further includes: Provide a second wiring layer; The second rewiring layer is bonded to the first rewiring layer by a second adhesive layer; A third via is formed on the second overlay layer to electrically connect the first overlay layer and the second overlay layer.

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