Memory device with shared access line for 2-transistor vertical memory cell

Abstract

Some embodiments include devices and methods of forming the devices. One of the devices includes a memory cell located above a substrate and a first data line, a second data line, and a third data line. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the device and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the device and electrically coupled to the charge storage structure. The first data line and the second data line are located on a third level of the device and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Provisional Application No. 62 / 785,150, filed on December 26, 2018, which is incorporated herein by reference in its entirety. Background Art

[0003] Memory devices are widely used in computers and many other electronic items to store information. Memory devices are generally classified into two types: volatile memory devices and non-volatile memory devices. Examples of volatile memory devices include dynamic random access memory (DRAM) devices. Examples of non-volatile memory devices include flash memory devices (e.g., flash memory sticks). Memory devices generally have many memory cells to store information. In volatile memory devices, if the power supply is disconnected from the memory device, the information stored in the memory cells is lost. In non-volatile memory devices, the information stored in the memory cells is retained even if the power supply is disconnected from the memory device.

[0004] The description herein relates to volatile memory devices. Most conventional volatile memory devices store information in the form of electric charge in a capacitor structure contained in a memory cell. As the demand for device storage density increases, many conventional techniques provide ways to reduce the size of the memory cell in order to increase the device storage density for a given device area. However, if the memory cell size is reduced to a certain size, then physical limitations and manufacturing constraints may pose challenges to such conventional techniques. Unlike some conventional memory devices, the memory devices described herein include features that can overcome the challenges faced by conventional techniques. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A block diagram is shown of an apparatus in the form of a memory device including volatile memory cells according to some embodiments described herein.

[0006] Figure 2 A schematic diagram showing a portion of a memory device including a memory array of two-transistor (2T) memory cells according to some embodiments described herein.

[0007] Figure 3 A diagram showing example voltages used during a read operation of a memory device according to some embodiments described herein Figure 2 Memory device.

[0008] Figure 4 Demonstrating some embodiments described herein Figure 2A memory device of the invention is provided, including example voltages used during a write operation of the memory device.

[0009] Figure 5 , Figure 6 , Figure 7 and Figure 8 Demonstrating some embodiments described herein Figure 2 Different views of the structure of a memory device.

[0010] Figures 9 to 19 A process of forming a memory device according to some embodiments described herein is shown.

[0011] Fig. 20 Demonstrating that a method for forming a Figures 9 to 19 A variation of the process of a memory device is used to form another memory device.

[0012] Fig.21A , Fig.21B and Fig. 21C Different views of the structure of a memory device including multiple stacks of memory cells according to some embodiments described herein are shown. DETAILED DESCRIPTION

[0013] The memory devices described herein include volatile memory cells, wherein each of the memory cells may include two transistors (2T). One of the two transistors has a charge storage structure that may form a memory element of the memory cell to store information. The memory devices described herein may have a structure that allows the size of the memory device to be relatively smaller than the size of similar conventional memory devices (e.g., a 4F2 cell footprint). The described memory devices may include signal access lines to control the two transistors of the memory cell. This may reduce power consumption and improve processing. Reference is made below to Figures 1 to 20 Other improvements and benefits of the described memory device and variations thereof are discussed.

[0014] Figure 1A block diagram of an apparatus in the form of a memory device 100 including volatile memory cells according to some embodiments described herein is shown. The memory device 100 includes a memory array 101, which may contain memory cells 102. The memory device 100 is a volatile memory device (e.g., a DRAM device), such that the memory cells 102 are volatile memory cells. Therefore, if a power source (e.g., a power supply voltage Vcc) is disconnected from the memory device 100, the information stored in the memory cell 102 may be lost (e.g., invalid). Hereinafter, Vcc is referred to as representing some voltage level, however, it is not limited to the power supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator ( Figure 1 Not shown), then such internal voltage can be used instead of Vcc.

[0015] In the physical structure of the memory device 100, each of the memory cells 102 may include transistors (e.g., two transistors) vertically formed in different levels (e.g., stacked on top of each other in different layers) above a substrate (e.g., a semiconductor substrate) of the memory device 100. The structure of the memory array 101 including the memory cells 102 may include the following reference Figures 2 to 20 Describes the structure of the memory array and memory cells.

[0016] like Figure 1 , memory device 100 can include access lines (e.g., word lines) 104 and data lines (e.g., bit lines) 105. Memory device 100 can use signals on access lines 104 (e.g., word line signals) to access memory cells 102, and use signals on data lines 105 to provide information (e.g., data) to be stored (e.g., written) in memory cells 102 or read (e.g., sensed) from memory cells 102.

[0017] The memory device 100 may include an address register 106 to receive address information ADDR (e.g., row address signals and column address signals) on lines (e.g., address lines) 107. The memory device 100 may include a row access circuit system (e.g., X-decoder) 108 and a column access circuit system (e.g., Y-decoder) 109 that may be used to decode the address information ADDR from the address register 106. Based on the decoded address information, the memory device 100 may determine which memory cells 102 to access during a memory operation. The memory device 100 may perform a write operation to store information in the memory cell 102, and perform a read operation to read (e.g., sense) the information in the memory cell 102 (e.g., previously stored information). The memory device 100 may also perform an operation (e.g., a refresh operation) to refresh the value of the information stored in the memory cell 102 (e.g., to keep it valid). Each of memory cells 102 may be configured to store information that may represent at most one bit (e.g., a single bit having binary zero (“0”) or binary one (“1”), or more than one bit (e.g., multiple bits having a combination of at least two binary bits).

[0018] Memory device 100 may receive supply voltages on lines 130 and 132, respectively, including supply voltages Vcc and Vss. Supply voltage Vss may operate at ground potential (e.g., having a value of substantially zero volts). Supply voltage Vcc may include an external voltage supplied to memory device 100 from an external power source such as a battery or alternating current to direct current (AC-DC) converter circuitry.

[0019] like Figure 1 , the memory device 100 may include a memory control unit 118 that includes circuitry (e.g., hardware components) to control memory operations (e.g., read and write operations) of the memory device 100 based on control signals on lines (e.g., control lines) 120. Examples of signals on lines 120 include a row access select signal RAS*, a column access select signal CAS*, a write enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock enable signal CKE. These signals may be part of the signals provided to the DRAM device.

[0020] like Figure 1, memory device 100 can include lines (e.g., global data lines) 112 that can carry signals DQ0-DQN. In a read operation, the value of the information (read from memory cell 102) provided to line 112 (in the form of signals DQ0-DQN) (e.g., a "0" or a "1") can be based on the value of the signal on data line 105. In a write operation, the value of the information (e.g., a "0" or a "1") provided to data line 105 (to be stored in memory cell 102) can be based on the value of signals DQ0-DQN on line 112.

[0021] Memory device 100 may include sensing circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. Column access circuitry 109 may selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Selection circuitry 115 may respond to signals on lines 114 to select signals on data lines 105. The signals on data lines 105 may represent the value of information to be stored in memory cell 102 (e.g., during a write operation) or the value of information to be read (e.g., sensed) from memory cell 102 (e.g., during a read operation).

[0022] I / O circuitry 116 may be operable to provide information read from memory cell 102 to line 112 (e.g., during a read operation) and to provide information from line 112 (e.g., provided by an external device) to data line 105 for storage in memory cell 102 (e.g., during a write operation). Line 112 may include a node within memory device 100 or a pin (or solder ball) on a package in which memory device 100 may reside. Other devices external to memory device 100 (e.g., a hardware memory controller or a hardware processor) may communicate with memory device 100 via lines 107, 112, and 120.

[0023] The memory device 100 may include other components. Figure 1 At least a portion of the memory device 100 (eg, a portion of the memory array 101) may include the same memory device 100 as described below. Figures 2 to 20 Similar or identical structure and operation to any of the memory devices described.

[0024] Figure 2 A schematic diagram showing a portion of a memory device 200 including a memory array 201 according to some embodiments described herein. The memory device 200 may correspond to Figure 1 For example, the memory array 201 may be formed Figure 1 A portion of the memory array 101. Figure 2, memory device 200 may include memory cells 210-215, which are volatile memory cells (eg, DRAM cells). For simplicity, similar or identical elements among memory cells 210-215 are given the same labels.

[0025] Each of the memory cells 210 to 215 may include two transistors T1 and T2. Therefore, each of the memory cells 210 to 215 may be referred to as a 2T memory cell (e.g., a 2T gain cell). Each of the transistors T1 and T2 may include a field effect transistor (FET). The transistor T1 may include a charge storage-based structure (e.g., a floating gate-based structure). Figure 2 As shown in FIG. 1 , each of the memory cells 210 to 215 may include a charge storage structure 202, which may include a floating gate of a transistor T1. The charge storage structure 202 may form a memory element of a corresponding memory cell among the memory cells 210 to 215. The charge storage structure 202 may store charge. The value of the information stored in a particular memory cell among the memory cells 210 to 215 (e.g., "0" or "1") may be based on the amount of charge in the charge storage structure 202 of the particular memory cell.

[0026] like Figure 2 , the transistor T2 (e.g., the channel region of the transistor T2) of a particular memory cell among the memory cells 210-215 may be electrically coupled to (e.g., directly coupled to) the charge storage structure 202 of the particular memory cell. Thus, a circuit path (e.g., a current path) may be formed directly between the transistor T2 of the particular memory cell and the charge storage structure 202 of the particular memory cell during operation (e.g., a write operation) of the memory device 200.

[0027] Memory cells 210 to 215 may be arranged in memory cell groups 2010 and 2011. As an example, Figure 2 Two memory cell groups (e.g., 2010 and 2011) are shown. However, memory device 200 may include more than two memory cell groups. Memory cell groups 2010 and 2011 may include the same number of memory cells. For example, memory cell group 2010 may include memory cells 210, 212, and 214, and memory cell group 2011 may include memory cells 211, 213, and 215. As an example, Figure 2 Three memory cells are shown in each of memory cell groups 2010 and 2011. The number of memory cells in memory cell groups 2010 and 2011 may be different than three.

[0028] The memory device 200 may perform a write operation to store information in the memory cells 210 to 215, and perform a read operation to read (e.g., sense) information from the memory cells 210 to 215. The memory device 200 may be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure such as a container of a capacitor, the memory device 200 may store information in the form of charge in a charge storage structure 202 (which may be a floating gate structure). As mentioned above, the charge storage structure 202 may include a floating gate of the transistor T1. Therefore, the memory device 200 may be referred to as a floating gate-based DRAM device.

[0029] like Figure 2 , the memory device 200 may include access lines (e.g., word lines) 241, 242, and 243 that may carry respective signals (e.g., word line signals) WL1, WL2, and WLn. The access lines 241, 242, and 243 may be used to access both memory cell groups 2010 and 2011. Each of the access lines 241, 242, and 243 may be configured as at least one conductive line (e.g., one conductive line or multiple conductive lines that may be electrically coupled to each other (e.g., shorted)). The access lines 241, 242, and 243 may be selectively activated (e.g., activated one at a time) during operation (e.g., read or write operation) of the memory device 200 to access one or more selected memory cells among the memory cells 210 to 215. The selected cells may be referred to as target cells. In a read operation, information may be read from the one or more selected memory cells. In a write operation, information may be stored in the one or more selected memory cells.

[0030] In the memory device 200, a single access line (e.g., a single word line) may be used to control (e.g., turn on or off) the transistors T1 and T2 of the respective memory cells during a read or write operation of the memory device 200. Two separate access lines may be used to control the respective transistors T1 and T2 during access to the respective memory cells during read and write operations. However, using a shared access line (e.g., a single access line) in the memory device 200 to control both the transistors T1 and T2 of the respective memory cells may save space and simplify the operation of the memory device 200.

[0031] In memory device 200, the gate of each of transistors T1 and T2 may be part of a corresponding access line (eg, a corresponding word line). Figure 2 As shown in , the gate of each of the transistors T1 and T2 of the memory cell 210 can be part of the access line 241. The gate of each of the transistors T1 and T2 of the memory cell 211 can be part of the access line 241.

[0032] The gate of each of the transistors T1 and T2 of the memory cell 212 may be part of the access line 242. The gate of each of the transistors T1 and T2 of the memory cell 213 may be part of the access line 242.

[0033] The gate of each of the transistors T1 and T2 of the memory cell 214 may be part of the access line 243. The gate of each of the transistors T1 and T2 of the memory cell 215 may be part of the access line 243.

[0034] The memory device 200 may include data lines (e.g., read bit lines) 221, 222, and 223 that may carry corresponding signals (e.g., read bit line signals) BL1, BL2, and BL*, and data lines (e.g., write bit lines) 221W and 222W that may carry corresponding signals (e.g., write bit line signals) BL1W and BL2W. Each of the data lines 221, 222, 223, 221W, and 222W may be configured as a conductive line.

[0035] The data line 223 may be a common data line (eg, a shared data line) of the memory cell group 2010 or the memory cell group 2011. For example, Figure 2 , data line 223 may include a combination of data line 223A of memory cell group 2010 and 223B of memory cell group 2011, where data lines 223A and 223B may be electrically coupled (e.g., shorted) together. In an alternative example of memory device 200, data lines 223A and 223B may not be electrically coupled (e.g., not shorted) to each other. In this alternative example of memory device 200, the values ​​(e.g., voltage values) of signals (e.g., bit line signals) on separate data lines 223A and 223B during a read or write operation of memory device 200 may be different from those of bit line signals. Figure 2 The voltage value of the signal BL* is the same.

[0036] exist Figure 2 During a read operation, memory device 200 may use data line 223 to obtain information read (e.g., sensed) from selected memory cells in memory cell group 2010 or memory cell group 2011. During a write operation, memory device 200 may use data line 221W to provide information to be stored in selected memory cells in memory cell group 2010, and use data line 222W to provide information to be stored in selected memory cells in memory cell group 2011.

[0037] The memory device 200 may include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation may be obtained via the read path coupled to the selected memory cell. In the memory cell group 2010, the read path of a particular memory cell (e.g., 210, 212, or 214) may include a current path (e.g., a read current path) through a channel region of a transistor T1 of the particular memory cell and data lines 221 and 223. In the memory cell group 2011, the read path of a particular memory cell (e.g., 211, 213, or 215) may include a current path (e.g., a read current path) through a channel region of a transistor T1 of the particular memory cell and data lines 222 and 223. Since the transistor T1 may be used for the read path to read information from the corresponding memory cell during a read operation, the transistor T1 may be referred to as a read transistor and the channel region of the transistor T1 may be referred to as a read channel region.

[0038] The memory device 200 may include a write path (e.g., a circuit path). Information to be stored in a selected memory cell during a write operation may be provided to the selected memory cell via a write path coupled to the selected memory cell. In the memory cell group 2010, the write path of a particular memory cell may include a current path (e.g., a write current path) through a channel region of a transistor T2 of the particular memory cell and a data line 221W. In the memory cell group 2011, the write path of a particular memory cell (e.g., 211, 213, or 215) may include a current path (e.g., a write current path) through a channel region of a transistor T2 of the particular memory cell and a data line 222W. Since the transistor T2 may be used for the write path to store information in the corresponding memory cell during a write operation, the transistor T2 may be referred to as a write transistor and the channel region of the transistor T2 may be referred to as a write channel region.

[0039] Each of transistors T1 and T2 may have a threshold voltage (Vt). Transistor T1 has a threshold voltage Vt1. Transistor T2 has a threshold voltage Vt2. The values ​​of threshold voltages Vt1 and Vt2 may be different (e.g., unequal values). For example, the value of threshold voltage Vt2 may be greater than the value of threshold voltage Vt1. The difference in the values ​​of threshold voltages Vt1 and Vt2 allows reading (e.g., sensing) information stored in charge storage structure 202 in transistor T1 on the read path without affecting (e.g., without turning on) transistor T2 on the write path (e.g., the path through transistor T2). This may prevent charge from leaking from charge storage structure 202 through transistor T2 of the write path.

[0040] In the structure of the memory device 200, transistors T1 and T2 can be formed (e.g., engineered) such that the threshold voltage Vt1 of transistor T1 can be less than zero volts (e.g., Vt1 < 0V) regardless of the value of the information stored in the charge storage structure 202 of transistor T1 (e.g., “0” or “1”), and Vt1 < Vt2. When information having a value “0” is stored in the charge storage structure 202, the charge storage structure 202 can be in state “0”. When information having a value “1” is stored in the charge storage structure 202, the charge storage structure 202 can be in state “1”. Thus, in this structure, the relationship between the values of the threshold voltages Vt1 and Vt2 can be expressed as follows: Vt1 for state “0” < Vt1 for state “1” < 0V, and Vt2 = 0V (or alternatively Vt2 > 0V).

[0041] In an alternative structure of the memory device 200, transistors T1 and T2 can be formed (e.g., engineered) such that Vt1 for state “0” < Vt1 for state “1”, where Vt1 for state “0” < 0V (or alternatively Vt1 for state “0” = 0V), Vt1 for state “1” > 0V, and Vt1 < Vt2.

[0042] In another alternative structure, transistors T1 and T2 can be formed (e.g., engineered) such that Vt1 for state “0” < Vt1 for state “1”, where Vt1 for state “0” = 0V (or alternatively Vt1 for state “0” > 0V), and Vt1 < Vt2.

[0043] During a read operation of the memory device 200, only one memory cell in the same memory cell group can be selected at a time to read information from the selected memory cell. For example, memory cells 210, 212, and 214 in memory cell group 2010 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 in memory cell group 2011 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 211, 213, and 215 in this example).

[0044] During a read operation, memory cells in different groups of memory cells (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access lines 241, 242, or 243) may be selected one at a time. For example, memory cells 210 and 211 may be selected one at a time, memory cells 212 and 213 may be selected one at a time, and memory cells 214 and 215 may be selected one at a time. Alternatively, pairs of memory cells coupled to the same access line may be selected to read information from one memory cell in each of the selected pairs of memory cells. For example, a pair of memory cells 210 and 211 (which are coupled to access line 241) may be selected (e.g., selected in parallel) during a read operation, as well as other one or more pairs of memory cells (not shown) coupled to access line 241. As an example, Figure 2 One memory cell pair is shown coupled to each respective access line 241, 242, or 243. However, the memory device 200 may include Figure 2 Each of the additional pairs of memory cells may have a respective common data line (eg, similar to data line 223).

[0045] exist Figure 2 In the example, the value of information read from a selected memory cell in the memory cell group 2010 during a read operation may be determined based on the value of a current detected (e.g., sensed) from a read path (described above) including the transistor T1 of the selected memory cell (e.g., memory cell 210, 212, or 214) and data lines 221 and 223. The value of information read from a selected memory cell in the memory cell group 2011 during a read operation may be determined based on the value of a current detected (e.g., sensed) from a read path including the transistor T1 of the selected memory cell (e.g., memory cell 211, 213, or 215) and data lines 222 and 223.

[0046] The memory device 200 may include a detection circuit system (not shown) that may operate during a read operation to detect (e.g., sense) a current I1 on a read path including data lines 221 and 223 when a memory cell in the memory cell group 2010 is selected, and to detect a current I2 on a read path including data lines 222 and 223 when a memory cell in the memory cell group 2011 is selected. The value of the detected current may be based on the value of the information stored in the selected memory cell. For example, depending on the value of the information stored in the selected memory cell in the memory cell group 2010, the value of the detected current between the data lines 221 and 223 (e.g., the value of the current I1) may be zero or greater than zero. Similarly, depending on the value of the information stored in the selected memory cell in the memory cell group 2011, the value of the detected current between the data lines 222 and 223 (e.g., the value of the current I2) may be zero or greater than zero. Memory device 200 may include circuitry (not shown) that converts the value of the detected current into the value of information stored in a selected memory cell (eg, a "0," "1," or a combination of multi-bit values).

[0047] During a write operation of the memory device 200, only one memory cell in the same memory cell group may be selected at a time to store information in the selected memory cell. For example, the memory cells 210, 212, and 214 in the memory cell group 2010 may be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of the memory cells 210, 212, and 214 in this example). In another example, the memory cells 211, 213, and 215 in the memory cell group 2011 may be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of the memory cells 211, 213, and 215 in this example).

[0048] During a write operation, memory cells in different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access line 241, 242, or 243) may be selected in parallel (or alternatively may be selected sequentially). For example, memory cells 210 and 211 may be selected in parallel during a write operation to store (e.g., store in parallel) information in memory cells 210 and 211. Memory cells 212 and 213 may be selected in parallel during a write operation to store (e.g., store in parallel) information in memory cells 212 and 213. Memory cells 214 and 215 may be selected in parallel during a write operation to store (e.g., store in parallel) information in memory cells 214 and 215.

[0049] Information to be stored in a selected memory cell in the memory cell group 2010 during a write operation may be provided via a write path including data line 221W and transistor T2 of a selected memory cell (e.g., memory cell 210, 212, or 214). Information to be stored in a selected memory cell in the memory cell group 2011 during a write operation may be provided via a write path including data line 222W and transistor T2 of a selected memory cell (e.g., memory cell 211, 213, or 215). As described above, the value (e.g., binary value) of the information stored in a particular memory cell among the memory cells 210-215 may be based on the amount of charge in the charge storage structure 202 of the particular memory cell.

[0050] In a write operation, the amount of charge in the charge storage structure 202 of the selected memory cell may be changed (to reflect the value of the information stored in the selected memory cell) by applying a voltage on a write path including the transistor T2 of the particular memory cell and a data line (e.g., data line 221W or 222W) coupled to the particular memory cell. For example, if the information to be stored in the selected memory cell among the memory cells 210, 212, and 214 has one value (e.g., “0”), a voltage having one value (e.g., 0V) may be applied to the data line 221W (e.g., 0V may be provided to the signal BL1W). In another example, if the information to be stored in the selected memory cell among the memory cells 210, 212, and 214 has another value (e.g., “1”), a voltage having another value (e.g., a positive voltage) may be applied to the data line 221W (e.g., a positive voltage may be provided to the signal BL1W). Thus, information may be stored (eg, directly stored) in the charge storage structure 202 of a particular memory cell by providing the information to be stored (eg, in the form of a voltage) on the write path of the particular memory cell (which includes transistor T2).

[0051] Figure 3 1 shows a flowchart including example voltages V0, V1, V2, and V3 used during a read operation of the memory device 200 according to some embodiments described herein. Figure 2 A memory device 200 is provided. Figure 3 The example assumes that memory cell 210 is a selected memory cell (e.g., a target memory cell) for reading (e.g., sensing) information stored (e.g., previously stored) in memory cell 210 during a read operation. Memory cells 211 to 215 are assumed to be unselected memory cells. This means that in Figure 3 When information is read from memory cell 210 in the example of , memory cells 211 to 215 are not accessed and information stored in memory cells 211 to 215 is not read.

[0052] exist Figure 3 , voltages V0, V1, V2, and V3 may represent different voltages applied to the corresponding access lines 241, 242, and 243 and data lines 221, 222, 223, 221W, and 222W during a read operation of the memory device 200. As an example, the voltages V0, V1, V2, and V3 may have values ​​of 0V (e.g., ground), -0.3V, -0.75V, and 0.5V, respectively. These values ​​are example values. Different values ​​may be used.

[0053] exist Figure 3 In the read operation shown in , voltage V1 may have a value (voltage value) to turn on transistor T1 of memory cell 210 (the selected memory cell in this example) and turn off (or keep off) transistor T2 of memory cell 210. This allows information to be read from memory cell 210. Voltages V0 and V2 and may have values ​​such that transistors T1 and T2 of each of memory cells 211 to 215 (unselected memory cells in this example) are turned off (e.g., kept off). Voltage V3 may have a value such that a current (e.g., a read current) may be formed on a read path including data lines 221 and 223 and transistor T1 of memory cell 210. This allows current to be detected on a read path coupled to memory cell 210. The detection circuitry (not shown) of memory device 200 is operable to convert the value of the detected current (during reading of information from the selected memory cell) into the value of the information read from the selected memory cell (e.g., a combination of "0", "1", or a multi-bit value). In Figure 3 In the example of , the values ​​of the detected currents on the data lines 221 and 223 may be converted into the values ​​of the information read from the memory cell 210 .

[0054] exist Figure 3, the voltages applied to the respective access lines 241, 242, and 243 may cause the transistors T1 and T2 of each of the memory cells 210 to 215, except for the transistor T1 of the memory cell 210, to be turned off (or remain turned off). Depending on the value of the threshold voltage Vt1 of the transistor T1 of the memory cell 210, the transistor T1 of the memory cell 210 may or may not be turned on. For example, if the transistor T1 of each of the memory cells (e.g., the memory cells 210 to 215) of the memory device 200 is configured (e.g., constructed) so that the threshold voltage of the transistor T1 is less than zero (e.g., Vt1<0V) regardless of the value (e.g., state) of the information stored in the respective memory cell 210, then the transistor T1 of the memory cell 210 in this example may be turned on and conduct a current (e.g., a current I1) between the data lines 221 and 223 (via the transistor T1 of the memory cell 210). The memory device 200 may determine the value of information stored in the memory cell 210 based on the value of the current (e.g., current I1) between the data lines 221 and 223. As described above, the memory device 200 may include detection circuitry that measures the value of the current (e.g., current I1) between the data lines 221 and 223 (or between the data lines 222 and 223) during a read operation.

[0055] Figure 4 Demonstrating some embodiments described herein Figure 2 Memory device 200 of FIG. 1 includes example voltages V0 , V4 , V5 , V6 , and V7 used during a write operation of memory device 200 . Figure 4 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) for storing information in memory cells 210 and 211 during a write operation. Memory cells 212 to 215 are assumed to be unselected memory cells. This means that when information is stored in Figure 4 When the memory cells 210 and 211 in the example of FIG. 1 are accessed, the memory cells 212 to 215 are not accessed and the information is not stored in the memory cells 212 to 215.

[0056] exist Figure 4, voltages V0, V4, V5, V6, and V7 may represent different voltages applied to the corresponding access lines 241, 242, and 243 and data lines 221, 222, 221W, and 222W during a write operation of the memory device 200. As an example, the voltages V0, V4, and V5 may have values ​​of 0V, 3.3V, and -0.75V, respectively. Depending on the value of the information to be stored in the memory cells 210 and 211 (e.g., "0" or "1"), the value of each of the voltages V6 and V7 may be in the range of 0V to 3V. The specific values ​​of the voltages used in this specification are merely example values. Different values ​​may be used.

[0057] Depending on the value of the information to be stored in the memory cells 210 and 211 (e.g., "0" or "1"), the values ​​of the voltages V6 and V7 may be the same or different. For example, if the memory cells 210 and 211 are to store information having the same value, the values ​​of the voltages V6 and V7 may be the same (e.g., V6=V7). As an example, if the information to be stored in each memory cell 210 and 211 is "0", then V6=V7=0V and V4=3.3V, and if the information to be stored in each memory cell 210 and 211 is "1", then V6=V7=1V to 3V and V4=3.3V.

[0058] In another example, if memory cells 210 and 211 are to store information with different values, the values ​​of voltages V6 and V7 may be different (e.g., V6≠V7). As an example, if "0" is to be stored in memory cell 210 and "1" is to be stored in memory cell 211, then V6=0V, V7=1V to 3V, and V4=3.3V. As another example, if "1" is to be stored in memory cell 210 and "0" is to be stored in memory cell 211, then V6=1V to 3V, V7=0V, and V4=3.3V.

[0059] A range of voltages of 1 V to 3 V is used here as an example. Different voltage ranges may be used. In addition, instead of applying 0 V (e.g., V6=0 V or V7=0 V) to a specific write data line (e.g., data line 221W or 222W) for storing information having a value of "0" to a memory cell (e.g., memory cell 210 or 211) coupled to the specific write data line, a positive voltage (e.g., V6>0 V or V7>0 V) may be applied to the specific write data line.

[0060] exist Figure 4In a write operation of the memory device 200 of FIG. 1 , the voltage V5 may have a value such that the transistors T1 and T2 of each of the memory cells 212 to 215 (unselected memory cells in this example) are turned off (e.g., remain turned off). The voltage V4 may have a value to turn on the transistor T2 of each of the memory cells 210 and 211 (selected memory cells in this example) and form a write path between the charge storage structure 202 of the memory cell 210 and the data line 221W, and a write path between the charge storage structure 202 of the memory cell 211 and the data line 222W. A current (e.g., a write current) may be formed between the charge storage structure 202 of the memory cell 210 and the data line 221W. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 210 to reflect the value of the information to be stored in the memory cell 210. A current (e.g., another write current) may be formed between the charge storage structure 202 of the memory cell 211 and the data line 222W. This current may affect (eg, change) the amount of charge on the charge storage structure 202 of the memory cell 211 to reflect the value of the information to be stored in the memory cell 211 .

[0061] exist Figure 4 In the example write operation of , the value of voltage V6 may cause the charge storage structure 202 of memory cell 210 to discharge or charge, so that the resulting charge on the charge storage structure 202 of memory cell 210 (e.g., the charge remaining after the discharge or charge action) may reflect the value of the information stored in memory cell 210. Similarly, the value of voltage V7 in this example may cause the charge storage structure 202 of memory cell 211 to discharge or charge, so that the resulting charge on the charge storage structure 202 of memory cell 211 (e.g., the charge remaining after the discharge or charge action) may reflect the value of the information stored in memory cell 211.

[0062] Figure 4The example write operation of assumes that memory cells 210 and 211 are selected (e.g., selected in parallel) to store (e.g., store in parallel) information. In another write operation, memory cell 210 or memory cell 211 may be selected to store information. For example, in another write operation, memory cell 210 may be selected and memory cells 211 to 215 may be unselected memory cells. In such a write operation, voltage V7 may represent a voltage (e.g., a write inhibit voltage (e.g., V7=V4)) such that memory cell 211 is inhibited from storing information when information is stored in memory cell 210 (e.g., the selected memory cell). Similarly, if memory cell 211 is selected to store information and memory cells 210 and 212 to 215 are unselected memory cells, voltage V6 may represent a voltage (e.g., a write inhibit voltage (e.g., V6=V4)) such that memory cell 210 is inhibited from storing information when information is stored in memory cell 211 (e.g., the selected memory cell).

[0063] According to some embodiments described herein, Figure 5 , Figure 6 , Figure 7 and Figure 8 exhibit Figure 2 Different views of the structure of the memory device 200 with respect to the X, Y and Z directions. Figure 5 A side view of memory device 200 relative to the XZ direction is shown. Figure 6 , Figure 7 and Figure 8 Show respectively along Figure 5 Views taken along lines 6-6, 7-7 and 8-8.

[0064] For simplicity, Figures 5 to 8 Focus on the structure of memory cells 210 and 211. Figure 2 The structures of other memory cells (e.g., memory cells 212, 213, 214, and 215) of the memory device 200 may be similar to those of the memory device 200. Figure 5 The structures of the memory cells 210 and 211 shown in FIG. are similar or identical. Figures 5 to 8 (which shows the physical structure of memory device 200) and Figure 2 (which shows a memory device 200 in circuit schematic form), like elements are given like reference numerals.

[0065] The following description refers to Figures 5 to 8 For simplicity, Figures 5 to 8 The detailed description of the same element is not repeated in the description of FIG. Figures 5 to 8 and other figures in the drawings described herein (e.g., Figures 9 to 20) are cross-sectional lines (eg, hatching) for most elements shown in the drawings. Some elements of memory device 200 may be omitted from certain figures in the drawings to avoid obscuring the description of the elements described in that certain figure. Figures 5 to 8 The sizes of the elements shown are not to scale.

[0066] like Figure 5 , memory device 200 may include a substrate 599 on which memory cells 210 and 211 may be formed (e.g., formed vertically in the Z direction relative to substrate 599). Substrate 599 may be a semiconductor substrate (e.g., a silicon-based substrate) or other type of substrate. The Z direction may be a direction perpendicular to substrate 599 (e.g., a vertical direction relative to substrate 599). The X direction and the Y direction are perpendicular to each other and perpendicular to the Z direction.

[0067] like Figures 5 to 8 , each of the data lines (e.g., read bit lines) 221, 222, and 223 (associated with signals BL1, BL2, and BL*, respectively) and the data lines (e.g., write bit lines) 221W and 222W (associated with signals BL1W and BL2W, respectively) may have a length in the Y direction, a width in the X direction, and a thickness in the Z direction. Each of the data lines 221, 222, 223, 221W, and 222W may include a conductive material (or combination of materials) that may be configured as a conductive line (e.g., a conductive region). Example materials for the data lines 221, 222, 223, 221W, and 222W include metals, conductively doped polysilicon, or other conductive materials.

[0068] like Figure 5 As shown in FIG. 5 , data lines 221, 222, 223, 221W, and 222W may include corresponding conductive regions (eg, portions of corresponding conductive materials forming data lines 221, 222, 223, 221W, and 222W) that are electrically separated from one another and located in the same level above substrate 599.

[0069] Access line 241 (associated with signal WL1) may be constructed from (eg, may include) a combination of portions 541F and 541B (eg, a front conductive portion and a rear conductive portion with respect to the Y direction). Figure 5 , portions 541F and 541B are partially shown to avoid blocking portions of other elements of memory device 200.

[0070] Each of portions 541F and 541B may include a structure of conductive material (e.g., a sheet of material (a layer of material)). Examples of conductive materials include metal, conductively doped polysilicon, or other conductive materials. Each of portions 541F and 541B may include a conductive material (or a combination of materials) that may be configured as a conductive line (e.g., a conductive region) having a length extending continuously in the X direction, a width in the Z direction (in Figure 5 ) and the thickness in the Y direction (in Figure 8 (shown in the).

[0071] Portions 541F and 541B may be electrically coupled to each other. For example, memory device 200 may include a conductive material (e.g., not shown) that may contact (e.g., electrically couple to) portions 541F and 541B so that the same signal (e.g., signal WL1) may be applied to portions 541F and 541B (which are part of a shared (or single) access line 241) in parallel.

[0072] In an alternative configuration of memory device 200, portion 541F or portion 541B may be omitted such that access line 241 may include only portion 541F or portion 541B. Figure 5 In the structure shown in FIG. 1 , including two portions 541F and 541B can help better control the transistor T1 (eg, Figure 2 Schematically shown transistor T1).

[0073] like Figure 5 , memory device 200 may include a dielectric 590 formed on a portion of a substrate 599. Dielectric 590 may include silicon oxide. Figure 5 In the example, the area marked as "channel" can show Figure 5 590 may electrically separate elements (e.g., channel regions) of memory cells (e.g., memory cells 210 and 211) of memory device 200 from substrate 599.

[0074] The charge storage structure 202 may include a structure of semiconductor material, which may include a piece (e.g., layer) of semiconductor material (e.g., polysilicon), a piece (e.g., layer) of metal, or a piece of one or more materials that can trap charge. The materials used for the charge storage structure 202 and the portions 541F and 541B of the access line 241 may be the same or different. Figure 5As shown in , the charge storage structure 202 may be located on a level above the substrate 599 and below (with respect to the Z direction) the level at which the data lines 221, 222, 223, 221W, and 222W are located. Thus, the charge storage structure 202 is located between the substrate 599 and the level at which the data lines 221, 222, 223, 221W, and 222W are located.

[0075] like Figure 5 As shown in , the charge storage structure 202 may be closer to the substrate 599 (eg, may extend closer to the substrate in the Z direction) than each of the portions 541F or 541B. Figure 5 As shown in FIG. , the distance in the Z direction between the substrate 599 and the edge of the material forming the charge storage structure 202 (e.g., the bottom edge relative to the Z direction) is smaller than (e.g., shorter than) the distance in the Z direction between the substrate 599 and the edge of the material forming each of portions 541F and 541B (e.g., the bottom edge relative to the Z direction).

[0076] Figure 5 The top edge of the charge storage structure 202 is shown to be a certain distance (eg, a bottom edge) from the edge (eg, bottom edge) of each of the portions 541F and 541B of the access line 241. Figure 5 However, the distance between the top edge of charge storage structure 202 and the edge (eg, bottom edge) of each of portions 541F and 541B may vary.

[0077] Figure 5 An example is shown where portions 541F and 541B overlap (in the Z direction) the charge storage structure 202. However, portions 541F and 541B may not overlap the charge storage structure 202.

[0078] The memory device 200 may include a material 520 located at a level above the level at which the charge storage structure 202 is located, such that the charge storage structure 202 is between the material 520 and the substrate 599. The material 520 may be electrically coupled to the data line (e.g., write bit line) 221W and the charge storage structure 202 of the memory cell 210. As described above, the charge storage structure 202 of the memory cell 210 may form a memory element of the memory cell 210. Thus, as described above, Figure 5 , memory cell 210 may include a memory element (which is charge storage structure 202 ) located between substrate 599 and material 520 with respect to the Z direction, and the memory element contacts (eg, is directly coupled to) material 520 .

[0079] The material 520 may form a source (eg, source terminal), a drain (eg, drain terminal), and a channel region (eg, write channel region) between the source and drain of the transistor T2 of the memory cell 210. Figure 5 , the source, channel region, and drain of the transistor T2 of the memory cell 210 may be formed of a single structure (e.g., a single piece) of the same material, such as material 520 (or alternatively, a single structure (e.g., a single piece) of the same material combination). Therefore, the source, drain, and channel region of the transistor T2 of the memory cell 210 may be formed of the same material (e.g., material 520) of the same conductivity type (e.g., n-type or p-type).

[0080] The memory device 200 may include a material 521 that may form a source (eg, source terminal), a drain (eg, drain terminal), and a channel region (eg, write channel region) between the source and drain of the transistor T2 of the memory cell 211. Figure 5 , the source, channel region, and drain of transistor T2 of memory cell 211 may be formed from a single structure (eg, a single piece) of the same material, such as material 521 (or alternatively, a single piece of the same material combination).

[0081] Materials 520 and 521 may be the same. For example, each of materials 520 and 521 may include a semiconductor material piece (e.g., layer). The semiconductor material piece may include an oxide material piece. Examples of oxide materials for materials 520 and 521 include semiconductor oxide materials, transparent conductive oxide materials, and other oxide materials.

[0082] As an example, each of materials 520 and 521 may include at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), Indium Zinc Oxide (In x Zn y O z ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zrx In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a )、Zirconium oxide zinc tin (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

[0083] The use of the materials listed above in the memory device 200 provides improvements and benefits to the memory device 200. For example, during a read operation to read information from a selected memory cell (e.g., memory cell 210 or 211), charge from the charge storage structure 202 of the selected memory cell may leak to the transistor T2 of the selected memory cell. Using the materials listed above for the channel region of transistor T2 (e.g., material 520 or 521) can reduce or prevent such leakage. This improves the accuracy of the information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory devices described herein (e.g., memory device 200).

[0084] The materials listed above are examples of materials 520 and 521. However, other materials (eg, relatively high bandgap materials) other than those listed above may be used.

[0085] exist Figure 5In the embodiment, the material 520 of the memory cell 210 and the charge storage structure 202 can be electrically coupled to each other (e.g., directly coupled) such that the material 520 can contact the charge storage structure 202 of the memory cell 210 without an intermediate material (e.g., no conductive material) between the charge storage structure 202 of the memory cell 210 and the material 520. In another example, the material 520 can be electrically coupled to the charge storage structure 202 of the memory cell 210 such that the material 520 is not directly coupled to (e.g., not in contact with) the charge storage structure 202 of the memory cell 210, but the material 520 is electrically coupled to the charge storage structure 202 of the memory cell 210 through an intermediate material (e.g., conductive material) between the charge storage structure 202 of the memory cell 210 and the material 520. Figure 5 2. A charge storage structure 202 (not shown) is coupled to (eg, indirectly contacts) a memory cell 210. As shown in FIG.

[0086] like Figure 5 , memory device 200 may include portions 510A, 510B, 510C, 510D, and 510E electrically coupled to each other, and portions (e.g., dielectric portions) 515A, 515B, 515C, 525A, 525B, and 525C. Portions 515A, 515B, and 515C may include dielectric material and may be gate oxide regions of memory cell 210 that electrically separate material 520 of memory cell 210 and each of charge storage structures 202 from portions 510A, 510C, and 510D. Portions 525A, 525B, and 525C may include dielectric material and may be gate oxide regions of memory cell 211 that electrically separate material 521 of memory cell 211 and each of charge storage structures 202 from portions 510B, 510E, and 510C. Example materials for portions 515A, 515B, 515C, 525A, 525B, and 525C may include silicon dioxide, hafnium dioxide (eg, HfO 2 ), aluminum oxide (eg, Al 2 O 3 ), or other dielectric materials.

[0087] Each of portions 510A, 510B, 510C, 510D, and 510E may include a structure (e.g., a piece) of semiconductor material. Example materials for each of portions 510A, 510B, 510C, 510D, and 510E include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon germanium, or other semiconductor materials.

[0088] As described below, portion 510C may be shared between transistor T1 of memory cell 210 and transistor T1 of memory cell 211. Data line 223 may be shared between memory cells 210 and 211 to conduct current I1 between data lines 221 and 223 (via portions 510A, 510D, and 510C) and conduct current I2 between data lines 222 and 223 (via portions 510B, 510E, and 510C).

[0089] As mentioned above Figure 2 As described, the transistor T1 of the memory cell 210 includes a channel region (eg, a read channel region). Figure 5 , the channel region of transistor T1 of memory cell 210 may include at least a portion of each of portions 510A, 510D, and 510C. Portions 510A, 510D, and 510C may be electrically coupled to data lines 221 and 223. Figure 2 As described, memory unit 210 may include a read path. Figure 5 , portions 510A, 510D, and 510C (e.g., a read channel region of transistor T1 of memory cell 210) may be part of a read path of memory cell 210, which may carry current I1 (e.g., a read current) during a read operation to read information from memory cell 210. For example, during a read operation to read information from memory cell 210, portions 510A, 510D, and 510C may conduct current I1 between data lines 221 and 223. The direction of current I1 may be from data line 221 to data line 223 (through portions 510A, 510D, and 510C).

[0090] Therefore, if Figure 5 , the transistor T1 of the memory cell 210 may include a channel region (e.g., a read channel region) formed by portions 510A, 510D, and 510C. Portion 510A may be located on (e.g., adjacent to) one side (e.g., the left side in the X direction) of the charge storage structure 202 (e.g., a memory element) and the material 520 (e.g., a write channel region of the transistor T2) of the memory cell 210. Portion 510C may be located on (e.g., adjacent to) one side (e.g., the right side (opposite to the left side) in the X direction) of the charge storage structure 202 and the material 520 of the memory cell 210. Portion 510D may be located on (e.g., adjacent to) one side (e.g., the bottom side in the Z direction) of the charge storage structure 202 of the memory cell 210 and located on a level between the charge storage structure 202 of the memory cell 210 and the substrate 599 (in the Z direction).

[0091] As mentioned above Figure 2As described, the transistor T1 of the memory cell 211 includes a channel region (eg, a read channel region). Figure 5 , the channel region of transistor T1 of memory cell 211 may include at least a portion of each of portions 510B, 510E, and 510C. Portions 510B, 510E, and 510C may be electrically coupled to data lines 222 and 223. Figure 2 As described, memory unit 211 may include a read path. Figure 5 , portions 510B, 510E, and 510C (e.g., a read channel region of transistor T1 of memory cell 211) may be part of a read path of memory cell 211, which may carry current I2 (e.g., a read current) during a read operation to read information from memory cell 211. For example, during a read operation to read information from memory cell 211, portions 510B, 510E, and 510C may conduct current I2 between data lines 222 and 223. The direction of current I2 may be from data line 222 to data line 223 (through portions 510B, 510E, and 510C).

[0092] Therefore, if Figure 5 , the transistor T1 of the memory cell 211 may include a channel region formed by portions 510B, 510E, and 510C. Portion 510B may be located on (e.g., adjacent to) one side (e.g., the right side in the X direction) of the charge storage structure 202 (e.g., memory element) and the material 521 (e.g., write channel region of the transistor T2) of the memory cell 211. Portion 510C may be located on (e.g., adjacent to) one side (e.g., the left side (opposite to the right side) in the X direction) of the charge storage structure 202 and the material 521 of the memory cell 211. Portion 510D may be located on (e.g., adjacent to) one side (e.g., the bottom side in the Z direction) of the charge storage structure 202 of the memory cell 211 and located on a level (in the Z direction) between the charge storage structure 202 of the memory cell 211 and the substrate 599.

[0093] like Figure 5 , portions of portion 541F may span (e.g., overlap in the X direction) portions of portions 510A and 510C and portions of material 520. As described above, portions 510A and 510C may form portions of a read channel region of transistor T1 of memory cell 210, and material 520 may form portions of a write channel region of transistor T2 of memory cell 210. Thus, as shown in FIG. Figure 5, a portion of portion 541F may span (e.g., overlap) portions of both the read channel region of transistor T1 and the write channel region of transistor T2 of memory cell 210 (e.g., on one side (e.g., the front side) in the Y direction). Figure 5 , but portions of portion 541B may span (e.g., overlap in the X direction) portions of portions 510A and 510C (e.g., on the other side (e.g., the back side as opposed to the front side) in the Y direction) and portions of material 520 of memory cell 210. Figure 5 As shown in , portions 541F and 541B of access line 241 may also span (e.g., overlap in the X direction) portions 510B and 510C (e.g., the read channel region of transistor T1 of memory cell 211) and portions of material 521 (e.g., the write channel region of transistor T2 of memory cell 211).

[0094] Access line 241 spanning (e.g., overlapping) portions 510A and 510C and materials 520 and 521 allows access line 241 (e.g., a shared access line) to control (e.g., turn on or off) both transistors T1 and T2 of memory cell 210. Access line 241 spanning (e.g., overlapping) portions 510B and 510C also allows access line 241 to control (e.g., turn on or off) both transistors T1 and T2 of memory cell 211.

[0095] like Figures 6 to 8 , memory device 200 may include portions (e.g., dielectric portions) 515E and 515F (e.g., oxide regions) to electrically separate portions 541F and 541B of access line 241 from other elements of memory cells 210 and 211 (e.g., from portions 510A, 510B, 510C, 510D, and 510E (e.g., read channel regions) and from charge storage structure 202). Example materials for portions 515E and 515F may include silicon dioxide, hafnium dioxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

[0096] The one or more dielectric materials separating portions 510A, 510B, 510C, 510D, and 510E (read channel regions) from portions 541F and 541B of access line 241 may be the same as (or, alternatively, different from) the one or more materials separating charge storage structure 202 from portions 541F and 541B of access line 241. In addition, the thickness of the one or more dielectric materials separating portions 510A, 510B, 510C, 510D, and 510E (read channel regions) from portions 541F and 541B of access line 241 may be the same as (or, alternatively, different from) the thickness of the one or more materials separating charge storage structure 202 from portions 541F and 541B of access line 241.

[0097] like Figure 8 , portions 541F and 541B may be adjacent to respective sides of material 520 (e.g., a write channel region) and charge storage structure 202 of memory cell 210. For example, portion 541F may be located on one side of a portion of each of material 520 and charge storage structure 202 (e.g., Figure 8 In another example, portion 541B may be located on the other side of a portion of each of material 520 and charge storage structure 202 (eg, Figure 8 On the left side (opposite to the right side) in the X-direction in the view of FIG.

[0098] Figures 9 to 19 A cross-sectional view showing elements in a process of forming memory device 900 according to some embodiments described herein. Some or all of the processes used to form memory device 900 may be used to form the memory device 900 described above. Figures 2 to 8 A memory device 200 is described.

[0099] Fig. 9 Memory device 900 is shown after dielectric material 990, semiconductor material 910, and dielectric material 935 are formed in respective levels (e.g., layers) in the Z direction over substrate 999. The Z direction (e.g., vertical direction) is a direction perpendicular to substrate 999 (e.g., outward from the substrate). The Z direction is also perpendicular to the X direction. Substrate 999 may be disposed adjacent to substrate 999. Figure 5 The dielectric material 990 may include an oxide material (e.g., silicon dioxide SiO2). The material of the semiconductor material 910 may be the same as that of the portions 510A, 510B, 510C, 510D, and 510E ( Figure 5 ) are the same material for each of them. Dielectric material 990, semiconductor material 910, and dielectric material 935 may be formed over substrate 999 in a sequential manner, one material after another. For example, Fig. 9 The process used may include forming (e.g., depositing) a dielectric material 990 above a substrate 999, forming (e.g., depositing) a semiconductor material 910 above the dielectric material 990, and forming (e.g., depositing) a dielectric material 935 (e.g., silicon nitrite SiN4) above the semiconductor material 910.

[0100] Fig.10 Memory device 900 is shown after forming openings (e.g., trenches) 1031 and 1032 and portions 910A', 910B', 910C', 910D', and 910E'. Forming openings 1031 and 1032 may include removing (e.g., by patterning) portions of dielectric material 935 and portions of semiconductor material 910 at the locations of openings 1031 and 1032. Portions 935A', 935B', and 935C' are the remaining portions of dielectric material 935. Portions 910A', 910B', 910C', 910D', and 910E' are the remaining portions of semiconductor material 910.

[0101] Fig.11 Memory device 900 is shown after forming dielectric material 1115. Dielectric material 1115 may include an oxide material (eg, silicon dioxide SiO2).

[0102] Fig.12 Memory device 900 is shown after forming materials 1202', 1220', and 1221' and portions 1115A', 1115B', and 1115C'. Fig.12 The process in may include a planarization process (eg, a chemical mechanical polishing (CMP) process) for removing portions (eg, a top portion) of dielectric material 1115. The remaining portions of dielectric material 1115 are portions 1115A', 1115B', and 1115C'.

[0103] Fig.12 The process may include forming a dielectric material 1115 ( Fig.11 ) on the openings 1031 and 1032 ( Fig.10 ) is formed (e.g., deposited) at a location of the memory device 900. As described below, in a subsequent process of forming the memory device 900, the material 1202' can be constructed to form a charge storage structure (e.g., a memory element) of a corresponding memory cell of the memory device 900. The material 1202' can include the same Figure 2 ) of the charge storage structure 202 of the memory cell (eg, memory cell 210 or 211) may be made of a material similar to or the same as that of the charge storage structure 202 of the memory cell (eg, memory cell 210 or 211).

[0104] Fig.12The process in may include forming (e.g., depositing) material 1220' on material 1202' (e.g., directly on the material) at the location of opening 1032, and forming (e.g., depositing) material 1221' on material 1202' (e.g., directly on the material) at the location of opening 1031. Materials 1220' and 1221' may be the same material. Materials 1220' and 1221' may be formed (deposited) simultaneously. Materials 1220' and 1221' may include Figure 2 The material 520 or 521 of the transistor T2 of the memory device 200 ( Figure 5 ) (e.g., write channel region). As described below, in a subsequent process of forming the memory device 900, each of the materials 1220' and 1221' can form a channel region (e.g., write channel region) of a transistor (e.g., transistor T2) of a corresponding memory cell of the memory device 900.

[0105] Fig.13 Show relative to Fig. 9 For simplicity, the top view of the memory device 900 in the XY direction is not repeated. Fig.13 Description of the components shown in Fig.12 to describe). Fig.13 , elements of memory device 900 may include strips (e.g., lines) of material having a length extending in the Y direction. Subsequent processes of forming memory device 900 may include removing (e.g., cutting (e.g., etching) in the Z direction) material at locations 1361, 1362, and 1363 down to dielectric material 990 ( Fig. 9 ) (e.g., stopping at the dielectric material).

[0106] exist Fig.13 , after removing portions of the material at positions 1361, 1362 and 1363, portions 935A and 935A" (at positions 1371 and 1372, respectively) will be the remaining portions of portion 935A'; portions 1220 and 1220E (at positions 1371 and 1372, respectively) will be the remaining portions of material 1220'; portions 935B and 935B" (at positions 1371 and 1372, respectively) will be the remaining portions of portion 935B'; portions 1221 and 1221E (at positions 1371 and 1372, respectively) will be the remaining portions of material 1221'; and portions 935C and 935C" (at positions 1371 and 1372, respectively) will be the remaining portions of portion 935C'. Fig.14 Another view of memory device 900 along line 14-14 is shown in FIG.

[0107] Fig.14The openings (eg, grooves) 1361', 1362', and 1363' are shown formed at locations 1361, 1362, and 1363, respectively. Fig.13 ) and then along the YZ direction Fig.13 14-14. Openings 1361', 1362', and 1363' may be formed by removing portions of each of the material at locations 1361, 1362, and 1363 (as mentioned above). Fig.14 In the Y direction, the portions 910D and 910F are the portions 910D'( Fig.10 ), and the Y-direction portions 1115C and 1115E are the portion 1115C'( Fig.12 ) The remaining part of the Y direction is the material 1202' ( Fig.12 ), and portions 1220 and 1220E in the Y direction are the remaining portions of material 1220' (as described above in Fig.13 ). Fig.14 , the material of memory device 900 includes structures (eg, protrusions (eg, islands)) 1471 and 1472 extending outward from substrate 999. Each of structures 1471 and 1472 can form part of a memory cell in a subsequent process of forming memory device 900.

[0108] Fig.15 The conductive lines (e.g., conductive regions) 1501, 1502, 1503, and 1504 (1501-1504) and dielectric materials 1515A, 1515B, 1515C, 1515D, 1515E, and 1515F (1515A-1515F) are shown formed in the corresponding openings 1363', 1362', and 1361' ( Fig.14 ) Fig.14 Memory device 900 of the present invention. Each of dielectric materials 1515A to 1515F may include silicon dioxide or other dielectric materials. Each of conductive lines 1501 to 1504 may include metal, conductively doped polysilicon, or other conductive materials. Portions of dielectric materials 1515A to 1515F (e.g., portions of dielectric materials 1515D, 1515E, and 1515F) may form a gate oxide structure to electrically separate conductive lines 1501, 1502, 1503, and 1504 from portions 1202, 1220, 1220E, 910D, and 910F.

[0109] Conductive lines 1501-1504 may form part of access lines (eg, word lines) to access memory cells 210' and 212' of memory device 900. Memory cells 210' and 212' may be, respectively. Figure 2Memory cells 210 and 212 of the memory device 200.

[0110] exist Fig.15 , conductive lines 1501 and 1502 may form part of an access line (eg, a word line) to access memory cell 210′ ​​and other memory cells (eg, word lines) of memory device 900. Fig.15 Such other memory cells may be located in the same row in the X direction as memory cell 210'.

[0111] exist Fig.15 , conductive lines 1503 and 1504 may form part of access lines (eg, word lines) to access memory cell 212' and other memory cells (not shown) of memory device 900. Such other memory cells may be located in the same row in the X direction as memory cell 212'.

[0112] Therefore, if Fig.15 , conductive line 1501 may have a portion adjacent to one side (e.g., the right side in the Y direction) of the channel region (e.g., portion 1202) of memory cell 210'. Conductive line 1502 may have a portion adjacent to the other side (e.g., the left side (opposite to the right side) in the Y direction) of the channel region (e.g., portion 1202) of memory cell 210'.

[0113] Similarly, the conductive lines 1503 and 1504 may have corresponding portions (eg, corresponding conductive regions) adjacent to corresponding sides (opposite sides) of a channel region (eg, a read channel region) of the memory cell 212 ′ in the Y direction. Fig.16 Another view of memory device 900 along line 16-16 is shown in FIG.

[0114] Fig.16 Displays the XZ direction along Fig.15 A side view of line 16-16. Fig.16 , conductive lines 1501 and 1502 are partially shown to avoid blocking portions of other elements of memory device 900. Fig.16 As shown in FIG. 1 , each of conductive lines 1501 and 1502 may have a length in the X direction, a width in the Z direction, and a thickness in the Y direction (eg, less than the width) (in Fig.15 (shown in the).

[0115] exist Fig.16 In the embodiment, the dielectric parts 1115A, 1115B and 1115C are respectively Fig.12 The parts 1115A', 1115B' and 1115C' are in Fig.14After removing (eg, cutting) a portion of each of portions 1115A', 1115B', and 1115C' during Fig.15 The remaining portion of the conductive lines 1501 to 1504 is formed before the conductive lines 1501 to 1504 are formed during the process.

[0116] exist Fig.16 In the embodiment, the dielectric parts 1125A, 1125B and 1125C are respectively Fig.12 The parts 1125A', 1125B' and 1125C' are in Fig.14 After removing (eg, cutting) a portion of each of portions 1125A', 1125B', and 1125C' during (and after Fig.15 The remaining portion of the conductive lines 1501 to 1504 is formed before the conductive lines 1501 to 1504 are formed during the process.

[0117] exist Fig.16 In the embodiment, parts (dielectric parts) 935A, 935B and 935C are respectively Fig.12 Parts 935A', 935B' and 935C' are in Fig.14 After removing (eg, cutting) a portion of each of portions 935A', 935B', and 935C' during Fig.15 The remaining portion of the conductive lines 1501 to 1504 is formed before the conductive lines 1501 to 1504 are formed during the process.

[0118] exist Fig.16 In the embodiment, parts 910A, 910B, 910C, 910D and 910E are respectively Fig.12 The parts 910A', 910B', 910C', 910D' and 910E' are in Fig.14 After removing (eg, cutting) a portion of each of portions 910A′, 910B′, 910C′, 910D′, and 910E′ during (and after Fig.15 Each of the portions 910A, 910B, 910C, 910D, and 910E may include Fig. 9 A structure (eg, a sheet) of semiconductor material 910 is formed during the process.

[0119] Portions 910A, 910D, and 910C may form a channel region (eg, a read channel region) of transistor T1 of memory cell 210'. Transistor T1 of memory cell 210' may be Figure 2 and Figure 5 The transistor T1 of the memory cell 210 of the memory device 200 is shown in FIG.

[0120] Portions 910B, 910E, and 910C may form a channel region (eg, a read channel region) of transistor T1 of memory cell 211'. Transistor T1 of memory cell 211' may be Figure 2 and Figure 5 The transistor T1 of the memory cell 211 of the memory device 200 is shown in FIG.

[0121] exist Fig.16 In section 1202 Fig.13 Materials 1202' Fig.14 After removing (eg, cutting) a portion of material 1202′ during (and before Fig.15 The remaining portion (hidden in FIG. 1 ) before the conductive lines 1501 to 1504 are formed in the process Fig.13 Each of the portions 1202 may form a charge storage structure (eg, a memory element) of the transistor T1 of the corresponding memory cell 210 ′ or 211 ′.

[0122] like Fig.16 As shown in FIG. 1 , a portion (e.g., a charge storage structure) 1202 of transistor T1 of each of memory cells 210 ′ and 211 ′ may be closer to substrate 999 (e.g., may extend closer to the substrate in the Z direction) than each of conductive lines 1501 and 1502. For example, Fig.16 As shown in FIG. 1 , the distance in the Z direction between the substrate 999 and the edge (e.g., the bottom edge relative to the Z direction) of the material forming the portion of the transistor T1 (e.g., the charge storage structure) 1202 of each of the memory cells 210′ ​​and 211′ is smaller than (e.g., shorter than) the distance in the Z direction between the substrate 999 and the edge (e.g., the bottom edge relative to the Z direction) of the material forming each of the conductive lines 1501 and 1502.

[0123] exist Fig.16 , conductive lines 1501 and 1502 may be part of an access line (e.g., a shared word line) 1541 that may receive a signal (e.g., a word line signal) WL1 during operation of the memory device 900 to access memory cells 210′ ​​and 211′ of the memory device 900. For example, the signal (e.g., WL1) on conductive lines 1501 and 1502 may be used to control (e.g., turn on or off) transistors T1 and T2 of the memory cell 210′ ​​and transistors T1 and T2 of the memory cell 211′.

[0124] like Fig.16, portions of conductive line 1501 may span (e.g., overlap in the X direction) portions of portions 910A and 910C and portions of portion 1220 of memory cell 210′. As described above, portions 910A and 910C may form portions of the read channel region of transistor T1 of memory cell 210′, and portion 1220 may form portions of the write channel region of transistor T2 of memory cell 210′. Thus, as Fig.16 As shown in , a portion of the conductive line 1501 may span (eg, overlap) a portion of both the read channel region of the transistor T1 and the write channel region of the transistor T2 of the memory cell 210' (eg, on one side (eg, the front side) in the Y direction). Fig.16 Although hidden in the view shown in , a portion of the conductive line 1502 may span (e.g., overlap in the X direction) portions 910A and 910C (e.g., on the other side in the Y direction (e.g., the back side opposite the front side)) and a portion of the portion 1220 of the memory cell 210' (e.g., the read channel region of the transistor T1 and the write channel region of the transistor T2).

[0125] Similarly, for memory cell 211', a portion of conductive line 1501 may span (e.g., overlap in the X direction) a portion of portions 910B and 910C and a portion of portion 1221 of memory cell 211'. As described above, portions 910B and 910C may form a portion of the read channel region of transistor T1 of memory cell 211', and portion 1221 may form a portion of the write channel region of transistor T2 of memory cell 211'. Thus, as Fig.16 As shown in FIG. 1 , a portion of the conductive line 1501 may span (eg, overlap) a portion of both the read channel region of the transistor T1 and the write channel region of the transistor T2 of the memory cell 211 ′ (eg, on one side (eg, the front side) in the Y direction). Fig.16 Although hidden in the view shown in , a portion of the conductive line 1502 may span (e.g., overlap in the X direction) portions of portions 910B and 910C (e.g., on the other side in the Y direction (e.g., the back side opposite to the front side)) and a portion of portion 1221 of the memory cell 211' (e.g., the read channel region of transistor T1 and the write channel region of transistor T2).

[0126] Since conductive lines 1501 and 1502 may cross respective portions of transistors T1 and T2 of memory cells 210' and 211', conductive lines 1501 and 1502 may have portions adjacent to respective portions of transistors T1 and T2 of memory cells 210' and 211'. Fig.16, the conductive line 1501 may have a portion adjacent to one side (e.g., the front side in the Y direction) of the channel region of the transistor T1 of the memory cell 210′ ​​(e.g., the portions 910A and 910C) and adjacent to one side (e.g., the front side in the Y direction) of the channel region of the transistor T2 of the memory cell 210′ ​​(e.g., the portion 1220). The conductive line 1502 may have a portion adjacent to the other side (e.g., the rear side (opposite to the front side) in the Y direction) of the channel region of the transistor T1 of the memory cell 210′ ​​(e.g., the portions 910A and 910C) and adjacent to the other side (e.g., the rear side (opposite to the front side) in the Y direction) of the channel region of the transistor T2 of the memory cell 210′ ​​(e.g., the portion 1220).

[0127] Similarly, for the memory cell 211', the conductive line 1501 may have a portion adjacent to one side (e.g., the front side in the Y direction) of the channel region of the transistor T1 of the memory cell 211' (e.g., the portions 910B and 910C) and adjacent to one side (e.g., the front side in the Y direction) of the channel region of the transistor T2 of the memory cell 211' (e.g., the portion 1221). The conductive line 1502 may have a portion adjacent to the other side (e.g., the rear side (opposite to the front side) in the Y direction) of the channel region of the transistor T1 of the memory cell 211' (e.g., the portions 910B and 910C) and adjacent to the other side (e.g., the rear side (opposite to the front side) in the Y direction) of the channel region of the transistor T2 of the memory cell 211' (e.g., the portion 1221).

[0128] form Fig.16 The process of forming memory device 900 in FIG. 1 may include forming a conductive connector 1501′ (which may include a conductive material (e.g., metal)) that electrically couples conductive lines 1501 and 1502 to each other. Similarly, the process of forming memory device 900 may include forming conductive lines 1503 and 1504 ( Fig.15 ) are electrically coupled to each other (not shown).

[0129] Fig.17 Shown with portions 935A, 935B and 935C removed ( Fig.16 ) and memory device 900 after removing portions 1115A, 1115B, 1125A, 1125B, 1220, and 1221. Fig.17 The process in may include a planarization process (eg, a CMP process) for removing portions 935A, 935B, and 935C and portions 1115A, 1115B, 1125A, 1125B, 1220 , and 1221 .

[0130] Fig.18Memory device 900 is shown after forming data lines (eg, read bit lines) 1821, 1822, and 1823 and data lines (eg, write bit lines) 1821W and 1822W. Each of data lines 1821, 1822, 1823, 1821W, and 1822W may have a length in the Y direction. Fig.18 The process in the memory device 900 may include depositing a conductive material (e.g., metal) over portions 910A, 910B, 910C, 1115A, 1115B, 1125A, 1125B, 1220, and 1221. Portions of the conductive material may then be removed (e.g., patterned) to form data lines 1821, 1822, 1823, 1821W, and 1822W that are electrically coupled to (e.g., contact) respective portions 910A, 910B, 910C, 1220, and 1221. In operation of the memory device 900, the data lines 1821, 1822, 1823, 1821W, and 1822W may have signals BL1, BL2, BL*, BL1W, and BL2W, respectively. The data lines 1821, 1822, 1823, 1821W, and 1822W may represent Figure 2 The data lines 221, 222, 223, 221W and 222W of the memory device 200 are shown.

[0131] Fig.19 Memory device 900 is shown after forming dielectric material 1915. The process of forming memory device 900 may include other processes not described in this specification in order not to obscure the embodiments described herein. Fig.19 As shown in , the memory device 900 may include memory cells 210' and 211', which may include: a transistor (e.g., transistor T1) and a corresponding channel region (e.g., a read channel region) formed by portions 910A, 910B, 910C, 910D, and 910E; a transistor (e.g., transistor T2) and a corresponding channel region (e.g., a write channel region) formed by portions 1220 and 1221; and a charge storage structure (e.g., a memory element) formed by portion 1202.

[0132] Fig.19 The memory device 900 may include data lines (e.g., read bit lines) 1821, 1822, and 1823 and data lines (e.g., write bit lines) 1821W and 1822W. The memory device 900 may include conductive lines 1501 and 1502, which may be electrically coupled to each other to form access lines (e.g., shared access lines) to control two transistors (e.g., T1 and T2) in each of the memory cells 210' and 211'. Figures 9 to 19 Other elements of memory device 900 are described.

[0133] Fig. 20 Memory device 2000 is shown, which may be Fig.19 Thus, the process used to form memory device 900 can be used to form memory device 2000. The differences between memory devices 900 and 2000 include the location of data lines (e.g., read bit lines) 1821, 1822, and 1823 relative to data lines (e.g., write bit lines) 1821W and 1822W. For example, Fig. 20 , data lines 1821, 1822, and 1823 may be located on the same level of memory device 2000. However, data lines 1821, 1822, and 1823 may be located on a level different from that of data lines 1821W and 1822W.

[0134] Fig.21A , Fig.21B and Fig. 21C Different views of the structure of a memory device 2100 including multiple stacks of memory cells according to some embodiments described herein are shown. Fig.21A An exploded view (eg, in the Z direction) of memory device 2100 is shown. Fig.21B Side views (eg, cross-sectional views) in the X-direction and the Z-direction of the memory device 210 are shown. Fig. 21C Side views (eg, cross-sectional views) in the Y-direction and the Z-direction of the memory device 2100 are shown.

[0135] like Fig.21A , the memory device 2100 may include stacks (stacks of memory cells) 21050, 21051, 21052, and 21053, which are shown separated from each other in an exploded view to facilitate viewing of the stack structure of the memory device 2100. In practice, the stacks 21050, 21051, 21052, and 21053 may be attached to each other in an arrangement where one stack may be formed (e.g., stacked) over a substrate (e.g., a semiconductor (e.g., silicon) substrate) 2199 over another stack. For example, as shown in FIG. Fig.21A As shown in , stacks 21050 , 21051 , 21052 , and 21053 may be formed in a Z direction perpendicular to the substrate 2199 (eg, formed vertically in the Z direction relative to the substrate 2199 ).

[0136] like Fig.21A, each of the stacks 21050, 21051, 21052, and 21053 may have memory cells arranged in the X direction and the Y direction (e.g., arranged in rows in the X direction and arranged in columns in the Y direction). For example, the stack 21050 may include memory cells 21100, 21110, 21120, and 21130 (e.g., arranged in rows), memory cells 21200, 21210, 21220, and 21230 (e.g., arranged in rows), and memory cells 21300, 21310, 21320, and 21330 (e.g., arranged in rows).

[0137] Stack 21051 may include memory cells 21101, 21111, 21121, and 21131 (eg, arranged in rows), memory cells 21201, 21211, 21221, and 21231 (eg, arranged in rows), and memory cells 21301, 21311, 21321, and 21331 (eg, arranged in rows).

[0138] Stack 21052 can include memory cells 21102, 21112, 21122, and 21132 (eg, arranged in rows), memory cells 21202, 21212, 21222, and 21232 (eg, arranged in rows), and memory cells 21302, 21312, 21322, and 21332 (eg, arranged in rows).

[0139] Stack 21053 can include memory cells 21103, 21113, 21123, and 21133 (e.g., arranged in rows), memory cells 21203, 21213, 21223, and 21233 (e.g., arranged in rows), and memory cells 21303, 21313, 21323, and 21333 (e.g., arranged in rows).

[0140] like Fig.21A , stacks 21050, 21051, 21052, and 21053 may be positioned (e.g., formed vertically in the Z direction) on levels (e.g., portions) 2150, 2151, 2152, and 2153, respectively, of the memory device 2100. The arrangement of the stacks 21050, 21051, 21052, and 21053 forms a 3-dimensional (3D) structure of memory cells of the memory device 2100, wherein different levels of memory cells of the memory device 2100 may be positioned (e.g., formed) in different levels (e.g., different vertical portions) 2150, 2151, 2152, and 2153 of the memory device 2100.

[0141] The stacks 21050, 21051, 21052, and 21053 may be formed one stack at a time. For example, the stacks 21050, 21051, 21052, and 21053 may be formed sequentially in the order of the stacks 21050, 21051, 21052, and 21053 (e.g., stack 21051 is formed first and stack 21053 is formed last). In this example, the memory cells of one stack (e.g., stack 21051) may be formed after forming the memory cells of another stack (e.g., stack 21050) or before forming the memory cells of another stack (e.g., stack 21052). Alternatively, stacks 21050, 21051, 21052, and 21053 may be formed in parallel (e.g., simultaneously) such that memory cells of stacks 21050, 21051, 21052, and 21053 may be formed in parallel. For example, memory cells in levels 2150, 2151, 2152, and 2153 of memory device 2100 may be formed in parallel.

[0142] The structure of the memory cells in each of the stacks 21050, 21051, 21052, and 21053 may include the above reference Figures 1 to 20 For example, the structure of the memory cells of stacks 21050, 21051, 21052, and 21053 may include the structure of the memory cells of memory devices 200, 900, and 2000.

[0143] The memory device 2100 may include data lines (eg, bit lines) and access lines (eg, word lines) to access the memory cells of the stacks 21050, 21051, 21052, and 21053. For simplicity, Fig.21A The data lines and access lines of the memory cells are omitted. However, the data lines and access lines of the memory device 2100 may be similar to those described above. Figures 1 to 20 Data lines and access lines of a memory device are described.

[0144] As an example, Fig.21A A memory device 2100 is shown that includes four stacks (e.g., 21050, 21051, 21052, and 21053). However, the number of stacks may be different than four. As an example, Fig.21A Each of the stacks 21050, 21051, 21052, and 21053 is shown including one level (e.g., layer) of memory cells. However, at least one of the stacks (e.g., one or more of the stacks 21050, 21051, 21052, and 21053) may have two (or more) levels of memory cells. Fig.21AAn example is shown where each of the stacks 21050, 21051, 21052, and 21053 includes four memory cells in the X direction (e.g., in rows) and three memory cells in the Y direction (e.g., in columns). However, the number of memory cells in rows, columns, or both can vary.

[0145] The description of apparatus (e.g., memory devices 100, 200, 900, 2000, and 2100) and methods (e.g., the operation of memory devices 100 and 200 and methods of forming memory devices 900 and 2000) is intended to provide a general understanding of the structure of various embodiments and is not intended to provide a complete description of all elements and features of apparatus that may utilize the structure described herein. An apparatus herein refers to, for example, a device (e.g., any one of memory devices 100, 200, 900, 2000, and 2100) or a system (e.g., an electronic article that may include any one of memory devices 100, 200, 900, 2000, and 2100).

[0146] References Figures 1 to 20 Any of the described components may be implemented in a number of ways, including via software simulation. Thus, the features of the apparatus (e.g., memory devices 100, 200, 900, 2000, and 2100) or portions of each of these memory devices described above may be "modules" herein. Such modules may include hardware circuitry, single and / or multi-processor circuits, memory circuits, software program modules and objects, and / or firmware, and combinations thereof, as required and / or appropriate for the particular implementation of the various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package, and / or a combination of software and hardware to operate or simulate the operation of the various potential embodiments.

[0147] The memory devices described herein (e.g., memory devices 100, 200, 900, 2000, and 2100) may be included in an apparatus (e.g., electronic circuit system), such as a high-speed computer, a communication and signal processing circuit system, a single processor or a multi-processor module, a single or multiple embedded processors, a multi-core processor, a message information switch, and a dedicated module including a multi-layer, multi-chip module. Such an apparatus may further be included as a subcomponent in a variety of other apparatuses (e.g., electronic systems) (e.g., televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, etc.).

[0148] References Figures 1 to 20 Embodiments described include devices and methods of forming the devices. One of the devices includes a memory cell located above a substrate and a first data line, a second data line, and a third data line. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the device, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the device and electrically coupled to the charge storage structure. The first data line and the second data line are located on a third level of the device and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region. Other embodiments including additional devices and methods are described.

[0149] In the detailed description and claims, the terms "on", one "on" another, used with respect to two or more elements (e.g., materials), mean at least some contact between the elements (e.g., between the materials). The term "over" means that the elements (e.g., materials) are in close proximity, but there may be one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither "on" nor "over" implies any directionality as used herein unless so stated.

[0150] In the detailed description and claims, a list of items joined by the term "at least one of" may mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0151] In the detailed description and claims, a list of items joined by the term "one of" may mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means either only A (not including B) or only B (not including A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0152] The above description and drawings illustrate some embodiments of the subject matter of the present invention to enable those skilled in the art to practice the embodiments of the subject matter of the present invention. Other embodiments may have structural, logical, electrical, process and other changes. The examples represent possible changes only. Portions and features of some embodiments may be included in those portions and features of other embodiments, or replace those portions and features. After reading and understanding the above description, those skilled in the art will understand many other embodiments.

Claims

1. A device comprising: A memory cell located above a substrate, the memory cell comprising: a first transistor comprising a charge storage structure located on a first level of the device, and a first channel region electrically isolated from the charge storage structure; and a second transistor including a second channel region located on a second level of the device and electrically coupled to the charge storage structure; a first data line electrically coupled to the first channel region; a second data line electrically coupled to the first channel region, the first data line and the second data line being located on a third level of the device, the second level being between the first level and the third level; as well as A third data line is electrically coupled to the second channel region and electrically separated from the first channel region. 2 . The apparatus of claim 1 , further comprising an access line including a portion spanning a portion of the first channel region and a portion of the second channel region.

3. The apparatus of claim 1 , wherein the first channel region comprises: a first portion located on a first side of the charge storage structure; a second portion located on a second side of the charge storage structure; and The third portion is located between the charge storage structure and the substrate. 4 . The apparatus of claim 1 , wherein the first channel region and the second channel region comprise different materials.

5. The apparatus of claim 1, wherein the charge storage structure comprises a semiconductor material.

6. The apparatus of claim 1, wherein the charge storage structure comprises a metal.

7. The apparatus of claim 1, wherein the second channel region comprises at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), Indium Zinc Oxide (In x Zn y O z ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a )、Zirconium oxide zinc tin (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

8. A device comprising: A first memory cell is located above the substrate, the first memory cell comprising: a first transistor comprising a first charge storage structure and a first region electrically isolated from the first charge storage structure; and a second transistor including a second region electrically coupled to the first charge storage structure; as well as a second memory cell located above the substrate, the second memory cell comprising: a third transistor comprising a second charge storage structure and a third region electrically isolated from the second charge storage structure; as well as a fourth transistor comprising a fourth region electrically coupled to the second charge storage structure; a first data line electrically coupled to the first region; a second data line electrically coupled to the third region; a third data line electrically coupled to the first region and the third region; and An access line spans a portion of each of the first region, the second region, the third region, and the fourth region.

9. The apparatus of claim 8, wherein the first data line, the second data line, and the third data line have a length in a first direction, and the access line has a length in a second direction.

10. The apparatus of claim 8, wherein a distance between each of the first charge storage structure and the second charge storage structure and the substrate is smaller than a distance between the access line and the substrate.

11. The apparatus of claim 8, wherein each of the first and third regions comprises a sheet of semiconductor material, and each of the second and fourth regions comprises a sheet of oxide material. 12 . The device of claim 8 , wherein the first data line, the second data line, and the third data line are located on a same level of the device.

13. The apparatus of claim 8, wherein: The first region is used to conduct current between the first data line and the third data line during an operation performed on the first memory cell; and The third region is used to conduct current between the second data line and the third data line during an operation performed on the second memory cell.

14. The apparatus of claim 8, wherein: The second region is used to conduct current between the second region and the first charge storage structure during operations performed on the first memory cell; and The fourth region is used to conduct current between the fourth region and the second charge storage structure during an operation performed on the second memory cell.

15. The apparatus of claim 8, wherein: The first transistor and the second transistor have different threshold voltages; and The third transistor and the fourth transistor have different threshold voltages.

16. A method for forming a memory device, comprising: forming a first transistor of a memory cell, including forming a charge storage structure above a substrate and forming a first channel region electrically separated from the charge storage structure; forming a second transistor of the memory cell, including forming a second channel region directly on the charge storage structure and electrically separated from the first channel region; forming a first data line electrically coupled to the first channel region; as well as A second data line electrically coupled to the first channel region is formed, wherein the first data line and the second data line are formed after forming the first channel region.

17. The method according to claim 16, further comprising: A third data line is formed that is electrically coupled to the second channel region and electrically separated from the first channel region, wherein the first data line, the second data line, and the third data line are formed on a same level of the memory device including the memory cell.

18. The method of claim 16, wherein forming the first data line and the second data line comprises: depositing a conductive material over at least a portion of the first channel region; and Portions of the conductive material are removed such that a first remaining portion of the conductive material forms the first data line and a second remaining portion of the conductive material forms the second data line.

19. The method of claim 16, further comprising: forming a first conductive line adjacent to a first side of each of the first channel region and the second channel region; as well as A second conductive line is formed adjacent to a second side of each of the first channel region and the second channel region, wherein the first conductive line and the second conductive line are formed before forming the first data line and the second data line.

20. The method of claim 16, wherein forming the charge storage structure and the second channel region comprises: depositing a first semiconductor material over the dielectric material; depositing a second semiconductor material directly on the first semiconductor material; removing a portion of the first semiconductor material to form the charge storage structure from a remaining portion of the first semiconductor material; as well as Portions of the second semiconductor material are removed to form the second channel region.

21. A method for forming a memory device, comprising: forming an opening in a semiconductor material; as well as forming at least a portion of a first transistor and a second transistor of a memory cell in the opening, comprising: forming a charge storage structure of the first transistor in the opening; forming a channel region of the second transistor in the opening; as well as forming a dielectric material in the opening to electrically separate the charge storage structure and the channel region from a first portion of the semiconductor material, to electrically separate the charge storage structure and the channel region from a second portion of the semiconductor material, and to electrically separate the charge storage structure and the channel region from a third portion of the semiconductor material; forming a first conductive line so that the first conductive line spans across first sides of the first and second portions of the semiconductor material and a first side of the channel region; forming a second conductive line so that the second conductive line spans second sides of the first and second portions of the semiconductor material and a second side of the channel region; forming a first data line electrically coupled to the first portion of the semiconductor material; as well as A second data line is formed that is electrically coupled to the second portion of the semiconductor material.

22. The method of claim 21 , wherein forming the charge storage structure and the channel region comprises: depositing a first semiconductor material over a portion of the dielectric material at the location of the opening; depositing a second semiconductor material directly on the first semiconductor material; removing a portion of the first semiconductor material to form the charge storage structure from a remaining portion of the first semiconductor material; as well as Portions of the second semiconductor material are removed to form the channel region.

23. The method of claim 21, further comprising forming a third data line electrically coupled to the channel region, wherein the forming the first data line, the second data line, and the third data line comprises: depositing a conductive material over at least a portion of the channel region and over the first portion and the second portion of the semiconductor material; and Portions of the conductive material are removed such that a first remaining portion of the conductive material forms the first data line, a second remaining portion of the conductive material forms the second data line, and a third remaining portion of the conductive material forms the third data line.

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