Display devices

Abstract

A display device includes a display panel, a drive controller, and a data driver. The drive controller processes input image data according to a variable input frequency and generates a data signal with a variable frame length. The data driver converts the data signal into a data voltage and outputs the data voltage to the display panel. The drive controller determines a variable frequency mode and generates an asymmetric data signal in the variable frequency mode, including a positive data signal and a negative data signal for the same grayscale value that are asymmetric with respect to a common voltage.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for driving the display device. More particularly, embodiments of the present invention relate to a display device synchronized with a variable frequency and a method for driving the display device. Background Art

[0002] A display device includes a display panel and a display panel driver. The display panel driver includes a drive controller, a gate driver, and a data driver. The drive controller adjusts the drive timing of the gate driver and the data driver. The gate driver outputs gate signals to the gate lines, and the data driver outputs data voltages to the data lines.

[0003] The host that provides the input image data to the driving controller may provide the input image data at a variable frequency. The driving controller processes the input image data in synchronization with the variable frequency. Summary of the Invention

[0004] When a display panel displays an image at a variable frequency, a difference in brightness of the image may be generated according to a frame rate, and a display defect may be exhibited due to the difference in brightness of the image.

[0005] An embodiment of the present invention provides a display device that is synchronized with a variable frequency and capable of improving display quality.

[0006] An embodiment of the present invention further provides a method for driving a display device.

[0007] In an embodiment of a display device according to the present invention, the display device includes a display panel, a drive controller, and a data driver. The drive controller processes input image data according to a variable input frequency and generates a data signal having a variable frame length. The data driver converts the data signal into a data voltage and outputs the data voltage to the display panel. The drive controller determines a variable frequency mode and generates an asymmetric data signal in the variable frequency mode, including a positive data signal and a negative data signal for the same grayscale value that are asymmetric with respect to a common voltage.

[0008] In an embodiment, the driving controller may determine whether the initial variable frequency mode starts. The driving controller may determine that the variable input frequency of the input image data changes in the initial variable frequency mode and determine the variable frequency mode.

[0009] In an embodiment, the driving controller may determine that the initial variable frequency mode starts when the pixel clock of the current frame is equal to the pixel clock of the maximum input frequency.

[0010] In an embodiment, the drive controller may determine that the initial variable frequency mode starts when the drive controller receives a variable frequency mode signal from the host.

[0011] In an embodiment, the driving controller may compare lengths of vertical blank periods of N frames, where N is a natural number equal to or greater than 2, and determine that the variable input frequency is changed when at least one of the vertical blank periods has a different length.

[0012] In an embodiment, when it is determined that the variable input frequency of the input image data is fixed, the variable frequency mode may be terminated.

[0013] In an embodiment, the driving controller may compare lengths of vertical blank periods of N frames, where N is a natural number equal to or greater than 2, and determine that the variable input frequency is fixed when the lengths of the vertical blank periods of the N frames are the same.

[0014] In an embodiment, the driving controller may generate an asymmetric data signal having an asymmetric value that is independent of the variable input frequency and varies according to a grayscale value of the input image data in a first frame of the variable frequency mode.

[0015] In an embodiment, the driving controller may generate an asymmetric data signal having an asymmetric value varying according to the variable input frequency and a grayscale value of the input image data in a subsequent frame of the variable frequency mode after the first frame of the variable frequency mode.

[0016] In an embodiment, in the second frame of the variable frequency mode, the driving controller may generate an asymmetric data signal based on the variable input frequency of the first frame of the variable frequency mode.

[0017] In an embodiment, the driving controller may generate an asymmetric data signal having an asymmetric value that varies according to a variable input frequency and a grayscale value of the input image data in a variable frequency mode.

[0018] In an embodiment, in a first frame of the variable frequency mode, the driving controller may generate an asymmetric data signal based on an input frequency of a last frame before the variable frequency mode.

[0019] In an embodiment, the driving controller may generate asymmetric data signals for grayscale values ​​that are equal to or less than a threshold grayscale value.

[0020] In an embodiment, the positive data signal of the asymmetric data signal may have a value smaller than the value of the positive data signal of the symmetric data signal.The negative data signal of the asymmetric data signal may have a value smaller than the value of the negative data signal of the symmetric data signal.

[0021] In an embodiment of a method for driving a display device, the method includes processing input image data according to a variable input frequency to generate a data signal having a varying frame length, converting the data signal into a data voltage, and outputting the data voltage to a display panel. Processing the input image data includes determining a variable frequency pattern and generating an asymmetric data signal in the variable frequency pattern, including a positive data signal and a negative data signal for the same grayscale value that are asymmetric with respect to a common voltage.

[0022] In an embodiment, determining the variable frequency mode may include determining whether an initial variable frequency mode starts and determining whether the variable input frequency of the input image data changes in the initial variable frequency mode to determine the variable frequency mode.

[0023] In an embodiment, determining the variable frequency mode may further include determining to terminate the variable frequency mode when it is determined that the variable input frequency of the input image data is fixed.

[0024] In an embodiment, in the first frame of the variable frequency mode, the asymmetric data signal may have an asymmetric value that is independent of the variable input frequency and varies according to the grayscale value of the input image data.

[0025] In an embodiment, in subsequent frames of the variable frequency mode after the first frame of the variable frequency mode, the asymmetric data signal may have an asymmetric value that varies according to the variable input frequency and the grayscale value of the input image data.

[0026] In an embodiment, in the variable frequency mode, the asymmetric data signal may have an asymmetric value that varies according to a variable input frequency and a grayscale value of the input image data.

[0027] According to the display device and the method of driving the same, a display panel is driven using an asymmetric data signal having positive and negative data signals asymmetric with respect to a common voltage in a variable frequency mode, so that a difference in brightness of an image according to frequency can be prevented.

[0028] Furthermore, the variable frequency pattern is accurately determined, so that display defects due to asymmetric data signals in the fixed frequency pattern can be prevented.

[0029] Therefore, the display quality of a display panel that displays images at a variable frequency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features and advantages of the present invention will become more apparent by describing in detail embodiments of the present invention with reference to the accompanying drawings, in which:

[0031] Figure 1 is a block diagram showing an embodiment of a display device according to the present invention;

[0032] Figure 2 It shows Figure 1 Schematic diagram of image processing of a drive controller;

[0033] Figure 3 It shows Figure 1 A schematic diagram of the operation of the drive controller;

[0034] Figure 4 It shows Figure 1 The timing diagram of the operation of the drive controller;

[0035] Figure 5 It shows Figure 1 A graph showing a voltage-transmittance curve of a display panel;

[0036] Figure 6 It is shown by Figure 1 Schematic diagram of asymmetric data generated by the drive controller;

[0037] Figure 7 It shows that according to Figure 1 A graph showing asymmetric data of grayscale values ​​generated by a driving controller;

[0038] Figure 8 It shows that according to Figure 1 A graph showing asymmetric data of frequency and grayscale value generated by a driving controller;

[0039] Figure 9 It shows Figure 1 A flowchart of the operation of the drive controller;

[0040] Figure 10 It shows that Figure 1 The vertical start signal output by the drive controller and Figure 1 A graph showing the brightness of a display panel;

[0041] Figure 11 is a schematic diagram illustrating an embodiment of the operation of a drive controller for a display device according to the present invention; and

[0042] Figure 12 It shows Figure 11 Timing diagram of the operation of the drive controller. DETAILED DESCRIPTION

[0043] Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.

[0044] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0045] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this document, the "first element," "first component," "first region," "first layer," or "first part" discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0046] The wording used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, which include "at least one", unless the content clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when the terms "comprise" and / or "comprises", or "includes" and / or "includes" are used in this specification, it indicates the presence of the stated features, regions, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or groups thereof.

[0047] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the accompanying drawings. In an embodiment, when the device in one of the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will subsequently be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" can include both "lower" and "upper" orientations depending on the specific orientation of the accompanying drawings. Similarly, when the device in one of the drawings is turned over, the element described as being "below" or "beneath" the other elements will subsequently be oriented as being "above" the other elements. Thus, the exemplary term "below" or "beneath" can include both "upper" and "lower" orientations.

[0048] As used herein, "about" or "approximately" includes the stated value and the mean within an acceptable range of deviations from the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0050] The embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shapes that are, for example, caused by manufacturing. In embodiments, regions shown or described as flat may generally have rough and / or nonlinear features. In addition, sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0051] Figure 1 is a block diagram showing an embodiment of a display device according to the present invention.

[0052] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display device may further include a host 600.

[0053] In an embodiment, for example, the driving controller 200 and the data driver 500 may be integrated. In an embodiment, for example, the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 may be integrated. A driving module including at least the integrated driving controller 200 and the data driver 500 may be referred to as a timing controller embedded data driver ("TED").

[0054] The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels P connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 crossing the first direction D1.

[0055] In an embodiment, for example, the display panel 100 may be a liquid crystal display panel including a liquid crystal layer. In an alternative embodiment, for example, the display panel 100 may be an organic light emitting display panel including an organic light emitting element.

[0056] The drive controller 200 receives input image data IMG and input control signals CONT from the host 600. In one embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. In one embodiment, for example, the input image data IMG may include white image data. In one embodiment, for example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signals CONT may include a master clock signal and a data enable signal. The input control signals CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0057] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0058] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may further include a vertical start signal and a gate clock signal.

[0059] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0060] The driving controller 200 generates a data signal DATA based on the input image data IMG and outputs the data signal DATA to the data driver 500 .

[0061] In this embodiment, for example, the driving controller 200 may process the input image data IMG according to a variable input frequency and generate the data signal DATA having a variable frame length.

[0062] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0063] Reference Figures 2 to 9 The structure and operation of the driving controller 200 are explained in detail.

[0064] The gate driver 300 generates a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 outputs the gate signal to the gate line GL. In an embodiment, for example, the gate driver 300 may sequentially output the gate signal to the gate line GL. In an embodiment, for example, the gate driver 300 may be provided (e.g., mounted) on the display panel 100. In an embodiment, for example, the gate driver 300 may be integrated on the display panel 100.

[0065] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0066] In an embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500 .

[0067] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog data voltage using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0068] The host 600 may output the input image data IMG and the input control signal CONT to the driving controller 200. In an embodiment, for example, the host 600 may output a variable frequency mode signal indicating that the input image data IMG has a variable frequency. In an embodiment, for example, the host 600 may be a graphics processing unit.

[0069] Figure 2 It shows Figure 1 Schematic diagram of image processing of the driving controller 200.

[0070] Reference Figure 1 and Figure 2 , the host 600 may output the input image data IMG having a variable input frequency to the driving controller 200 .

[0071] The driving controller 200 may generate the data signal DATA having a variable frame length by processing the input image data IMG having a variable input frequency.

[0072] The data signal DATA may include active periods AC1, AC2, AC3, AC4, and AC5 and blank periods BL1, BL2, BL3, BL4, and BL5. The data signal DATA may include grayscale data during the active periods AC1, AC2, AC3, AC4, and AC5. The data signal DATA may not include grayscale data during the blank periods BL1, BL2, BL3, BL4, and BL5. In an embodiment, for example, the active periods AC1, AC2, AC3, AC4, and AC5 may correspond to scan periods of gate signals. In an embodiment, for example, the blank periods BL1, BL2, BL3, BL4, and BL5 may correspond to non-scanning periods of gate signals. The blank periods BL1, BL2, BL3, BL4, and BL5 may also be referred to as vertical blank periods.

[0073] The drive controller 200 can adjust the lengths of the blank periods BL1, BL2, BL3, BL4, and BL5 of the data signal DATA according to the variable input frequency. In contrast, the lengths of the active periods AC1, AC2, AC3, AC4, and AC5 can be consistent regardless of the variable input frequency. The drive controller 200 can set the lengths of the active periods AC1, AC2, AC3, AC4, and AC5 based on the maximum input frequency of the input image data IMG.

[0074] exist Figure 2 In the embodiment, a first frame data signal having a first active period AC1 and a first blank period BL1 may be generated corresponding to a first frame FRAME1 having a first input frequency.

[0075] A second frame data signal having a second active period AC2 and a second blank period BL2 may be generated corresponding to a second frame FRAME2 having a second input frequency. In one embodiment, for example, the second input frequency may be lower than the first input frequency. Therefore, the length of the second frame FRAME2 may be longer than the length of the first frame FRAME1. The length of the second active period AC2 may be substantially the same as the length of the first active period AC1. The length of the second blank period BL2 may be longer than the length of the first blank period BL1.

[0076] A third frame data signal having a third active period AC3 and a third blank period BL3 may be generated corresponding to a third frame FRAME3 having a third input frequency. In one embodiment, for example, the third input frequency may be higher than the first input frequency. Therefore, the length of the third frame FRAME3 may be shorter than that of the first frame FRAME1. The length of the third active period AC3 may be substantially the same as that of the first active period AC1. The length of the third blank period BL3 may be shorter than that of the first blank period BL1.

[0077] A fourth frame data signal having a fourth active period AC4 and a fourth blank period BL4 may be generated corresponding to a fourth frame FRAME4 having a fourth input frequency. In an embodiment, for example, the fourth input frequency may be lower than the first input frequency. The length of the fourth active period AC4 may be substantially the same as the length of the first active period AC1. The length of the fourth blank period BL4 may be longer than the length of the first blank period BL1.

[0078] A fifth frame data signal having a fifth active period AC5 and a fifth blank period BL5 may be generated corresponding to a fifth frame FRAME5 having a fifth input frequency. In an embodiment, for example, the fifth input frequency may be higher than the first input frequency. The length of the fifth active period AC5 may be substantially the same as the length of the first active period AC1. The length of the fifth blank period BL5 may be shorter than the length of the first blank period BL1.

[0079] As explained above, the driving controller 200 may process the input image data IMG according to a variable input frequency to generate the data signal DATA having a variable frame length.

[0080] Figure 3 It shows Figure 1 Schematic diagram of the operation of the drive controller 200. Figure 4 It shows Figure 1 A timing diagram of the operation of the driving controller 200.

[0081] Reference Figures 1 to 4 , the driving controller 200 may determine a variable frequency mode and generate an asymmetric data signal DATA including a positive data signal and a negative data signal that are asymmetric with respect to a common voltage for the same grayscale value in the variable frequency mode.

[0082] In an embodiment, for example, the variable frequency mode may be a gaming mode that means the user plays a game. The variable frequency mode may also be referred to as a free synchronization mode.

[0083] exist Figure 4 , the pulse of the vertical start signal STV can indicate the starting point of a frame of the input image data IMG, and the data enable signal DE can indicate a vertical active period (corresponding to a high period of the data enable signal DE) and a vertical blank period (corresponding to a low period of the data enable signal DE) of the input image data IMG.

[0084] The driving controller 200 may determine whether an initial variable frequency mode starts (operation S310 ), and determine whether the input frequency of the input image data IMG changes in the initial variable frequency mode to accurately determine the variable frequency mode (operation S320 ).

[0085] In an embodiment, when the pixel clock of the current frame is equal to the pixel clock of the maximum input frequency, the drive controller 200 may determine that the initial variable frequency mode has begun. The pixel clock may be expressed as the product of the horizontal resolution, the vertical resolution, and the input frequency. The horizontal resolution may correspond to the horizontal active period and the horizontal blank period. The vertical resolution may correspond to the vertical active period and the vertical blank period. In an embodiment, for example, the maximum input frequency may be approximately 240 Hz.

[0086] In an embodiment, for example, when the pixel clock corresponds to about 60 Hz and then the pixel clock has changed to correspond to about 240 Hz, the driving controller 200 may determine that the initial variable frequency mode starts.

[0087] In an embodiment, the drive controller 200 can determine that the initial variable frequency mode starts when the drive controller 200 receives the variable frequency mode signal from the host 600. When the host 600 outputs the variable frequency mode signal to the drive controller 200, the drive controller 200 can relatively easily determine that the initial variable frequency mode starts.

[0088] The driving controller 200 may determine whether the input frequency of the input image data IMG is changed in the initial variable frequency mode to determine the variable frequency mode (operation S320).

[0089] In an embodiment, for example, the driving controller 200 may compare lengths of vertical blank periods of N frames, where N is a natural number equal to or greater than 2, and determine that the input frequency changes when at least one of the vertical blank periods has a different length.

[0090] Although for the convenience of explanation Figure 4 In the embodiment, N is 3, but the present invention is not limited thereto. In an embodiment, for example, N can be set to be long enough for variable frequency determination and fixed frequency determination. In an embodiment, for example, N can have a value in the tens of thousands.

[0091] The driving controller 200 compares the lengths of the vertical blank periods of the N frames and determines that the input frequency is variable when at least one of the vertical blank periods has a different length. Therefore, when the length of the vertical blank period of the previous frame is different from the length of the vertical blank period of the current frame, the driving controller 200 can immediately determine that the input frequency is variable.

[0092] exist Figure 4In the embodiment, the initial variable frequency mode starts at a first time point T1, and the length of the first vertical blank period BA of the first frame of the initial variable frequency mode is equal to the length of the second vertical blank period BB of the second frame of the initial variable frequency mode, so that the driving controller 200 does not determine that the input frequency is variable in the second frame of the initial variable frequency mode.

[0093] The length of the second vertical blank period BB of the second frame of the initial variable frequency mode is different from the length of the third vertical blank period BC of the third frame of the initial variable frequency mode, so that the driving controller 200 can determine that the input frequency is variable in the third frame of the initial variable frequency mode.

[0094] The driving controller 200 may apply the asymmetric data signal DATA starting from a second time point T2 corresponding to a start point of a fourth frame of the initial variable frequency mode to drive the display device.

[0095] When the variable frequency mode starts (at the second time point T2), the frequency may vary frame by frame. However, when the frequency of the frame is fixed for a predetermined time period, the variable frequency mode may terminate. When the asymmetric data signal DATA is continuously applied even when the frequency is fixed, display quality may deteriorate.

[0096] When the driving controller 200 determines that the frequency is fixed, the driving controller 200 may determine that the variable frequency mode is terminated. When the variable frequency mode is terminated, the display device may operate in the fixed frequency mode.

[0097] In an embodiment, for example, the driving controller 200 may compare the lengths of vertical blank periods of N frames and determine that the input frequency is fixed when the lengths of the vertical blank periods of the N frames are all the same.

[0098] As mentioned above, although for the convenience of explanation Figure 4 In the embodiment, N is 3, but the present invention may not be limited thereto. In the embodiment, for example, N may be set to be long enough for variable frequency determination and fixed frequency determination.

[0099] exist Figure 4 In the embodiment of the present invention, after the variable frequency mode starts (at the second time point T2), the frequency may vary frame by frame. However, when the length of the vertical blank period is the same for N (e.g., three) frames such as BD, BE, and BF, the driving controller 200 may determine that the input frequency is fixed (at the fourth time point T4).

[0100] Figure 5 It shows Figure 1 FIG. 1 is a graph showing a voltage-transmittance curve of the display panel 100 . Figure 6 It is shown by Figure 1Schematic diagram of asymmetric data generated by the driving controller 200. Figure 7 It shows that according to Figure 1 A graph showing asymmetric data of grayscale values ​​generated by the driving controller 200. Figure 8 It shows that according to Figure 1 A graph of asymmetric data of frequency and grayscale value generated by the driving controller 200.

[0101] Reference Figures 1 to 8 , in the first frame T2-T3 of the variable frequency mode (between the second time point T2 and the third time point T3), the driving controller 200 may generate an asymmetric data signal DATA having an asymmetric value, wherein the asymmetric value is independent of the input frequency and varies according to the grayscale value of the input image data IMG (operation S330).

[0102] When the data signal is not compensated in the first frame of the variable frequency mode (for example, when the data signal is a symmetrical data signal including a positive data signal and a negative data signal that are symmetrical with respect to a common voltage), the brightness of the displayed image may decrease. Due to the decrease in the brightness of the displayed image, flickering may be displayed to the user, so that the display quality may be degraded.

[0103] In contrast, when the asymmetrical data signal DATA is generated in the first frame of the variable frequency mode, the brightness difference between the first frame of the variable frequency mode and the previous frame may be minimized, thereby preventing flicker.

[0104] like Figure 5 As shown, the driving controller 200 can generate an asymmetric data signal DATA for grayscale values ​​equal to or less than the threshold grayscale value GTH. For a voltage corresponding to a grayscale value equal to or less than the threshold grayscale value GTH, Figure 5 The voltage-transmittance curve of may be nonlinear, so that brightness compensation using the asymmetric data signal DATA may be more effective for grayscale values ​​equal to or less than the threshold grayscale value GTH.

[0105] Although the asymmetric data signal DATA is used for grayscale values ​​equal to or less than the threshold grayscale value GTH in the embodiment, the present invention is not limited thereto. According to the voltage-transmittance characteristic of the display panel 100, the asymmetric data signal DATA may be used for the entire grayscale region.

[0106] exist Figure 6 In the embodiment, the first positive data signal VP1 and the first negative data signal VN1 are symmetrical with respect to the common voltage VCOM, so that the first positive data signal VP1 and the first negative data signal VN1 can represent symmetrical data signals. Figure 6In the embodiment, the second positive data signal VP2 and the second negative data signal VN2 are asymmetric with respect to the common voltage VCOM, so that the second positive data signal VP2 and the second negative data signal VN2 may represent asymmetric data signals.

[0107] In an embodiment, the second positive data signal VP2 of the asymmetric data signal may have a value smaller than the first positive data signal VP1 of the symmetric data signal. In addition, the second negative data signal VN2 of the asymmetric data signal may have a value smaller than the first negative data signal VN1 of the symmetric data signal.

[0108] In an alternative embodiment, the second positive data signal VP2 of the asymmetric data signal can be adjusted to have a value greater than the value of the first positive data signal VP1 of the symmetric data signal. In addition, the second negative data signal VN2 of the asymmetric data signal can be adjusted to have a value greater than the value of the first negative data signal VN1 of the symmetric data signal.

[0109] The brightness of the displayed image may be defined by the difference between the second positive data signal VP2 and the common voltage VCOM, and by the difference between the second negative data signal VN2 and the common voltage VCOM. Therefore, when the second positive data signal VP2 and the second negative data signal VN2 of asymmetric data have values ​​smaller than the values ​​of the first positive data signal VP1 and the first negative data signal VN1 of symmetric data, respectively, the brightness of the displayed image may not be reduced.

[0110] When the asymmetry between the second positive data signal VP2 and the second negative data signal VN2 increases, due to Figure 5 By making the voltage-transmittance curve nonlinear, the brightness of the displayed image can be increased.

[0111] Figure 7 Represents the asymmetric data signal DATA in the first frame T2-T3 of the variable frequency mode.

[0112] The asymmetric data signal DATA in the first frame T2 - T3 of the variable frequency mode may be independent of the input frequency and may vary according to the grayscale value of the input image data IMG.

[0113] like Figure 7 As shown, the asymmetry degree of the asymmetric data signal DATA may vary according to the grayscale value of the input image data IMG.

[0114] In the first frame T2-T3 of the variable frequency mode, the asymmetric data signal DATA may be determined based on the minimum frequency.

[0115] In the first frame T2-T3 of the variable frequency mode, there is no information of the previous frame, so that an asymmetric data signal DATA can be generated regardless of the input frequency.

[0116] In subsequent frames T3-T4 of the variable frequency mode after the first frame T2-T3 of the variable frequency mode (between the third time point T3 and the fourth time point T4), the driving controller 200 may generate an asymmetric data signal DATA having an asymmetric value that varies according to the input frequency and grayscale value of the input image data IMG (operation S340).

[0117] Herein, in the second frame of the variable frequency mode, the driving controller 200 may generate the asymmetric data signal DATA based on the input frequency of the first frame of the variable frequency mode.

[0118] Figure 8 represents the asymmetric data signal DATA in subsequent frames T3-T4 of the variable frequency mode after the first frame T2-T3 of the variable frequency mode.

[0119] like Figure 8 As shown in , the degree of asymmetry of the asymmetric data signal DATA may vary according to the grayscale value of the input image data IMG and according to the input frequency.

[0120] In subsequent frames T3-T4 of the variable frequency mode after the first frame T2-T3 of the variable frequency mode, as the input frequency decreases, the absolute value of the asymmetric data signal DATA increases. Figure 8 In the embodiment, a graph corresponding to an input frequency of about 240 Hz may be set closest to the common voltage VCOM, and a graph corresponding to an input frequency of about 48 Hz may be set farthest from the common voltage VCOM.

[0121] In subsequent frames T3-T4 of the variable frequency mode after the first frame T2-T3 of the variable frequency mode, the gap between the positive data signal and the negative data signal can be adjusted according to the frequency and grayscale value to compensate for the brightness of the displayed image by maintaining the asymmetry degree (asymmetry ratio) of the first frame T2-T3.

[0122] In an embodiment, for example, when grayscale values ​​of 32, 64, and 128 are mapped to grayscale values ​​of 27, 43, and 106 in the positive region and grayscale values ​​of 45, 88, and 152 in the negative region for a frequency (reference frequency) of approximately 240 Hz in a variable frequency mode, for a grayscale value of 32 of the input image data IMG having a frequency of approximately 240 Hz, the positive data signal has a grayscale value of 27 and the negative data signal has a grayscale value of 45, for a grayscale value of 64 of the input image data IMG having a frequency of approximately 240 Hz, the positive data signal has a grayscale value of 43 and the negative data signal has a grayscale value of 88, and for a grayscale value of 128 of the input image data IMG having a frequency of approximately 240 Hz, the positive data signal has a grayscale value of 106 and the negative data signal has a grayscale value of 152.

[0123] In a similar manner, input image data IMG having an input frequency other than approximately 240 Hz may be obtained using Figure 8 The curve for input frequencies other than about 240 Hz is converted into a data signal. Figure 8 The interpolation method of the frequency curve shown in the figure produces Figure 8 Input image data IMG having an input frequency other than the frequencies shown in .

[0124] Figure 9 It shows Figure 1 Flowchart of the operation of the drive controller 200.

[0125] Reference Figures 1 to 9 The operation of S901 represents an operation of counting pixel clocks. In the operation of S902, it is determined whether the clock count CLK_CNT is equal to the product of the horizontal resolution H_TOTAL, the vertical resolution V_TOTAL, and the maximum input frequency FREQ_GAME. In the operation of S903, when the clock count CLK_CNT is equal to the product of the horizontal resolution H_TOTAL, the vertical resolution V_TOTAL, and the maximum input frequency FREQ_GAME, it is determined whether the data enable signal DE is in an active state. In this article, when the data enable signal DE is in an active state, asymmetric data driving is not required, so that the clock count can be reset (operation S916).

[0126] In the operation of S904 and the operation of S905 , until the data enable signal DE is input, a vertical blank count may be accumulated to determine the length of the vertical blank period.

[0127] In operation S906 , the length of the vertical blank period V_BLK_CNT_FN of each frame is determined using the length of the vertical blank period determined in operations S904 and S905 .

[0128] In operation S907 , when the lengths of the vertical blank periods V_BLK_CNT_FN of N frames are all the same, it is determined to be a fixed frequency mode and it is determined that asymmetric data driving is not required, so that the reset process can be operated (operations S913 , S914 , S915 and S916 ).

[0129] In operation S907, when at least one of the lengths of the vertical blank periods V_BLK_CNT_FN of the N frames is different, it is determined as a variable frequency mode so that asymmetric data driving is operated (operation S908), and then the reset process can be operated (operations S909, S910, S911 and S912).

[0130] Figure 10 It shows that Figure 1 The vertical start signal STV output by the driving controller 200 and Figure 1 A graph showing the brightness of the display panel 100 is shown in FIG.

[0131] Reference Figures 1 to 10 , Figure 10 L1 in represents the brightness curve corresponding to the embodiment, and Figure 10 L2 in φ represents a brightness curve corresponding to a conventional brightness compensation method. In the conventional brightness compensation method, as the length of the vertical blank period increases, the driving voltage of the data driver 500 increases, so that the brightness reduction in the variable frequency mode can be compensated.

[0132] In conventional brightness compensation methods, the compensation driving voltage of the data driver 500 is applied to the next frame, so that the brightness can be significantly reduced in the first frame of the variable frequency mode. In contrast, in an embodiment, the drive controller 200 can generate an asymmetric data signal DATA having an asymmetric value that is independent of the input frequency and varies according to the grayscale value of the input image data IMG in the first frame T2-T3 of the variable frequency mode. Therefore, when the asymmetric data signal DATA is generated in the first frame of the variable frequency mode, the brightness difference between the first frame of the variable frequency mode and the previous frame can be minimized, so that flicker can be prevented. In the brightness curve of the embodiment, the asymmetric data signal DATA can be used to solve the single-frame delay problem.

[0133] Furthermore, in subsequent frames T3-T4 of the variable frequency mode following the first frame T2-T3 of the variable frequency mode, as the input frequency decreases, the absolute value of the asymmetric data signal DATA increases. In subsequent frames T3-T4 of the variable frequency mode following the first frame T2-T3 of the variable frequency mode, the gap between the positive data signal and the negative data signal can be adjusted based on the frequency and grayscale value to compensate for the brightness of the displayed image by maintaining the degree of asymmetry (asymmetry ratio) of the first frame T2-T3. After the first frame T2-T3 of the variable frequency mode, the asymmetric data signal DATA based on the frequency and grayscale value can be used to compensate for the decrease in brightness, thereby improving brightness uniformity in the variable frequency mode.

[0134] According to an embodiment, the display panel 100 is driven using an asymmetric data signal DATA having positive and negative data signals that are asymmetric with respect to a common voltage in the variable frequency mode, so that a difference in image brightness according to frequency can be prevented in the first frame T2-T3 of the variable frequency mode and in subsequent frames T3-T4 of the variable frequency mode after the first frame T2-T3 of the variable frequency mode.

[0135] Furthermore, the variable frequency pattern is accurately determined, so that display defects due to asymmetric data signals in the fixed frequency pattern can be prevented.

[0136] Therefore, the display quality of the display panel 100 displaying an image at a variable frequency can be improved.

[0137] Figure 11 is a schematic diagram illustrating an embodiment of the operation of a driving controller of a display device according to the present invention. Figure 12 It shows Figure 11 Timing diagram of the operation of the drive controller.

[0138] The display device and the method for driving the display device in the embodiment are similar to those in the reference Figures 1 to 10 The display device and the method of driving the display device of the aforementioned embodiment are substantially the same except for the structure and operation of the driving controller. Therefore, the same reference numerals will be used to represent the same Figures 1 to 10 The components are the same as or similar to those described in the aforementioned embodiments, and any repeated explanation concerning the above elements will be omitted.

[0139] Reference Figure 1 、 Figure 2 as well as Figures 5 to 12 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display device may further include a host 600.

[0140] The driving controller 200 may determine a variable frequency mode and generate an asymmetric data signal DATA including a positive data signal and a negative data signal that are asymmetric with respect to a common voltage for the same grayscale value in the variable frequency mode.

[0141] The driving controller 200 may determine whether the initial variable frequency mode starts (operation S1110 ), and determine whether the input frequency of the input image data IMG changes in the initial variable frequency mode to accurately determine the variable frequency mode (operation S1120 ).

[0142] The driving controller 200 may determine whether the input frequency of the input image data IMG is changed in the initial variable frequency mode to determine the variable frequency mode (operation S1120).

[0143] In this embodiment, in the first frame T2-T3 of the variable frequency mode, the driving controller 200 may generate the asymmetric data signal DATA having an asymmetric value that varies according to the input frequency and grayscale value of the input image data IMG (operation S1130).

[0144] Furthermore, in subsequent frames T3-T4 of the variable frequency mode after the first frame T2-T3 of the variable frequency mode, the driving controller 200 may generate an asymmetric data signal DATA having an asymmetric value varying according to the input frequency and grayscale value of the input image data IMG (operation S1130).

[0145] In the first frame T2 - T3 of the variable frequency mode, the driving controller 200 may generate the asymmetric data signal DATA based on the input frequency of the last frame before the variable frequency mode.

[0146] In the second frame of the variable frequency mode, the driving controller 200 may generate the asymmetric data signal DATA based on the input frequency of the first frame T2 - T3 of the variable frequency mode.

[0147] exist Figure 3 and Figure 4 In the first frame T2-T3 of the variable frequency mode, the driving controller 200 may generate an asymmetric data signal DATA having an asymmetric value that is independent of the input frequency and varies according to the grayscale value of the input image data IMG. Figure 3 and Figure 4 The embodiments are different. Figure 11 and Figure 12In the embodiment, the driving controller 200 can use the input frequency of the last frame before the variable frequency mode to generate an asymmetric data signal DATA having an asymmetric value that varies according to the input frequency and grayscale value of the input image data IMG from the first frame T2-T3 of the variable frequency mode. In the embodiment, the asymmetric data signal DATA can be generated in the same manner for the first frame of the variable frequency mode and the remaining frames of the variable frequency mode, so that the asymmetric data signal DATA can be generated by simple logic compared to the previous embodiment, and similar effects as the previous embodiment can be achieved.

[0148] According to an embodiment, the display panel 100 is driven using an asymmetric data signal DATA having positive and negative data signals that are asymmetric with respect to a common voltage in the variable frequency mode, so that a difference in image brightness according to frequency can be prevented in the first frame T2-T3 of the variable frequency mode and in subsequent frames T3-T4 of the variable frequency mode after the first frame T2-T3 of the variable frequency mode.

[0149] Furthermore, the variable frequency pattern is accurately determined, so that display defects due to asymmetric data signals in the fixed frequency pattern can be prevented.

[0150] Therefore, the display quality of the display panel 100 displaying an image at a variable frequency can be improved.

[0151] According to the present invention as explained above, the power consumption of the display device can be reduced and the display quality of the display panel can be improved.

[0152] The foregoing is illustrative of the present invention and should not be construed as limiting the present invention. Although some embodiments of the present invention have been described, it will be readily understood by those skilled in the art that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover structures described herein as performing the described functions, and not only structural equivalents, but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the present invention and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the present invention.

Claims

1. A display device, comprising: Display panel; a drive controller that processes input image data according to a variable input frequency and generates a data signal having a varying frame length; as well as a data driver, converting the data signal into a data voltage and outputting the data voltage to the display panel; The driving controller determines a variable frequency mode and generates an asymmetric data signal including a positive data signal and a negative data signal that are asymmetric with respect to a common voltage for the same grayscale value in the variable frequency mode, and determines a fixed frequency mode and does not generate the asymmetric data signal in the fixed frequency mode.

2. The display device according to claim 1, wherein The drive controller determines whether an initial variable frequency mode is started, and The driving controller determines that the variable input frequency of the input image data is changed in the initial variable frequency mode and determines the variable frequency mode.

3. The display device according to claim 2, wherein When the pixel clock of the current frame is equal to the pixel clock of the maximum input frequency, the driving controller determines that the initial variable frequency mode starts.

4. The display device according to claim 2, wherein When the drive controller receives a variable frequency mode signal from a host, the drive controller determines that the initial variable frequency mode starts.

5. The display device according to claim 2, wherein The driving controller compares lengths of vertical blank periods of N frames, where N is a natural number equal to or greater than 2, and determines that the variable input frequency is changed when at least one of the vertical blank periods has a different length. The display device according to claim 2 , wherein: When it is determined that the variable input frequency of the input image data is fixed, the variable frequency mode is terminated.

7. The display device according to claim 6, wherein The driving controller compares lengths of vertical blank periods of N frames, where N is a natural number equal to or greater than 2, and determines that the variable input frequency is fixed when the lengths of the vertical blank periods of the N frames are the same.

8. The display device according to claim 1, wherein The driving controller generates the asymmetric data signal having an asymmetric value that is independent of the variable input frequency and varies according to a grayscale value of the input image data in a first frame of the variable frequency mode.

9. The display device according to claim 8, wherein The driving controller generates the asymmetric data signal having an asymmetric value that varies according to the variable input frequency and the grayscale value of the input image data in a subsequent frame of the variable frequency mode after the first frame of the variable frequency mode.

10. The display device according to claim 9, wherein In a second frame of the variable frequency mode, the driving controller generates the asymmetric data signal based on the variable input frequency of the first frame of the variable frequency mode.

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