Package, package structure, and method for forming package

Abstract

An embodiment of the present application provides a packaging structure, including: an optical plug-in connected to a package substrate, wherein the optical plug-in includes: a silicon waveguide; a first photonic component optically connected to the silicon waveguide; a second photonic component optically connected to the silicon waveguide; and an interconnection structure extending above the silicon waveguide, above the first photonic component, and above the second photonic component, wherein the interconnection structure is electrically connected to the first photonic component and to the second photonic component; a first semiconductor device connected to the interconnection structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnection structure; and a second semiconductor device connected to the interconnection structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnection structure. According to other embodiments of the present application, a package and a method of forming a package are also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to packages and package structures and methods of forming packages. Background Art

[0002] Electronic signaling and processing is one technology used for signal transmission and processing.In recent years, optical signaling and processing has been used in an increasing number of applications, particularly due to the use of optical fiber related applications for signal transmission.

[0003] Optical signaling and processing are often combined with electronic signaling and processing to provide comprehensive applications. For example, optical fibers can be used for long-distance signal transmission, while electrical signals can be used for short-distance signal transmission as well as processing and control. Summary of the invention

[0004] According to one embodiment of the present application, a package is provided, comprising: a first optical plug-in connected to a package substrate, wherein the first optical plug-in comprises: a first waveguide located on the first substrate; and at least one photonic device located on the first substrate, wherein the at least one photonic device is optically connected to the first waveguide; a second optical plug-in connected to the package substrate, wherein the second optical plug-in comprises: a second waveguide located on the second substrate; and at least one photonic device located on the second substrate, wherein the at least one photonic device is optically connected to the second waveguide; an electronic plug-in connected to the package substrate, wherein the electronic plug-in comprises an interconnection structure located on a third substrate; a first semiconductor device connected to the first optical plug-in and to the electronic plug-in, wherein the first semiconductor device is electrically connected to at least one photonic device of the first optical plug-in and to the interconnection structure of the electronic plug-in; and a second semiconductor device connected to the second optical plug-in and to the electronic plug-in, wherein the second semiconductor device is electrically connected to at least one photonic device of the second optical plug-in and to the interconnection structure of the electronic plug-in.

[0005] According to another embodiment of the present application, a packaging structure is provided, including: an optical plug-in connected to a package substrate, wherein the optical plug-in includes: a silicon waveguide; a first photonic component optically connected to the silicon waveguide; a second photonic component optically connected to the silicon waveguide; and an interconnect structure extending above the silicon waveguide, above the first photonic component, and above the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component; a first semiconductor device connected to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component via the interconnect structure; and a second semiconductor device connected to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component via the interconnect structure.

[0006] According to another embodiment of the present application, a method for forming a package is provided, comprising: forming a first optical plug-in, including: patterning a silicon layer disposed on a first substrate to form a waveguide; forming a photodetector and an optical modulator adjacent to the waveguide; forming a dielectric layer located above the waveguide, the photodetector, and the optical modulator; and forming a conductive contact extending through the dielectric layer to contact the photodetector and the optical modulator; forming an electronic plug-in, including: forming a through-hole extending through a second substrate; and forming a redistribution structure located on the through-hole and on the second substrate; connecting the first optical plug-in and the electronic plug-in to an interconnect substrate; and connecting a first semiconductor device to the first optical plug-in and to the electronic plug-in, wherein the first semiconductor device is electrically connected to the first optical plug-in and to the electronic plug-in.

[0007] Embodiments of the present application relate to photonic semiconductor devices and methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figures 1 to 9 A cross-sectional view showing an intermediate step in forming an optical insert according to some embodiments;

[0010] Fig.10 shows a cross-sectional view of an optical plug-in having a grating connector connected to an optical fiber according to some embodiments;

[0011] Fig.11 shows a cross-sectional view of an optical insert having an edge connector connected to an optical fiber according to some embodiments;

[0012] Figures 12 to 18 A cross-sectional view illustrating an intermediate step in forming an electronic package according to some embodiments;

[0013] Fig.19 illustrates a cross-sectional view of a computing system according to some embodiments;

[0014] Fig. 20 shows a plan view of a computing system according to some embodiments;

[0015] Figure 21A-21B illustrates cross-sectional and plan views of a computing system according to some embodiments;

[0016] Figure 22A-22B illustrates cross-sectional and plan views of a computing system according to some embodiments;

[0017] Figure 23A-23Billustrates cross-sectional and plan views of a computing system according to some embodiments;

[0018] Fig.24 shows a cross-sectional view of a computing unit according to some embodiments;

[0019] Fig.25 A schematic diagram of a computing network with multiple computing units is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0021] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0022] In the present disclosure, various aspects of a computing system and its formation are described. According to some embodiments, a three-dimensional (3D) package including both a photonic device and an electronic device and a method of forming the same are provided. In particular, an optical plug-in including a waveguide and a photonic device is capable of optical communication for a computing system. An optical fiber can be connected to the optical plug-in to provide optical communication with an external component. The optical plug-in can also have a waveguide that facilitates optical communication between components within the computing system. According to some embodiments, intermediate stages of forming a computing system are shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, similar reference numerals are used to represent similar elements.

[0023] Figures 1 to 11 The optical insert 100 (see FIG. Figure 10-11). In some embodiments, optical plug-in 100 is used as an optical interconnect that enables the use of optical plug-in 100 in a computing system (e.g., Fig.19 The computing system 300) is capable of high bandwidth optical communication. First, turn to Figure 1 According to some embodiments, a buried oxide (“BOX”) substrate 102 is connected to a first carrier 160. The first carrier 160 may be, for example, a wafer (e.g., a silicon wafer), a panel, a glass substrate, a ceramic substrate, etc. The BOX substrate 102 may be connected to the first carrier 160 using, for example, an adhesive or a peeling layer (not shown).

[0024] The BOX substrate 102 includes an oxide layer 102B formed on a substrate 102C, and a silicon layer 102A formed on the oxide layer 102B. The substrate 102C may be, for example, a material such as glass, ceramic, dielectric, semiconductor, etc., or a combination thereof. In some embodiments, the substrate 102C may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 102C may be a wafer, such as a silicon wafer (e.g., a 12-inch silicon wafer). Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 102C may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; etc., or a combination thereof. The oxide layer 102B may be, for example, silicon oxide, etc. In some embodiments, the oxide layer 102B may have a thickness between about 0.5 μm and about 4 μm. In some embodiments, the silicon layer 102A may have a thickness between about 0.1 μm and about 1.5 μm. These thicknesses are examples, and other values ​​are possible and contemplated within the scope of the present disclosure. The BOX substrate 102 may be referred to as having a front side or front surface (e.g., Figure 1 ), and the back side or back surface (e.g. Figure 1 The side of the first carrier 160 facing downward is connected to the first carrier 160).

[0025] exist Figure 2 In some embodiments, the silicon layer 102A is patterned to form silicon regions for the waveguide 104 and the photonic components. The silicon layer 102A can be patterned using suitable photolithography and etching techniques. For example, in some embodiments, a hard mask layer (e.g., a nitride layer or other dielectric material, Figure 2102A) can be formed over the silicon layer 102A and patterned. The pattern of the hard mask layer can then be transferred to the silicon layer 102A using one or more etching techniques, such as dry etching and / or wet etching techniques. For example, the silicon layer 102A can be etched to form a recess that defines the waveguide 104, wherein the remaining silicon area forms the waveguide 104, and wherein the sidewalls of the remaining non-recessed portion define the sidewalls of the waveguide 104. In some embodiments, more than one photolithography and etching sequence can be used to pattern the silicon layer 102A. One waveguide 104 or multiple waveguides 104 can be patterned from the silicon layer 102A. If multiple waveguides 104 are formed, the multiple waveguides 104 can be separate independent waveguides 104 or connected as a single continuous structure. In some embodiments, one or more waveguides 104 form a continuous loop. Other configurations or arrangements of the waveguides 104 are possible.

[0026] Still reference Figure 2 According to some embodiments, photonic components such as photodetectors 120, optical modulators 122, and grating connectors 124 are also formed in the silicon layer 102A. The photonic components are optically connected to the waveguide 104 to interact with the optical signal within the waveguide 104, and can physically contact the waveguide 104 or be separated from the waveguide 104. The photonic components can be integrated with the waveguide 104 and can be formed using some or all of the same processing steps used to form the silicon waveguide 104. One or more photodetectors 120 can be optically connected to the waveguide 104 to detect the optical signal within the waveguide 104, and one or more modulators 122 can be optically connected to the waveguide 104 to generate an optical signal within the waveguide 104 by modulating the optical power within the waveguide 104.

[0027] In some embodiments, the photodetector 120 may be formed by, for example, partially etching an area of ​​the waveguide 104 and growing an epitaxial material on the remaining silicon in the etched area. The waveguide 104 may be etched using acceptable photolithography and etching techniques. The epitaxial material may include, for example, a semiconductor material that may be doped or undoped, such as germanium (Ge). In some embodiments, as part of the formation of the photodetector 120, an implantation process may be performed to introduce dopants into the silicon in the etched area. The silicon in the etched area may be doped with a p-type dopant, an n-type dopant, or a combination.

[0028] In some embodiments, the modulator 122 can be formed by, for example, partially etching an area of ​​the waveguide 104 and then implanting appropriate dopants into the remaining silicon in the etched area. The waveguide 104 can be etched using acceptable photolithography and etching techniques. In some embodiments, the etched area for the photodetector 120 and the etched area for the modulator 122 can be formed using the same photolithography or etching steps, one or more steps. The silicon in the etched area can be doped with p-type dopants, n-type dopants, or a combination. In some embodiments, the etched area for the photodetector 120 and the etched area for the modulator 122 can be implanted using the same implantation steps, one or more steps.

[0029] In some embodiments, one or more grating connectors 124 may be integrated with the waveguide 104 and may be formed together with the waveguide 104. In some embodiments, in addition to the grating connector 124, an edge connector 144 (see Fig.11 ), or may include an edge connector 144 (see Fig.11 ) instead of the grating connector 124. The grating connector 124 allows optical signals and / or optical power to be transmitted to the overlying optical fiber 150 (see Fig.10 ) and the waveguide 104 of the optical plug-in 100. The grating connector 124 can be formed by, for example, partially etching a region of the waveguide 104 using acceptable photolithography and etching techniques. In some embodiments, the grating connector 124 is formed using the same photolithography or etching steps as the waveguide 104 and / or other photonic components. In other embodiments, the grating connector 124 is formed after the waveguide 104 and / or other photonic components are formed.

[0030] exist Figure 3In some embodiments, a dielectric layer 108 is formed on the front side of the BOX substrate 102. The dielectric layer 108 may be formed over the waveguide 104, the photonic components, and the oxide layer 102B. The dielectric layer 108 may be formed by one or more layers of silicon oxide, silicon nitride, combinations thereof, and the like, and may be formed by CVD, PVD, atomic layer deposition (ALD), a spin-on dielectric process, or the like, or a combination thereof. In some embodiments, the dielectric layer 108 may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system, and post-curing to convert it into another material such as an oxide), or the like, or a combination thereof. Other dielectric materials formed by any acceptable process may be used. In some embodiments, a planarization process such as a CMP process, a grinding process, or the like is then used to planarize the dielectric layer 108. In some embodiments, dielectric layer 108 may be formed to have a thickness between about 1000 μm and about 2000 μm over oxide layer 102B, or may be formed to have a thickness between about 800 μm and about 1800 μm over waveguide 104. These thicknesses are examples, and other values ​​are possible and contemplated within the scope of the present disclosure.

[0031] Due to the difference in refractive index of the materials of the waveguide 104 and the dielectric layer 108, the waveguide 104 has a high internal reflection such that light is substantially confined within the waveguide 104, depending on the wavelength of the light and the refractive index of the respective materials. In one embodiment, the refractive index of the material of the waveguide 104 is higher than the refractive index of the material of the dielectric layer 108. For example, the waveguide 104 may include silicon, and the dielectric layer 108 may include silicon oxide and / or silicon nitride.

[0032] exist Figure 4 In some embodiments, one or more openings 111 are formed to extend into the substrate 102C. The openings 111 are formed to extend through the dielectric layer 108 and the oxide layer 102B, and partially extend into the substrate 102C. The openings 111 may be formed by acceptable photolithography and etching techniques, such as by forming and patterning a photoresist, and then performing an etching process using the patterned photoresist as an etching mask. The etching process may include, for example, a dry etching process and / or a wet etching process.

[0033] exist Figure 5In some embodiments, a conductive material is formed in the opening 111, thereby forming a through hole 112. In some embodiments, a liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. may be formed in the opening 111 by TaN, Ta, TiN, Ti, CoW, etc., or a combination thereof, and may be formed using a suitable deposition process such as ALD, etc. In some embodiments, a seed layer (not shown) that may include copper or a copper alloy may then be deposited in the opening 111. The conductive material of the through hole 112 is formed in the opening 111 using, for example, ECP or electroless plating. The conductive material may include, for example, a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, an alloy thereof, etc., or a combination thereof. A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material along the top surface of the dielectric layer 108 so that the through hole 112 is flush with the top surface of the dielectric layer 108.

[0034] Figure 5 Also shown is the formation of a contact 113 extending through the dielectric layer 108 and electrically connected to the photodetector 120 and the modulator 122. The contact 113 may be formed before or after the formation of the through hole 112, and the formation of the contact 113 and the formation of the through hole 112 may share some steps, such as the deposition and / or planarization of the conductive material. In some embodiments, the contact may be formed by a metal damascene process, such as a single metal damascene, a dual metal damascene, etc. For example, in some embodiments, an opening (not shown) for the contact 113 is first formed in the dielectric layer 108 using acceptable photolithography and etching techniques. Then a conductive material may be formed in the opening to form the contact 113. Excess conductive material may be removed using a CMP process or the like. The conductive material of the contact 113 may be formed by a metal or a metal alloy, which may include aluminum, copper, tungsten, etc., which may be the same material as the through hole 112. The contact 113 may be formed using other techniques or materials in other embodiments.

[0035] exist Figure 6In some embodiments, a passivation layer 114 and a contact pad 116 are formed over the dielectric layer 108. The contact pad 116 allows electrical connection to be made to the contact 113 and the via 112. The passivation layer 114 may include one or more dielectric materials similar to those described above for the dielectric layer 108, such as silicon oxide or silicon nitride, or may include different materials. The passivation layer 114 may be formed using techniques similar to those described above for the dielectric layer 108, or may be formed using different techniques. The contact pad 116 may be formed using a suitable process such as a metal damascene process, such as a single metal damascene, a dual metal damascene, etc. A planarization process (e.g., a CMP process, etc.) may be implemented after forming the contact pad 116 so that the surfaces of the contact pad 116 and the passivation layer 114 are substantially coplanar. In some embodiments, additional layers including wires and vias (e.g., a redistribution layer, etc.) may be formed between the contact 113 / via 112 and the contact pad 116 to provide additional electrical wiring.

[0036] exist Figure 7 In some embodiments, the structure is peeled off from the first carrier substrate 160, flipped over, and connected to the second carrier substrate 162. The second carrier substrate 162 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. The adhesive layer or the peeling layer ( Figure 7 ) may be formed on a second carrier substrate 162 to facilitate connection of the structures. Figure 8 In some embodiments, the back side of substrate 102C is thinned to expose via 112. Substrate 102C may be thinned by a CMP process, a mechanical grinding process, or the like.

[0037] exist Fig. 9In some embodiments, a conductive pad 130 and a conductive connector 132 are formed. According to some embodiments, the conductive pad 130 is formed on the exposed through hole 112 and on the substrate 102C. The conductive pad 130 may be a conductive pad or a conductive column electrically connected to the through hole 112. The conductive pad 130 may be formed by a conductive material such as copper, another metal or metal alloy, or a combination thereof. The material of the conductive pad 130 may be formed by a suitable process such as plating. For example, in some embodiments, the conductive pad 130 is a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column may be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer (not shown) is formed on top of the conductive pad 130. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, under bump metallization (UBM, not shown) may be formed over conductive pad 130. In some embodiments, a passivation layer (not shown) such as silicon oxide or silicon nitride may be formed over substrate 102C to surround or partially cover conductive pad 130.

[0038] According to some embodiments, the conductive connector 132 can then be formed on the conductive pad 130. In other embodiments, the conductive connector 132 is not formed on the conductive pad 130. The conductive connector 132 can be, for example, a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by electroless nickel electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 132 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 132 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In some embodiments, before connecting to an external component (e.g. Fig.19 Before the interconnect substrate 302 is electrically connected, the conductive connector 132 is not formed on the conductive pad 130.

[0039] Fig.10 and Fig.11 An optical insert 100 is shown according to some embodiments. Fig.10An optical plug-in 100 is shown with an optical fiber 150 connected to the optical plug-in 100 such that the optical fiber 150 is optically connected to a grating connector 124. The grating connector 124 facilitates the transmission of optical signals or optical power between the optical fiber 150 and one or more waveguides 104. The optical fiber 150 may be connected to the optical plug-in through a reflector 140, which may include optical components (e.g., lenses, mirrors, gratings, prisms, etc.) to facilitate the transmission of optical signals or optical power between the optical fiber 150 and the waveguide 104. In some embodiments, an optical glue is used to connect the optical fiber 150 and / or the reflector 140 to the optical plug-in 100. In some embodiments, before connecting the optical fiber 150 and / or the reflector 140, a region of the passivation layer 114 and / or the dielectric layer 108 located above the grating connector 124 may be recessed or removed. The region of the passivation layer 114 and / or the dielectric layer 108 may be recessed or removed using, for example, a suitable photolithography and etching process. Recessing or removing material above the grating connector 124 may allow for a more efficient optical connection between the grating connector 124 and the optical fiber 150 and / or the reflector 140 .

[0040] Fig.11 The optical insert 100 shown is similar to Fig.10 The optical plug-in 100 is shown in the same manner as that shown in FIG. 1 , except that an optical fiber 150 is connected to the optical plug-in 100 such that the optical fiber 150 is optically connected to an edge connector 144. The edge connector 144 facilitates the transmission of optical signals or optical power between the optical fiber 150 and the one or more waveguides 104. In some embodiments, the passivation layer 114 and / or the dielectric layer 108 can be recessed or removed in an area adjacent to the edge connector 144 to form a recess 152 in which the optical fiber 150 is connected. The recess 152 can be, for example, a groove, a recess (e.g., a "v-groove"), etc., which helps to secure and align the optical fiber 150 with the edge connector 144. In some embodiments, an optical adhesive is used to connect the optical fiber 150 to the optical plug-in 100 within the recess 152.

[0041] Figures 12 to 18 An electronic package 200 (see FIG. 1 ) is shown in accordance with some embodiments. Fig.18 ). In some embodiments, electronic package 200 includes conductive wiring that provides a computing system (e.g. Fig.19 The electrical interconnections between components in the computing system 300). Turning first to Fig.12 According to some embodiments, substrate 202 is connected to a second carrier substrate 260. Second carrier substrate 260 may be, for example, a wafer (e.g., a silicon wafer), a panel, a glass substrate, a ceramic substrate, etc. Substrate 202 may be connected to second carrier substrate 260 using, for example, an adhesive or a release layer (not shown).

[0042] The substrate 202 may be, for example, a material such as glass, ceramic, dielectric, semiconductor, etc., or a combination thereof. In some embodiments, the substrate 102C may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 202 may be a wafer, such as a silicon wafer (e.g., a 12-inch silicon wafer). Other substrates, such as a multilayer substrate or a gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 202 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; etc., or a combination thereof. The substrate 202 may be referred to as having a front side or a front surface (e.g., Fig.12 ), and the back side or back surface (e.g. Fig.12 In some embodiments, substrate 202 has no active and / or passive components. In other embodiments, substrate 202 includes active and / or passive components.

[0043] Fig.12 Also shown are one or more openings 205 formed to extend into the substrate 202 according to some embodiments. The openings 205 may extend partially into the substrate 202. The openings 205 may be formed by acceptable photolithography and etching techniques, such as by forming and patterning a photoresist and then performing an etching process using the patterned photoresist as an etching mask. The etching process may include, for example, a dry etching process and / or a wet etching process.

[0044] exist Fig.13 In some embodiments, a conductive material is formed in the opening 205 to form a via 206. In some embodiments, a liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. may be formed in the opening 205 by TaN, Ta, TiN, Ti, CoW, etc., or a combination thereof, and may be formed using a suitable deposition process such as ALD, etc. In some embodiments, a seed layer (not shown) that may include copper or a copper alloy may then be deposited in the opening 205. The conductive material of the via 206 is formed in the opening 205 using, for example, ECP or chemical plating. The conductive material may include, for example, a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, an alloy thereof, etc., or a combination thereof. A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material along the top surface of the substrate 202 so that the via 206 is flush with the top surface of the substrate 202.

[0045] exist Fig.14 , a first interconnect structure 210 is formed over the substrate 202 and over the via 206. In the illustrated embodiment, the first interconnect structure 210 includes dielectric layers 212A-C, metallization patterns 214A-B (sometimes referred to as redistribution layers or redistribution lines), and pads 216. The first interconnect structure 210 is shown as an illustrative example having two layers of metallization patterns (214A and 214B), but the first interconnect structure 210 may have more or fewer dielectric layers and metallization patterns than shown. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

[0046] First, a dielectric layer 212A is deposited on the substrate 202 and the via 206. In some embodiments, the dielectric layer 212A is formed of a polymer material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 212A is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., or the like. The dielectric layer 212A can be formed by any acceptable deposition process such as spin coating, CVD, ALD, lamination, etc., or a combination thereof. Then, the dielectric layer 212A is patterned to expose a portion of the through-via 206. The patterning can be performed using an acceptable process, such as by exposing the dielectric layer 212A to light when the dielectric layer 212A is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 212A is a photosensitive material, the dielectric layer 212A may be developed after exposure.

[0047] Then, metallization pattern 214A can be formed on dielectric layer 212A.Metallization pattern 214A includes a wire portion (also referred to as a wire) located on the main surface of dielectric layer 212A and extending along the main surface of dielectric layer 212A.Metallization pattern 214A also includes a through-hole portion (also referred to as a conductive through-hole) extending through dielectric layer 212A to physically and electrically connect through-hole 206.As an example for forming metallization pattern 214A, a seed layer is formed above dielectric layer 212A.In some embodiments, the seed layer is a metal layer, which can be a single layer, or a composite layer including multiple sub-layers formed by different materials.In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer.The seed layer can be formed using, for example, physical vapor deposition (PVD) and the like.Then, a photoresist is formed and patterned on the seed layer.The photoresist can be formed by spin coating and the like, and can be exposed to light for patterning.The pattern of the photoresist corresponds to metallization pattern 214A. Patterning can form an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms a metallization pattern 214A.

[0048] Then, dielectric layer 212B is deposited on metallization pattern 214A and dielectric layer 212A. Dielectric layer 212B can be formed in a similar manner to dielectric layer 212A and can be formed by a material similar to dielectric layer 212A. Then metallization pattern 214B is formed. Metallization pattern 214B includes a wire portion located on the main surface of dielectric layer 212B and extending along the main surface of dielectric layer 212B. Metallization pattern 214B also includes a through-hole portion extending through dielectric layer 212B to be physically and electrically connected to metallization pattern 214A. Metallization pattern 214B can be formed in a similar manner and with a similar material as metallization pattern 214A.

[0049] In some embodiments, different metallization patterns of the first interconnect structure 210 have different sizes than other metallization patterns of the first interconnect structure 210. For example, the wires and / or vias of the metallization pattern 214B may be wider or thicker than the wires and / or vias of the metallization pattern 214A. In addition, the metallization pattern 214B may be formed with a larger pitch than the metallization pattern 214A. The metallization pattern 214B is the topmost metallization pattern of the first interconnect structure 210. In this way, all intermediate metallization patterns of the first interconnect structure 210 (e.g., the metallization pattern 214A) are disposed between the metallization pattern 214B and the substrate 202.

[0050] The dielectric layer 212C is deposited on the metallization pattern 214B and the dielectric layer 212B. The dielectric layer 212C can be formed in a manner similar to the dielectric layer 212A or 212B, and can be formed of the same material as the dielectric layer 212A or 212B. The dielectric layer 212C is the topmost dielectric layer of the first interconnect structure 210. In this way, all metallization patterns (e.g., metallization patterns 214A-B) of the first interconnect structure 210 are disposed between the dielectric layer 212C and the substrate 202. In addition, all intermediate dielectric layers (e.g., dielectric layers 212A-B) of the first interconnect structure 210 are disposed between the dielectric layer 212C and the substrate 202.

[0051] It should be understood that the first interconnect structure 210 may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, steps and processes similar to those discussed above may be repeated. The metallization pattern may include wires and conductive vias. Conductive vias may be formed by forming a seed layer and conductive materials of the metallization pattern in the openings of the underlying dielectric layer during the formation of the metallization pattern. Thus, the conductive vias may interconnect and electrically connect various wires. In other embodiments, the metallization pattern of the first interconnect structure 210 may be formed using a process different from that described above, such as by using a metal damascene process such as dual metal damascene, single metal damascene, etc.

[0052] Still reference Fig.14 According to some embodiments, a pad 216 is formed for external electrical connection to the first interconnect structure 210. In an example of forming the pad 216, the topmost dielectric layer 212C is first patterned to form an opening that exposes a portion of the topmost metallization pattern 214B. The patterning can be performed using an acceptable process, such as by exposing the dielectric layer 212C to light when the dielectric layer 212C is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 212C is a photosensitive material, the dielectric layer 212C can be developed after exposure.

[0053] The pad 216 may be formed by a conductive material such as the same material as the metallization pattern 214A-B, and may be formed using a process similar to the metallization pattern 214A-B (e.g., plating). The pad 216 may have a through-hole portion extending through the topmost dielectric layer 212C to physically and electrically connect the topmost metallization pattern 214B. In some embodiments, the pad 216 has a portion located on the main surface of the dielectric layer 212C and extending along the main surface of the dielectric layer 212C. In some embodiments, the pad 216 has a size (e.g., width, thickness, etc.) different from the metallization pattern 214A-B. A planarization process (e.g., CMP process, etc.) may be implemented after forming the pad 216 so that the surface of the pad 216 and the topmost dielectric layer 212C are substantially coplanar. In some embodiments, the pad 216 may include a micro-bump, a conductive pad, an under-bump metallization structure (UBM), a solder connector, and / or the like.

[0054] exist Fig.15 In the embodiment, the structure is peeled off from the second carrier substrate 260, turned over, and connected to the third carrier substrate 262. The third carrier substrate 262 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (eg, a silicon wafer), etc. The adhesive layer or the peeling layer ( Fig.15 A third carrier substrate 262 (not shown) may be formed on the third carrier substrate 262 to facilitate connection of the structures.

[0055] exist Fig.16 In some embodiments, the back side of substrate 202 is thinned to expose through-hole 206 and form an optional second interconnect structure 220. Substrate 202 can be thinned by a CMP process, a mechanical grinding process, etc. In the embodiment shown, second interconnect structure 220 includes dielectric layers 222A-B and metallization pattern 224. Second interconnect structure 220 can have more or fewer dielectric layers and metallization patterns than shown. Second interconnect structure 220 is optional. In some embodiments, a dielectric layer without a metallization pattern is formed instead of second interconnect structure 220.

[0056] In some embodiments, dielectric layer 222A is first deposited on the back side of substrate 202 and on through hole 206. Dielectric layer 222A can be formed by materials similar to any dielectric layer 212A-C of first interconnect structure 210, and can be formed in a manner similar to dielectric layer 212A-C. Then metallization pattern 224 is formed. Metallization pattern 224 includes a wire portion located on the main surface of dielectric layer 222A and extending along the main surface of dielectric layer 222A. Metallization pattern 224 also includes a through hole portion extending through dielectric layer 222A to physically and electrically connect through hole 206. Metallization pattern 224 can be formed in a manner similar to any metallization pattern 214A-B and with similar materials. Then dielectric layer 222B is deposited on metallization pattern 224 and dielectric layer 222A. Dielectric layer 240 can be formed in a manner similar to dielectric layer 222A, and can be formed by the same material as dielectric layer 222A.

[0057] exist Fig.17 In some embodiments, UBM 225 and conductive connector 226 are formed to make electrical connections to second interconnect structure 220. Fig.18 In the embodiment, the structure is peeled off from the third carrier substrate 262 to form the electronic package 200. The UBM 225 may have a bump portion located on the main surface of the dielectric layer 222B and extending along the main surface of the dielectric layer 222B, and may have a through hole portion extending through the dielectric layer 222B to physically and electrically connect the metallization pattern 224. The UBM 225 may be formed of the same material as the metallization pattern 224. In some embodiments, the UBM 225 has a different size from the metallization pattern 224.

[0058] Conductive connector 226 may be formed on UBM 225. Conductive connector 226 may be similar to the previously described Fig. 9Conductive connector 132 described. For example, conductive connector 226 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by chemical nickel plating chemical palladium immersion gold technology (ENEPIG), etc. Conductive connector 226 can include conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, conductive connector 226 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the structure, reflow can be implemented to shape the material into the desired bump shape. In another embodiment, conductive connector 226 includes a metal column (e.g., a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal cover layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, in conjunction with external components (e.g. Fig.19 Before making electrical connections to the interconnect substrate 302 shown in FIG. 1 , the conductive connector 226 is not formed on the UBM 225 .

[0059] Fig.19 A computing system 300 according to some embodiments is shown. The computing system 300 includes one or more optical plug-ins 100 and one or more electronic plug-ins 200 connected to an interconnect substrate 302 (also referred to as a "packaging substrate"), and one or more semiconductor devices 310 connected to the one or more optical plug-ins 100 and / or the one or more electronic plug-ins 200. For example, Fig.19 The semiconductor device 310A shown is electrically connected to the optical package 100A and the electronic package 200, while the semiconductor device 310B is electrically connected to the optical package 100B and the electronic package 200. By using the optical package 100 described herein, high bandwidth communications using optical interconnects can be enabled within the computing system 300, and the size and / or power consumption of the computing system 300 can be reduced. The optical package 100 can communicate with components of an optical network or external optical connection using one or more optical fibers 150. The use of the electronic package 200 described herein allows electrical communication between the semiconductor devices 310 of the computing system 300. The computing system 300 may include more than Fig.19 More or fewer components than shown. Optical plug-in 100 and electronic plug-in 200 can be arranged in any suitable configuration within computing system 300, thereby allowing for flexible design and formation of optically connected computing systems of larger sizes. In some embodiments, computing system 300 includes an optional heat sink 330 that can facilitate heat dissipation. These and other configurations are considered to be within the scope of the present invention.

[0060] Fig.19 The computing system 300 shown includes two semiconductor devices 310A-B, although in other embodiments, the computing system 300 may include more or fewer devices and / or devices of different types than these devices. The semiconductor device 310 of the computing system 300 may include similar devices, different devices, or a combination thereof. The semiconductor device 310 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a high-performance computing (HPC) die, a field programmable gate array (FPGA), a machine learning (ML) device such as an ML accelerator (sometimes referred to as an artificial intelligence (AI) accelerator), or a combination thereof. The semiconductor device 310 may include a memory device, such as, for example, a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), another type of memory, etc. In some embodiments, processing and memory functions may be integrated within the same semiconductor device 310. The semiconductor device 310 may include a system-on-chip (SoC) device, a system-on-integrated circuit (SoIC) device, a "chiplet", etc., or a combination thereof.

[0061] In some embodiments, one or more semiconductor devices 310 of computing system 300 may include multiple semiconductor dies bonded together. Fig.19 The semiconductor device 310A shown includes a semiconductor die 312 bonded to a semiconductor die 314 via a conductive connector (e.g., solder bumps, etc.). As another example, the semiconductor device 310B includes a semiconductor die 322 bonded to a semiconductor die 324 via a dielectric-dielectric bond and / or a metal-metal bond (e.g., direct bond, fusion bond, oxide-oxide bond, hybrid bond, etc.). The semiconductor device 310 may include one, two, or more than two semiconductor dies.

[0062] In some embodiments, the semiconductor device 310 includes circuits (e.g., integrated circuits and related components) configured to interface with one or more photonic components (e.g., photodetectors 120 or optical modulators 122) of the optical plug-in 100. These circuits may be referred to herein as "interface circuits". For example, the semiconductor device 310A includes an interface circuit 316 configured to interface with the optical plug-in 100A, and the semiconductor device 310B includes an interface circuit 326 configured to interface with the optical plug-in 100B. The interface circuits of the semiconductor device 310 may be positioned relatively close to the corresponding optical plug-in 100, for example, directly above the optical plug-in 100. The interface circuits of the semiconductor device 310 may include, for example, a controller, a driver, a transimpedance amplifier, etc., or a combination thereof. The interface circuit may include circuits for processing electrical signals received from the photonic components, such as circuits for processing electrical signals received from the photodetector 120, and may provide serializer / deserializer (SerDes) functions. The interface circuit may include circuits for controlling high-frequency signals of the photonic components, such as circuits for controlling modulation of the optical modulator 122. In some embodiments, the interface circuit may be incorporated into a separate device such as an electronic integrated circuit (EIC) chip that is bonded to the semiconductor device 310 .

[0063] The interconnection substrate 302 may be, for example, a glass substrate, a ceramic substrate, a dielectric substrate, an organic substrate (e.g., an organic core), a semiconductor substrate (e.g., a semiconductor wafer), etc., or a combination thereof. In some embodiments, the interconnection substrate 302 includes a conductive pad 304 and conductive wiring (e.g., a wire, a via, a redistribution structure, etc.). The interconnection substrate 302 may not have active or passive devices. In other embodiments, the interconnection substrate 302 may include passive or active devices. In some embodiments, the interconnection substrate 302 may be another type of structure, such as an integrated fan-out structure, a redistribution structure, etc.

[0064] The conductive connectors 132 of the optical package 100 and the conductive connectors 226 of the electronic package 200 may be electrically connected to the conductive pads 304 of the interconnect substrate 302. Then, one or more semiconductor devices 310 may be electrically connected to the contact pads 116 of the optical package 100 and / or the pads 216 of the electronic package 200 through conductive connectors (e.g., solder bumps, etc.). In some embodiments, the one or more semiconductor devices 310 may also be directly connected to the conductive pads 304 of the interconnect substrate 302. In some embodiments, an underfill material or the like (not shown in the figure) may be formed around, between, or below the optical package 100, the electronic package 200, and / or the semiconductor devices 310.

[0065] In some embodiments, the optical plug-in 100 of the computing system 300 receives an external optical signal from the optical fiber 150 detected using the photodetector 120 of the optical plug-in 100. The corresponding electrical signal can then be transmitted from the photodetector 120 to the semiconductor device 310 connected to the optical plug-in. The semiconductor device 310 can then process the electrical signal or provide other appropriate computing functions. In some embodiments, the semiconductor device 310 generates an electrical signal that can be transmitted to the modulator 122 of the optical plug-in 100. The modulator 122 generates a corresponding optical signal that can be transmitted externally through the optical fiber 150. Using the optical plug-in in this manner, the size, power consumption, cost, or latency of the computing system 300 can be reduced while providing high-speed optical communication with external optical components.

[0066] Fig. 20 FIG. 3 is a plan view of a computing system 300 according to some embodiments. Fig.19 100A and 100B are similar, except that both optical packages 100A and 100B are connected to a plurality of optical fibers 150. In addition, optical package 100A has optical fibers 150 arranged in a different direction than optical package 100B, as an example of how optical fibers 150 and optical package 100 can have different configurations within computing system 300. The relative size, shape, or number of optical package 100, electronic package 200, or semiconductor device 310 may be different than the relative size, shape, or number of optical package 100, electronic package 200, or semiconductor device 310. Fig. 20 The components of computing system 300 may also have Fig. 20 Different arrangements are shown.

[0067] Fig. 20 The optical inserts 100 shown each include an optical fiber 150 mounted within one or more recesses 152, similar to Fig.11 In other embodiments, one or more optical plug-ins 100 may have a configuration such as Fig.10 1 and 12. In some embodiments, the optical plug-in 100 may include an optical component 142 (e.g., a lens, a reflector, a grating, a prism, etc.) to facilitate the transmission of optical signals or optical power between the waveguide 104 and the photonic components (e.g., the photodetector 120, the modulator 122). Fig. 20 As shown, the use of the optical insert 100 described herein allows for flexible design of the computing system 300. For example, the design of the computing system 300 can be optimized for a particular application.

[0068] Figure 21A-21B4 shows a cross-sectional view and a plan view of a computing system 400 according to some embodiments. The computing system 400 includes an optical plug-in 450 connected to an interconnect substrate 302, and one or more semiconductor devices 310 connected to the optical plug-in 450. The optical plug-in 450 can be similar to the previously described optical plug-in 100, except that the optical plug-in 450 also includes an interconnect structure 410, which includes wires 404 and other conductive features (e.g., conductive pads, vias, etc.). In some embodiments, the optical plug-in 450 is formed in a similar manner to the optical plug-in 100, except that the interconnect structure 410 is formed on the substrate 302. Figure 5 is shown above dielectric layer 108. Interconnect structure 410 may be fabricated using a method similar to that described for Fig.14 The interconnect structure 410 provides electrical interconnection between the semiconductor device 310 and other components of the optical package 450.

[0069] The optical plug-in 450 includes one or more waveguides 104 that allow optical communication between two or more semiconductor devices 310 within the computing system 400. The semiconductor devices 310 can each be connected to a photonic component that facilitates communication using optical signals within the waveguide 104. For example, Fig.21A The semiconductor device 310A is shown connected to the photonic component 120A / 122A, and the semiconductor device 310B is connected to the photonic component 120B / 122B. In some embodiments, the optical plug-in 450 may use one or more optical fibers 150 ( Figure 21A-21B 4. In some embodiments, the optical plug-in 450 may include an optical power source such as a laser diode.

[0070] The optical plug-in 450 described herein allows high bandwidth communications using optical interconnects within the computing system 400, which can reduce the size and / or power consumption of the computing system 400. In addition, the interconnect structure 410 of the optical plug-in 450 allows electrical communication between the semiconductor device 310 or other components. The computing system 400 may include more than Figure 21A-21B More or fewer components than shown. In some embodiments, computing system 400 includes an optional heat sink that can facilitate heat dissipation. These and other configurations are considered to be within the scope of the present invention.

[0071] Figure 22A-22B5 shows a cross-sectional view and a plan view of a computing system 500 according to some embodiments. The computing system 500 includes an optical plug-in 550 embedded in an interconnect substrate 502, and one or more semiconductor devices 310 connected to the optical plug-in 550 and / or the interconnect substrate 502. The optical plug-in 550 can be similar to the optical plug-in 450 described previously. For example, the optical plug-in 550 includes a waveguide 104, a photonic component (e.g., 120 / 122), and an interconnect structure 510 including a conductor 504 and other conductive features (e.g., conductive pads, vias, etc.). In some embodiments, the optical plug-in 550 is formed in a similar manner to the optical plug-in 450. The interconnect structure 510 can be formed using a method similar to that described for the optical plug-in 450. Fig.14 The interconnect structure 510 provides electrical interconnection from the semiconductor device 310 to the photonic components within the optical insert 550 , and may also provide electrical interconnection between the semiconductor devices 310 .

[0072] The interconnect substrate 502 can be similar to the interconnect substrate 302 described previously, except that a recess or cavity is formed in the interconnect substrate 502, and the optical plug 550 is placed therein. The recess can be formed by a suitable etching process. In some embodiments, the optical plug 550 is connected to the recess of the interconnect substrate 502 by an adhesive. Relative to the top surface of the interconnect substrate 502, the optical plug 550 can have a top surface below, approximately flush with, or above.

[0073] The optical plug-in 550 includes one or more waveguides 104 that allow optical communication between two or more semiconductor devices 310 within the computing system 500. The semiconductor devices 310 can each be connected to a photonic component that facilitates communication using optical signals within the waveguide 104. For example, Fig.22A Semiconductor device 310A is shown coupled to photonic assembly 120A / 122A, and semiconductor device 310B is shown coupled to photonic assembly 120B / 122B. In some embodiments, optical plug 550 may include an optical power source such as a laser diode.

[0074] The optical plug-in 550 described herein allows high bandwidth communications using optical interconnects within the computing system 500, which can reduce the size and / or power consumption of the computing system 500. In addition, the interconnect structure 510 of the optical plug-in 550 allows electrical communication between semiconductor devices 310 or other components. The computing system 500 may include more than Figure 22A-22B More or fewer components than shown. In some embodiments, computing system 500 includes an optional heat sink that can facilitate heat dissipation. These and other configurations are considered to be within the scope of the present invention.

[0075] Figure 23A-23B A cross-sectional view and a plan view of a computing system 600 according to some embodiments are shown. The computing system 600 includes an optical plug-in 650 connected to an interconnect substrate 302, one or more semiconductor devices 310 connected to the optical plug-in 650, and one or more optical switching devices 620 connected to the optical plug-in 650. The optical plug-in 650 can be similar to the optical plug-in 450 described previously, except that the optical plug-in 650 includes a photonic switching network 604 electrically connected to the optical switching device 620. The optical switching device 620 controls the transmission of optical signals within the optical plug-in 650 using the photonic switching network 604, as described in more detail below.

[0076] The optical plug-in 650 includes one or more waveguides 104 that allow optical communication between two or more semiconductor devices 310 within the computing system 600. The semiconductor devices 310 can each be connected to a photonic component that facilitates communication using optical signals within the waveguide 104. For example, Fig.23A A semiconductor device 310A is shown connected to the photonic component 120A / 122A, and a semiconductor device 310B is shown connected to the photonic component 120B / 122B. The waveguide 104 associated with each semiconductor device 310 may be connected to the photonic switching network 604. Fig. 23B A single optical switching device 620 is shown connected to the waveguides 104 associated with four semiconductor devices 310A-D, but other numbers of optical switching devices 620 or semiconductor devices 310 may be connected to the optical plug-in 650 in any suitable arrangement or configuration. The photonic switching network 604 or waveguides 104 may also be arranged in any suitable arrangement or configuration within the optical plug-in 650. In some embodiments, the optical plug-in 650 is formed in a manner similar to the optical plug-in 450. In some embodiments, the optical plug-in 650 may include an optical power source such as a laser diode.

[0077] In some embodiments, the optical switching device 620 controls the transmission of optical signals within the optical plug-in 650 using the photon switching network 604. For example, the photon switching network 604 may include a waveguide and a photon component (e.g., an optical modulator, etc.) connected to the waveguide 104 and controllable to control the optical signal within the waveguide 104. For example, the photon switching network 604 may be controlled to copy, redirect, change, amplify, terminate, generate, or implement other functions on the optical signal within the waveguide 104. In this way, the optical switching device 620 can control the data flow between the semiconductor device 310 or other components within the computing system 600. The optical switching device 620 can also detect and / or process the optical signal within the waveguide 104, and can control the optical switching based on these optical signals. In some embodiments, the semiconductor device 310 of the computing system 600 can be configured in a hierarchy in which the optical switching device 620 controls the data I / O of the computing system 600.

[0078] The optical interposer 650 described herein allows high bandwidth and / or long distance communication between semiconductor devices 310 or other components using optical interconnects within the computing system 600, which can reduce the size, latency, or power consumption of the computing system 600. In addition, the optical interposer 650 allows electrical communication between semiconductor devices 310 or other components. The computing system 600 may include more than Figure 23A-23B More or fewer components than shown. In some embodiments, computing system 600 includes an optional heat sink that can facilitate heat dissipation. These and other configurations are considered to be within the scope of the present invention.

[0079] Fig.24 302, and one or more semiconductor devices 310 connected to the optical plug 750. The optical plug 750 may be similar to Fig.10 or Fig.11 The optical plug-in 100 shown in FIG. 750 is configured to facilitate optical communication from the optical fiber 150 to the semiconductor device 310, or from the semiconductor device 310 to the optical fiber 150. The optical plug-in 750 can use one or more optical fibers 150 to communicate with components of an optical network or external optical connection. The optical plug-in 750 allows optical communication between the semiconductor device 310 of the computing unit 700 and external components. For example, two independent computing units 700 can use the optical fiber 150 to communicate using optical signals. The computing unit 700 can include more than one optical fiber 150. Fig.24 More or fewer components than shown.

[0080] Fig.25FIG. 8 is a schematic diagram of a computing network 800 including a plurality of computing units 700 according to some embodiments. Fig.25 As shown, each independent computing unit 700 can be optically connected to one or more other computing units 700 via optical fiber 150. The use of optical plug-in 750 within computing unit 700 allows high bandwidth optical communication between computing units 700. Some or all of computing units 700 can be similar, or some computing units 700 can be different in function or structure from other computing units 700. Computing network 800 can have Fig.25 Different numbers or different configurations of computing units 700 are shown. As described herein, using multiple computing units 700 to form an optically connected computing network 800 can allow for lower power consumption, lower latency, or higher frequency operation of the computing network. The use of multiple independent computing units 700 can also allow for improved flexibility in the size or connectivity of the computing network.

[0081] The use of optical plug-ins as described herein can achieve benefits. The optical plug-in facilitates high-speed optical communication between components of a computing system and external optical connections using optical fibers. The optical plug-in also allows high-speed optical communication between components within the same computing system. The use of optical plug-ins as described herein can reduce the size, power consumption, cost, or latency of a computing system while providing internal and / or external high-speed optical communication capabilities. In addition to optical plug-ins, electronic plug-ins can also be used to provide electrical communication between components within a computing system. The use of optical plug-ins and electronic plug-ins allows for increased design flexibility and reduced costs.

[0082] According to an embodiment of the present invention, a package includes: a first optical plug-in connected to a package substrate, wherein the first optical plug-in includes: a first waveguide located on the first substrate; and at least one photonic device located on the first substrate, wherein the at least one photonic device is optically connected to the first waveguide; a second optical plug-in connected to the package substrate, wherein the second optical plug-in includes: a second waveguide located on the second substrate; and at least one photonic device located on the second substrate, wherein the at least one photonic device is optically connected to the second waveguide; an electronic plug-in connected to the package substrate, wherein the electronic plug-in includes an interconnection structure located on a third substrate; a first semiconductor device connected to the first optical plug-in and to the electronic plug-in, wherein the first semiconductor device is electrically connected to at least one photonic device of the first optical plug-in and to the interconnection structure of the electronic plug-in; and a second semiconductor device connected to the second optical plug-in and to the electronic plug-in, wherein the second semiconductor device is electrically connected to at least one photonic device of the second optical plug-in and to the interconnection structure of the electronic plug-in. In one embodiment, the package includes: a first optical fiber connected to the first optical plug-in, wherein the first optical fiber is optically connected to the first waveguide. In one embodiment, the first optical plug-in includes a grating connector located on the first substrate, wherein the first optical fiber is optically connected to the first waveguide through the grating connector. In one embodiment, the electronic plug-in is laterally arranged on the package substrate between the first optical plug-in and the second optical plug-in. In one embodiment, the first semiconductor device includes a first semiconductor die, and the first semiconductor die is bonded to the second semiconductor die. In one embodiment, the package includes: a heat sink covering the first semiconductor device and the second semiconductor device. In one embodiment, at least one photonic device located on the first substrate includes a photodetector or an optical modulator. In one embodiment, the first semiconductor device includes an interface circuit associated with at least one photonic device of the first optical plug-in, and wherein the interface circuit is arranged directly above the at least one photonic device. In one embodiment, the first semiconductor device is connected to the first optical plug-in through a first set of solder bumps and is connected to the electronic plug-in through a second set of solder bumps.

[0083] According to an embodiment of the present invention, a structure includes: an optical plug-in connected to a package substrate, wherein the optical plug-in includes: a silicon waveguide; a first photonic component optically connected to the silicon waveguide; a second photonic component optically connected to the silicon waveguide; and an interconnection structure extending above the silicon waveguide, above the first photonic component, and above the second photonic component, wherein the interconnection structure is electrically connected to the first photonic component and to the second photonic component; a first semiconductor device connected to the interconnection structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnection structure; and a second semiconductor device connected to the interconnection structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnection structure. In one embodiment, the interconnection structure includes at least one wire electrically connected to the first semiconductor device and to the second semiconductor device. In one embodiment, the optical plug-in includes a through-hole electrically connected to the interconnection structure and to the package substrate. In one embodiment, the package substrate includes a recess, and wherein the optical plug-in is disposed in the recess. In one embodiment, the structure includes: an optical modulator disposed in the silicon waveguide between the first photonic component and the second photonic component; and the structure includes: a third semiconductor device connected to the interconnection structure, wherein the third semiconductor device is electrically connected to the optical modulator. In one embodiment, the first semiconductor device comprises a machine learning (ML) accelerator die. In one embodiment, the first photonic component comprises a photodetector or an optical modulator.

[0084] According to an embodiment of the present invention, a method of forming a first optical plug-in includes: patterning a silicon layer disposed on a first substrate to form a waveguide; forming a photodetector and an optical modulator adjacent to the waveguide; forming a dielectric layer located above the waveguide, the photodetector, and the optical modulator; and forming a conductive contact extending through the dielectric layer to contact the photodetector and the optical modulator; forming an electronic plug-in, including: forming a through-hole extending through a second substrate; and forming a redistribution structure located on the through-hole and on the second substrate; connecting the first optical plug-in and the electronic plug-in to an interconnect substrate; and connecting a first semiconductor device to the first optical plug-in and to the electronic plug-in, wherein the first semiconductor device is electrically connected to the first optical plug-in and to the electronic plug-in. In one embodiment, the method includes: connecting an optical fiber to the first optical plug-in, wherein the optical fiber is optically connected to the waveguide. In one embodiment, the method includes: connecting a second optical plug-in to the interconnect substrate, and further includes: connecting a second semiconductor device to the second optical plug-in and to the electronic plug-in, wherein the second semiconductor device is electrically connected to the second optical plug-in and to the electronic plug-in. In one embodiment, the method includes: connecting a heat sink to the interconnect substrate, the heat sink extending above the first semiconductor device.

[0085] According to one embodiment of the present application, a package is provided, comprising: a first optical plug-in connected to a package substrate, wherein the first optical plug-in comprises: a first waveguide located on the first substrate; and at least one photonic device located on the first substrate, wherein the at least one photonic device is optically connected to the first waveguide; a second optical plug-in connected to the package substrate, wherein the second optical plug-in comprises: a second waveguide located on the second substrate; and at least one photonic device located on the second substrate, wherein the at least one photonic device is optically connected to the second waveguide; an electronic plug-in connected to the package substrate, wherein the electronic plug-in comprises an interconnection structure located on a third substrate; a first semiconductor device connected to the first optical plug-in and to the electronic plug-in, wherein the first semiconductor device is electrically connected to at least one photonic device of the first optical plug-in and to the interconnection structure of the electronic plug-in; and a second semiconductor device connected to the second optical plug-in and to the electronic plug-in, wherein the second semiconductor device is electrically connected to at least one photonic device of the second optical plug-in and to the interconnection structure of the electronic plug-in. In some embodiments, the package further comprises: a first optical fiber connected to the first optical plug-in, wherein the first optical fiber is optically connected to the first waveguide. In some embodiments, the first optical plug-in further comprises a grating connector on the first substrate, wherein the first optical fiber is optically connected to the first waveguide via the grating connector. In some embodiments, the electronic plug-in is laterally disposed on the package substrate between the first optical plug-in and the second optical plug-in. In some embodiments, the first semiconductor device comprises a first semiconductor die bonded to the second semiconductor die. In some embodiments, the package further comprises: a heat sink covering the first semiconductor device and the second semiconductor device. In some embodiments, wherein at least one photonic device on the first substrate comprises a photodetector or an optical modulator. In some embodiments, the first semiconductor device comprises an interface circuit associated with at least one photonic device of the first optical plug-in, and wherein the interface circuit is disposed directly above the at least one photonic device. In some embodiments, the first semiconductor device is connected to the first optical plug-in via a first set of solder bumps, and is connected to the electronic plug-in via a second set of solder bumps.

[0086] According to another embodiment of the present application, a packaging structure is provided, comprising: an optical plug-in connected to a package substrate, wherein the optical plug-in comprises: a silicon waveguide; a first photonic component optically connected to the silicon waveguide; a second photonic component optically connected to the silicon waveguide; and an interconnection structure extending above the silicon waveguide, above the first photonic component, and above the second photonic component, wherein the interconnection structure is electrically connected to the first photonic component and to the second photonic component; a first semiconductor device connected to the interconnection structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnection structure; and a second semiconductor device connected to the interconnection structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnection structure. In some embodiments, the interconnection structure comprises at least one wire electrically connected to the first semiconductor device and to the second semiconductor device. In some embodiments, the optical plug-in further comprises a through-hole electrically connected to the interconnection structure and to the package substrate. In some embodiments, the package substrate comprises a recess, and wherein the optical plug-in is disposed in the recess. In some embodiments, the packaging structure further comprises: an optical modulator disposed in the silicon waveguide between the first photonic component and the second photonic component; and further comprises: a third semiconductor device connected to the interconnection structure, wherein the third semiconductor device is electrically connected to the optical modulator. In some embodiments, the first semiconductor device comprises a machine learning (ML) accelerator die. In some embodiments, the first photonic component comprises a photodetector or an optical modulator.

[0087] According to another embodiment of the present application, a method for forming a package is provided, comprising: forming a first optical plug-in, comprising: patterning a silicon layer disposed on a first substrate to form a waveguide, forming a photodetector and an optical modulator adjacent to the waveguide; forming a dielectric layer located above the waveguide, the photodetector, and the optical modulator; and forming a conductive contact extending through the dielectric layer to contact the photodetector and the optical modulator; forming an electronic plug-in, comprising: forming a through-hole extending through a second substrate; and forming a redistribution structure located on the through-hole and on the second substrate; connecting the first optical plug-in and the electronic plug-in to an interconnect substrate; and connecting a first semiconductor device to the first optical plug-in and to the electronic plug-in, wherein the first semiconductor device is electrically connected to the first optical plug-in and to the electronic plug-in. In some embodiments, the method for forming a package further comprises: connecting an optical fiber to the first optical plug-in, wherein the optical fiber is optically connected to the waveguide. In some embodiments, the method for forming a package further comprises: connecting a second optical plug-in to the interconnect substrate, and further comprises: connecting a second semiconductor device to the second optical plug-in and to the electronic plug-in, wherein the second semiconductor device is electrically connected to the second optical plug-in and to the electronic plug-in. In some embodiments, the method of forming a package further includes connecting a heat sink to the interconnect substrate, the heat sink extending above the first semiconductor device.

[0088] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A package comprising: A first optical plug-in connected to the package substrate, wherein the first optical plug-in comprises: a first waveguide disposed on the first substrate; and at least one photonic device disposed on the first substrate, wherein the at least one photonic device is optically connected to the first waveguide; a first dielectric layer extending over the first waveguide and the at least one photonic device; A second optical plug-in is connected to the package substrate, wherein the second optical plug-in comprises: a second waveguide disposed on the second substrate; and at least one photonic device disposed on the second substrate, wherein the at least one photonic device is optically connected to the second waveguide; a second dielectric layer extending over the second waveguide and the at least one photonic device; an electronic package connected to the package substrate, wherein the electronic package includes an interconnect structure located on a third substrate; a first semiconductor device connected to the first optical package and to the electronic package, wherein the first semiconductor device is electrically connected to the at least one photonic device of the first optical package and to the interconnect structure of the electronic package; and A second semiconductor device is connected to the second optical package and to the electronic package, wherein the second semiconductor device is electrically connected to the at least one photonic device of the second optical package and to the interconnect structure of the electronic package.

2. The package according to claim 1, further comprising: A first optical fiber is connected to the first optical plug, wherein the first optical fiber is optically connected to the first waveguide.

3. The package according to claim 2, wherein: The first optical plug-in further includes a grating connector on the first substrate, wherein the first optical fiber is optically connected to the first waveguide through the grating connector.

4. The package according to claim 1, wherein: The electronics package is disposed laterally on the package substrate between the first optical package and the second optical package.

5. The package according to claim 1, wherein: The first semiconductor device includes a first semiconductor die bonded to a second semiconductor die.

6. The package according to claim 1, further comprising: A heat sink covers the first semiconductor device and the second semiconductor device.

7. The package according to claim 1, wherein: The at least one photonic device located on the first substrate includes a photodetector or an optical modulator.

8. The package according to claim 1, wherein: The first semiconductor device includes an interface circuit associated with the at least one photonic device of the first optical package, and wherein the interface circuit is disposed directly above the at least one photonic device.

9. The package according to claim 1, wherein: The first semiconductor device is connected to the first optical package via a first set of solder bumps and to the electronic package via a second set of solder bumps.

10. A packaging structure, comprising: An optical plug-in unit connected to the package substrate, wherein the optical plug-in unit comprises: Silicon waveguide; a first photonic component optically connected to the silicon waveguide; a second photonic component optically coupled to the silicon waveguide; and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component; a dielectric layer extending over the silicon waveguide, the first photonic component, and the second photonic component; a first semiconductor device connected to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure; and A second semiconductor device is connected to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

11. The structure according to claim 10, wherein: The interconnect structure includes at least one conductive line electrically connected to the first semiconductor device and to the second semiconductor device.

12. The structure according to claim 10, wherein: The optical interposer also includes through vias electrically connected to the interconnect structure and to the package substrate.

13. The structure according to claim 10, wherein: The package substrate includes a recess, and wherein the optical insert is disposed within the recess.

14. The structure according to claim 10, further comprising: An optical modulator is disposed in the silicon waveguide between the first photonic component and the second photonic component; and further includes: a third semiconductor device connected to the interconnect structure, wherein the third semiconductor device is electrically connected to the optical modulator.

15. The structure according to claim 10, wherein: The first semiconductor device includes a machine learning (ML) accelerator die.

16. The structure of claim 10, wherein: The first photonic component includes a photodetector or an optical modulator.

17. A method of forming a package, comprising: A first optical insert is formed, comprising: patterning a silicon layer disposed on a first substrate to form a waveguide; forming a photodetector and an optical modulator adjacent to the waveguide; forming a dielectric layer over the waveguide, the photodetector, and the optical modulator; and forming conductive contacts extending through the dielectric layer to contact the photodetector and the optical modulator; Form an electronic plug-in, including: forming a through via extending through the second substrate; and forming a redistribution structure on the through via and on the second substrate; connecting the first optical package and the electronic package to an interconnect substrate; and A first semiconductor device is connected to the first optical package and to the electronic package, wherein the first semiconductor device is electrically connected to the first optical package and to the electronic package.

18. The method according to claim 17, further comprising: An optical fiber is connected to the first optical insert, wherein the optical fiber is optically connected to the waveguide.

19. The method according to claim 17, further comprising: Connecting a second optical package to the interconnect substrate and further comprising: connecting a second semiconductor device to the second optical package and to the electronic package, wherein the second semiconductor device is electrically connected to the second optical package and to the electronic package.

20. The method of claim 17, further comprising: A heat sink is connected to the interconnect substrate, the heat sink extending over the first semiconductor device.

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