Semiconductor devices

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a III-V semiconductor layer containing n-type impurities; a first conductive layer, which is arranged on the III-V semiconductor layer, contains Ti (titanium) and a first element that can become a p-type impurity of the III-V semiconductor layer, and has a first region and a second region in which the concentration of the first element is higher than that of the first region; and a second conductive layer arranged on the first conductive layer.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-43857 (filing date: March 13, 2020), and the present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] The embodiments mainly relate to semiconductor devices. Background Art

[0004] In the semiconductor layer of a semiconductor device, an electrode for collecting current is sometimes formed. The contact between the semiconductor layer and the electrode is preferably ohmic. Summary of the invention

[0005] Embodiments of the present invention provide a semiconductor device having an electrode with low contact resistance.

[0006] A semiconductor device according to an embodiment includes a III-V semiconductor layer containing an n-type impurity, a first conductive layer provided on the III-V semiconductor layer, and a second conductive layer provided on the first conductive layer. The first conductive layer contains Ti (titanium) and a first element that can become a p-type impurity of the III-V semiconductor layer, and has a first region and a second region in which the concentration of the first element is higher than that of the first region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment.

[0008] Figure 2 Schematic cross-sectional views showing the manufacturing process of a semiconductor device of a comparative embodiment.

[0009] Figure 3 is a schematic cross-sectional view showing a semiconductor device of a comparative embodiment.

[0010] Figure 4 This is an example of a SIMS profile of a comparative semiconductor device.

[0011] Figure 5 This is another example of a SIMS profile of a comparative semiconductor device.

[0012] Figure 6 This is another example of a SIMS profile of a comparative semiconductor device.

[0013] Figure 7 This is an example of a SIMS profile of the semiconductor device according to the embodiment. DETAILED DESCRIPTION

[0014] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same components and the like are denoted by the same reference numerals, and the description of components and the like that have been described once will be appropriately omitted.

[0015] In this specification, in order to indicate the positional relationship of components, the upper side of the drawings is described as "upper" and the lower side of the drawings is described as "lower". In this specification, the concepts of "upper" and "lower" are not necessarily terms indicating the relationship with the direction of gravity.

[0016] (Implementation Method)

[0017] A semiconductor device of an embodiment comprises: a III-V semiconductor layer containing n-type impurities; a first conductive layer, which is arranged on the III-V semiconductor layer, contains Ti (titanium) and a first element that can become a p-type impurity of the III-V semiconductor layer, and has a first region and a second region in which the concentration of the first element is higher than that of the first region; and a second conductive layer arranged on the first conductive layer.

[0018] Figure 1 2 is a schematic cross-sectional view of a semiconductor device 100 according to the present embodiment.

[0019] The semiconductor device 100 includes a III-V semiconductor layer 2 , a fifth conductive layer 4 , a first conductive layer 6 , and a second conductive layer 12 .

[0020] The fifth conductive layer 4 , the first conductive layer 6 , and the second conductive layer 12 are used as electrodes of the Group III-V semiconductor layer 2 , for example.

[0021] The III-V semiconductor layer 2 contains n-type impurities. The so-called III-V semiconductor is a semiconductor using a III-group element and a V-group element. The III-group element is, for example, Al (aluminum), Ga (gallium), or In (indium). The V-group element is, for example, N (nitrogen), P (phosphorus), arsenic (As), or Sb (antimony). The n-type impurity is, for example, Si (silicon), Sn (tin), S (sulfur), Se (selenium), or Te (tellurium).

[0022] The fifth conductive layer 4 is provided on the III-V semiconductor layer 2. The fifth conductive layer 4 is used for ohmic contact with the III-V semiconductor layer 2. The fifth conductive layer 4 contains, for example, 99.5 atomic % of Au (gold) and 0.5 atomic % of Ge (germanium).

[0023] The first conductive layer 6 is provided on the fifth conductive layer 4. The first conductive layer 6 contains Ti (titanium) and a first element that can be a p-type impurity of the III-V semiconductor layer 2. The first element is Zn (zinc), Mg (magnesium) or Be (beryllium).

[0024] The first conductive layer 6 has a first region 6a and a second region 6b. The first element concentration of the second region 6b is higher than the first element concentration of the first region 6a. For example, the second region 6b is provided on the first region 6a. However, the second region 6b may also be provided under the first region 6a. Figure 1 , the shapes of the first region 6a and the second region 6b in the cross section of the semiconductor device 100 are shown as rectangles. However, the shapes of the first region 6a and the second region 6b in the cross section of the semiconductor device 100 are not limited to rectangles.

[0025] The second conductive layer 12 is provided on the first conductive layer 6. The second conductive layer 12 has a third conductive layer 8 and a fourth conductive layer 10. The third conductive layer 8 is, for example, a Pt conductive layer containing Pt (platinum). The fourth conductive layer 10 is, for example, an Au conductive layer containing Au. For example, a welding wire (not shown) is bonded to the fourth conductive layer 10. In order to ensure good bonding properties, the Au used in the fourth conductive layer 10 preferably contains as few impurities as possible. The third conductive layer 8 is used to improve the adhesion between the first conductive layer 6 and the fourth conductive layer 10.

[0026] Next, a method for manufacturing the semiconductor device 100 according to the present embodiment will be described.

[0027] First, the fifth conductive layer 4 containing 99.5 atomic % Au and 0.5 atomic % Ge is formed on the III-V semiconductor layer 2, which is a GaAs (gallium arsenide) layer containing n-type impurities. The film thickness of the fifth conductive layer 4 is, for example, 100 nm.

[0028] Next, a first conductive layer 6 containing Ti and Zn as a first element is formed on the fifth conductive layer 4. It should be noted that in the formation of the first conductive layer 6, Ti and Zn are simultaneously formed in the first conductive layer 6 by, for example, so-called simultaneous sputtering. However, a Ti film and a Zn film may be formed alternately by sputtering. The film thickness of the first conductive layer 6 is, for example, 100 nm.

[0029] Next, a third conductive layer 8, which is, for example, a Pt conductive layer, is formed on the first conductive layer 6. The film thickness of the third conductive layer 8 is, for example, 70 nm.

[0030] Next, the fourth conductive layer 10, which is, for example, an Au conductive layer, is formed on the third conductive layer 8. The film thickness of the fourth conductive layer 10 is, for example, 600 nm.

[0031] The fifth conductive layer 4 , the first conductive layer 6 , the third conductive layer 8 , and the fourth conductive layer 10 are formed by, for example, sputtering or vacuum deposition.

[0032] Next, heat treatment is performed in an Ar (argon) atmosphere at, for example, 370° C. for 3 minutes. Thus, the first region 6 a and the second region 6 b are formed in the first conductive layer 6. In this way, the semiconductor device 100 of the present embodiment is obtained.

[0033] Next, the effects of the semiconductor device 100 according to the present embodiment will be described.

[0034] Figure 2 Schematic cross-sectional views showing the manufacturing process of a semiconductor device 800 of a comparative embodiment. Figure 3 FIG. 8 is a schematic cross-sectional view of a semiconductor device 800 showing a comparative method. A method for manufacturing the semiconductor device 800 is described below. Figure 2 As shown in , on the III-V semiconductor layer 2, for example, a GaAs layer containing n-type impurities, a fifth conductive layer 4 containing, for example, 99.5 atomic % of Au and 0.5 atomic % of Ge is formed. On the fifth conductive layer 4, a conductive layer 92 containing, for example, Au and Zn is formed. On the conductive layer 92, a conductive layer 94 containing, for example, Ti is formed. On the conductive layer 94, a third conductive layer 8 containing, for example, a Pt conductive layer is formed. On the third conductive layer 8, a fourth conductive layer 10 containing, for example, an Au conductive layer is formed. Thereafter, the ohmic property as an electrode is ensured by heat treatment, and at the same time, as shown in Figure 3 As shown in , a conductive layer 96 in which Zn in the conductive layer 92 and a portion of Ti in the conductive layer 94 are alloyed is formed between the conductive layer 92 and the conductive layer 94. The conductive layer 96 functions as a barrier metal that prevents diffusion of constituent elements and other elements in the III-V semiconductor layer 2.

[0035] Here, there is the following problem: due to the uneven process in the heat history during the heat treatment and the subsequent chip manufacturing process, the alloy form of Zn and Ti becomes unstable and the function as a barrier metal is reduced. That is, if AuZn and Ti are formed in a stacked structure and subjected to heat treatment, Zn forms an alloy with Ti and also diffuses in the opposite direction of the conductive layer 94 containing Ti (the direction of the III-V semiconductor layer 2). Therefore, the concentration of Zn that should be alloyed with Ti changes with the change of the heat treatment process, and the alloy form becomes unstable. As a result, there is a problem that the barrier function also becomes uneven.

[0036] Figure 4 This is an example of a SIMS (Secondary Ion Mass Spectroscopy) profile of a semiconductor device 800 of a comparative embodiment. Figure 4 This is a SIMS distribution diagram when the barrier property provided by the conductive layer 96 is maintained. Figure 4The so-called "semiconductor layer" is the III-V semiconductor layer 2. The so-called "conductive layer" includes a conductive layer disposed on the III-V semiconductor layer 2. For example, Figure 4 In the case of , the “conductive layer” includes the fifth conductive layer 4 , the conductive layer 92 , the conductive layer 96 , the conductive layer 94 , the third conductive layer 8 , and the fourth conductive layer 10 .

[0037] exist Figure 4 In the figure, it can be seen that Ga, a constituent element of the III-V semiconductor layer 2, diffuses into the stacked metal (conductive layer), but it is found that the diffusion stops in the portion where the secondary ion intensity of Ti and Zn is high and TiZn is alloyed.

[0038] Figure 5 This is another example of a SIMS (Secondary Ion Mass Spectroscopy) profile of the semiconductor device 800 of the comparative method. Figure 5 This is a SIMS distribution diagram of the case where the barrier property is reduced by the conductive layer 96. Figure 4 Compared with the SIMS distribution diagram of , although there is no significant difference in the distribution diagram of TiZn, the expansion of the distribution diagram of Zn is slightly larger, and Ga penetrates to the surface of the laminated metal (the surface of the fourth conductive layer 10). The fourth conductive layer 10 functions as a bonding layer connected to a welding wire (not shown), but the Ga that reaches the surface forms an oxide film on the outermost surface of the fourth conductive layer 10, which may be the main cause of hindering bonding. In this way, in the conductive layer 96 produced by the same formation process, there is also a problem in the stability of performance due to the process unevenness in the heat history during the heat treatment and the subsequent chip manufacturing process.

[0039] Figure 6 This is another example of SIMS of the semiconductor device 800 of the comparative method. Figure 6 This is an example of an attempt to increase the amount of Zn in the metal by increasing the deposited film thickness during the formation of the conductive layer 92 in order to stabilize the morphology of the Ti-Zn alloy. Figure 6 In this way, although the amount of Zn itself increases, the influence of diffusion to the semiconductor side caused by heat treatment cannot be prevented. Therefore, there is a problem that the morphology of the Ti-Zn alloy cannot be stabilized.

[0040] Therefore, in the semiconductor device 100 of the present embodiment, the first conductive layer 6 including Ti (titanium) and the first element that can become a p-type impurity of the III-V semiconductor layer is formed. That is, in the comparative embodiment, an alloy of Zn and Ti is formed by sequentially forming AuZn and Ti in a stacked structure and applying heat treatment. On the other hand, in the semiconductor device 100 of the present embodiment, a TiZn alloy is formed by applying heat treatment to a structure formed in the form of Ti-Zn in advance.

[0041] Figure 7 1 is an example of a SIMS profile of the semiconductor device 100 according to the embodiment. The region where the secondary ion intensity of Zn is particularly high between the depth of 0.7 μm and the depth of 0.8 μm is the second region 6b. In addition, the region where the secondary ion intensity of Zn is lower than that of the second region 6b between the depth of 0.8 μm and the depth of 1.2 μm is the first region 6a. In either the first region 6a or the second region 6b, if Figure 4 and Figure 5 Comparing the SIMS distribution diagram shown in , the secondary ion intensity of Zn is higher.

[0042] exist Figure 7 In the comparison method, the diffusion of Ga is suppressed at a depth deeper than the depth corresponding to the second region 6b. Therefore, it is known that the first conductive layer 6 functions as a good barrier layer. Figure 4 In the SIMS distribution diagram of , the distribution diagram of Ga diffusion front and the distribution diagram of Zn decrease in the same area. Figure 7 In the SIMS distribution diagram, the Ga content decreases deeper than the Zn content area. Figure 4 In the SIMS distribution diagram, at the depth where the secondary ion intensity of Zn is high and the secondary ion intensity of Ti is high, the secondary ion intensity of Ga is 1×10 4 In contrast, Figure 7 In the SIMS distribution diagram, at the depth where the secondary ion intensity of Zn is high and the secondary ion intensity of Ti is high, the secondary ion intensity of Ga is 1×10 3 As described below, in the semiconductor device 100 of the embodiment, it is considered that since the amount of Zn is large, the amount of alloy with Ti is also large, and sufficient barrier performance can be obtained; and as a result, it is considered that the margin for stopping Ga diffusion increases.

[0043] The difference in SIMS profiles between the semiconductor device 100 of the present embodiment and the semiconductor device 800 of the comparative embodiment is caused by the formation of the first conductive layer 6 containing Ti and the first element that can become a p-type impurity of the III-V semiconductor layer. In addition, since the secondary ion intensity of Zn is high in the semiconductor device 100, the diffusion of Ga is suppressed. Furthermore, it is considered that since the second region 6b having a higher first element concentration than the first region 6a is provided, the element diffusion is further suppressed in the second region 6b in particular.

[0044] It should be noted that the film thickness of the fifth conductive layer 4 and the first conductive layer 6 are both preferably in the range of 50 to 500 nm. In addition, the heat treatment temperature is preferably in the range of 280°C to 400°C.

[0045] According to the present invention, it is possible to effectively suppress the diffusion of impurities from the semiconductor layer into the conductive layer. Therefore, in the bonding layer as a surface layer connected to a metal wire, for example, the formation of an oxide film due to the diffusion of impurities and the resulting impairment of bonding can be suppressed.

[0046] It should be noted that in Figure 4 , Figure 5 , Figure 6 and Figure 7 In the SIMS profile shown in , no absolute correction of the concentration of each element is performed. Figure 4 , Figure 5 and Figure 6 The relationship between the concentrations of the elements shown in FIG. 8 is different from the relationship between the concentrations of the elements in the actual semiconductor device 800. Figure 7 The relationship between the elements shown in FIG. 1 is different from the relationship between the concentrations of the elements in the actual semiconductor device 100. Figure 4 , Figure 5 , Figure 6 and Figure 7 In the SIMS profiles shown in FIG. 1 , the Zn amount, the Ti amount, and the Ga amount can be compared between the SIMS profiles shown in different drawings.

[0047] It should be noted that in Figure 4 In the SIMS distribution diagram shown in , the Ti amount in the depth direction, the Zn amount in the depth direction, and the Ga amount in the depth direction can be compared. Figure 4 In the SIMS distribution diagram shown in , since the absolute correction of the concentration of each element is not implemented as described above, it is impossible to compare the amount of Ti with the amount of Zn, the amount of Ti with the amount of Ga, and the amount of Zn with the amount of Ga. Figure 5 , Figure 6 and Figure 7The same is true in the SIMS profile shown in .

[0048] According to the semiconductor device of this embodiment, a semiconductor device having electrodes with low contact resistance can be provided.

[0049] Several embodiments and examples of the present invention have been described, but these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: A III-V semiconductor layer, wherein the III-V semiconductor layer includes n-type impurities; a first conductive layer disposed on the III-V semiconductor layer, comprising Ti (titanium) and Zn (zinc), and having a first region and a second region having a higher concentration of Zn (zinc) than the first region; and The second conductive layer is disposed on the first conductive layer and includes Au (gold).

2. The semiconductor device according to claim 1, in, The second region is disposed on the first region.

3. The semiconductor device according to claim 1, in, The second conductive layer includes a third conductive layer including Pt (platinum) and a fourth conductive layer provided on the third conductive layer and including Au (gold). 4 . The semiconductor device according to claim 1 , further comprising a fifth conductive layer provided between the III-V semiconductor layer and the first conductive layer.

5. The semiconductor device according to claim 4, in, The fifth conductive layer includes Au (gold) and Ge (germanium).

6. The semiconductor device according to claim 4, in, The fifth conductive layer contains 99.5 atomic % of Au (gold) and 0.5 atomic % of Ge (germanium).

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