A solar cell and a back contact structure thereof, a cell assembly and a photovoltaic system

Abstract

The application belongs to the technical field of solar cells, and provides a solar cell, a back contact structure of the solar cell, a cell module and a photovoltaic system. The back contact structure comprises a first doped region opposite to the polarity of a silicon substrate and a second doped region with the same polarity as the silicon substrate, which are arranged at intervals on the back of the silicon substrate, and a protection region is arranged on the first doped region. The first doped region and the second doped region each comprise a first doped layer, a passivation layer and a second doped layer. The protection region comprises an insulating layer and a third doped layer with the same polarity as the second doped region. An isolation region is arranged between the first doped region and the second doped region. The protection region is provided with an opening to connect the first conductive layer with the first doped region. The height of the first doped region and the second doped region is higher than the height of the isolation region. The back contact structure provided in the application solves the problem of scratches caused by belt transmission in the preparation process of the existing cell.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of solar cells, and particularly relates to a solar cell, a back contact structure of the solar cell, a solar cell module and a photovoltaic system. BACKGROUND

[0002] Solar cell power generation is a sustainable clean energy source, which can convert sunlight into electricity by using the photovoltaic effect of a semiconductor p-n junction, and the conversion efficiency is an important indicator of the performance of solar cells. The IBC (Interdigitated back contact) cell, also known as the interdigital back contact cell, has both positive and negative electrodes designed on the back surface of the cell, so that the front surface is completely free from the shading of metal grid lines, eliminating the optical loss caused by the shading of metal grid lines, and the electrode width can be designed wider than the existing one, which reduces the series resistance loss, thereby greatly improving the conversion efficiency. In addition, the design of the front surface without electrodes makes the product appearance more beautiful, which is suitable for various application scenarios.

[0003] The existing IBC cell with doped polysilicon passivation forms an isolation between the doped polysilicon and the silicon substrate through a tunneling layer, so as to form a doped polysilicon-tunneling layer (insulating layer)-silicon substrate laminated type passivation contact structure. In the preparation process of the existing IBC cell, multiple processes such as polishing, doping, etching, film plating, screen printing, etc. are required, and the cell needs to be transported through multiple transportation modes such as belts, graphite boats, and suction cups during the flow between the processes.

[0004] However, during the transmission of the cell piece using the belt, the cell piece is in complete contact with the belt, and at this time, the rough surface on the belt may scratch the cell piece during the transmission process. In the early preparation process of the cell piece, the scratch layer can be removed through subsequent texturing, etching and other processes, but after the preparation of the passivation contact structure, it is difficult to remove the scratch of the doped polysilicon in the passivation contact structure of the cell piece caused by the belt, or additional process flow is required to remove it. At this time, if the scratch of the cell piece is not treated, the defects caused by the scratch of the cell piece still exist in the subsequent processes of plating the back passivation film and screen printing the electrode, which affects the conversion efficiency of the cell piece. SUMMARY

[0005] The purpose of the embodiment of the present application is to provide a back contact structure of a solar cell, which aims to solve the problem of scratches caused by belt transmission in the existing cell preparation process.

[0006] The embodiment of the present application is implemented as follows: a back contact structure of a solar cell, comprising:

[0007] The first doped region and the second doped region are arranged on the back of the silicon substrate, and the first doped region is arranged on the protective region.

[0008] The first doped region and the second doped region each include a first doped layer, a passivation layer, and a second doped layer.

[0009] The protective region includes an insulating layer and a third doped layer with the same polarity as the second doped region.

[0010] The first doped region and the second doped region are separated by an isolation region.

[0011] The protective region has an opening to connect the first conductive layer to the first doped region.

[0012] The first doped region and the second doped region each have a height higher than that of the isolation region.

[0013] Further, the height of the first doped region is higher than that of the second doped region.

[0014] Further, the passivation layer is a porous structure with the first doped layer and / or the second doped layer in the pore region.

[0015] Further, one of the first doped region and the second doped region is a P-type doped region, and the other is an N-type doped region, and the thickness of the passivation layer in the P-type doped region is greater than that in the N-type doped region.

[0016] Further, one of the first doped region and the second doped region is a P-type doped region, and the other is an N-type doped region, and the pore density of the passivation layer in the P-type doped region is greater than that in the N-type doped region.

[0017] Further, the first doped layer and the second doped layer have the same doping polarity.

[0018] Further, the height difference between the first doped region and the second doped region is 1-8 um.

[0019] Further, the height difference between the second doped region and the isolation region is 0.5-8 um.

[0020] Further, the pore diameter in the porous structure is less than 20 um.

[0021] Further, the area ratio of the pore region in the porous structure to the overall area of the porous structure is less than 20%.

[0022] Further, the thickness of the passivation layer is 0.5-10nm.

[0023] Further, the passivation layer and / or the insulation layer is one or a combination of an oxide layer, a silicon carbide layer, and an amorphous silicon layer.

[0024] Further, the doping concentration of the first doped layer is between the doping concentration of the silicon substrate and the doping concentration of the second doped layer.

[0025] Further, the junction depth of the first doped layer is less than 1.5um.

[0026] Further, the first doped layer is a doped single-crystal silicon layer doped with a group III or group V element.

[0027] Further, the second doped layer and / or the third doped layer comprises a doped polysilicon layer or a doped silicon carbide layer or a doped amorphous silicon layer.

[0028] Further, the doped silicon carbide layer in the second doped layer and / or the third doped layer is composed of at least one doped silicon carbide film with different refractive indexes, and the refractive indexes of the doped silicon carbide films decrease from the silicon substrate outward.

[0029] Further, the doped silicon carbide layer in the second doped layer and / or the third doped layer comprises a doped hydrogenated silicon carbide layer, and the conductivity of the doped hydrogenated silicon carbide layer is greater than 0.01S·cm and the thickness is greater than 10nm.

[0030] Further, the thickness of the insulation layer is 5-150nm.

[0031] Further, the thickness of the insulation layer is greater than the thickness of the passivation layer.

[0032] Another embodiment of the present application also provides a solar cell, comprising:

[0033] a silicon substrate;

[0034] a back contact structure as described above disposed on the back side of the silicon substrate;

[0035] a first dielectric layer disposed on the front side of the silicon substrate;

[0036] a first conductive layer disposed on the first doped region in the back contact structure and a second conductive layer disposed on the second doped region in the back contact structure; and

[0037] a second dielectric layer disposed on the back contact structure and between the first conductive layer and the second conductive layer.

[0038] Further, the first dielectric layer and the second dielectric layer are one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer and a silicon oxide layer.

[0039] Further, the first dielectric layer and / or the second dielectric layer are an aluminum oxide layer and a silicon carbide layer, or a silicon oxide layer and a silicon carbide layer.

[0040] The thickness of the first dielectric layer is greater than 50 nm, and the thickness of the second dielectric layer is greater than 25 nm.

[0041] Further, the thickness of the aluminum oxide layer or the silicon oxide layer in the first dielectric layer is less than 40 nm, the thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the silicon carbide layer in the first dielectric layer and / or the second dielectric layer is greater than 10 nm.

[0042] Further, the silicon carbide layer in the first dielectric layer and / or the second dielectric layer is composed of at least one silicon carbide film with different refractive indexes, and the refractive indexes of the silicon carbide films decrease from the silicon substrate outward.

[0043] Further, the outer layer of the first dielectric layer and / or the second dielectric layer is further provided with a magnesium fluoride layer.

[0044] Further, the first conductive layer and the second conductive layer are a TCO transparent conductive film and / or a metal electrode.

[0045] Further, the metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-coated copper electrode or a silver-coated copper electrode.

[0046] Further, the silicon substrate is further provided with an electric field layer or a floating junction between the front surface and the first dielectric layer.

[0047] Another object of another embodiment of the present application is to provide a battery assembly comprising the solar cell as described above.

[0048] Another object of another embodiment of the present application is to provide a photovoltaic system comprising the battery assembly as described above.

[0049] The back contact structure of the solar cell provided by the embodiment of the present application sets the protection area on the first doped area, and does not process the second doped area, so that the third doped layer in the protection area is set on the outermost layer to achieve the anti-scratch effect, avoiding scratching the first doped area inside the protection area. At the same time, since the height of the second doped area is lower than the height of the protection area, only the protection area is attached to the belt during the transmission process, and there is a certain gap between the second doped area and the belt to achieve suspension, thereby avoiding scratching the second doped area during the belt transmission process. The problem of scratching the first doped area and the second doped area during the belt transmission process is avoided, and the problem of scratching caused by the belt transmission in the existing cell preparation process is solved.

[0050] Meanwhile, the second doped region and the protection region can reuse the same process to be made synchronously, so that the protection region can be used as an intermediate product generated in the process of producing the second doped region, and the protection region is locally reserved through a graphic design, so that an additional process is not needed to be generated, thereby reducing the process flow, process time and process cost. Meanwhile, the protection region is provided with an opening, and the first conductive layer passes through the opening to be connected with the first doped region, so that the first conductive layer is arranged on the first doped region, and thus the first doped region located at the periphery of the first conductive layer can form an isolation protection for the first conductive layer, so that the isolation effect is improved, and the recombination of the space charge region is reduced. Meanwhile, the protection region also plays a role of a contaminant barrier to reduce the sensitivity of surface contamination. Meanwhile, the opening provided by the protection region can be used as an alignment reference in the preparation of the first conductive layer, so that the first conductive layer is prepared more accurately. Meanwhile, the first doped layer changes the Fermi level, increases the solid concentration of transition metals to enhance gettering, and the third doped layer changes the Fermi level to increase the interface defects, so that non-uniform nucleation points can be formed on the interface defects to enhance the gettering effect, thereby achieving an additional gettering effect. Meanwhile, the isolation region is arranged between the first doped region and the second doped region, so that the first doped region and the second doped region can be separated, and the leakage and other adverse phenomena caused by the unblocked connection between the first doped region and the second doped region are avoided. Meanwhile, the passivation layer is provided with a porous structure, and the first doped layer and / or the second doped layer is embedded in the hole region of the passivation layer, so that a conductive channel is formed in the hole region of the passivation layer, thereby forming a good resistivity for the passivation layer, reducing the sensitivity of the thickness of the passivation layer to the resistance, thereby reducing the control requirement for the thickness of the passivation layer, so that the preparation method of the passivation layer is more diverse than the prior art. Meanwhile, the first doped layer arranged between the silicon substrate and the passivation layer forms an enhanced separation electric field of surface electrons and holes, so that the field passivation effect is improved. Meanwhile, the second doped layer and the third doped layer contain hydrogen elements, which can diffuse into the interior during high-temperature process, so that the hydrogen passivation is enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 is a structural schematic diagram of a back contact structure of a solar cell provided by an embodiment of the present application;

[0052] Figure 2 and Figure 3 is a structural schematic diagram of various embodiments of a solar cell provided by an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0054] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting", "fixing" and the like should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0055] The present application sets a protection zone on the first doped region, and does not process the second doped region, so that the third doped layer in the protection zone is arranged at the outermost layer to play an anti-scratch effect, avoiding scratching the first doped region inside the protection zone, and at the same time, since the height of the second doped region is lower than the height of the protection zone, only the protection zone is attached to the belt during transmission, and there is a gap between the second doped region and the belt to realize suspension, thereby avoiding scratching the second doped region during belt transmission, so that the problem of scratching the first doped region and the second doped region during belt transmission is avoided, and the problem of scratching caused by belt transmission in the existing battery preparation process is solved.

[0056] Example One

[0057] The embodiment of the present application provides a back contact structure of a solar cell, for the convenience of description, only the part related to the embodiment of the present application is shown, and the back contact structure 20 of the solar cell provided by the embodiment of the present application comprises: Figure 1 As shown in the figure, the back contact structure 20 of the solar cell provided by the embodiment of the present application comprises:

[0058] The first doped region 21 and the second doped region 22 are arranged at intervals on the back of the silicon substrate 10 and are opposite in polarity to the silicon substrate 10, and the first doped region 21 is provided with a protection zone 23;

[0059] The first doped region 21 and the second doped region 22 both comprise a first doped layer 211, a passivation layer 212 and a second doped layer 213;

[0060] The protection zone 23 comprises an insulating layer 231 and a third doped layer 232 which is the same in polarity as the second doped region 22;

[0061] An isolation region 24 is provided between the first doping region 21 and the second doping region 22;

[0062] The protection area 23 is provided with an opening to connect the first conductive layer to the first doped region 21;

[0063] The heights of the first doping region 21 and the second doping region 22 are both higher than that of the isolation region 24 .

[0064] In one embodiment of the present invention, the silicon substrate 10 has a front side facing the sun during normal operation and a back side opposite to the front side, the front side is the light-receiving side, and the back side is located on the other side of the silicon substrate 10 relative to the front side; that is, the above-mentioned front side and back side are located on different sides of the silicon substrate 10 and are opposite sides. In this embodiment, the silicon substrate 10 is an N-type single crystal silicon wafer. It can be understood that in other embodiments, the silicon substrate 10 can also be other types of silicon wafers such as polycrystalline silicon wafers or quasi-single crystal silicon wafers, and the type of the silicon substrate 10 can also be set to P-type. The silicon substrate 10 is set according to actual use needs and is not specifically limited here.

[0065] In one embodiment of the present invention, referring to Figure 1 As shown, its back contact structure 20 includes a first region and a second region alternately arranged on the back of the silicon substrate 10 and having opposite polarities, wherein the first region includes a first doping region 21 arranged on the back of the silicon substrate 10 and a protection region 23 arranged on the first doping region 21, and the second region includes a second doping region 22 arranged on the back of the silicon substrate 10, wherein the polarity of the first region is opposite to the polarity of the silicon substrate 10, and the polarity of the second region is the same as the polarity of the silicon substrate 10. Therefore, in this embodiment, the first doping region 21 in the first region is a P-type doping region, and the second doping region 22 in the second region is an N-type doping region. It can be understood that in other embodiments of the present invention, when the silicon substrate 10 is a P-type silicon wafer, the first doping region 21 is correspondingly an N-type doping region, and the second doping region 22 is correspondingly a P-type doping region.

[0066] Further, in one embodiment of the present application, the first doped region 21 and the second doped region 22 each include a first doped layer 211, a passivation layer 212, and a second doped layer 213, the guard region 23 includes an insulating layer 231 and a third doped layer 232 having the same polarity as the second doped region 22, that is, the first region specifically includes the first doped layer 211, the passivation layer 212, the second doped layer 213, the insulating layer 231, and the third doped layer 232, and the polarity of the third doped layer 232 is opposite to that of the second doped layer 213, and the second region specifically includes the first doped layer 211, the passivation layer 212, and the second doped layer 213. That is, the first region specifically has the insulating layer 231 and the third doped layer 232 in the guard region 23 in addition to the second region. Further, the guard region 23 is provided with an opening, so that the first conductive layer is connected to the first doped region 21 after passing through the opening thereof, that is, the insulating layer 231 and the third doped layer 232 are provided with a through opening, so that the first conductive layer can be connected to the second doped layer 213 after passing through the opening thereof. It should be noted that, as shown in Figure 1 the opening is arranged at the middle position of the insulating layer 231 and the third doped layer 232, so that when the first conductive layer is connected to the second doped layer 213 after passing through the opening, the insulating layer 231 and the third doped layer 232 at the periphery of the first conductive layer can form an isolation protection for the first conductive layer. Therefore, in the battery prepared according to the back contact structure 20 in the present embodiment, as shown in Figure 2 and Figure 3 the first conductive layer arranged on the emitter and the back surface field is isolated, so as to reduce the load of the space charge region; at the same time, the guard region 23 also plays a role of a contaminant barrier, so as to reduce the sensitivity of surface contamination; at the same time, the opening of the guard region 23 can be used as an alignment reference in the subsequent preparation of the first conductive layer, so that the first conductive layer can be prepared more accurately. In the present embodiment, the third doped layer 232 in the guard region 23 is arranged at the outermost layer, so as to play a role of scratch resistance, and avoid scratching the first doped region 21 inside the guard region 23; at the same time, since the guard region 23 is arranged on the first doped region 21, and no treatment is performed on the second doped region 22, the height of the second doped region 22 is lower than that of the guard region 23, so that only the guard region 23 is attached to the belt during the transmission process, and there is a gap between the second doped region 22 and the belt, so as to be suspended, thereby avoiding scratching the second doped region 22 during the transmission process of the belt.

[0067] Furthermore, in one embodiment of the present invention, an isolation region 24 is provided between the first doping region 21 and the second doping region 22; and the heights of the first doping region 21 and the second doping region 22 are both higher than the height of the isolation region 24. It should be noted that the height indicated is the distance from the front surface of the silicon substrate 10 to the corresponding structure, such as the height of the first doping region 21 specifically refers to the distance between the front surface of the silicon substrate 10 and the outermost third doping layer 232 in the first doping region 21, and the height of the isolation region 24 specifically refers to the distance between the front surface of the silicon substrate 10 and the isolation region 24. Specifically, in one embodiment of the present invention, the isolation region 24 is a trench, wherein the first doping region 21 and the second doping region 22 are provided on the back surface of the silicon substrate 10, and the trench is opened on the back surface of the silicon substrate 10 toward the inside thereof, so the height of the isolation region 24 must be smaller than the heights of the first doping region 21 and the second doping region 22, refer to Figure 2 As shown. The height difference between the second doping region 22 and the isolation region 24 is 0.5-8 μm. The trench provided between the first doping region 21 and the second doping region 22 separates the first doping region 21 and the second doping region 22, thereby preventing undesirable phenomena such as leakage caused by the first doping region 21 and the second doping region 22 being connected together without any barrier. It should be pointed out that the surface morphology of the groove in contact with the silicon substrate 10 can be provided with a rough texture structure, wherein the rough texture structure is usually formed by texturing, which includes but is not limited to alkali polishing surface, mechanical polishing surface, random pyramid shape, inverted pyramid shape, spherical crown shape, V-shaped groove shape, and morphology between the above morphologies. It can usually form an irregular hemispherical texture through acid texturing, form a pyramid texture through alkali texturing, or first form a pyramid texture through alkali texturing and then smooth the pyramid top through acid texturing. At this time, the surface morphology formed at the groove on the back side of the silicon substrate 10 is conducive to increasing the absorption and reuse of light by the silicon substrate 10, thereby increasing the short-circuit current density, thereby improving the conversion efficiency of the solar cell.

[0068] Further, in other embodiments of the present application, the isolation region 24 can also be a protrusion formed from the base of the silicon substrate 10, in which grooves are spaced apart on the back surface of the silicon substrate 10, and the first region and the second region are alternately arranged in each groove, and the grooves can be formed by laser ablation or by a combination of a mask (such as a hard mask, a silicon oxide mask, a silicon nitride mask, a photoresist mask, etc.) and wet / dry etching. At this time, due to the grooves spaced apart on the back surface of the silicon substrate 10, the area between two adjacent grooves of the silicon substrate 10 is generally in the shape of a protrusion, so that the back surface pattern of the silicon substrate 10 generally presents an interlaced arrangement of grooves and protrusions. At this time, the protrusion serves as the isolation region 24 between the first doped region 21 and the second doped region 22, and the height of the first doped region 21 and the second doped region 22 is higher than the height of the isolation region 24, so that the outermost third doped layer 232 of the first doped region 21 and the second doped region 22 extends out of the surface of the protrusion at the top end of the groove. At this time, the protrusion structure between the grooves of the silicon substrate 10 itself can achieve the isolation of the first doped region 21 and the second doped region 22 arranged in each groove. It should be noted that the surface topography of the protrusion structure can also be provided with a rough texture structure, which will be described in detail above. Of course, alternatively, a trench can also be provided between the protrusion structure or the groove between the first doped region 21 and the second doped region 22, so that the first doped region 21 and the second doped region 22 are doubly isolated by the protrusion structure and the trench structure between the grooves of the silicon substrate 10 itself.

[0069] Further, in one embodiment of the present application, the grooves are circular arc-shaped, trapezoidal, or square-shaped. The grooves are preferably circular arc-shaped or trapezoidal. When the grooves are circular arc-shaped or trapezoidal, the reflection of light by the inner wall of the groove is better, and the surface area of the contact between the passivation layer 212 and the first doped layer 211 is increased. Of course, when the grooves are square-shaped, the actual production process is simpler. It should be noted that the shapes of the grooves can be the same or different, such as the grooves for the first doped region 21 and the grooves for the second doped region 22 are both square-shaped, or the grooves for the first doped region 21 are square-shaped and the grooves for the second doped region 22 are circular arc-shaped, etc. Therefore, the shapes of the grooves can be set according to actual needs, which are not limited herein. Further, the width and depth of each groove can be the same or different, which can be set according to actual needs, which are not limited herein.

[0070] Furthermore, in one embodiment of the present invention, the height of the first doping region 21 is higher than the height of the second doping region 22. Specifically, the height of the first doping region 21 is higher than the height of the second doping region 22 by controlling the thickness of the first doping layer 211, the passivation layer 212, and the second doping layer 213 in the first doping region 21 and the second doping region 22 respectively. Of course, it is also possible to arrange grooves at intervals on the back side of the silicon substrate 10, and arrange the first doping region 21 outside the grooves and the second doping region 22 inside the grooves, so that the height of the first doping region 21 is higher than the height of the second doping region 22, as shown in FIG. Figure 3 As shown. Preferably, the height difference between the first doping region 21 and the second doping region 22 is 1-8um, that is, when the film thickness of the first doping region 21 and the second doping region 22 is the same, the depth of the groove is preferably 1-8um. In order to achieve the barrier between the first doping region 21 and the second doping region 22, a groove may be provided between the first doping region 21 and the second doping region 22, and the first doping region 21 and the second doping region 22 are separated by the groove. The first doping region 21 can also be set in a partial area outside the groove, and the second doping region 22 can be set in a partial area inside the groove, so that the silicon substrate 10 that does not cover the first doping region 21 and the second doping region 22 inside and outside the groove can separate the first doping region 21 and the second doping region 22. Furthermore, the height difference between the second doping region 22 and the isolation region 24 is 0.5-8um.

[0071] Among them, in one embodiment of the present invention, the passivation layer 212 in the first doping region 21 and the second doping region 22 is preferably a combination of one or more of an oxide layer, a silicon carbide layer, and an amorphous silicon layer; as some examples of the present invention, for example, the passivation layer 212 can be an oxide layer of a single material, or a combination of oxide layers of multiple materials and an amorphous silicon layer, or a combination of multiple layers of amorphous silicon with different refractive indices of a single material. In addition, the passivation layer 212 can also be a silicon oxynitride layer, a silicon nitride layer, etc. It can be understood that the specific structural arrangement of the passivation layer 212 includes but is not limited to the several methods listed above. The passivation layer 212 is set accordingly according to actual use needs and is not specifically limited here. Further, the thickness of the passivation layer 212 is 0.5-10nm. As a preferred embodiment of the present invention, the thickness of the passivation layer 212 is preferably 0.8-2nm. At this time, the thickness of the passivation layer 212 in the first doping region 21 and the second doping region 22 can be set to the tunneling layer thickness in the prior art, or can be set to be thicker than the existing tunneling layer thickness, etc. It is set according to actual use needs and is not specifically limited here.

[0072] In a preferred embodiment of the present application, specifically, the passivation layer 212 is preferably an oxidation layer and a silicon carbide layer, at this time, the oxidation layer and the silicon carbide layer are arranged in sequence from the silicon substrate 10 outward, the oxidation layer is in contact with the first doped layer 211 on the inner side, and the silicon carbide layer is in contact with the second doped layer 213 on the outer side. Further, the oxidation layer is preferably composed of one or more layers of a silicon oxide layer and an aluminum oxide layer; therefore, the passivation layer 212 can also be a combination of the silicon oxide layer and the aluminum oxide layer in the oxidation layer. Among them, the silicon carbide layer in the passivation layer 212 includes a hydrogenated silicon carbide layer. At this time, the hydrogen in the hydrogenated silicon carbide layer enters the silicon substrate 10 under the action of diffusion mechanism and thermal effect, neutralizes the dangling bonds on the back of the silicon substrate 10, passivates the defects of the silicon substrate 10 well, and thus converts the energy band in the forbidden band into the valence band or the conduction band, so as to improve the probability of carriers passing through the passivation layer 212 into the second doped layer 213.

[0073] Further, in an embodiment of the present application, as shown in Figure 1 The passivation layer 212 in the first doped region 21 and the second doped region 22 is a porous structure with the first doped layer 211 and / or the second doped layer 213 in the pore region at this time, the passivation layer 212 is a porous structure, which can be prepared by additional chemical etching, dry etching or thermal diffusion impact, etc., and is prepared according to actual use requirements, which is not specifically limited here. It should be noted that the porous structure is a porous structure observed from the top view of the passivation layer 212, and is a multi-channel structure observed from the cross-sectional view of the passivation layer 212. At this time, the pores in the porous structure completely penetrate the passivation layer 212; there are also pores that do not completely penetrate the passivation layer 212, but form grooves / indentations on the surface of the passivation layer 212. Among them, the pore size of the porous structure is less than 20um, which can be specifically that the average pore size of each pore is less than 20um, or also can be that the pore size of 90% of all pores is less than 20um. At the same time, the area ratio of the pore region of the porous structure to the overall area of the porous structure is less than 20%, that is, the passivation layer 212 is sparsely distributed with each pore.

[0074] In one embodiment of the present application, the porous structure has a first doped layer 211 and / or a second doped layer 213 in the pore region, that is, the pore region can contain the first doped layer 211 entirely, or the second doped layer 213 entirely, or both the first doped layer 211 and the second doped layer 213. It should be noted that in actual production, the porous structure can also have the first doped layer 211 and / or the second doped layer 213 in part of the pore region, and the other part without the first doped layer 211 and / or the second doped layer 213 is a void region. It should also be noted that in addition to the first doped layer 211 and / or the second doped layer 213, the pore region can also contain impurities (such as hydrogen, oxygen, and various metal elements) generated by precipitation or segregation due to a heat process (there can be multiple high-temperature processing procedures in the production of solar cells according to different process flows). Since the passivation layer 212 is provided with a porous structure and has the first doped layer 211 and / or the second doped layer 213 in the pore region, an electrically conductive channel is formed in the pore region of the passivation layer 212, thereby forming a good resistivity for the passivation layer 212, reducing the sensitivity of the thickness of the passivation layer 212 to the resistance, and thus reducing the control requirements for the thickness of the passivation layer 212. Therefore, the preparation method of the passivation layer 212 can be more diverse than before. Meanwhile, the second doped layer 213 is connected to the silicon substrate 10 through the doped pore region and the first doped layer 211 in the porous structure, further reducing the overall resistance of the prepared battery, and ultimately improving the conversion efficiency of the battery.

[0075] Further, in one embodiment of the present application, the non-pore region of the porous structure contains a dopant of the same type as the first doped layer 211 and / or the second doped layer 213. For example, when the first doped layer 211 and the second doped layer 213 in the first doped region 21 are P-type doped (such as boron doping) in the present embodiment, the non-pore region of the passivation layer 212 in the first doped region 21 contains diffused P-type dopants. When the first doped layer 211 and the second doped layer 213 in the second doped region 22 are N-type doped (such as phosphorus doping), the non-pore region of the passivation layer 212 in the second doped region 22 contains diffused N-type dopants.

[0076] In one embodiment of the present application, the first doped layer 211 is located between the silicon substrate 10 and the passivation layer 212. The first doped layer 211 can be a doped layer directly deposited on the silicon substrate 10 by ion implantation or the like. In this case, the first doped layer 211 is located on the silicon substrate 10, and the passivation layer 212 is prepared on the first doped layer 211. Alternatively, the first doped layer 211 can be a doped layer formed in the silicon substrate 10 by using a doping source that directly penetrates the passivation layer 212 or penetrates the holes in the porous structure during preparation of the second doped layer 213. In this case, the first doped layer 211 is located in the silicon substrate 10, and the passivation layer 212 is prepared on the silicon substrate 10. During preparation of the second doped layer 213, the doping source diffuses into the silicon substrate 10, and a portion of the silicon substrate 10 is diffused into the first doped layer 211. In this case, the doping concentration of the first doped layer 211 is between the doping concentration of the silicon substrate 10 and the doping concentration of the second doped layer 213. In a preferred embodiment of the present application, the first doped layer 211 and the second doped layer 213 have the same doping polarity. For example, when the second doped layer 213 in the first doped region 21 is a P-type doped layer, the first doped layer 211 in the first doped region 21 is also preferably a P-type doped layer. When the second doped layer 213 in the second doped region 22 is an N-type doped layer, the first doped layer 211 in the second doped region 22 is also preferably an N-type doped layer. In this case, the doping polarity of the first doped layer 211 and the second doped layer 213 in the first doped region 21 is opposite to the doping polarity of the silicon substrate 10.

[0077] Preferably, the material of the first doped layer 211 is the same as that of the silicon substrate 10. For example, when the silicon substrate 10 is a single crystal silicon wafer, the first doped layer 211 is also preferably a single crystal silicon wafer. The first doped layer 211 is a doped single crystal silicon layer doped with Group III or Group V elements. When the second doped layer 213 is an N-type doped layer, the first doped layer 211 is a doped single crystal silicon layer doped with nitrogen, phosphorus, arsenic or other Group V elements. When the second doped layer 213 is a P-type doped layer, the first doped layer 211 is a doped single crystal silicon layer doped with boron, aluminum, gallium or other Group III elements. It can be understood that when the silicon substrate 10 is another type of silicon wafer, the first doped layer 211 can also be another type of doped silicon wafer doped with Group III or Group V elements.

[0078] Further, in one embodiment of the present application, the first doped layer 211 can be discrete or continuous, which can be completely continuous between the silicon substrate 10 and the passivation layer 212, or can be discrete and locally distributed around the holes of the passivation layer 212. In this case, the distribution of the first doped layer 211 can be controlled by the doping process. The longer the doping time and the more the doping amount, the higher the proportion of the continuous first doped layer 211, until a layer of the first doped layer 211 completely covers the silicon substrate 10. Further, the junction depth of the first doped layer 211 is less than 1.5 um. Since the first doped layer 211 is arranged between the silicon substrate 10 and the passivation layer 212 to form an enhanced surface electron-hole separation field, the field passivation effect is improved. At the same time, the first doped layer 211 changes the Fermi level, increases the solid concentration of transition metals, and enhances the gettering effect, thereby achieving an additional gettering effect.

[0079] In one embodiment of the present application, the second doped layer 213 includes a doped polysilicon layer, a doped silicon carbide layer, or a doped amorphous silicon layer. The doped silicon carbide layer in the second doped layer 213 is composed of at least one doped silicon carbide film with different refractive indexes, and the refractive indexes of the doped silicon carbide films decrease from the silicon substrate 10 outward. It should be noted that the thickness and refractive index of the doped silicon carbide film can be set according to actual needs, which mainly satisfies the decrease from the silicon substrate 10 outward, and is not specifically limited here. Since the optical band gap of the silicon carbide material is wide and the absorption coefficient is low, the parasitic absorption can be reduced, and the short-circuit current density can be effectively improved. Further, the doped silicon carbide layer in the second doped layer 213 includes a doped hydrogenated silicon carbide layer, the conductivity of the doped hydrogenated silicon carbide layer is greater than 0.01 S·cm, and the thickness is greater than 10 nm. Correspondingly, the conductivity and thickness can also be set to other values, which can meet the conductivity requirements of the second doped layer 213 by controlling the conductivity and thickness of the doped hydrogenated silicon carbide layer, and are not specifically limited here. It should be noted that the materials of the first doped layer 211 and the second doped layer 213 can be the same or different, for example, the first doped layer 211 and the second doped layer 213 are both doped polysilicon; or the first doped layer 211 is doped monocrystalline silicon and the second doped layer 213 is doped silicon carbide, etc., which can be set according to actual needs, and is not specifically limited here.

[0080] It should be noted that the first doped region 21 and the second doped region 22 both include the first doped layer 211, the passivation layer 212, and the second doped layer 213. At this time, the materials and thicknesses of the layer structures in the first doped region 21 can be the same as or different from those of the layer structures in the second doped region 22. For example, when the passivation layer 212 in the first doped region 21 is specifically selected to be a silicon oxide layer and a silicon carbide layer, the passivation layer 212 in the second doped region 22 can be selected to be the same as the passivation layer 212 in the first doped region 21, or to be a different material such as an aluminum oxide layer and a silicon carbide layer.

[0081] Meanwhile, the thickness of the passivation layer 212 in the first doped region 21 can be the same as or different from that of the passivation layer 212 in the second doped region 22. Preferably, regardless of whether the materials of the passivation layer 212 in the first doped region 21 and the passivation layer 212 in the second doped region 22 are the same, the thickness of the passivation layer 212 corresponding to the first doped layer 211 doped with the group III element is set to be thicker, and the thickness of the passivation layer 212 corresponding to the first doped layer 211 doped with the group V element is set to be thinner. When one of the first doped region 21 and the second doped region 22 is a P-type doped region, and the other is an N-type doped region, the thickness of the passivation layer 212 in the P-type doped region is greater than that of the passivation layer 212 in the N-type doped region. Specifically, in the embodiment, the thickness of the passivation layer 212 in the first doped region 21 is greater than that of the passivation layer 212 in the second doped region 22. Correspondingly, when the silicon substrate 10 is a P-type silicon wafer, the thickness of the passivation layer 212 in the second doped region 22 is greater than that of the passivation layer 212 in the first doped region 21. The main reason is that the P-type doped region requires a boron doping process at a higher temperature and needs to undergo multiple heat treatment processes, and thus needs a thicker passivation layer 212. In the embodiment, the materials and thicknesses of the layer structures in the first doped region 21 and the second doped region 22 are set according to actual needs, which are not specifically limited herein.

[0082] Meanwhile, in the preferred embodiment of the present application, the hole density of the passivation layer 212 in the P-type doped region is greater than that of the passivation layer 212 in the N-type doped region. The hole density refers to the number of holes per unit area, that is, the number of holes in the passivation layer 212 in the P-type doped region is greater than that in the passivation layer 212 in the N-type doped region per unit area. The main reason is that the conductivity of the P-type doped region is poor, and thus more holes are needed to improve the conductivity. In addition, because the thickness of the passivation layer 212 in the P-type doped region is thicker, more holes are needed to improve the conductivity. Specifically, in the embodiment, the hole density of the passivation layer 212 in the first doped region 21 is greater than that of the passivation layer 212 in the second doped region 22.

[0083] In one embodiment of the present invention, the insulating layer 231 in the protection zone 23 is specifically described with reference to the above-mentioned passivation layer 212, that is, the insulating layer 231 is a combination of one or more of an oxide layer, a silicon carbide layer, and an amorphous silicon layer. Specifically, the insulating layer 231 is preferably an oxide layer and a silicon carbide layer. In this case, the oxide layer and the silicon carbide layer are arranged sequentially from the silicon substrate 10 outward, with the oxide layer in contact with the inner second doped layer 213 and the silicon carbide layer in contact with the outer third doped layer 232. The silicon carbide layer in the insulating layer 231 includes a hydrogenated silicon carbide layer. However, it should be noted that the insulating layer 231 is not a porous structure as described above. It should also be noted that the film structure of the passivation layer 212 and the insulating layer 231 can be the same or different. Therefore, the passivation layer 212 and / or the insulating layer 231 are one or more combinations of oxide layers, silicon carbide layers, and amorphous silicon layers. In this case, for example, the passivation layer 212 and the insulating layer 231 are both silicon oxide layers and silicon carbide layers; or the passivation layer 212 can be a silicon oxide layer and a silicon carbide layer, and the insulating layer 231 can be an aluminum oxide layer and a silicon carbide layer. The passivation layer 212 and the insulating layer 231 can be set separately according to actual use needs, and no specific limitation is made here. Furthermore, in this embodiment, the thickness of the insulating layer 231 is 5-150nm, and preferably the thickness of the insulating layer 231 is greater than the thickness of the passivation layer 212. The insulating layer 231 can also contain dopants of the same doping type as the second doping layer 213 and / or the third doping layer 232.

[0084] In one embodiment of the present application, the third doped layer 232 in the guard band 23 is as described above for the second doped layer 213, i.e. the third doped layer 232 comprises a doped polysilicon layer or a doped silicon carbide layer or a doped amorphous silicon layer. The doped silicon carbide layer in the third doped layer 232 is composed of at least one doped silicon carbide film with different refractive indexes, and the refractive indexes of the doped silicon carbide films decrease in turn from the silicon substrate 10 outward. The doped silicon carbide layer in the third doped layer 232 comprises a doped hydrogenated silicon carbide layer with a conductivity greater than 0.01 S-cm and a thickness greater than 10 nm. Since the second doped layer 213 and the third doped layer 232 contain hydrogen, the hydrogen can diffuse inward during high temperature processing, thereby enhancing hydrogen passivation. It should be noted that the materials of the second doped layer 213 and the third doped layer 232 can be the same or different, and thus the second doped layer 213 and / or the third doped layer 232 comprises a doped polysilicon layer or a doped silicon carbide layer or a doped amorphous silicon layer. It should also be noted that the second doped layer 213 in the first doped region 21 and the third doped layer 232 in the guard band 23 have opposite doping polarities. In the present embodiment, the second doped layer 213 in the first doped region 21 is a P-type doped layer, and thus the third doped layer 232 in the guard band 23 is an N-type doped layer. The third doped layer 232 changes the Fermi level, increases the interface defects, and forms non-uniform nucleation points on the interface defects, thereby enhancing gettering and achieving an additional gettering effect.

[0085] In one embodiment of the present application, the back contact structure 20 is prepared by first preparing the first doped region 21 on the back of the silicon substrate 10. As described above, the passivation layer 212 is first prepared in the first doped region 21, then a porous structure is prepared on the passivation layer 212 by additional chemical etching, dry etching or thermal diffusion impact, and then the second doped layer 213 is prepared in the first doped region 21, specifically, intrinsic amorphous silicon is deposited on the passivation layer 212, then a P-type doping source containing boron, aluminum, gallium, etc. is deposited on the intrinsic amorphous silicon, or P-type ions containing boron, aluminum, gallium, etc. are implanted, and then high-temperature crystallization treatment is performed to change the intrinsic amorphous silicon into P-type doped polysilicon. At this time, during the high-temperature crystallization treatment, the doping source directly passes through the passivation layer 212 or passes through the pores in the porous structure to form the first doped layer 211 in the silicon substrate 10, thereby preparing the first doped region 21 on the entire back of the silicon substrate 10. Then, the first doped region 21 at the position where the second doped region 22 is to be prepared is removed by patterned etching treatment (such as mask treatment) to expose the silicon substrate 10, and then the second doped region 22 is prepared on the entire back of the silicon substrate 10. The preparation process is as described above. Since the passivation layer 212 and the second doped layer 213 in the second doped region 22 have similar structures and can use the same materials as the insulating layer 231 and the third doped layer 232 in the protection region 23, and the doping polarity of the second doped layer 213 in the second doped region 22 is the same as that of the third doped layer 232 in the protection region 23, the second doped region 22 and the protection region 23 can be made by the same process simultaneously, but it should be noted that the insulating layer 231 does not need to be prepared with a porous structure by additional chemical etching, dry etching or thermal diffusion impact, and the deposition time of the insulating layer 231 is longer than that of the passivation layer 212 in the second doped region 22, so the thickness of the insulating layer 231 is greater than that of the passivation layer 212 in the second doped region 22. At this time, the protection region 23 is an intermediate product generated during the process of producing the second doped region 22, which is obtained by local retention through patterned design, without the need to add additional processes, thereby reducing the process flow, process time and process cost.

[0086] In the embodiment, by setting the protection area on the first doped area and without any treatment on the second doped area, the third doped layer in the protection area is set on the outermost layer to play the anti-scratch effect, avoiding scratching the first doped area inside the protection area. At the same time, since the height of the second doped area is lower than the height of the protection area, only the protection area is attached to the belt during the transmission process, and there is a certain gap between the second doped area and the belt to achieve suspension. Therefore, the problem of scratching the first doped area and the second doped area during the belt transmission process is avoided, and the problem of scratching caused by the belt transmission in the existing battery preparation process is solved.

[0087] Meanwhile, the second doped region and the protection region can reuse the same process to be made synchronously, so that the protection region can be used as an intermediate product generated in the process of producing the second doped region, and the protection region is locally reserved through a graphic design, so that an additional process is not needed to be generated, thereby reducing the process flow, process time and process cost. Meanwhile, the protection region is provided with an opening, and the first conductive layer passes through the opening to be connected with the first doped region, so that the first conductive layer is arranged on the first doped region, and thus the first doped region located at the periphery of the first conductive layer can form an isolation protection for the first conductive layer, so that the isolation effect is improved, and the recombination of the space charge region is reduced. Meanwhile, the protection region also plays a role of a contaminant barrier to reduce the sensitivity of surface contamination. Meanwhile, the opening provided by the protection region can be used as an alignment reference in the preparation of the first conductive layer, so that the first conductive layer is prepared more accurately. Meanwhile, the first doped layer changes the Fermi level, increases the solid concentration of transition metals to enhance gettering, and the third doped layer changes the Fermi level to increase the interface defects, so that non-uniform nucleation points can be formed on the interface defects to enhance the gettering effect, thereby achieving an additional gettering effect. Meanwhile, the isolation region is arranged between the first doped region and the second doped region, so that the first doped region and the second doped region can be separated, and the leakage and other adverse phenomena caused by the unblocked connection between the first doped region and the second doped region are avoided. Meanwhile, the passivation layer is provided as a porous structure, and the first doped layer and / or the second doped layer is embedded in the hole region of the passivation layer, so that a conductive channel is formed in the hole region of the passivation layer, thereby forming a good resistivity for the passivation layer, reducing the sensitivity of the influence of the thickness of the passivation layer on the resistance, thereby reducing the control requirement for the thickness of the passivation layer, so that the preparation method of the passivation layer can be more diverse compared with the prior art. Meanwhile, the first doped layer arranged between the silicon substrate and the passivation layer forms an enhanced separation electric field of surface electrons and holes, so that the field passivation effect is improved. Meanwhile, the second doped layer and the third doped layer contain hydrogen elements, which can diffuse into the interior in a high-temperature process, so that the hydrogen passivation is enhanced.

[0088] Example Two

[0089] The second embodiment of the present application provides a solar cell, for the convenience of description, only the parts related to the embodiments of the present application are shown, and the solar cell provided by the embodiments of the present application is shown in FIGS. Figure 2 and Figure 3 The solar cell provided by the embodiments of the present application includes:

[0090] a silicon substrate 10;

[0091] a back contact structure 20 disposed on the back surface of the silicon substrate 10;

[0092] a first dielectric layer 30 disposed on the front surface of the silicon substrate 10;

[0093] a first conductive layer 40 disposed on the first doped region 21 in the back contact structure 20 and a second conductive layer 50 disposed on the second doped region 22 in the back contact structure 20; and

[0094] a second dielectric layer 60 disposed on the back contact structure 20 and between the first conductive layer 40 and the second conductive layer 50.

[0095] In one embodiment of the present application, the first dielectric layer 30 and the second dielectric layer 60 are one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer and a silicon oxide layer. The first dielectric layer 30 and the second dielectric layer 60 have a passivation effect, and the first dielectric layer 30 and the second dielectric layer 60 are at least provided in a structure of one layer, and the refractive indexes of the layers are arranged in a manner of gradually decreasing from the silicon substrate 10 outward, so that the film layer close to the silicon substrate 10 has a passivation effect, and the film layer far from the silicon substrate 10 has an antireflection effect, so that the antireflection effect can be enhanced, thereby increasing the absorption and utilization of light by the silicon substrate 10, and increasing the short-circuit current density. Each layer of the first dielectric layer 30 and the second dielectric layer 60 can also be composed of multiple layers of films with different refractive indexes, and arranged in a manner of gradually decreasing from the silicon substrate 10 outward, for example, the silicon oxide layer in the first dielectric layer 30 can be composed of multiple layers of silicon oxide films with gradually decreasing refractive indexes from the silicon substrate 10 outward.

[0096] It should be noted that the structures of the first dielectric layer 30 and the second dielectric layer 60 can be the same or different, and the respective film layer structures of the first dielectric layer 30 and the second dielectric layer 60 are set according to actual needs, which are not limited here. Preferably, the first dielectric layer 30 and the second dielectric layer 60 are the same, so that the first dielectric layer 30 and the second dielectric layer 60 can be prepared on the front and back surfaces of the silicon substrate 10 by the same process.

[0097] In the preferred embodiment of the present application, the first dielectric layer 30 and / or the second dielectric layer 60 is preferably a two-layer structure of an aluminum oxide layer and a silicon carbide layer, or a two-layer structure of a silicon oxide layer and a silicon carbide layer; at this time, the overall thickness of the first dielectric layer 30 is greater than 50 nm, and the overall thickness of the second dielectric layer 60 is greater than 25 nm. It can be understood that the specific structural arrangement of the first dielectric layer 30 and the second dielectric layer 60 includes but is not limited to the specific examples listed above.

[0098] Further, in an embodiment of the present application, the thickness of the aluminum oxide layer or the silicon oxide layer in the first dielectric layer 30 is less than 40 nm, the thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer 60 is less than 25 nm, and the thickness of the silicon carbide layer in the first dielectric layer 30 and / or the second dielectric layer 60 is greater than 10 nm. At this time, the silicon carbide layer in the first dielectric layer 30 and / or the second dielectric layer 60 not only provides hydrogen passivation effect, but also reduces parasitic light absorption due to its large optical band gap and small absorption coefficient.

[0099] It should be noted that in the multi-layer structure referred to in the embodiments of the present application, the order is arranged from the silicon substrate 10 outward, for example, when the first dielectric layer 30 is an aluminum oxide layer and a silicon carbide layer as described above, the aluminum oxide layer is close to the silicon substrate 10, and the silicon carbide layer is close to the outside. At the same time, it should be noted that in the drawings, as shown in Figure 2 and Figure 3 , only the two-layer structure of the first dielectric layer 30 and the second dielectric layer 60 is shown, and it can be understood that the first dielectric layer 30 and the second dielectric layer 60 can also have other numbers of layers, and the specific structure is set according to actual needs, and does not completely follow the drawings shown in the specification. At the same time, it should be noted that in each of the drawings of the present application, only the specific structure distribution in the solar cell is described, but it is not the actual size of each structure, and the actual size in the embodiments is not completely shown in the drawings, and it should be in accordance with the specific parameters provided in the embodiments.

[0100] Further, the silicon carbide layer in the first dielectric layer 30 and / or the second dielectric layer 60 is composed of at least one silicon carbide film with different refractive indices. The refractive indices of each layer of silicon carbide film decrease in turn from the silicon substrate 10 outward. Optionally, the refractive indices of the above-mentioned various materials can be selected as follows: the refractive index of single crystal silicon is 3.88; the refractive index of amorphous silicon is 3.5-4.2; the refractive index of polycrystalline silicon is 3.93; the refractive index of silicon carbide is 2-3.88; the refractive index of silicon nitride is 1.9-3.88; the refractive index of silicon oxynitride is 1.45-3.88; the refractive index of silicon oxide is 1.45; and the refractive index of aluminum oxide is 1.63. It can be understood that the refractive indices of the above-mentioned various materials can also be set to other values according to actual use needs, which are not limited here.

[0101] Further, in one embodiment of the present application, the outer layer of the first dielectric layer 30 and / or the second dielectric layer 60 is further provided with a magnesium fluoride layer, that is, on the basis of one or more combinations of the selected alumina layer, silicon nitride layer, silicon oxynitride layer, silicon carbide layer, amorphous silicon layer and silicon oxide layer of the first dielectric layer 30 and the second dielectric layer 60, the outer layer of the first dielectric layer 30 and / or the second dielectric layer 60 can be further provided with a magnesium fluoride layer. The refractive index of the magnesium fluoride layer is required to be the lowest, and generally the refractive index is set to 1.4, which is used to enhance the optical effect of anti-reflection.

[0102] Further, in one embodiment of the present application, an electric field layer or a floating junction is further provided between the front surface of the silicon substrate 10 and the first dielectric layer 30, which is specifically an electric field layer prepared by phosphorus diffusion of the silicon substrate 10 or a floating junction prepared by boron diffusion, at this time the electric field layer or the floating junction serves as the front surface electric field of the solar cell.

[0103] Further, in one embodiment of the present application, the front surface of the silicon substrate 10 is further subjected to a texturing process before the preparation of the first dielectric layer 30, so that the topography formed on the front surface includes but is not limited to alkali polishing surface, mechanical polishing surface, random pyramid, inverted pyramid, spherical cap, V-shaped groove, and topography between the above-mentioned topographies, at this time the surface topography formed on the front surface of the silicon substrate 10 is beneficial to reduce the reflection of the front surface sunlight and improve the conversion efficiency of the solar cell.

[0104] In one embodiment of the present application, the first conductive layer 40 and / or the second conductive layer 50 is a TCO transparent conductive film and / or a metal electrode. The metal electrode includes silver electrode, copper electrode, aluminum electrode, tin-coated copper electrode or silver-coated copper electrode. Further, the copper electrode is electroplated copper prepared by electroplating process or copper electrode prepared by physical vapor deposition. The electroplated copper uses nickel, chromium, titanium, tungsten electrode as its seed layer or protective layer. It should be noted that the first conductive layer 40 and the second conductive layer 50 can also be selected to be the same or different, for example, the first conductive layer 40 and the second conductive layer 50 are both selected to be aluminum electrode; or the first conductive layer 40 is selected to be silver electrode, and the second conductive layer 50 is selected to be aluminum electrode.

[0105] Further, in one embodiment of the present application, the first conductive layer 40 is provided on the first doped region 21 and is arranged in the opening provided by the protection region 23, and the second conductive layer 50 is provided on the second doped region 22. At this time, the second dielectric layer 60 is arranged on the back contact structure 20 and between the first conductive layer 40 and the second conductive layer 50, at this time, correspondingly, the second dielectric layer 60 is arranged on the outermost side of the entire back surface of the silicon substrate 10 except the first conductive layer 40 and the second conductive layer 50, which is described in detail with reference to Figure 2 andFigure 3 As shown, when the isolation region 24 is a groove, the second dielectric layer 60 also covers the groove. Correspondingly, during preparation, the second dielectric layer 60 can be completely covered on the entire back surface of the silicon substrate 10 first, and then the first conductive layer 40 is formed to be electrically connected with the first doped region 21 by perforating the second dielectric layer 60; the second conductive layer 50 is formed to be electrically connected with the second doped region 22 by perforating the second dielectric layer 60. The conductive polarity of the first conductive layer 40 and the second conductive layer 50 is determined according to the polarity of the first doped region 21 and the second doped region 22, which is not specifically limited herein.

[0106] In this embodiment, by setting the protection region on the first doped region and not doing any treatment on the second doped region, the third doped layer in the protection region is set on the outermost layer to play the anti-scratch effect, avoiding scratching the first doped region inside the protection region. At the same time, since the height of the second doped region is lower than the height of the protection region, only the protection region is attached to the belt during transmission, and there is a gap between the second doped region and the belt to achieve suspension, thus avoiding scratching the second doped region during belt transmission. Therefore, the problem of scratching the first doped region and the second doped region during belt transmission is avoided, and the problem of scratching caused by belt transmission in the existing battery preparation process is solved.

[0107] Meanwhile, the second doped region and the protection region can reuse the same process to be made synchronously, so that the protection region can be used as an intermediate product generated in the process of producing the second doped region, and the protection region is locally reserved through a graphic design, so that an additional process is not needed to be generated, thereby reducing the process flow, process time and process cost. Meanwhile, the protection region is provided with an opening, and the first conductive layer passes through the opening to be connected with the first doped region, so that the first conductive layer is arranged on the first doped region, and thus the first doped region located at the periphery of the first conductive layer can form an isolation protection for the first conductive layer, so that the isolation effect is improved, and the recombination of the space charge region is reduced. Meanwhile, the protection region also plays a role of a contaminant barrier to reduce the sensitivity of surface contamination. Meanwhile, the opening provided by the protection region can be used as an alignment reference in the preparation of the first conductive layer, so that the first conductive layer is prepared more accurately. Meanwhile, the first doped layer changes the Fermi level, increases the solid concentration of transition metals to enhance gettering, and the third doped layer changes the Fermi level to increase the interface defects, so that non-uniform nucleation points can be formed on the interface defects to enhance the gettering effect, thereby achieving an additional gettering effect. Meanwhile, the isolation region is arranged between the first doped region and the second doped region, so that the first doped region and the second doped region can be separated, and the leakage and other adverse phenomena caused by the unblocked connection between the first doped region and the second doped region are avoided. Meanwhile, the passivation layer is provided with a porous structure, and the first doped layer and / or the second doped layer is inlaid in the hole region of the passivation layer, so that a conductive channel is formed in the hole region of the passivation layer, thereby forming a good resistivity for the passivation layer, reducing the sensitivity of the influence of the thickness of the passivation layer on the resistance, thereby reducing the control requirement for the thickness of the passivation layer, so that the preparation method of the passivation layer can be more diverse compared with the prior art. Meanwhile, the first doped layer arranged between the silicon substrate and the passivation layer forms an enhanced separation electric field of surface electrons and holes, so that the field passivation effect is improved. Meanwhile, the second doped layer and the third doped layer contain hydrogen elements, which can diffuse into the interior in a high-temperature process, so that the hydrogen passivation is enhanced.

[0108] Example Three

[0109] The third embodiment of the present application also provides a battery assembly, which comprises the solar cell of the second embodiment.

[0110] Example Four

[0111] The fourth embodiment of the present application also provides a photovoltaic system, comprising the battery assembly as described in the foregoing embodiment three.

[0112] The above only provides the preferred embodiments of the present application and is not used to limit the present application, any modification, equivalent replacement and improvement within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A back contact structure of a solar cell, characterized in that: include: A first doping region with a polarity opposite to that of the silicon substrate and a second doping region with a polarity identical to that of the silicon substrate are arranged at intervals on the back side of the silicon substrate, wherein a protection zone is provided on the first doping region; The first doping region and the second doping region each include a first doping layer, a passivation layer, and a second doping layer; The protection zone includes an insulating layer and a third doping layer having the same polarity as the second doping zone; An isolation region is provided between the first doping region and the second doping region; The protection zone is provided with an opening to connect the first conductive layer with the first doped region; Grooves are arranged at intervals on the back side of the silicon substrate, the first doped region is arranged outside the grooves, the second doped region is arranged inside the grooves, and the isolation region is arranged inside the grooves; The heights of the first doping region and the second doping region are both higher than the height of the isolation region, the passivation layer is a porous structure having the first doping layer and / or the second doping layer in the hole area, one of the first doping region and the second doping region is a P-type doping region, and the other is an N-type doping region, and the hole density of the passivation layer in the P-type doping region is greater than the hole density of the passivation layer in the N-type doping region.

2. The back contact structure according to claim 1, wherein: The height of the first doping region is higher than that of the second doping region.

3. The back contact structure according to claim 1, wherein: One of the first doping region and the second doping region is a P-type doping region, and the other is an N-type doping region. The thickness of the passivation layer in the P-type doping region is greater than the thickness of the passivation layer in the N-type doping region.

4. The back contact structure according to claim 1, wherein: The first doping layer and the second doping layer have the same doping polarity.

5. The back contact structure according to claim 2, wherein: The height difference between the first doping region and the second doping region is 1-8 um.

6. The back contact structure according to claim 1 or 2, characterized in that: A height difference between the second doping region and the isolation region is 0.5-8 um.

7. The back contact structure according to claim 1, wherein: The pore size of the porous structure is less than 20 μm.

8. The back contact structure according to claim 1, wherein: The ratio of the area of ​​the hole region of the porous structure to the overall area of ​​the porous structure is less than 20%.

9. The back contact structure according to claim 1, wherein: The thickness of the passivation layer is 0.5-10 nm.

10. The back contact structure according to claim 1, wherein: The passivation layer and / or the insulating layer is one or more combinations of an oxide layer, a silicon carbide layer, and an amorphous silicon layer.

11. The back contact structure according to claim 1, wherein: The doping concentration of the first doping layer is between the doping concentration of the silicon substrate and the doping concentration of the second doping layer.

12. The back contact structure according to claim 1, wherein: The junction depth of the first doped layer is less than 1.5 μm.

13. The back contact structure according to claim 1, wherein: The first doped layer is a doped single crystal silicon layer doped with group III or group V elements.

14. The back contact structure according to claim 1, wherein: The second doping layer and / or the third doping layer includes a doped polysilicon layer, a doped silicon carbide layer, or a doped amorphous silicon layer.

15. The back contact structure according to claim 14, wherein: The doped silicon carbide layer in the second doped layer and / or the third doped layer is composed of at least one layer of doped silicon carbide film with different refractive index, and the refractive index of each layer of the doped silicon carbide film decreases from the silicon substrate outward.

16. The back contact structure according to claim 14, wherein: The doped silicon carbide layer in the second doping layer and / or the third doping layer includes a doped hydrogenated silicon carbide layer. The doped hydrogenated silicon carbide layer has an electrical conductivity greater than 0.01 S·cm and a thickness greater than 10 nm.

17. The back contact structure according to claim 1, wherein: The thickness of the insulating layer is 5-150 nm.

18. The back contact structure according to claim 1, wherein: The thickness of the insulating layer is greater than the thickness of the passivation layer.

19. A solar cell, characterized in that: include: Silicon substrate; A back contact structure according to any one of claims 1 to 18 provided on the back side of the silicon substrate; a first dielectric layer disposed on the front surface of the silicon substrate; a first conductive layer disposed on the first doped region in the back contact structure and a second conductive layer disposed on the second doped region in the back contact structure; and A second dielectric layer is disposed on the back contact structure and between the first conductive layer and the second conductive layer.

20. The solar cell according to claim 19, wherein The first dielectric layer and the second dielectric layer are one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, and a silicon oxide layer.

21. The solar cell according to claim 20, wherein The first dielectric layer and / or the second dielectric layer is an aluminum oxide layer and a silicon carbide layer, or a silicon oxide layer and a silicon carbide layer; The thickness of the first dielectric layer is greater than 50 nm, and the thickness of the second dielectric layer is greater than 25 nm.

22. The solar cell according to claim 21, wherein The thickness of the aluminum oxide layer or silicon oxide layer in the first dielectric layer is less than 40 nm, the thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the silicon carbide layer in the first dielectric layer and / or the second dielectric layer is greater than 10 nm.

23. The solar cell according to claim 20 or 21, wherein: The silicon carbide layer in the first dielectric layer and / or the second dielectric layer is composed of at least one silicon carbide film with different refractive indexes, and the refractive index of each silicon carbide film layer decreases from the silicon substrate outwards.

24. The solar cell according to claim 20, wherein The outer layer of the first dielectric layer and / or the second dielectric layer is further provided with a magnesium fluoride layer.

25. The solar cell according to claim 19, wherein The first conductive layer and the second conductive layer are TCO transparent conductive films and / or metal electrodes.

26. The solar cell according to claim 25, wherein The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode or a silver-clad copper electrode.

27. The solar cell according to claim 19, wherein An electric field layer or a floating junction is further provided between the front surface of the silicon substrate and the first dielectric layer.

28. A battery assembly, characterized in that: The battery assembly includes the solar cell according to any one of claims 19 to 27.

29. A photovoltaic system, characterized in that: The photovoltaic system includes the battery assembly according to claim 28.

Images