Low dropout linear regulator compensation circuit and low dropout linear regulator

Abstract

The present application discloses a low dropout linear regulator compensation circuit and a low dropout linear regulator. The circuit includes a first error amplifier, a first loop, and a second loop. The first error amplifier is configured to adjust the output voltage of the low dropout linear regulator compensation circuit according to a reference voltage and the output voltage of the low dropout linear regulator compensation circuit. The first loop is used for sourcing current. When sourcing current, a first current generating circuit generates a first current, and the first current acts on a first compensation circuit, so that the first compensation circuit can adjust a first output impedance of the first error amplifier through the first current. The second loop is used for sinking current. When sinking current, a second current generating circuit generates a second current, and the second current acts on a second compensation circuit, so that the second compensation circuit can adjust a second output impedance of the first error amplifier through the second current.

Description

Technical Field

[0001] This application relates to the technical field of voltage regulators, and particularly to a low-dropout linear regulator compensation circuit and a low-dropout linear regulator. Background Art

[0002] A low-dropout voltage regulator (LDO) is a DC linear voltage regulator with an input voltage greater than the output voltage. It has advantages such as fast input-output response and low noise, and can be applied to the power supplies of memories such as DDR (Double Data Rate) and DDR2 (Double Data Rate 2). Memories such as DDR and DDR2 require a power supply with strong load driving ability, high output accuracy, good transient performance, and the ability to sink / source large currents. For an LDO that can sink / source large currents, stability compensation within the full load range is a difficult point in the industry. Currently, there is a lack of a circuit that can perform stability compensation on an LDO with the ability to sink / source large currents. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application proposes a low-dropout linear regulator compensation circuit that can compensate the low-dropout linear regulator when the low-dropout linear regulator sinks or sources current.

[0004] This application also proposes a low-dropout linear regulator including the above-mentioned low-dropout linear regulator compensation circuit.

[0005] The first aspect embodiment of this application provides a low-dropout linear regulator compensation circuit, including:

[0006] A first error amplifier, the first input terminal of the first error amplifier is used to connect to a reference voltage, the second input terminal of the first error amplifier is connected to the output terminal of the low-dropout linear regulator compensation circuit, and the first error amplifier is used to adjust the output voltage of the low-dropout linear regulator compensation circuit according to the reference voltage and the output voltage of the low-dropout linear regulator compensation circuit;

[0007] A first loop for sinking current; the first loop includes a first current generation circuit and a first compensation circuit. The first output terminal of the first error amplifier is connected to the first current generation circuit through the first compensation circuit. The first current generation circuit is used to generate a first current acting on the first compensation circuit, and the first compensation circuit is used to adjust the first output impedance of the first error amplifier through the first current;

[0008] A second loop for sink current. The second loop includes a second current generation circuit and a second compensation circuit. The second output terminal of the first error amplifier is connected to the second current generation circuit through the second compensation circuit. The second current generation circuit is configured to generate a second current acting on the second compensation circuit, and the second compensation circuit is configured to adjust the second output impedance of the first error amplifier through the second current.

[0009] The low dropout linear regulator compensation circuit according to the embodiments of the first aspect of the present application has at least the following beneficial effects: The low dropout linear regulator compensation circuit includes a first error amplifier, a first loop, and a second loop. The first error amplifier is configured to adjust the output voltage of the low dropout linear regulator compensation circuit according to a reference voltage and the output voltage of the low dropout linear regulator compensation circuit. The first loop is for sourcing current. When sourcing current, the first current generation circuit generates a first current, and the first current acts on the first compensation circuit, so that the first compensation circuit can adjust the first output impedance of the first error amplifier through the first current to achieve a compensation effect and improve the load regulation rate of the output voltage of the low dropout linear regulator compensation circuit. The second loop is for sink current. When sinking current, the second current generation circuit generates a second current, and the second current acts on the second compensation circuit, so that the second compensation circuit can adjust the second output impedance of the first error amplifier through the second current to achieve a compensation effect and improve the load regulation rate of the output voltage of the low dropout linear regulator compensation circuit.

[0010] According to some embodiments of the first aspect of the present application, the first error amplifier includes a first operational amplifier, a first P-channel field effect transistor, a second P-channel field effect transistor, a third P-channel field effect transistor, and a fourth P-channel field effect transistor.

[0011] The non-inverting input terminal of the first operational amplifier serves as the first input terminal of the first error amplifier and is configured to receive a reference voltage. The inverting input terminal of the first operational amplifier serves as the second input terminal of the first error amplifier and is connected to the output terminal of the low dropout linear regulator compensation circuit. The first output terminal of the first operational amplifier is connected to the drain of the first P-channel field effect transistor, and the second output terminal of the first operational amplifier is connected to the drain of the third P-channel field effect transistor.

[0012] The gate of the first P-channel field effect transistor is connected to the gate of the second P-channel field effect transistor, and the gate of the first P-channel field effect transistor is connected to the drain of the first P-channel field effect transistor.

[0013] The gate of the third P-channel MOSFET is connected to the gate of the fourth P-channel MOSFET. The drain of the third P-channel MOSFET is connected to the gate of the third P-channel MOSFET. The drain of the fourth P-channel MOSFET serves as the second output terminal of the first error amplifier and is connected to the second compensation circuit. The drain of the second P-channel MOSFET serves as the first output terminal of the first error amplifier and is connected to the first compensation circuit;

[0014] The sources of the first P-channel MOSFET, the second P-channel MOSFET, the third P-channel MOSFET, and the fourth P-channel MOSFET are all used to connect to the first power supply.

[0015] According to some embodiments of the first aspect of the present application, the first compensation circuit includes a first resistor, a first N-channel MOSFET, a second N-channel MOSFET, and a third N-channel MOSFET;

[0016] The drain of the first N-channel MOSFET is respectively connected to the drain of the second P-channel MOSFET and one end of the first current generation circuit. The drain of the second N-channel MOSFET is respectively connected to the drain of the second P-channel MOSFET and one end of the first current generation circuit through the first resistor. The sources of the first N-channel MOSFET, the second N-channel MOSFET, and the third N-channel MOSFET are all connected to the output terminal of the low-dropout linear regulator compensation circuit. The gate of the first N-channel MOSFET is connected to the drain of the first N-channel MOSFET. The gate of the second N-channel MOSFET is connected to the gate of the third N-channel MOSFET. The gate of the third N-channel MOSFET is connected to the drain of the third N-channel MOSFET. The drain of the third N-channel MOSFET is connected to the other end of the first current generation circuit.

[0017] According to some embodiments of the first aspect of the present application, the first current generation circuit includes a second resistor, a third resistor, a fourth N-channel MOSFET, a fifth N-channel MOSFET, and a second operational amplifier;

[0018] The gate of the fourth N-channel MOSFET is connected to the drain of the first N-channel MOSFET. The gate of the fourth N-channel MOSFET is connected to the drain of the second N-channel MOSFET through the first resistor. The drain of the fourth N-channel MOSFET is used to connect to the second power supply. The source of the fourth N-channel MOSFET is connected to the output terminal of the low-dropout linear regulator compensation circuit;

[0019] The gate of the fifth N-channel field effect transistor is connected to the gate of the fourth N-channel field effect transistor. The drain of the fifth N-channel field effect transistor is connected to the inverting input terminal of the second operational amplifier. The drain of the fifth N-channel field effect transistor is used to connect to the second power supply through the second resistor. The non-inverting input terminal of the second operational amplifier is used to connect to the second power supply through the third resistor. The output terminal of the second operational amplifier is connected to the drain of the third N-channel field effect transistor.

[0020] According to some embodiments of the first aspect of the present application, the second compensation circuit includes a sixth N-channel field effect transistor, a seventh N-channel field effect transistor, an eighth N-channel field effect transistor, and a fourth resistor. The drain of the sixth N-channel field effect transistor is connected to the second output terminal of the first error amplifier. The drain of the seventh N-channel field effect transistor is connected to the gate of the sixth N-channel field effect transistor and one end of the second current generation circuit through the fourth resistor. The gate of the sixth N-channel field effect transistor is connected to the drain of the sixth N-channel field effect transistor. The gate of the seventh N-channel field effect transistor is connected to the gate of the eighth N-channel field effect transistor. The drain of the eighth N-channel field effect transistor is connected to the other end of the second current generation circuit and the gate of the eighth N-channel field effect transistor. The source of the sixth N-channel field effect transistor, the source of the seventh N-channel field effect transistor, and the source of the eighth N-channel field effect transistor are all grounded.

[0021] According to some embodiments of the first aspect of the present application, the second current generation circuit includes a ninth N-channel field effect transistor, a tenth N-channel field effect transistor, and a third operational amplifier. The drain of the ninth N-channel field effect transistor is connected to the output terminal of the low dropout linear regulator compensation circuit. The source of the ninth N-channel field effect transistor is grounded. The gate of the ninth N-channel field effect transistor is connected to the gate of the tenth N-channel field effect transistor. The gate of the ninth N-channel field effect transistor is connected to the drain of the seventh N-channel field effect transistor through the fourth resistor. The source of the tenth N-channel field effect transistor is grounded. The drain of the tenth N-channel field effect transistor is connected to the inverting input terminal of the third operational amplifier. The non-inverting input terminal of the third operational amplifier is connected to the output terminal of the low dropout linear regulator compensation circuit. The output terminal of the third operational amplifier is connected to the drain of the eighth N-channel field effect transistor.

[0022] According to some embodiments of the first aspect of the present application, the second operational amplifier includes a fourth operational amplifier, an eleventh N-channel field effect transistor, a twelfth N-channel field effect transistor, a thirteenth N-channel field effect transistor, a fourteenth N-channel field effect transistor, a fifth P-channel field effect transistor, a sixth P-channel field effect transistor, and a first current source.

[0023] The non-inverting input terminal of the fourth operational amplifier serves as the non-inverting input terminal of the second operational amplifier, and the inverting input terminal of the fourth operational amplifier serves as the inverting input terminal of the second operational amplifier. The non-inverting input terminal of the fourth operational amplifier is also connected to the drain of the eleventh N-channel field effect transistor, the output terminal of the fourth operational amplifier is connected to the gate of the eleventh N-channel field effect transistor, and the gate of the eleventh N-channel field effect transistor is connected to the gate of the twelfth N-channel field effect transistor;

[0024] The gate of the thirteenth N-channel field effect transistor is connected to its drain, the gate of the thirteenth N-channel field effect transistor is connected to the gate of the fourteenth N-channel field effect transistor, the drain of the fourteenth N-channel field effect transistor is connected to the drain of the fifth P-channel field effect transistor, the drain of the fifth P-channel field effect transistor is connected to its gate, the gate of the fifth P-channel field effect transistor is connected to the gate of the sixth P-channel field effect transistor, and the drain of the sixth P-channel field effect transistor serves as the output terminal of the second operational amplifier;

[0025] The output terminal of the first current source (A1) is respectively connected to the drain of the twelfth N-channel field effect transistor (MN8) and the drain of the thirteenth N-channel field effect transistor (MN9); the output terminal of the first current source (A1) is also connected between the gate of the thirteenth N-channel field effect transistor (MN9) and the gate of the fourteenth N-channel field effect transistor (MN10);

[0026] The input terminal of the first current source, the source of the fifth P-channel field effect transistor, and the source of the sixth P-channel field effect transistor are all used to connect to the first power supply;

[0027] The sources of the eleventh N-channel field effect transistor, the twelfth N-channel field effect transistor, the thirteenth N-channel field effect transistor, and the fourteenth N-channel field effect transistor are all grounded.

[0028] According to some embodiments of the first aspect of the present application, the third operational amplifier includes a fifth operational amplifier, a seventh P-channel field effect transistor, an eighth P-channel field effect transistor, a ninth P-channel field effect transistor, a tenth P-channel field effect transistor, a fifteenth N-channel field effect transistor, a sixteenth N-channel field effect transistor, a seventeenth N-channel field effect transistor, an eighteenth N-channel field effect transistor, a nineteenth N-channel field effect transistor, and a second current source;

[0029] The non-inverting input terminal of the fifth operational amplifier serves as the inverting input terminal of the third operational amplifier, and the inverting input terminal of the fifth operational amplifier serves as the non-inverting input terminal of the third operational amplifier. The non-inverting input terminal of the fifth operational amplifier is connected to the source of the fifteenth N-channel field effect transistor, and the output terminal of the fifth operational amplifier is connected to the gate of the fifteenth N-channel field effect transistor. The drain of the fifteenth N-channel field effect transistor is connected to the drain of the seventh P-channel field effect transistor, the gate of the seventh P-channel field effect transistor, and the gate of the eighth P-channel field effect transistor;

[0030] The drain of the seventeenth N-channel field effect transistor is connected to the output terminal of the second current source;

[0031] The sources of the seventh P-channel field effect transistor, the eighth P-channel field effect transistor, the ninth P-channel field effect transistor, the tenth P-channel field effect transistor, and the input terminal of the second current source are all connected to the first power supply;

[0032] The gate of the sixteenth N-channel field effect transistor is connected to the drain of the sixteenth N-channel field effect transistor, the drain of the eighth P-channel field effect transistor, and the gate of the seventeenth N-channel field effect transistor. The drain of the seventeenth N-channel field effect transistor is connected to the drain of the eighteenth N-channel field effect transistor, the gate of the eighteenth N-channel field effect transistor, and the gate of the nineteenth N-channel field effect transistor. The drain of the nineteenth N-channel field effect transistor is connected to the drain of the ninth P-channel field effect transistor, the gate of the ninth P-channel field effect transistor, and the gate of the tenth P-channel field effect transistor. The drain of the tenth P-channel field effect transistor serves as the output terminal of the third operational amplifier;

[0033] The sources of the sixteenth N-channel field effect transistor, the seventeenth N-channel field effect transistor, the eighteenth N-channel field effect transistor, and the nineteenth N-channel field effect transistor are all grounded.

[0034] According to some embodiments of the first aspect of the present application, a load circuit is further included. The load circuit includes a load capacitor and a load resistor. The load capacitor and the load resistor are connected in parallel. One end of the load resistor is connected to the output terminal of the low dropout linear regulator compensation circuit, and the other end is grounded.

[0035] An embodiment of the second aspect of the present application provides a low dropout linear regulator, including the low dropout linear regulator compensation circuit according to any one of the embodiments of the first aspect of the present application.

[0036] The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present application. Description of the Drawings

[0037] Additional aspects and advantages of the present application will become apparent and be readily understood in the description of the embodiments in conjunction with the following drawings, in which:

[0038] Figure 1 is a schematic structural diagram of a low dropout linear regulator compensation circuit in the related art;

[0039] Figure 2 is a schematic structural diagram of a low dropout linear regulator compensation circuit according to some embodiments of the first aspect of the present application;

[0040] Figure 3 is Figure 2 a schematic internal circuit diagram of the second operational amplifier in;

[0041] Figure 4 is Figure 2 a schematic internal circuit diagram of the third operational amplifier in. Detailed Description of the Embodiments

[0042] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0043] In the description of the present application, if the first and second are described only for the purpose of distinguishing technical features, they should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0044] In the description of the present application, unless otherwise clearly defined, terms such as "set", "installed", and "connected" should be understood in a broad sense. Those skilled in the relevant art can reasonably determine the specific meanings of the above terms in the present application in combination with the specific content of the technical solution.

[0045] In the related art, referring to Figure 1 , Figure 1Schematic diagram of the structure of a low dropout linear regulator compensation circuit in the related art. The low dropout linear regulator compensation circuit in the related art includes a second error amplifier. The second error amplifier includes an operational amplifier AMP4, a P-channel field effect transistor M4, a P-channel field effect transistor M5, a P-channel field effect transistor M6, and a P-channel field effect transistor M7. The low dropout linear regulator compensation circuit in the related art further includes an N-channel field effect transistor M3, an N-channel field effect transistor M2, an N-channel field effect transistor M1, and an N-channel field effect transistor M0. The low dropout linear regulator compensation circuit in the related art further includes a capacitor C1 and a resistor R3. The first output terminal of the operational amplifier AMP4 is connected to the drain of the P-channel field effect transistor M4. The second output terminal of the operational amplifier AMP4 is connected to the drain of the P-channel field effect transistor M6. The non-inverting input terminal of the operational amplifier AMP4 is connected to the reference voltage VREF. The inverting input terminal of the operational amplifier AMP4 is connected to the output terminal V0 of the low dropout linear regulator compensation circuit. The sources of the P-channel field effect transistor M4, the P-channel field effect transistor M5, the P-channel field effect transistor M6, and the P-channel field effect transistor M7 are all connected to the first power supply VCC. The gate of the P-channel field effect transistor M4 is connected to the drain of the P-channel field effect transistor M4 and the gate of the P-channel field effect transistor M5. The drain of the P-channel field effect transistor M6 is connected to the gate of the P-channel field effect transistor M6 and the gate of the P-channel field effect transistor M7. The drain of the P-channel field effect transistor M7 is connected to the drain of the N-channel field effect transistor M1, the gate of the N-channel field effect transistor M1, and the gate of the N-channel field effect transistor M0. The sources of the N-channel field effect transistor M1, the N-channel field effect transistor M0, and the N-channel field effect transistor M2 are all connected to the output V0 of the low dropout linear regulator compensation circuit in the related art. The drain of the N-channel field effect transistor M0 is connected to the second power supply VLDOIN. The gate of the N-channel field effect transistor M3 is connected to the drain of the N-channel field effect transistor M3, the drain of the P-channel field effect transistor M5, and the gate of the N-channel field effect transistor M2. The sources of the N-channel field effect transistor M3 and the N-channel field effect transistor M2 are both grounded. One end of the resistor R3 is connected to the output V0 of the low dropout linear regulator compensation circuit in the related art. The other end of the resistor R3 is grounded. The capacitor C1 is connected in parallel with the resistor R3.

[0046] In the low dropout linear regulator compensation circuit of the related art, when drawing current, if the size of the N-channel MOSFET M1 is small, for example, the size ratio of the N-channel MOSFET M1 to the N-channel MOSFET M0 is 1:2400. When the output of the low dropout linear regulator compensation circuit is unloaded or lightly loaded, the current flowing through the N-channel MOSFET M0 approaches 0. At this time, the output impedance of the second error amplifier approaches infinity, causing the position of the second pole of the second error amplifier to approach the dominant pole. At this time, the phase margin of the low dropout linear regulator compensation circuit is negative. To increase the phase margin of the low dropout linear regulator compensation circuit, an N-channel MOSFET M1 with a larger size is required. For example, the size ratio of the N-channel MOSFET M1 to the N-channel MOSFET M0 is 1:24, to reduce the output impedance of the second error amplifier, so that the position of the second pole of the second error amplifier is far from the position of the dominant pole, thereby increasing the phase margin of the low dropout linear regulator compensation circuit. However, when using an N-channel MOSFET M1 with a larger size, when the low dropout linear regulator compensation circuit is heavily loaded, the gain of the circuit will decrease to a negative value, and the output voltage will also decrease to a negative value. At this time, the load regulation rate of the output voltage is relatively high.

[0047] In the low dropout linear regulator compensation circuit of the related art, when sinking current, if the size of the N-channel MOSFET M3 is small, for example, the size ratio of the N-channel MOSFET M3 to the N-channel MOSFET M2 is 1:6000. When the low dropout linear regulator compensation circuit of the related art is unloaded or lightly loaded, the current flowing through the N-channel MOSFET M3 approaches 0. At this time, the output impedance of the second error amplifier approaches infinity, thereby causing the position of the second pole of the second error amplifier to approach the dominant pole. At this time, the phase margin of the low dropout linear regulator compensation circuit is negative. To increase the phase margin of the low dropout linear regulator compensation circuit, an N-channel MOSFET M3 with a larger size is required. For example, the size ratio of the N-channel MOSFET M3 to the N-channel MOSFET M2 is 1:60, to reduce the output impedance of the second error amplifier, so that the position of the second pole of the second error amplifier is far from the position of the dominant pole, thereby increasing the phase margin of the low dropout linear regulator compensation circuit. However, when using an N-channel MOSFET M3 with a larger size, when the low dropout linear regulator compensation circuit is heavily loaded, the gain of the circuit will decrease to a negative value, and the output voltage will also decrease to a negative value. At this time, the load regulation rate of the output voltage is relatively high.

[0048] To solve the problems existing in the low dropout linear regulator compensation circuit of the above related art, the first aspect embodiment of the present application provides a low dropout linear regulator compensation circuit.

[0049] Refer to Figure 2, the low-dropout linear regulator compensation circuit according to the first aspect embodiment of the present application includes a first error amplifier 100. The first input terminal of the first error amplifier 100 is used to access a reference voltage. The second input terminal of the first error amplifier 100 is connected to the output terminal V0 of the low-dropout linear regulator compensation circuit. The first error amplifier is used to adjust the output voltage of the low-dropout linear regulator compensation circuit according to the reference voltage and the output voltage of the low-dropout linear regulator compensation circuit;

[0050] The first loop is used for sourcing current. The first loop includes a first current generation circuit 300 and a first compensation circuit 200. The first output terminal of the first error amplifier 100 is connected to the first current generation circuit 300 through the first compensation circuit 200. The first current generation circuit 300 is used to generate a first current acting on the first compensation circuit 200. The first compensation circuit 200 is used to adjust the first output impedance of the first error amplifier 100 through the first current;

[0051] The second loop is used for sinking current. The second loop includes a second current generation circuit 500 and a second compensation circuit 400. The second output terminal of the first error amplifier 100 is connected to the second current generation circuit 500 through the second compensation circuit 400. The second current generation circuit 500 is used to generate a second current acting on the second compensation circuit 400. The second compensation circuit 400 is used to adjust the second output impedance of the first error amplifier 100 through the second current.

[0052] The low-dropout linear regulator compensation circuit according to the first aspect embodiment of the present application can be applied to a low-dropout linear regulator with the ability to source or sink current, and includes a first error amplifier 100, a first loop and a second loop. The first error amplifier 100 is used to adjust the output voltage of the low-dropout linear regulator compensation circuit according to the reference voltage and the output voltage of the low-dropout linear regulator compensation circuit. The first loop is used for sourcing current. When sourcing current, the first current generation circuit 300 generates a first current, and the first current acts on the first compensation circuit 200, so that the first compensation circuit 200 can adjust the first output impedance of the first error amplifier 100 through the first current to achieve a compensation effect and improve the load regulation rate of the output voltage; The second loop is used for sinking current. When sinking current, the second current generation circuit 500 generates a second current, and the second current acts on the second compensation circuit 400, so that the second compensation circuit 400 can adjust the second output impedance of the first error amplifier 100 through the second current to achieve a compensation effect and improve the load regulation rate of the output voltage.

[0053] It can be understood that the first error amplifier 100 includes a first operational amplifier AMP1, a first P-channel MOSFET MP1, a second P-channel MOSFET MP2, a third P-channel MOSFET MP3, and a fourth P-channel MOSFET MP4; the non-inverting input terminal of the first operational amplifier AMP1 serves as the first input terminal of the first error amplifier 100 and is used to connect to a reference voltage, the inverting input terminal of the first operational amplifier AMP1 serves as the second input terminal of the first error amplifier 100 and is connected to the output terminal V0 of the low dropout linear regulator compensation circuit, the first output terminal of the first operational amplifier AMP1 is connected to the drain of the first P-channel MOSFET MP1, and the second output terminal of the first operational amplifier AMP1 is connected to the drain of the third P-channel MOSFET MP3; the gate of the first P-channel MOSFET MP1 is connected to the gate of the second P-channel MOSFET MP2, and the gate of the first P-channel MOSFET MP1 is connected to the drain of the first P-channel MOSFET MP1; the gate of the third P-channel MOSFET MP3 is connected to the gate of the fourth P-channel MOSFET MP4, the drain of the third P-channel MOSFET MP3 is connected to the gate of the third P-channel MOSFET MP3, the drain of the fourth P-channel MOSFET MP4 serves as the second output terminal of the first error amplifier 100 and is connected to the second compensation circuit, and the drain of the second P-channel MOSFET MP2 serves as the first output terminal of the first error amplifier 100 and is connected to the first compensation circuit; the sources of the first P-channel MOSFET MP1, the second P-channel MOSFET MP2, the third P-channel MOSFET MP3, and the fourth P-channel MOSFET MP4 are all used to connect to the first power supply VCC.

[0054] It can be understood that the first compensation circuit 200 includes a first resistor R1, a first N-channel MOSFET MN1, a second N-channel MOSFET MN2, and a third N-channel MOSFET MN3; the drain of the first N-channel MOSFET MN1 is respectively connected to the drain of the second P-channel MOSFET MP2 and one end of the first current generation circuit, and the drain of the second N-channel MOSFET MN2 is connected to the drain of the second P-channel MOSFET MP2 and one end of the first current generation circuit through the first resistor R1; the sources of the first N-channel MOSFET MN1, the second N-channel MOSFET MN2, and the third N-channel MOSFET MN3 are all connected to the output terminal V0 of the low dropout linear regulator compensation circuit, the gate of the first N-channel MOSFET MN1 is connected to the drain of the first N-channel MOSFET MN1, the gate of the second N-channel MOSFET MN2 is connected to the gate of the third N-channel MOSFET MN3, the gate of the third N-channel MOSFET MN3 is connected to the drain of the third N-channel MOSFET MN3, and the drain of the third N-channel MOSFET MN3 is connected to the other end of the first current generation circuit.

[0055] It can be understood that the first current generation circuit 300 includes a second resistor Rs1, a third resistor Rs2, a fourth N-channel MOSFET HS, a fifth N-channel MOSFET HS_Sns, and a second operational amplifier HS_CS;

[0056] The gate of the fourth N-channel MOSFET HS is connected to the drain of the first N-channel MOSFET MN1. The gate of the fourth N-channel MOSFET HS is connected to the drain of the second N-channel MOSFET MN2 through a first resistor R1. The drain of the fourth N-channel MOSFET HS is used to connect to a second power supply VLDOIN. The source of the fourth N-channel MOSFET HS is connected to the output terminal V0 of the low dropout linear regulator compensation circuit;

[0057] The gate of the fifth N-channel MOSFET HS_Sns is connected to the gate of the fourth N-channel MOSFET HS. The drain of the fifth N-channel MOSFET HS_Sns is connected to the inverting input terminal of the second operational amplifier HS_CS. The drain of the fifth N-channel MOSFET HS_Sns is used to connect to the second power supply VLDOIN through a second resistor Rs1. The non-inverting input terminal of the second operational amplifier HS_CS is used to connect to the second power supply VLDOIN through a third resistor Rs2. The output terminal of the second operational amplifier HS_CS is connected to the drain of the third N-channel MOSFET MN3.

[0058] It can be understood that the second compensation circuit 400 includes a sixth N-channel MOSFET MN4, a seventh N-channel MOSFET MN5, an eighth N-channel MOSFET MN6, and a fourth resistor R2. The drain of the sixth N-channel MOSFET MN4 is connected to the second output terminal of the first error amplifier. The drain of the seventh N-channel MOSFET MN5 is connected to the gate of the sixth N-channel MOSFET MN4 and one end of the second current generation circuit through the fourth resistor R2 respectively. The gate of the sixth N-channel MOSFET MN4 is connected to the drain of the sixth N-channel MOSFET MN4. The gate of the seventh N-channel MOSFET MN5 is connected to the gate of the eighth N-channel MOSFET MN6. The drain of the eighth N-channel MOSFET MN6 is connected to the other end of the second current generation circuit and the gate of the eighth N-channel MOSFET MN6 respectively; The sources of the sixth N-channel MOSFET MN4, the seventh N-channel MOSFET MN5, and the eighth N-channel MOSFET MN6 are all grounded.

[0059] It can be understood that the second current generation circuit 500 includes a ninth N-channel field effect transistor LS, a tenth N-channel field effect transistor LS_Sns, and a third operational amplifier LS_CS. The drain of the ninth N-channel field effect transistor LS is connected to the output terminal V0 of the low dropout linear regulator compensation circuit. The source of the ninth N-channel field effect transistor LS is grounded. The gate of the ninth N-channel field effect transistor LS is connected to the gate of the tenth N-channel field effect transistor LS_Sns. The gate of the ninth N-channel field effect transistor LS is connected to the drain of the seventh N-channel field effect transistor MN5 through a fourth resistor R2. The source of the tenth N-channel field effect transistor LS_Sns is grounded. The drain of the tenth N-channel field effect transistor LS_Sns is connected to the inverting input terminal of the third operational amplifier LS_CS. The non-inverting input terminal of the third operational amplifier LS_CS is connected to the output terminal V0 of the low dropout linear regulator compensation circuit. The output terminal of the third operational amplifier LS_CS is connected to the drain of the eighth N-channel field effect transistor MN6.

[0060] It can be understood that, with reference to Figure 3 , the second operational amplifier HS_CS includes a fourth operational amplifier AMP2, an eleventh N-channel field effect transistor MN7, a twelfth N-channel field effect transistor MN8, a thirteenth N-channel field effect transistor MN9, a fourteenth N-channel field effect transistor MN10, a fifth P-channel field effect transistor MP5, a sixth P-channel field effect transistor MP6, and a first current source A1;

[0061] The non-inverting input terminal of the fourth operational amplifier AMP2 serves as the non-inverting input terminal of the second operational amplifier HS_CS. The inverting input terminal of the fourth operational amplifier AMP2 serves as the inverting input terminal of the second operational amplifier HS_CS. The non-inverting input terminal of the fourth operational amplifier AMP2 is further connected to the drain of the eleventh N-channel field effect transistor MN7. The output terminal of the fourth operational amplifier AMP2 is connected to the gate of the eleventh N-channel field effect transistor MN7. The gate of the eleventh N-channel field effect transistor MN7 is connected to the gate of the twelfth N-channel field effect transistor MN8. The gate of the thirteenth N-channel field effect transistor MN9 is connected to its own drain. The gate of the thirteenth N-channel field effect transistor MN9 is connected to the gate of the fourteenth N-channel field effect transistor MN10. The drain of the fourteenth N-channel field effect transistor MN10 is connected to the drain of the fifth P-channel field effect transistor MP5. The drain of the fifth P-channel field effect transistor MP5 is connected to its own gate. The gate of the fifth P-channel field effect transistor MP5 is connected to the gate of the sixth P-channel field effect transistor MP6. The drain of the sixth P-channel field effect transistor MP6 serves as the output terminal of the second operational amplifier HS_CS;

[0062] The output terminal of the first current source A1 is respectively connected to the drain of the twelfth N-channel MOSFET MN8 and the drain of the thirteenth N-channel MOSFET MN9; the output terminal of the first current source A1 is also connected between the gate of the thirteenth N-channel MOSFET MN9 and the gate of the fourteenth N-channel MOSFET MN10;

[0063] The input terminal of the first current source A1, the source of the fifth P-channel MOSFET MP5, and the source of the sixth P-channel MOSFET MP6 are all used to connect to the first power supply VCC; the source of the eleventh N-channel MOSFET MN7, the source of the twelfth N-channel MOSFET MN8, the source of the thirteenth N-channel MOSFET MN9, and the source of the fourteenth N-channel MOSFET MN10 are all grounded.

[0064] It can be understood that, referring to Figure 4 , the third operational amplifier LS_CS includes a fifth operational amplifier AMP3, a seventh P-channel MOSFET MP7, an eighth P-channel MOSFET MP8, a ninth P-channel MOSFET MP9, a tenth P-channel MOSFET MP10, a fifteenth N-channel MOSFET MN11, a sixteenth N-channel MOSFET MN12, a seventeenth N-channel MOSFET MN13, an eighteenth N-channel MOSFET MN14, a nineteenth N-channel MOSFET MN15, and a second current source A2;

[0065] The non-inverting input terminal of the fifth operational amplifier AMP3 serves as the inverting input terminal of the third operational amplifier LS_CS, the inverting input terminal of the fifth operational amplifier AMP3 serves as the non-inverting input terminal of the third operational amplifier LS_CS, the non-inverting input terminal of the fifth operational amplifier AMP3 is connected to the source of the fifteenth N-channel MOSFET MN11, the output terminal of the fifth operational amplifier AMP3 is connected to the gate of the fifteenth N-channel MOSFET MN11, and the drain of the fifteenth N-channel MOSFET MN11 is connected to the drain of the seventh P-channel MOSFET MP7, the gate of the seventh P-channel MOSFET MP7, and the gate of the eighth P-channel MOSFET MP8;

[0066] The drain of the seventeenth N-channel MOSFET MN13 is connected to the output terminal of the second current source A2; the sources of the seventh P-channel MOSFET MP7, the eighth P-channel MOSFET MP8, the ninth P-channel MOSFET MP9, the tenth P-channel MOSFET MP10, and the input terminal of the second current source A2 are all connected to the first power supply VCC;

[0067] The gate of the sixteenth N-channel MOSFET MN12 is connected to the drain of the sixteenth N-channel MOSFET MN12, the drain of the eighth P-channel MOSFET MP8, and the gate of the seventeenth N-channel MOSFET MN13. The drain of the seventeenth N-channel MOSFET MN13 is connected to the drain of the eighteenth N-channel MOSFET MN14, the gate of the eighteenth N-channel MOSFET MN14, and the gate of the nineteenth N-channel MOSFET MN15. The drain of the nineteenth N-channel MOSFET MN15 is connected to the drain of the ninth P-channel MOSFET MP9, the gate of the ninth P-channel MOSFET MP9, and the gate of the tenth P-channel MOSFET MP10. The drain of the tenth P-channel MOSFET MP10 serves as the output terminal of the third operational amplifier LS_CS. The sources of the sixteenth N-channel MOSFET MN12, the seventeenth N-channel MOSFET MN13, the eighteenth N-channel MOSFET MN14, and the nineteenth N-channel MOSFET MN15 are all grounded.

[0068] It can be understood that the low dropout linear regulator compensation circuit of the embodiment of the present application further includes a load circuit 600. The load circuit 600 includes a load capacitor CL and a load resistor RL. The load capacitor CL and the load resistor RL are connected in parallel. One end of the load resistor RL is connected to the output terminal V0 of the low dropout linear regulator compensation circuit, and the other end of the load resistor RL is grounded.

[0069] The following refers to Figures 2 to 4 The working principle of the low dropout linear regulator compensation circuit according to the embodiment of the present application will be described in detail with a specific embodiment. It should be understood that the following description is only an exemplary illustration and not a specific limitation of the present application.

[0070] For example, when the low dropout linear regulator compensation circuit according to the embodiment of the present application is sourcing current, let the first power supply VCC = 3.3V, the second power supply VLDOIN = 1.8V, the reference voltage VREF = 0.9V, the load capacitance CL = 30uF, and the range of the first load current ILOAD1 of the low dropout linear regulator compensation circuit is from 0 to 3A. Those skilled in the art can understand that when the first load current of the low dropout linear regulator compensation circuit is 0, it is no-load; when the first load current of the low dropout linear regulator compensation circuit is greater than 0 and less than 100mA, it is light load; when the first load current is greater than or equal to 100mA and less than 1A, it is medium load; when the first load current is greater than or equal to 1A and less than 3A, it is heavy load. The second N-channel field effect transistor MN2 and the third N-channel field effect transistor MN3 are a current mirror with a size ratio of N2:1. The size ratio of the fifth N-channel field effect transistor HS_Sns and the fourth N-channel field effect transistor HS is 1:N1. Since the first load current ILOAD1 flows through the fourth N-channel field effect transistor HS, the first load current ILOAD1 flowing through the fourth N-channel field effect transistor HS can be sampled proportionally through the fourth operational amplifier AMP2, the second resistor Rs1, and the third resistor Rs2 to obtain a first sampled current Isns1 = ILOAD / N1, that is, the current flowing through the eleventh N-channel field effect transistor MN7 is Isns1. The size ratio of the eleventh N-channel field effect transistor MN7 and the twelfth N-channel field effect transistor MN8 is N3:1, so that the current flowing through the twelfth N-channel field effect transistor MN8 is Isns2 = Isns1 / N3 = ILOAD / (N1×N3); the first current source A1 outputs a first bias current IBIAS1, and the current difference between the current IBIAS1 and the first sampled current Isns1 is sampled through the thirteenth N-channel field effect transistor MN9. The thirteenth N-channel field effect transistor MN9 and the fourteenth N-channel field effect transistor MN10 are a current mirror with a size ratio of 1:1, and the fifth P-channel field effect transistor MP5 and the sixth P-channel field effect transistor MP6 are a current mirror with a size ratio of 1:1, so that the first current Icomp1 generated by the first current generation circuit 300 is Icomp1 = IBIAS1 - Isns2 = IBIAS1 - [ILOAD / (N1×N3)]. Then, as the first load current ILOAD1 increases, the first current Icomp1 gradually decreases.Let the first bias current \(I_{BIAS1}\) output by the first current source \(A1\) be \(2\ \mu A\), and \(N1\times N3 = 500000\). Then when the low dropout linear regulator compensation circuit is in the heavy load state, that is, the first load current \(I_{LOAD1}\) is greater than or equal to \(1\ A\), the first current \(I_{comp1}\) decreases to \(0\). At this time, the current mirrors composed of the thirteenth N-channel MOSFET \(MN9\) and the fourteenth N-channel MOSFET \(MN10\), the current mirrors composed of the fifth P-channel MOSFET \(MP5\) and the sixth P-channel MOSFET \(MP6\), and the current mirror composed of the second N-channel MOSFET \(MN2\) and the third N-channel MOSFET \(MN3\) are turned off. By using the method of turning off multiple current mirrors, the gain of the turn-off loop is made lower, so that the output voltage does not change suddenly when the current mirror is turned off, and the linearity of the output voltage is improved.

[0071] The equivalent resistance of the first N-channel MOSFET \(MN1\) is \(R_{n1}\), and the transconductance of the first N-channel MOSFET \(MN1\) is \(g_{mn1}\), and \(g_{mn1}\) and \(R_{n1}\) are reciprocals of each other; the equivalent resistance of the second N-channel MOSFET \(MN2\) is \(R_{n2}\), and the drain-source conductance of the second N-channel MOSFET \(MN2\) is \(g_{dsn2}\), and \(g_{dsn2}\) and \(R_{n2}\) are reciprocals of each other; the equivalent resistance of the second P-channel MOSFET \(MP2\) is \(R_{p2}\), and the drain-source conductance of the second P-channel MOSFET \(MP2\) is \(g_{dsp2}\), and \(g_{dsp2}\) and \(R_{p2}\) are reciprocals of each other. Then the first output impedance \(R_{EA1}\) of the first error amplifier \(100\) is \(R_{EA1}=[R_{n1} / / (R_{n2}+R1)] / / R_{p2}\). Since the drain of the second N-channel MOSFET \(MN2\) is connected to the first resistor \(R1\), the drain-source conductance \(g_{dsn2}\) of the second N-channel MOSFET \(MN2\) increases, and the equivalent resistance \(R_{n2}\) of the second N-channel MOSFET \(MN2\) decreases. Due to the existence of the first resistor \(R1\), the equivalent resistance \(R_{n2}\) of the second N-channel MOSFET \(MN2\) increases as the current flowing through the second N-channel MOSFET \(MN2\) decreases, that is, the equivalent resistance \(R_{n2}\) of the second N-channel MOSFET \(MN2\) increases as the first current \(I_{comp1}\) decreases. When the low dropout linear regulator compensation circuit is in the no-load state, that is, when the first load current \(I_{LOAD1}\) is \(0\), the first current \(I_{comp1}\) is the largest, and the equivalent resistance \(R_{n2}\) of the second N-channel MOSFET \(MN2\) is the smallest.

[0072] The main pole of the first error amplifier 100 obtained from the transfer function is P0 = 1 / [2×π×(Ro / / RL)×CL], and the secondary pole is P1 = 1 / [2×π×REA1×CEA1], where CEA1 is the first output capacitance of the first error amplifier 100, and Ro at this time is the output resistance when the low dropout linear regulator compensation circuit sinks current. It can be understood that to achieve the stability compensation of the low dropout linear regulator compensation circuit, it is necessary to make the secondary pole far from the main pole, and the secondary pole is determined by the first output impedance and the first output capacitance of the first error amplifier 100. In the embodiment of the present application, the position of the secondary pole P1 is changed by adjusting the first output impedance of the first error amplifier 100.

[0073] Since the drain-source conductance gdsp2 of the second P-channel MOSFET MP2 is small, that is, the equivalent resistance Rp2 of the second P-channel MOSFET MP2 is large and can be ignored, the first output impedance REA1 of the first error amplifier 100 can be approximated as REA1≈Rn1 / / (Rn2 + R1).

[0074] When the low dropout linear regulator compensation circuit is in the light load state, the first load current ILOAD1 is greater than 0 and less than 100 mA. The current flowing through the first N-channel MOSFET MN1 is close to 0 and can be ignored, while the current flowing through the second N-channel MOSFET MN2 is N2×Icomp1. Since the current flowing through the first N-channel MOSFET MN1 is close to 0, the transconductance gmn1 of the first N-channel MOSFET MN1 approaches 0, that is, the equivalent resistance Rn1 of the first N-channel MOSFET MN1 approaches infinity. Then the first output impedance REA1 of the first error amplifier 100 can be approximated as REA1≈Rn2 + R1. At this time, the first output impedance REA1 of the first error amplifier 100 is small, and the position of the secondary pole of the first error amplifier 100 is far from the position of the main pole. As the first load current ILOAD1 increases from 0 to nearly 100 mA, REA1 gradually increases, and the position of the secondary pole approaches the main pole as the load current increases. However, the phase margin of the low dropout linear regulator compensation circuit meets the stability requirements during this process.

[0075] When the low dropout linear regulator compensation circuit is in the medium load state, the first load current ILOAD1 is equal to or greater than 100 mA and less than 1 A. As the first load current ILOAD1 increases, the current flowing through the first N-channel MOSFET MN1 gradually increases. Since the first current Icomp1 gradually decreases, the current flowing through the second N-channel MOSFET MN2 gradually decreases. At this time, the first output impedance REA1 of the first error amplifier 100 can be approximated as REA1≈Rn1 / / (Rn2 + R1). Then, the position of the second pole of the first error amplifier 100 can be changed by changing the resistance value of the first resistor R1. At the same time, the existence of the first resistor R1 also introduces a zero, and the position of this zero is close to the position of the second pole, so that the phase margin of the low dropout linear regulator compensation circuit meets the requirements.

[0076] When the low dropout linear regulator compensation circuit is in the heavy load state, the first load current ILOAD1 is equal to or greater than 1 A and less than 3 A. At this time, the first current Icomp1 decreases to 0. Since the equivalent resistance Rn2 of the second N-channel MOSFET MN2 increases as the first current Icomp1 decreases, the equivalent resistance Rn2 of the second N-channel MOSFET MN2 is relatively large at this time and can also be ignored. The first output impedance REA1 of the first error amplifier 100 can be approximated as REA1≈Rn1. If a first N-channel MOSFET MN1 with a larger size is used, the drain-source voltage Vgs1 of the first N-channel MOSFET MN1 is smaller. When the first load current ILOAD1 is larger, the current flowing through the first N-channel MOSFET MN1 is also larger, that is, the first output impedance REA1 decreases. At this time, the gain of the first loop will also decrease, so that the output voltage will decrease a lot under heavy load, that is, the load regulation rate of the low dropout linear regulator compensation circuit is very poor. Therefore, in this application, a first N-channel MOSFET MN1 with a smaller size can be used to ensure that the first output impedance REA1 is at a relatively large value under heavy load, so as to avoid reducing the gain of the first loop, so as to avoid excessive reduction of the output voltage under heavy load and ensure the load regulation rate of the low dropout linear regulator. It should be noted that those skilled in the art can select the size of the first N-channel MOSFET MN1 according to actual needs as long as the phase margin of the first loop meets the requirements under heavy load.

[0077] It can be understood that in the light load, medium load, and heavy load conditions of the low dropout linear regulator compensation circuit according to the embodiments of the present application, the first error amplifier 100 has different first output impedances, thereby changing the secondary poles of the first error amplifier 100 to enable the phase margin of the low dropout linear regulator compensation circuit to meet the requirements. When in the light load condition, the first output impedance of the first error amplifier 100 is reduced by the action of the first current Icomp1. When in the medium load condition, as the first load current ILOAD1 increases, the first current Icomp1 gradually decreases, so that the effect of the first current Icomp1 on reducing the first output impedance gradually decreases. When in the heavy load condition, the first load current ILOAD1 is greater than or equal to 1 A and the second current Icomp2 is 0, to avoid the reduction of the gain of the low dropout linear regulator compensation circuit due to too low first output impedance, thereby improving the load regulation rate of the output voltage of the low dropout linear regulator compensation circuit.

[0078] It should be noted that those skilled in the art can set the values of N1, N2, N3, and IBIAS1 according to actual needs, and the present application does not make any limitations in this regard.

[0079] When the low dropout linear regulator compensation circuit according to the embodiments of the present application is performing sink current, let the first power supply VCC = 3.3 V, the second power supply VLDOIN = 1.2 V, the reference voltage VREF = 0.6 V, the load capacitance CL = 30 uF, and the second load current ILOAD2 is from 0 to 3 A. Those skilled in the art can understand that when the first load current of the low dropout linear regulator compensation circuit is 0, it is in the no-load state. When the second load current of the low dropout linear regulator compensation circuit is greater than 0 and less than 100 mA, it is in the light load state. When the second load current is greater than or equal to 100 mA and less than 1 A, it is in the medium load state. When the second load current is greater than or equal to 1 A and less than 3 A, it is in the heavy load state.

[0080] The size ratio of the ninth N-channel MOSFET LS to the tenth N-channel MOSFET LS_Sns is N4:1. Since the second load current ILOAD2 flows through the ninth N-channel MOSFET LS, the second load current ILOAD2 flowing through the ninth N-channel MOSFET LS can be sampled proportionally through the fifth operational amplifier AMP3, the fifteenth N-channel MOSFET MN11, the seventh P-channel MOSFET MP7, and the eighth P-channel MOSFET MP8. The size ratio of the seventh P-channel MOSFET MP7 to the eighth P-channel MOSFET MP8 is N6:1, so that the second sampled current Isns3 = Ipower / N4 can be obtained, that is, the current flowing through the fifteenth N-channel MOSFET MN11 and the seventh P-channel MOSFET MP7 is Isns3, and the current flowing through the eighth P-channel MOSFET MP8 is Isns4 = Isns3 / N6 = ILOAD2 / (N4×N6). The second current source A2 outputs a second bias current IBIAS2, and the current difference between the second bias current IBIAS2 and Isns4 is sampled through the eighteenth N-channel MOSFET MN14. The sixteenth N-channel MOSFET MN12 and the seventeenth N-channel MOSFET MN13 form a current mirror with a size ratio of 1:1, the eighteenth N-channel MOSFET MN14 and the nineteenth N-channel MOSFET MN15 form a current mirror with a size ratio of 1:1, and the ninth P-channel MOSFET MP9 and the tenth P-channel MOSFET MP10 form a current mirror with a size ratio of 1:1, so that the second current generated by the second current generation circuit 500 is:

[0081] Icomp2 = IBIAS2 - Isns4 = IBIAS2 - [ILOAD2 / (N4×N6)]. Then, as the second load current ILOAD2 increases, the second current Icomp2 gradually decreases. Let the second bias current IBIAS2 output by the second current source A2 be 2 μA, and N4×N6 = 500000. Then, when the low dropout linear regulator compensation circuit is in the heavy load state, that is, the second load current ILOAD2 is greater than or equal to 1 A, the second current Icomp2 decreases to 0. At this time, the current mirrors composed of the eighteenth N-channel MOSFET MN14 and the nineteenth N-channel MOSFET MN15, the current mirrors composed of the ninth P-channel MOSFET MP9 and the tenth P-channel MOSFET MP10, and the current mirrors composed of the seventh N-channel MOSFET MN5 and the eighth N-channel MOSFET MN6 are all turned off. By using the method of turning off multiple current mirrors, the gain of the turn-off loop is relatively low, so that the output voltage will not change suddenly when the current mirror is turned off, and the linearity of the output voltage is improved.

[0082] The equivalent resistance of the sixth N-channel MOSFET MN4 is Rn4, and the transconductance of the sixth N-channel MOSFET MN4 is gmn4. Rn4 and gmn4 are reciprocals of each other; the equivalent resistance of the seventh N-channel MOSFET MN5 is Rn5, and the drain-source conductance of the seventh N-channel MOSFET MN5 is gdsn5. Rn5 and gdsn5 are reciprocals of each other; the equivalent resistance of the fourth P-channel MOSFET MP4 is Rp4, and the drain-source conductance of the fourth P-channel MOSFET MP4 is gdsp4. Rp4 and gdsp4 are reciprocals of each other. Then, the second output impedance REA2 of the first error amplifier 100 = [Rn4 / / (Rn5 + R2)] / / Rp4. Since the drain of the seventh N-channel MOSFET MN5 is connected to the fourth resistor R2, the drain-source conductance gdsn5 of the seventh N-channel MOSFET MN5 increases, causing the equivalent resistance Rn5 of the seventh N-channel MOSFET MN5 to decrease. Due to the presence of the fourth resistor R2, the equivalent resistance Rn5 of the seventh N-channel MOSFET MN5 increases as the current flowing through the seventh N-channel MOSFET MN5 decreases, that is, the equivalent resistance Rn5 of the seventh N-channel MOSFET MN5 increases as the second current Icomp2 decreases. When the low-dropout linear regulator compensation circuit is in the no-load state, that is, when the second load current ILOAD2 is 0, the second current Icomp2 is the largest, and the equivalent resistance Rn5 of the seventh N-channel MOSFET MN5 is the smallest.

[0083] The main pole of the first error amplifier 100 obtained from the transfer function is P0 = 1 / [2×π×(Ro / / RL)×CL], and the secondary pole is P1 = 1 / [2×π×REA2×CEA2], where CEA2 is the second output capacitance of the first error amplifier 100, and Ro at this time is the output resistance when the low-dropout linear regulator compensation circuit sinks current. It can be understood that to achieve stability compensation of the low-dropout linear regulator compensation circuit, it is necessary to make the secondary pole far from the main pole, and the secondary pole is determined by the second output impedance of the first error amplifier 100 and the second output capacitance of the first error amplifier 100. In the embodiment of the present application, the position of the secondary pole P1 is changed by adjusting the second output impedance of the first error amplifier 100.

[0084] Since the drain-source conductance gdsp4 of the fourth P-channel MOSFET MP4 is small, that is, the equivalent resistance Rp4 of the fourth P-channel MOSFET MP4 is large and can be ignored, the second output impedance REA2 of the first error amplifier 100 can be approximated as REA2≈Rn4 / / (Rn5 + R2).

[0085] When the low dropout linear regulator compensation circuit is in the light load state, the second load current ILOAD2 is greater than 0 and less than 100 mA. The current flowing through the sixth N-channel MOSFET MN4 is close to 0 and can be ignored. The size ratio of the seventh N-channel MOSFET MN5 to the eighth N-channel MOSFET MN6 is N5:1. Therefore, the current flowing through the seventh N-channel MOSFET MN5 is N5×Icomp2. Since the current flowing through the sixth N-channel MOSFET MN4 is close to 0, the transconductance gmn4 of the sixth N-channel MOSFET MN4 approaches 0, that is, the equivalent resistance Rn4 of the sixth N-channel MOSFET MN4 approaches infinity. Then, the second output impedance REA2 of the first error amplifier 100 can be approximated as REA2≈Rn5+R2. At this time, the second output impedance REA2 of the first error amplifier 100 is small, and the position of the second pole of the first error amplifier 100 is far from the position of the main pole. As the second load current ILOAD2 increases from 0 to nearly 100 mA, REA2 gradually increases, and the position of the second pole approaches the main pole as the load current increases. During this process, the phase margin of the low dropout linear regulator compensation circuit meets the stability requirements.

[0086] When the low dropout linear regulator compensation circuit is in the medium load state, the second load current ILOAD2 is equal to or greater than 100 mA and less than 1 A. As the second load current ILOAD2 increases, the current flowing through the sixth N-channel MOSFET MN4 gradually increases. Since the second current Icomp2 gradually decreases, the current flowing through the seventh N-channel MOSFET MN5 gradually decreases. At this time, the second output impedance REA2 of the first error amplifier 100 can be approximated as REA2≈Rn4 / / (Rn5+R2). Then, the position of the second pole of the first error amplifier 100 can be changed by changing the resistance value of the fourth resistor R2. At the same time, the existence of the fourth resistor R2 also introduces a zero point, and the position of this zero point is close to the position of the second pole, making the phase margin of the low dropout linear regulator compensation circuit meet the requirements.

[0087] When the low dropout linear regulator compensation circuit is in the heavy load state, the second load current ILOAD2 is equal to or greater than 1 A and less than 3 A. At this time, the second current Icomp2 decreases to 0. Since the equivalent resistance Rn5 of the seventh N-channel MOSFET MN5 increases as the second current Icomp2 decreases, the equivalent resistance Rn5 of the seventh N-channel MOSFET MN5 is relatively large at this time and can be ignored. The second output impedance REA2 of the first error amplifier 100 can be approximated as REA2≈Rn4. If a relatively large-sized sixth N-channel MOSFET MN4 is used, the drain-source voltage Vgs4 of the sixth N-channel MOSFET MN4 is small. When the second load current ILOAD2 is large, the current flowing through the sixth N-channel MOSFET MN4 is also large, that is, the second output impedance REA2 decreases, and the gain of the second loop will also decrease at this time, resulting in a large increase in the output voltage of the low dropout linear regulator compensation circuit during heavy load, that is, the load regulation rate of the low dropout linear regulator compensation circuit is very poor. Therefore, in this application, a relatively small-sized sixth N-channel MOSFET MN4 can be used to ensure that the second output impedance REA2 is at a relatively large value during heavy load, avoiding a decrease in the gain of the second loop, so as to avoid excessive increase in the output voltage during heavy load and ensure the load regulation rate of the low dropout linear regulator compensation circuit. It should be noted that those skilled in the art can select the size of the sixth N-channel MOSFET MN4 according to actual needs as long as the phase margin of the second loop meets the requirements during heavy load.

[0088] It can be understood that the low dropout linear regulator compensation circuit according to the embodiments of this application has different second output impedances of the first error amplifier 100 during light load, medium load, and heavy load, so as to change the secondary pole of the first error amplifier 100 to meet the requirements of the phase margin of the low dropout linear regulator compensation circuit. During light load, the second output impedance of the first error amplifier 100 is reduced by the action of the second current Icomp2. During medium load, as the second load current ILOAD2 increases, the second current Icomp2 gradually decreases, so that the effect of the second current Icomp2 on reducing the second output impedance gradually decreases. During heavy load, the second load current ILOAD2 is greater than or equal to 1 A and the second current Icomp2 is 0, avoiding a decrease in the gain of the low dropout linear regulator compensation circuit due to too low second output impedance, thereby improving the load regulation rate of the output voltage of the low dropout linear regulator compensation circuit.

[0089] It should be noted that those skilled in the art can set the values of N4, N5, N6, and IBIAS2 according to actual needs, and this application does not make any limitations in this regard.

[0090] In addition, an embodiment of the second aspect of the present application provides a low dropout linear regulator, including the low dropout linear regulator compensation circuit according to any embodiment of the present application.

[0091] The embodiments of the present application have been described in detail above in conjunction with the accompanying drawings. However, the present application is not limited to the above embodiments. Within the knowledge scope of those of ordinary skill in the art, various changes can be made without departing from the purpose of the present application.

Claims

1. A low dropout linear regulator compensation circuit, characterized in that, Comprising: A first error amplifier, wherein a first input terminal of the first error amplifier is used to connect to a reference voltage, a second input terminal of the first error amplifier is connected to an output terminal of the low dropout linear regulator compensation circuit, and the first error amplifier is used to adjust the output voltage of the low dropout linear regulator compensation circuit according to the reference voltage and the output voltage of the low dropout linear regulator compensation circuit; A first loop, wherein the first loop is used for pulling current; the first loop includes a first current generating circuit and a first compensation circuit, a first output terminal of the first error amplifier is connected to the first current generating circuit through the first compensation circuit, the first current generating circuit is used to generate a first current acting on the first compensation circuit, and the first compensation circuit is used to adjust a first output impedance of the first error amplifier through the first current; A second loop, wherein the second loop is used for sinking current; the second loop includes a second current generating circuit and a second compensation circuit, a second output terminal of the first error amplifier is connected to the second current generating circuit through the second compensation circuit, the second current generating circuit is used to generate a second current acting on the second compensation circuit, and the second compensation circuit is used to adjust a second output impedance of the first error amplifier through the second current; The first error amplifier includes a first operational amplifier, a first P-channel field effect transistor, a second P-channel field effect transistor, a third P-channel field effect transistor, and a fourth P-channel field effect transistor; A non-inverting input terminal of the first operational amplifier serves as the first input terminal of the first error amplifier and is used to connect to a reference voltage, an inverting input terminal of the first operational amplifier serves as the second input terminal of the first error amplifier and is connected to an output terminal of the low dropout linear regulator compensation circuit, a first output terminal of the first operational amplifier is connected to a drain of the first P-channel field effect transistor, and a second output terminal of the first operational amplifier is connected to a drain of the third P-channel field effect transistor; A gate of the first P-channel field effect transistor is connected to a gate of the second P-channel field effect transistor, and the gate of the first P-channel field effect transistor is connected to a drain of the first P-channel field effect transistor; A gate of the third P-channel field effect transistor is connected to a gate of the fourth P-channel field effect transistor, a drain of the third P-channel field effect transistor is connected to a gate of the third P-channel field effect transistor, a drain of the fourth P-channel field effect transistor serves as the second output terminal of the first error amplifier and is connected to the second compensation circuit, and a drain of the second P-channel field effect transistor serves as the first output terminal of the first error amplifier and is connected to the first compensation circuit; Sources of the first P-channel field effect transistor, the second P-channel field effect transistor, the third P-channel field effect transistor, and the fourth P-channel field effect transistor are all used to connect to a first power supply; The first compensation circuit includes a first resistor, a first N-channel field effect transistor, a second N-channel field effect transistor, and a third N-channel field effect transistor; The drain of the first N-channel field effect transistor is respectively connected to the drain of the second P-channel field effect transistor and one end of the first current generation circuit. The drain of the second N-channel field effect transistor is connected to the drain of the second P-channel field effect transistor and one end of the first current generation circuit through the first resistor. The sources of the first N-channel field effect transistor, the second N-channel field effect transistor, and the third N-channel field effect transistor are all connected to the output end of the low dropout linear regulator compensation circuit. The gate of the first N-channel field effect transistor is connected to the drain of the first N-channel field effect transistor. The gate of the second N-channel field effect transistor is connected to the gate of the third N-channel field effect transistor. The gate of the third N-channel field effect transistor is connected to the drain of the third N-channel field effect transistor. The drain of the third N-channel field effect transistor is connected to the other end of the first current generation circuit.

2. The low dropout linear regulator compensation circuit according to claim 1, wherein The first current generation circuit includes a second resistor, a third resistor, a fourth N-channel field effect transistor, a fifth N-channel field effect transistor, and a second operational amplifier. The gate of the fourth N-channel field effect transistor is connected to the drain of the first N-channel field effect transistor. The gate of the fourth N-channel field effect transistor is connected to the drain of the second N-channel field effect transistor through the first resistor. The drain of the fourth N-channel field effect transistor is used to connect to the second power supply. The source of the fourth N-channel field effect transistor is connected to the output end of the low dropout linear regulator compensation circuit. The gate of the fifth N-channel field effect transistor (HS_Sns) is connected to the gate of the fourth N-channel field effect transistor. The drain of the fifth N-channel field effect transistor is connected to the inverting input terminal of the second operational amplifier. The drain of the fifth N-channel field effect transistor is used to connect to the second power supply through the second resistor. The non-inverting input terminal of the second operational amplifier is used to connect to the second power supply through the third resistor (Rs2). The output terminal of the second operational amplifier is connected to the drain of the third N-channel field effect transistor.

3. The low dropout linear regulator compensation circuit according to claim 1, wherein The second compensation circuit includes a sixth N-channel field effect transistor, a seventh N-channel field effect transistor, an eighth N-channel field effect transistor, and a fourth resistor. The drain of the sixth N-channel field effect transistor is connected to the second output terminal of the first error amplifier. The drain of the seventh N-channel field effect transistor is connected to the gate of the sixth N-channel field effect transistor and one end of the second current generation circuit through the fourth resistor. The gate of the sixth N-channel field effect transistor is connected to the drain of the sixth N-channel field effect transistor. The gate of the seventh N-channel field effect transistor is connected to the gate of the eighth N-channel field effect transistor. The drain of the eighth N-channel field effect transistor is connected to the other end of the second current generation circuit and the gate of the eighth N-channel field effect transistor. The sources of the sixth N-channel field effect transistor, the seventh N-channel field effect transistor, and the eighth N-channel field effect transistor are all grounded.

4. The low dropout linear regulator compensation circuit according to claim 3, wherein The second current generating circuit includes a ninth N-channel field effect transistor, a tenth N-channel field effect transistor, and a third operational amplifier. The drain of the ninth N-channel field effect transistor is connected to the output terminal of the low dropout linear regulator compensation circuit. The source of the ninth N-channel field effect transistor is grounded. The gate of the ninth N-channel field effect transistor is connected to the gate of the tenth N-channel field effect transistor. The gate of the ninth N-channel field effect transistor is connected to the drain of the seventh N-channel field effect transistor through the fourth resistor. The source of the tenth N-channel field effect transistor is grounded. The drain of the tenth N-channel field effect transistor is connected to the inverting input terminal of the third operational amplifier. The non-inverting input terminal of the third operational amplifier is connected to the output terminal of the low dropout linear regulator compensation circuit. The output terminal of the third operational amplifier is connected to the drain of the eighth N-channel field effect transistor.

5. The low dropout linear regulator compensation circuit according to claim 2, wherein The second operational amplifier includes a fourth operational amplifier, an eleventh N-channel field effect transistor, a twelfth N-channel field effect transistor, a thirteenth N-channel field effect transistor, a fourteenth N-channel field effect transistor, a fifth P-channel field effect transistor, a sixth P-channel field effect transistor, and a first current source; The non-inverting input terminal of the fourth operational amplifier serves as the non-inverting input terminal of the second operational amplifier. The inverting input terminal of the fourth operational amplifier serves as the inverting input terminal of the second operational amplifier. The non-inverting input terminal of the fourth operational amplifier is further connected to the drain of the eleventh N-channel field effect transistor. The output terminal of the fourth operational amplifier is connected to the gate of the eleventh N-channel field effect transistor. The gate of the eleventh N-channel field effect transistor is connected to the gate of the twelfth N-channel field effect transistor; The gate of the thirteenth N-channel field effect transistor is connected to its drain. The gate of the thirteenth N-channel field effect transistor is connected to the gate of the fourteenth N-channel field effect transistor. The drain of the fourteenth N-channel field effect transistor is connected to the drain of the fifth P-channel field effect transistor. The drain of the fifth P-channel field effect transistor is connected to its gate. The gate of the fifth P-channel field effect transistor is connected to the gate of the sixth P-channel field effect transistor. The drain of the sixth P-channel field effect transistor serves as the output terminal of the second operational amplifier; The output terminal of the first current source is respectively connected to the drains of the twelfth N-channel field effect transistor and the thirteenth N-channel field effect transistor. The output terminal of the first current source is further connected between the gates of the thirteenth N-channel field effect transistor and the fourteenth N-channel field effect transistor; The input terminal of the first current source, the sources of the fifth P-channel field effect transistor and the sixth P-channel field effect transistor are all used to connect to the first power supply; The sources of the eleventh N-channel field effect transistor, the twelfth N-channel field effect transistor, the thirteenth N-channel field effect transistor, and the fourteenth N-channel field effect transistor are all grounded.

6. The low dropout linear regulator compensation circuit according to claim 4, characterized in that, The third operational amplifier includes a fifth operational amplifier, a seventh P-channel field effect transistor, an eighth P-channel field effect transistor, a ninth P-channel field effect transistor, a tenth P-channel field effect transistor, a fifteenth N-channel field effect transistor, a sixteenth N-channel field effect transistor, a seventeenth N-channel field effect transistor, an eighteenth N-channel field effect transistor, a nineteenth N-channel field effect transistor, and a second current source; The non-inverting input terminal of the fifth operational amplifier serves as the inverting input terminal of the third operational amplifier, the inverting input terminal of the fifth operational amplifier serves as the non-inverting input terminal of the third operational amplifier, the non-inverting input terminal of the fifth operational amplifier is connected to the source electrode of the fifteenth N-channel field effect transistor, the output terminal of the fifth operational amplifier is connected to the gate electrode of the fifteenth N-channel field effect transistor, and the drain electrode of the fifteenth N-channel field effect transistor is connected to the drain electrode of the seventh P-channel field effect transistor, the gate electrode of the seventh P-channel field effect transistor, and the gate electrode of the eighth P-channel field effect transistor; The drain electrode of the seventeenth N-channel field effect transistor is connected to the output terminal of the second current source; The source electrodes of the seventh P-channel field effect transistor, the eighth P-channel field effect transistor, the ninth P-channel field effect transistor, the tenth P-channel field effect transistor, and the input terminal of the second current source are all connected to the first power supply; The gate electrode of the sixteenth N-channel field effect transistor is connected to the drain electrode of the sixteenth N-channel field effect transistor, the drain electrode of the eighth P-channel field effect transistor, and the gate electrode of the seventeenth N-channel field effect transistor. The drain electrode of the seventeenth N-channel field effect transistor is connected to the drain electrode of the eighteenth N-channel field effect transistor, the gate electrode of the eighteenth N-channel field effect transistor, and the gate electrode of the nineteenth N-channel field effect transistor. The drain electrode of the nineteenth N-channel field effect transistor is connected to the drain electrode of the ninth P-channel field effect transistor, the gate electrode of the ninth P-channel field effect transistor, and the gate electrode of the tenth P-channel field effect transistor. The drain electrode of the tenth P-channel field effect transistor serves as the output terminal of the third operational amplifier; The source electrodes of the sixteenth N-channel field effect transistor, the seventeenth N-channel field effect transistor, the eighteenth N-channel field effect transistor, and the nineteenth N-channel field effect transistor are all grounded.

7. The low dropout linear regulator compensation circuit according to any one of claims 1 to 6, characterized in that It further includes a load circuit. The load circuit includes a load capacitor and a load resistor. The load capacitor and the load resistor are connected in parallel. One end of the load resistor is connected to the output terminal of the low dropout linear regulator compensation circuit, and the other end is grounded.

8. A low dropout linear regulator, characterized in that, It includes the low dropout linear regulator compensation circuit according to any one of claims 1 to 7.

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