Semiconductor element and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor element and a method for preparing the semiconductor element. The semiconductor element has a substrate and a transistor, the substrate has a first region, and the first transistor is located in the first region. The first transistor has a first lower gate structure, a first channel layer, a first upper gate structure, and two first source / drain regions, the first lower gate structure is located on the substrate, the first channel layer is located on the first lower gate structure, the first upper gate structure is located on the first channel layer, and the two first source / drain regions are located on both sides of the first channel layer.

Description

[0001] The present invention claims priority to and the benefit of U.S. regular application No. 16 / 820,273, filed on March 16, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element and a method for preparing the semiconductor element, and more particularly to a semiconductor element having a channel layer and a method for preparing the semiconductor element having the channel layer, wherein the channel layer is controlled by a plurality of gate structures. Background Art

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor components is gradually reduced to meet the increasing demand for computing power. However, during the process of size reduction, different problems are added, and such problems continue to increase in number and complexity. Therefore, there is still a constant challenge to achieve improved quality, yield, performance and reliability, as well as reduced complexity.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] The purpose of the present disclosure is to provide a semiconductor element and a method for manufacturing the same to solve at least one of the above problems.

[0006] An embodiment of the present disclosure provides a semiconductor element, comprising a substrate, including a first region; and a first transistor, located in the first region. The first transistor comprises a first lower gate structure, a first channel layer, a first upper gate structure, and two first source / drain regions, wherein the first lower gate structure is located on the substrate, the first channel layer is located on the first lower gate structure, the first upper gate structure is located on the first channel layer, and the two first source / drain regions are located on both sides of the first channel layer.

[0007] In some embodiments of the present disclosure, the first lower gate structure includes a first lower gate electrode, two first lower gate spacers and a first lower gate dielectric, the first lower gate electrode is located on the substrate, the two first lower gate spacers are located on both sides of the first lower gate electrode, and the first lower gate dielectric is located between the first lower gate electrode and the first channel layer.

[0008] In some embodiments of the present disclosure, the first upper gate structure includes a first upper gate dielectric, a first lower work function layer and a first filling layer, the first upper gate dielectric is located on the first channel layer, the first lower work function layer is located on the first upper gate dielectric, and the first filling layer is located on the first lower work function layer.

[0009] In some embodiments of the present disclosure, the first lower work function layer has a thickness between about arrive between.

[0010] In some embodiments of the present disclosure, the semiconductor device further includes a first upper work function layer located between the first lower work function layer and the first filling layer.

[0011] In some embodiments of the present disclosure, the first upper work function layer has a thickness between about to approximately between.

[0012] In some embodiments of the present disclosure, the semiconductor device further includes two first upper gate spacers located on both sides of the first upper gate dielectric.

[0013] In some embodiments of the present disclosure, the semiconductor device further includes two first contact points located on the two first source / drain regions.

[0014] In some embodiments of the present disclosure, the semiconductor device further includes two first conductive layers located between the two first contact points and the two first source / drain regions.

[0015] In some embodiments of the present disclosure, each first conductive layer has a thickness ranging from about 2 nm to about 20 nm.

[0016] In some embodiments of the present disclosure, the semiconductor device further includes a first lower isolation layer located below the first lower gate structure.

[0017] In some embodiments of the present disclosure, the semiconductor device further includes a first channel separation layer located below the first lower isolation layer, wherein the first channel separation layer is doped with phosphorus, arsenic, antimony or boron.

[0018] In some embodiments of the present disclosure, the semiconductor device further includes a first buffer layer located below the first lower isolation layer, wherein the first buffer layer has a lattice constant different from a lattice constant of the substrate.

[0019] In some embodiments of the present disclosure, the semiconductor device further includes a second transistor located in a second region of the substrate. The second transistor includes a second lower gate structure, a second channel layer, and a second upper gate structure, wherein the second lower gate structure is located on the substrate, the second channel layer is located on the second lower gate structure, and the second upper gate structure is located on the second channel layer. The second channel layer and the first channel layer are located on the same vertical plane.

[0020] In some embodiments of the present disclosure, the second upper gate structure includes a second upper gate dielectric located on the second channel layer, and the second upper gate dielectric has a thickness that is less than a thickness of the first upper gate dielectric.

[0021] Another embodiment of the present disclosure provides a method for preparing a semiconductor element. The method includes: providing a substrate; forming a first lower gate structure on the substrate; forming a first channel layer on the first lower gate structure; forming a first upper gate structure on the first channel layer; and forming two first source / drain regions on both sides of the first channel layer.

[0022] In some embodiments of the present disclosure, the first channel layer is made of the following materials: silicon, germanium, silicon germanium, indium gallium arsenide, indium arsenide, gallium antimonide, indium antimonide or a combination thereof.

[0023] In some embodiments of the present disclosure, the step of forming the first lower gate structure includes: forming a layer of first semiconductor material, a layer of first isolation material, and a layer of second semiconductor material on the substrate; forming a first dummy structure on the layer of second semiconductor material; performing an etching process to form a plurality of recesses, and transforming the layer of first isolation material into a first lower gate dielectric and the layer of second semiconductor material into the first channel layer; performing a lateral etching process to form a plurality of lateral recesses, and transforming the layer of first semiconductor material into the first lower gate electrode; and forming two first lower gate spacers in the plurality of lateral recesses. The first lower gate electrode, the two first lower gate spacers, and the first lower gate dielectric together form the first lower gate structure.

[0024] In some embodiments of the present disclosure, the two first lower gate spacers are made of the following materials: silicon oxide, silicon nitride, silicon oxynitride or silicon nitride oxide.

[0025] In some embodiments of the present disclosure, the two first lower gate spacers have a porosity ranging from about 10% to about 100%.

[0026] Due to the design of the semiconductor device disclosed in the present invention, the conductive state of the first channel layer can be controlled by the first lower gate structure and the first upper gate structure at the same time. As a result, the leakage current in the first channel layer can be reduced. In addition, the first upper gate dielectric and the second upper gate dielectric having different thicknesses can have different threshold voltages and can provide different functions; therefore, the applicability of the semiconductor device can be increased.

[0027] The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] A more complete understanding of the disclosure of the present invention may be obtained by referring to the detailed description and claims in conjunction with the accompanying drawings, in which like reference numerals refer to like elements.

[0029] Figure 1 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0030] Figure 2 Based on Figure 1 An enlarged cross-sectional schematic diagram of the semiconductor element.

[0031] Figures 3 to 5 FIG. 4 is a schematic cross-sectional view of each semiconductor element according to an embodiment of the present disclosure.

[0032] Figure 6 Based on Figure 5 An enlarged cross-sectional schematic diagram of the semiconductor element.

[0033] Figure 7 It is an enlarged cross-sectional schematic diagram of a semiconductor element according to an embodiment of the present disclosure.

[0034] Figure 8 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0035] Fig. 9The figure is a schematic diagram of a process of manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0036] Figures 10 to 26 It is a cross-sectional schematic diagram of a process of a method for preparing the semiconductor device according to an embodiment of the present disclosure.

[0037] The reference numerals are as follows:

[0038] 10A:Semiconductor components

[0039] 10B: Semiconductor components

[0040] 10C: Semiconductor components

[0041] 10D: Semiconductor components

[0042] 10E: Semiconductor components

[0043] 10F: Semiconductor components

[0044] 101: Base

[0045] 103: District 1

[0046] 105: District 2

[0047] 107: Insulation structure

[0048] 109: First isolation layer

[0049] 201: first transistor

[0050] 203: first lower gate structure

[0051] 205: first lower gate electrode

[0052] 207: first lower gate spacer

[0053] 209: first lower gate dielectric

[0054] 211: First channel layer

[0055] 213: first upper gate structure

[0056] 215: first upper gate dielectric

[0057] 215-1: First Sublevel

[0058] 215-3: First intermediate sublayer

[0059] 215-5: First upper sublayer

[0060] 217: first lower work function layer

[0061] 219: first upper work function layer

[0062] 221: First filling layer

[0063] 223: first upper gate spacer

[0064] 225: first source / drain region

[0065] 227: First point of contact

[0066] 229: first conductive layer

[0067] 231: First channel separation layer

[0068] 233: first lower isolation layer

[0069] 235: First buffer layer

[0070] 237: First interface layer

[0071] 239: First dipole layer

[0072] 241: First functional layer

[0073] 243: First adjustment layer

[0074] 245: First protective layer

[0075] 247: first encapsulation layer

[0076] 249: First cover layer

[0077] 301: second transistor

[0078] 303: Second lower gate structure

[0079] 305: second lower gate electrode

[0080] 307: Second lower gate spacer

[0081] 309: Second lower gate dielectric

[0082] 311: Second channel layer

[0083] 313: Second upper gate structure

[0084] 315: Second upper gate dielectric

[0085] 315-1: Second lower layer

[0086] 315-3: Second intermediate sublayer

[0087] 315-5: Second upper sublayer

[0088] 317: Second lower work function layer

[0089] 321: Second filling layer

[0090] 323: Second upper gate spacer

[0091] 325: second source / drain region

[0092] 327: Second contact point

[0093] 329: second conductive layer

[0094] 331: Second channel separation layer

[0095] 333: Second lower isolation layer

[0096] 335: Second buffer layer

[0097] 343: Second adjustment layer

[0098] 349: Second cover layer

[0099] 401: First semiconductor material

[0100] 403: First isolation material

[0101] 405: Second semiconductor material

[0102] 407: Third isolation material

[0103] 409: Fourth isolation material

[0104] 411: Fifth isolation material

[0105] 413: Low work function materials

[0106] 415: Upper work function material

[0107] 417: Filling material

[0108] 501: First virtual structure

[0109] 503: First lower virtual layer

[0110] 505: First intermediate virtual layer

[0111] 507: First upper virtual layer

[0112] 601: Second virtual structure

[0113] 603: Second lower virtual layer

[0114] 605: Second intermediate virtual layer

[0115] 607: Second upper virtual layer

[0116] 701: Depression

[0117] 703: Lateral depression

[0118] 705: first groove

[0119] 707: Second groove

[0120] 709: Contact opening

[0121] 801: first mask layer

[0122] 803: Second mask layer

[0123] 805: Second isolation layer

[0124] Z: Direction

[0125] 20: Methods

[0126] S11: Steps

[0127] S13: Steps

[0128] S15: Steps

[0129] S17: Steps

[0130] S19: Steps

[0131] S21: Steps

[0132] S23: Steps

[0133] S25: Steps

[0134] S27: Steps

[0135] S29: Steps

[0136] S31: Steps DETAILED DESCRIPTION

[0137] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0138] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0139] It should be understood that when forming a component on, connected to and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0140] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0141] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variances that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar, is exactly the same, equal, or planar, or it may be the same, equal, or planar within an acceptable variance, and for example, the acceptable variance may occur due to the manufacturing process.

[0142] It should be understood that the term "about" modifies a quantity of an ingredient, component, or reactant of the present disclosure, which is a variation in the numerical quantity that may occur, for example, through typical measurements and liquid handling procedures, and the liquid handling procedures are used to make concentrates or solutions. Furthermore, the occurrence of variation may arise from inadvertent errors in the measurement procedures used to make the compositions or implement multiple methods or the like, differences in manufacturing, sources, or purity of the ingredients. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0143] In the present disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of semiconductor devices.

[0144] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the relative direction of the Z-direction arrow.

[0145] It should be understood that in the description of the present disclosure, a surface of an element (or a feature) located at the highest vertical height (level) along the direction Z is an upper surface of the element (or the feature). A surface of an element (or a feature) located at the lowest vertical height (level) along the direction Z is a lower surface of the element (or the feature).

[0146] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device 10A according to an embodiment of the present disclosure. Figure 2 Based on Figure 1 FIG. 1 is an enlarged cross-sectional schematic diagram of the semiconductor element 10A.

[0147] Please refer to Figure 1 The semiconductor device 10A may include a substrate 101 , a plurality of insulating structures 107 , a first isolation layer 109 , a first transistor 201 , and a second transistor 301 .

[0148] Please refer to Figure 1 and Figure 2, the substrate 101 may include a first region 103 and a second region 105. The first region 103 and the second region 105 may be disposed adjacent to each other. In some embodiments, the first region 103 and the second region 105 may be disposed separately from each other. For example, the substrate 101 may be made of the following materials: silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenic, indium arsenic, indium phosphorus, or other IV-IV, III-V, or II-VI semiconductor materials. The substrate 101 may have a first lattice constant. In some examples, the substrate 101 may include an organic semiconductor or a layered semiconductor, such as silicon / silicon germanium, silicon-on-insulator, or silicon germanium-on-insulator.

[0149] It should be understood that the first region 103 may include a portion of the substrate 101 and a space located on the portion of the substrate 101. When describing that an element is disposed on the first region 103, it means that the element is disposed on an upper surface of the portion of the substrate 101. In some embodiments, describing that an element is disposed in the first region 103 means that the element is disposed in the portion of the substrate 101; however, an upper surface of the element may be flush with the upper surface of the portion of the substrate 101. In some embodiments, describing that a part is disposed in the first region 103 means that some portions of the element are disposed in the substrate 101 and other portions of the element are disposed on or above the substrate 101.

[0150] Accordingly, the second region 105 may include other portions of the substrate 101 and a space on the other portions of the substrate 101 .

[0151] Please refer to Figure 1 and Figure 2, a plurality of insulating structures 107 may be disposed in the first region 103 and the second region 105. The upper surfaces of the plurality of insulating structures 107 may be located at a vertical plane that is higher than a vertical plane of the substrate 101. The plurality of insulating structures 107 disposed in the first region 103 may define a first active region. The plurality of insulating structures 107 disposed in the second region 105 may define a second active region. For example, the insulating structures 107 may be made of an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate.

[0152] It should be understood that in the present disclosure, silicon oxynitride represents a substance including silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide represents a substance including silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0153] Please refer to Figure 1 and Figure 2 , the first transistor 201 may be disposed in the first region 103, and the second transistor 301 may be disposed in the second region 105. In some embodiments, the first transistor 201 and the second transistor 301 may have the same threshold voltage. In some embodiments, the first transistor 201 and the second transistor 301 may have different threshold voltages. The first transistor 201 may have a first lower gate structure 203, a first channel layer 211, a first upper gate structure 213, two first source / drain regions 225, two first contacts 227, and two first conductive layers 229.

[0154] Please refer to Figure 1 and Figure 2 The first lower gate structure 203 may be disposed on the first region 103 and between an adjacent pair of insulating structures 107 disposed in the first region 103. The first lower gate structure 203 may have a first lower gate electrode 205, two first lower gate spacers 207, and a first lower gate dielectric 209.

[0155] Please refer to Figure 1 and Figure 2, the first lower gate electrode 205 may be disposed on the first region 103. For example, the first lower gate electrode 205 may be made of a conductive material, such as polycrystalline silicon, polycrystalline silicon germanium, or a combination thereof. In some embodiments, the first lower gate electrode 205 may be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. In some embodiments, for example, the first lower gate electrode 205 may be made of the following materials: tungsten, aluminum, titanium, copper, tantalum, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminide, titanium aluminum nitride, tantalum carbon nitride, tantalum carbide, tantalum silicon nitride, or a combination thereof.

[0156] Please refer to Figure 1 and Figure 2 , two first lower gate spacers 207 may be disposed on both sides of a lower gate electrode 205. In some embodiments, the interface between the first lower gate electrode 205 and the two first lower gate spacers 207 is curved ( Figure 1 In some embodiments, for example, the two first lower gate spacers 207 may be made of an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like.

[0157] In some embodiments, the two first lower gate spacers 207 may be made from an energy removable material and may have a porosity ranging from about 10% to about 100%. The two first lower gate spacers 207 may have a skeleton and a plurality of empty spaces, and the plurality of empty spaces are disposed between the skeletons. The plurality of empty spaces may be connected to each other and may be filled with air. For example, the skeleton may include silicon oxide, a low dielectric material, or methylsilsesquioxane. It should be understood that when the porosity is 100%, it means that the two first lower gate spacers 207 have only empty spaces, and the two first lower gate spacers 207 may be regarded as air gaps. In some embodiments, the porosity of the two first lower gate spacers 207 may be between 45% and 75%. The plurality of empty spaces of the two first lower gate spacers 207 may be filled with air. As a result, a dielectric constant of the two first lower gate spacers 207 may be significantly lower than a dielectric constant of a layer made of, for example, only silicon oxide. Therefore, as described below, the two first lower gate spacers 207 can greatly reduce the parasitic capacitance between the first lower gate electrode 205 and the two first source / drain regions 225. That is, the two first lower gate spacers 207 can greatly mitigate an interference effect between the electronic signals induced in the first transistor 201 or the electronic signals applied to the first transistor 201.

[0158] The energy removable material may include a material such as a thermally decomposable material, a photodecomposable material, an electron beam decomposable material, or a combination thereof. For example, the energy removable material has a base material and a decomposable porogen material that is substantially removed when exposed to an energy source.

[0159] In some embodiments, the energy removable material may include a relatively high concentration of decomposable porogen material and a relatively low concentration of base material, but is not limited thereto. For example, the energy removable material may include approximately 75% or more of the decomposable porogen material and approximately 25% or less of the base material. In another example, the energy removable material may include approximately 95% or more of the decomposable porogen material and approximately 5% or less of the base material. In another example, the energy removable material may include 100% of the decomposable porogen material without using the base material. In another example, the energy removable material may include approximately 45% or more of the decomposable porogen material and approximately 55% or less of the base material.

[0160] Please refer to Figure 1 and Figure 2, the first lower gate dielectric 209 may be disposed on the first lower gate electrode 205 and the two first lower gate spacers 207. In some embodiments, for example, the first lower gate dielectric 209 may be made of silicon oxide or the like. In some embodiments, the first lower gate dielectric 209 may be made of an isolation material having a dielectric constant of about 4.0 or greater.

[0161] Please refer to Figure 1 and Figure 2 , the first channel layer 211 may be disposed on the first lower gate dielectric 209. The first channel layer 211 may be made of a semiconductor material of Group IV, Group II-IV, or Group III-V. For example, the first channel layer 211 may include the following materials: silicon, germanium, silicon germanium, indium gallium arsenide, indium arsenide, gallium antimonide, indium antimonide, or a combination thereof.

[0162] Please refer to Figure 1 and Figure 2 The first upper gate structure 213 may be disposed on the first channel layer 211 . The first upper gate structure 213 may include a first upper gate dielectric 215 , a first lower work function layer 217 , a first upper work function layer 219 , a first filling layer 221 and two first upper gate spacers 223 .

[0163] Please refer to Figure 1 and Figure 2 In the embodiment described, the first upper gate dielectric 215 may be disposed on the first channel layer 211. The first upper gate dielectric 215 may have a first sublayer 215-1, a first intermediate sublayer 215-3, and a first upper sublayer 215-5. The first sublayer 215-1 may be disposed on the first channel layer 211 and may have a U-shaped cross-sectional profile. Due to the U-shaped cross-sectional profile, corner effects may be avoided. The first sublayer 215-1 may have a thickness ranging from 0.1 nm to 3.0 nm. Preferably, the thickness of the first sublayer 215-1 is between 0.5 nm and 2.5 nm. In some embodiments, for example, the first sublayer 215-1 may be made of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. In some embodiments, the first sublayer 215-1 may be made of an isolation material, and the isolation material has a dielectric constant of about 4.0 or greater.

[0164] The isolation material having a dielectric constant of about 4.0 or greater may be the following materials: hafnium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, aluminum oxide, aluminum silicon oxide, titanium oxide, tantalum pentoxide, lanthanum oxide, lanthanum silicon oxide, strontium titanate, lanthanum aluminate, yttrium oxide, gallium (III) trioxide, gadolinium gallium oxide, lead zirconium titanate, titanate, barium titanate, barium strontium titanate, barium zirconate, or a combination thereof.

[0165] Please refer to Figure 1 and Figure 2 , the first intermediate sublayer 215-3 may be disposed on the first sublayer 215-1. The first intermediate sublayer 215-3 may have a U-shaped cross-sectional profile. The first intermediate sublayer 215-3 may have a thickness ranging from about 0.1 nm to about 2.0 nm. Preferably, the thickness of the first intermediate sublayer 215-3 may be between about 0.5 nm and 1.5 nm. In some embodiments, for example, the first intermediate sublayer 215-3 may be made of an isolation material, and the isolation material has a dielectric constant of about 4.0 or greater. In some embodiments, for example, the first intermediate sublayer 215-3 may be the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like.

[0166] Please refer to Figure 1 and Figure 2, the first upper sublayer 215-5 may be disposed on the first intermediate sublayer 215-3. The first upper sublayer 215-5 may have a U-shaped cross-sectional profile. The first upper sublayer 215-5 may have a thickness ranging from about 0.5 nm to 5.0 nm. Preferably, the thickness of the first upper sublayer 215-5 may be between about 0.5 nm and 2.5 nm. In some embodiments, for example, the first upper sublayer 215-5 may be made of an isolation material, and the isolation material has a dielectric constant of about 4.0 or greater. In some embodiments, for example, the first upper sublayer 215-5 may be made of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like.

[0167] Please refer to Figure 1 and Figure 2 , the first lower work function layer 217 may be disposed on the first upper gate dielectric 215. In particular, the first lower work function layer 217 may be disposed on the first upper sub-layer 215-5. The first lower work function layer 217 may have a U-shaped cross-sectional profile. The first lower work function layer 217 may have a thickness between about to approximately Preferably, the thickness of the first lower work function layer 217 may be between about arrive For example, the first lower work function layer 217 can be made of the following materials: aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbidealuminum, titanium nitride aluminum, titanium siliconaluminum, tantalum nitride, tantalum carbide, tantalum silicon nitride, manganese, zirconium or tungsten nitride.

[0168] Please refer to Figure 1 and Figure 2 The first upper work function layer 219 may be disposed on the first lower work function layer 217. The first upper work function layer 219 may have a U-shaped cross-sectional profile. The first upper work function layer 219 may have a thickness between about arrive For example, the first upper work function layer 219 may be made of the following materials: titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride or ruthenium.

[0169] Please refer to Figure 1 and Figure 2, the first filling layer 221 may be disposed on the first upper work function layer 219. For example, the first filling layer 221 may be made of tungsten or aluminum.

[0170] Please refer to Figure 1 and Figure 2 , the two first upper gate spacers 223 may be respectively disposed on both sides of the first upper gate dielectric 215. In particular, the two first upper gate spacers 223 may be respectively disposed on both sides of the first sublayer 215-1. For example, the two first upper gate spacers 223 may be made of the following materials: silicon oxide, silicon nitride or the like.

[0171] Please refer to Figure 1 and Figure 2 , two first source / drain regions 225 may be disposed on both sides of the first lower gate structure 203 and on both sides of the first channel layer 211. The upper portions of the two first source / drain regions 225 may protrude in the Z direction away from the substrate 101. The upper portions of the two first source / drain regions 225 may be disposed adjacent to the two first upper gate spacers 223. The lower portions of the two first source / drain regions 225 may be located at a vertical level, which is lower than the lower surfaces of the two first lower gate spacers 207. In some embodiments, the lower portions of the two first source / drain regions 225 may be located at a vertical level, between the vertical level of the lower surfaces of the two first lower gate spacers 207 and a vertical level of the upper surfaces of the two first lower gate spacers 207. The plurality of insulating structures 107 disposed in the first region 103 may be disposed adjacent to the two first source / drain regions 225, respectively.

[0172] For example, the two first source / drain regions 225 may be made of the following materials: silicon, germanium, silicon germanium, indium gallium arsenide or silicon carbide. The two first source / drain regions 225 may be doped with a dopant, such as phosphorus, arsenic, antimony or boron. The two first source / drain regions 225 may have a first electrical form. In some embodiments, the two first source / drain regions 225 may have a uniform doping concentration. In some embodiments, different planes of the two first source / drain regions 225 may have various different doping concentrations. For example, in some embodiments, the upper portions of the two first source / drain regions 225 may have a doping concentration greater than the doping concentration of other portions of the two first source / drain regions 225. In some other embodiments, the middle portions of the two first source / drain regions 225 may have a doping concentration greater than the doping concentration of other portions of the two first source / drain regions 225. In some embodiments, the two first source / drain regions 225 may be made of a material that is different from the material of the first channel layer 211. For example, the first channel layer 211 may be made of germanium, and the two first source / drain regions 225 may be made of doped silicon germanium. Accordingly, the first channel layer 211 may include a strained channel. As a result, the carrier mobility of the first transistor 201 may be improved.

[0173] Please refer to Figure 1 and Figure 2, the first isolation layer 109 may be disposed on the plurality of insulating structures 107, the first channel layer 211, and the two first source / drain regions 225. The first isolation layer 109 may be disposed around the first upper gate structure 213. For example, the first isolation layer 109 may be made of the following materials: silicon nitride, silicon oxide, silicon oxynitride, flowable oxide, tonn silazen, undoped silica glass, borosilica glass, phosphosilica glass, borophosphosilica glass, plasma-enhanced tetra-ethylorthosilicate, fluoride silicate glass, carbon doped silicon oxide, amorphous fluorinated carbon, organosilicate glass, or a combination thereof.

[0174] Please refer to Figure 1 and Figure 2 , two first contact points 227 may be provided to pass through the first isolation layer 109, and respectively provided on the two first source / drain regions 225. The two first contact points 227 may have a tapered cross-sectional profile. In some embodiments, a width of the two first contact points 227 may gradually widen from top to bottom along the Z direction. In some embodiments, the sides of the two first contact points 227 may have a consistent slope. For example, the two first contact points 227 may be made of a conductive material, such as doped polysilicon, a metal, or a metal nitride. The metal may be aluminum, copper, or cobalt.

[0175] Please refer to Figure 1 and Figure 2 The two first conductive layers 229 may be respectively disposed between the two first contact points 227 and the two first source / drain regions 225. Each first conductive layer 229 may have a thickness ranging from about 2 nm to about 20 nm. For example, the two first conductive layers 229 may be made of the following materials: titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0176] Please refer to Figure 1 and Figure 2 The second transistor 301 may have a structure similar to the structure of the first transistor 201, but is not limited thereto. The second transistor 301 may include a second lower gate structure 303, a second channel layer 311, a second upper gate structure 313, two second source / drain regions 325, two second contacts 327, and two second conductive layers 329.

[0177] Please refer to Figure 1 and Figure 2 The second lower gate structure 303 may be disposed on the second region 105 and between an adjacent pair of insulating structures 107 disposed in the second region 105. The second lower gate structure 303 may be located in the same vertical plane as the first lower gate structure 203. The second lower gate structure 303 may include a second lower gate electrode 305, two second lower gate spacers 307, and a second lower gate dielectric 309.

[0178] Please refer to Figure 1 and Figure 2 , the second lower gate electrode 305 may be disposed on the second region 105. The second lower gate electrode 305 may be made of the same material as the first lower gate electrode 205, but is not limited thereto. Two second lower gate spacers 307 may be disposed on both sides of the second lower gate electrode 305. The two second lower gate spacers 307 may be made of the same material as the two first lower gate spacers 207, but is not limited thereto. A second lower gate dielectric 309 may be disposed on the second lower gate electrode 305 and the two second lower gate spacers 307. The second lower gate dielectric 309 may be made of the same material as the first lower gate dielectric 209, but is not limited thereto.

[0179] Please refer to Figure 1 and Figure 2 , the second channel layer 311 may be disposed on the second lower gate dielectric 309. The second channel layer 311 may be located on the same vertical plane as the first channel layer 211. The second channel layer 311 may be made of the same material as the second lower gate dielectric 309, but is not limited thereto.

[0180] Please refer to Figure 1 and Figure 2 The second upper gate structure 313 may be disposed on the second channel layer 311 . The second upper gate structure 313 may include a second upper gate dielectric 315 , a second lower work function layer 317 , a second filling layer 321 and two second upper gate spacers 323 .

[0181] Please refer to Figure 1 and Figure 2, the second upper gate dielectric 315 may be disposed on the second channel layer 311. The second upper gate dielectric 315 may have a thickness less than the thickness of the first upper gate dielectric 215. The second upper gate dielectric 315 may have a second lower sublayer 315-1 and a second middle sublayer 315-3.

[0182] Please refer to Figure 1 and Figure 2 , the second lower sublayer 315-1 may be disposed on the second channel layer 311 and may have a U-shaped cross-sectional profile. Due to the U-shaped cross-sectional profile, corner effects can be avoided. The second lower sublayer 315-1 may have the same thickness as the first sublayer 215-1, but is not limited thereto. The second lower sublayer 315-1 may be made of the same material as the first sublayer 215-1, but is not limited thereto. The second intermediate sublayer 315-3 may be disposed on the second lower sublayer 315-1. The second intermediate sublayer 315-3 may have a U-shaped cross-sectional profile. The second intermediate sublayer 315-3 may have the same thickness as the first intermediate sublayer 215-3, but is not limited thereto. The second intermediate sublayer 315-3 may be made of the same material as the first intermediate sublayer 215-1, but is not limited thereto.

[0183] Please refer to Figure 1 and Figure 2 , the second lower work function layer 317 may be disposed on the second upper gate dielectric 315. In particular, the second lower work function layer 317 may be disposed on the second intermediate sublayer 315-3. The second lower work function layer 317 may have a U-shaped cross-sectional profile. The second lower work function layer 317 may have the same thickness as the first lower work function layer 217, but is not limited thereto. The second lower work function layer 317 may be made of the same material as the first lower work function layer 217. The second filling layer 321 may be disposed on the second lower work function layer 317. The second filling layer 321 may be made of the same material as the first filling layer 221. Two second upper gate spacers 323 may be respectively disposed on both sides of the second upper gate spacer 315. In particular, the two second upper gate spacers 323 may be respectively disposed on both sides of the second lower sublayer 315-1. The two second upper gate spacers 323 may be made of the same material as the two first upper gate spacers 223, but is not limited thereto.

[0184] Please refer to Figure 1 and Figure 2, two second source / drain regions 325 may be disposed on both sides of the second lower gate structure 303 and on both sides of the second channel layer 311. The upper portions of the two second source / drain regions 325 may protrude in the direction away from the substrate 101 along the Z direction. The upper portions of the two second source / drain regions 325 may be disposed adjacent to the two second upper gate spacers 323. The lower portions of the two second source / drain regions 325 may be located in a vertical plane, which is lower than the lower surfaces of the two second lower gate spacers 307. In some embodiments, the lower surfaces of the two second source / drain regions 325 may be located in a vertical plane, which is between the vertical plane of the lower surfaces of the two second lower gate spacers 307 and a vertical plane of the upper surfaces of the two second lower gate spacers 307. The plurality of insulating structures 107 disposed in the second region 105 may be disposed in correspondence with each other adjacent to the two second source / drain regions 325. The two second source / drain regions 325 may be made of the same material as the two first source / drain regions 225 , but the invention is not limited thereto.

[0185] Please refer to Figure 1 and Figure 2 , two second contact points 327 may be provided to pass through the first isolation layer 109, and respectively provided on the two second source / drain regions 325. The two second contact points 327 may be made of the same material as the two first contact points 227, but not limited thereto. The two second conductive layers 329 may be respectively provided between the two second contact points 327 and the two second source / drain regions 325. The two second conductive layers 329 may have the same thickness as the two first conductive layers 229, but not limited thereto. The two second conductive layers 329 may be made of the same material as the two first conductive layers 229, but not limited thereto.

[0186] When operating the semiconductor device 10A, the first lower gate structure 203, the first upper gate structure 213, the second lower gate structure 303, and the second upper gate structure 313 can be electrically coupled to different voltage supplies. The conductive state of the first channel layer 211 can be controlled by the first lower gate structure 203 and the first upper gate structure 213 at the same time. As a result, the leakage current in the first channel layer 211 can be reduced. Accordingly, the conductive state of the second channel layer 311 can be controlled by the second lower gate structure 303 and the second upper gate structure 313 at the same time. In some embodiments, the first lower gate structure 203 and the first upper gate structure 213 can be electrically coupled to the same voltage supply.

[0187] Figures 3 to 5 1 is a schematic cross-sectional view of each semiconductor element 10B, 10C, and 10D according to an embodiment of the present disclosure. Figure 6 Based on Figure 5 FIG. 1 is an enlarged cross-sectional schematic diagram of the semiconductor element 10D. Figure 7 FIG. 1 is an enlarged cross-sectional view of a semiconductor device 10E according to an embodiment of the present disclosure. Figure 8 FIG. 1 is a schematic cross-sectional view of a semiconductor device 10F according to an embodiment of the present disclosure.

[0188] Please refer to Figure 3 In the semiconductor device 10B, a first bottom insulating layer 233 may be disposed below the first bottom gate structure 203 and between the two first source / drain regions 225. The first bottom insulating layer 233 may be made of the same material as the first bottom gate dielectric 209, but is not limited thereto. A first channel separation layer (first bottom insulating layer) 231 may be disposed below the first bottom insulating layer 233 and between the two first source / drain regions 225. A lower surface of the first channel separation layer 231 may be located at a vertical plane that is higher than the vertical plane of the lower surfaces of the two first source / drain regions 225. The first channel separation layer 231 may be doped with a dopant, such as phosphorus, arsenic, antimony or boron. The first channel separation layer 231 may have a second electrical state relative to the electrical state of the two first source / drain regions 225.

[0189] Please refer to Figure 3 , a second lower isolation layer 333 may be disposed below the second lower gate structure 303 and between the two second source / drain regions 325. The second lower isolation layer 333 may be made of the same material as the second lower gate dielectric 309, but is not limited thereto. A second channel separation layer 331 may be disposed below the second lower isolation layer 333 and between the two second source / drain regions 325. A lower surface of the second channel separation layer 331 may be located at a vertical plane that is higher than the vertical plane of the lower surfaces of the two second source / drain regions 325. The second channel separation layer 331 may be doped with a dopant, such as phosphorus, arsenic, antimony or boron. The second channel separation layer 331 may have an electrical form relative to the electrical form of the two second source / drain regions 325. The first channel separation layer 231 and the second channel separation layer 331 may prevent a channel from being formed on the upper surface of the substrate 101. Accordingly, a short channel effect may be avoided.

[0190] Please refer to Figure 4In the semiconductor device 10C, a first buffer layer 235 may be disposed below the first lower isolation layer 233. The lower surface of the first buffer layer 235 may be located at a vertical plane lower than the vertical plane of the lower surfaces of the two first source / drain regions 225. The first buffer layer 235 may be made of a material having a lattice constant that is different from the lattice constant of the substrate 101. A second buffer layer 335 may be disposed below the second lower isolation layer 333. The lower surface of the second buffer layer 335 may be located at a vertical plane lower than the vertical plane of the lower surfaces of the two second source / drain regions 325. The second buffer layer 335 may be made of a material having a lattice constant that is different from the lattice constant of the substrate 101. Due to the difference in lattice constants, the carrier mobility of the first transistor 201 or the carrier mobility of the second transistor 301 may be improved.

[0191] Please refer to Figure 5 and Figure 6 In the semiconductor device 10D, the thickness of the first upper gate dielectric 215 may be smaller than the thickness of the second upper gate dielectric 315. The first upper gate dielectric 215 may include a first lower sublayer 215-1 and a first intermediate sublayer 215-3. The first lower work function layer 217 may be disposed on the first intermediate sublayer 215-3.

[0192] Please refer to Figure 5 and Figure 6 , the second upper gate dielectric 315 may include a second lower sublayer 315-1, a second intermediate sublayer 315-3, and a second upper sublayer 315-5. The second upper sublayer 315-5 may be disposed on the second intermediate sublayer 315-3. The second upper sublayer 315-5 may have a U-shaped cross-sectional profile. The second upper sublayer 315-5 may have a thickness ranging from about 0.5 nm to about 5.0 nm. Preferably, the thickness of the second upper sublayer 315-5 may be between about 0.5 nm and 2.5 nm. It should be understood that the thickness of the second upper sublayer 315-5 may be set in an arbitrary range depending on the environment. In some embodiments, for example, the second upper sublayer 315-5 may be made of an isolation material having a dielectric constant of about 4.0 or greater. In some embodiments, for example, the second upper sublayer 315-5 may be made of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. The second lower work function layer 317 may be disposed on the second upper sub-layer 315 - 5 .

[0193] Please refer to Figure 7In the semiconductor device 10E, the first upper gate structure 213 may have a first interfacial layer 237, a first dipole layer 239, a first upper gate dielectric 215, a first functional layer 241, a first adjustment layer 243, a first protection layer 245, a first lower work function layer 217, a first upper work function layer 219, a first encapsulation layer 247, a first filling layer 221 and a first cap layer 249. The first interfacial layer 237 may be disposed between the first channel layer 211 and the first upper gate dielectric 215. The first interfacial layer 237 may help the formation of the first upper gate dielectric 215. The first interfacial layer 237 may have a thickness between about to approximately The first interface layer 237 may be formed by a chemical oxide of the underlying first channel layer 211, such as silicon oxide.

[0194] Please refer to Figure 7The first coupling layer 239 may be disposed between the first upper gate dielectric 215 and the first interface layer 237. The first coupling layer 239 may have a thickness less than 2 nm. The first coupling layer 239 may replace defects in the first upper gate dielectric 215 and may improve the mobility and reliability of the first upper gate structure 213. The first coupling layer 239 may be made of a material including one or more of the following: lutetium oxide, lutetium silicon oxide, yttrium oxide, yttrium silicon oxide, lanthanum oxide, lanthanum silicon oxide, barium oxide, barium silicon oxide, strontium oxide, strontium silicon oxide, aluminum oxide, aluminum silicon oxide, titanium oxide, titanium silicon oxide, hafnium oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, tantalum silicon oxide, scandium oxide, scandium silicon oxide, magnesium oxide, and magnesium silicon oxide.

[0195] Please refer to Figure 7 , the first functional layer 241 may be disposed on the first upper gate dielectric 215. The first functional layer 241 may have a thickness between about to approximately The first functional layer 241 may protect the first upper gate dielectric 215 from damage during the subsequent semiconductor process. The first adjustment layer 243 may be disposed on the first functional layer 214 and may include a material or an alloy including lanthanide nitride. The first adjustment layer 243 may be used to fine-tune the threshold voltage of the first upper gate structure 213. The first protection layer 245 may be disposed on the first adjustment layer 243 and may protect the first adjustment layer 243 from damage during the subsequent semiconductor process. For example, the first protection layer 245 may be made of titanium nitride.

[0196] Please refer to Figure 7 , the first encapsulation layer 247 may be disposed below the first filling layer 221. The first encapsulation layer 247 may have a thickness between about to approximately For example, the first encapsulation layer 247 may be made of titanium nitride. The first encapsulation layer 247 may protect the layers below the first encapsulation layer 247 from mechanical damage or diffusion of the first filling layer 221. The first capping layer 249 may be disposed on the first filling layer 221. For example, the first capping layer 249 may be made of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluorine-doped silicate.

[0197] Please refer to Figure 8 In the semiconductor device 10F, the first upper gate structure 213 may be disposed on the first channel layer 211, and may include a first sublayer 215-1, a first intermediate sublayer 215-3, a first lower work function layer 217, a first upper work function layer 219, a first adjustment layer 243, a first filling layer 221, a first cap layer 249, and two first upper gate spacers 223. The first sublayer 215-1 may be disposed on the first channel layer 211, and may have a U-shaped cross-sectional profile. The first intermediate sublayer 215-3 may be disposed on the first sublayer 215-1. The U-shaped cross-sectional profile of the first sublayer 215-1 may be regarded as a concave space. The first intermediate sublayer 215-3 may be disposed in the lower part of the concave space. The first lower work function layer 217 may be disposed on the first intermediate sublayer 215-3. The first upper work function layer 219 may be disposed on the first lower work function layer 217. The first adjustment layer 243 may be disposed on the first upper work function layer 219. The first filling layer 221 may be disposed on the first adjustment layer 243. The first capping layer 249 may be disposed on the first filling layer 221.

[0198] Please refer to Figure 8, the second upper gate structure 313 may be disposed on the second channel layer 311, and may have a second lower sublayer 315-1, a second intermediate sublayer 315-3, a second lower work function layer 317, a second adjustment layer 343, a second filling layer 321, a second cap layer 349, and two second upper gate spacers 323. The second lower sublayer 315-1 may be disposed on the second channel layer 311, and may have a U-shaped cross-sectional profile. The second intermediate sublayer 315-3 may be disposed on the second lower sublayer 315-1. The U-shaped cross-sectional profile of the second lower sublayer 315-1 may be regarded as a recessed space. The second intermediate sublayer 315-3 may be disposed in the lower part of the recessed space. The second lower work function layer 317 may be disposed on the second intermediate sublayer 315-3. The second adjustment layer 343 may be disposed on the second lower work function layer 317. The second filling layer 321 may be disposed on the second adjustment layer 343. The second capping layer 349 may be disposed on the second filling layer 321 .

[0199] It should be understood that the terms "forming", "formed" and "form" may refer to and include any method of creating, building, patterning, implanting or depositing an element, a dopant or a material. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusing, depositing, growing, implantation, photolithography, dry etching and wet etching.

[0200] Fig. 9 FIG. 2 is a schematic flow chart of a method 20 for manufacturing a semiconductor device 10A according to an embodiment of the present disclosure. Figures 10 to 26 FIG. 1 is a cross-sectional schematic diagram of a process of a method for manufacturing the semiconductor device 10A according to an embodiment of the present disclosure.

[0201] Please refer to Fig. 9 and Fig.10In step S11, a substrate 101 may be provided, and a layer of a first semiconductor material 401, a layer of a first isolation material 403, and a layer of a second semiconductor material 405 may be sequentially formed on the substrate 101. The substrate 101 may include a first region 103 and a second region 105. The first region 103 and the second region 105 may be disposed adjacent to each other. In some embodiments, the first region 103 and the second region 105 may be disposed separately from each other.

[0202] In some embodiments, for example, the first semiconductor material 401 may be made of a conductive material, such as polysilicon, polysilicon germanium, or a combination thereof. Dopants such as phosphorus, arsenic, antimony, or boron may be doped into the layer of the first semiconductor material 401 during the formation of the layer of the first semiconductor material 401. In some embodiments, for example, the first semiconductor material 401 may be the following materials: tungsten, aluminum, titanium, copper, tantalum, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminum, aluminum titanium nitride, tantalum carbide, tantalum silicon nitride, or a combination thereof.

[0203] In some embodiments, for example, the first isolation material 403 may be silicon oxide or the like. In some embodiments, for example, the first isolation material 403 may be an isolation material having a dielectric constant of about 4.0 or greater. In some embodiments, the second semiconductor material 405 may include a Group IV, Group II-IV, or Group III-V compound, such as silicon, germanium, silicon germanium, indium gallium arsenide, indium arsenide, antimony gallium, or antimony indium.

[0204] Please refer to Fig. 9 and Fig.11 In step S13, a plurality of insulating structures 107 are formed so as to pass through the layer of the second semiconductor material 405, the layer of the first isolation material 403, the layer of the first semiconductor material 401 and the substrate 101. Fig.11 A series of deposition processes may be performed to deposit a pad oxide layer (at Fig.11 ) and a nitride pad layer (not shown) (in Fig.11107 . A photolithography process may be performed to define the locations of the plurality of insulating structures 107. After the photolithography process, an etching process such as an anisotropic dry etching process may be performed to form a plurality of trenches through the oxide pad layer, the nitride pad layer and the substrate 101. An isolation material may be deposited in the plurality of trenches, and a planarization process such as chemical mechanical polishing may then be performed to remove excess filler material until the layer of the second semiconductor material 405 is exposed and the plurality of insulating structures 107 are formed simultaneously. For example, the isolation material may be the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluorine-doped silicate.

[0205] Please refer to Fig. 9 and Fig.12 In step S15, a first dummy structure 501 and a second dummy structure 601 may be formed on the layer of the second semiconductor material 405. The first dummy structure 501 may be formed in the first region 103, and may have a first lower dummy layer 503, a first middle dummy layer 505, a first upper dummy layer 507, and two first upper gate spacers 223. The second dummy structure 601 may be formed in the second region 105, and may have a second lower dummy layer 603, a second middle dummy layer 605, a second upper dummy layer 607, and two second upper gate spacers 323.

[0206] Please refer to Fig.12 , an etch stop layer, a sacrificial layer, and a mask layer may be sequentially formed on the layer of the second semiconductor material 405 and the plurality of insulating structures 107. For example, the etch stop layer may be made of the following materials: carbon-doped oxide, carbon incorporated silicon oxide, ornithine decarboxylase, or nitrogen-doped silicon carbide. For example, the sacrificial layer may be made of polysilicon. For example, the mask layer may be made of silicon oxide, silicon nitride, or the like. A photolithography process may be performed to define the positions of the first dummy structure 501 and the second dummy structure 601. After the photolithography process, an etching process such as an anisotropic dry etching process may be performed to remove portions of the etch stop layer, the sacrificial layer, and the mask layer. Meanwhile, the first lower dummy layer 503 , the first middle dummy layer 505 , the first upper dummy layer 507 , the second lower dummy layer 603 , the second middle dummy layer 605 , and the second upper dummy layer 607 may be formed after the etching process.

[0207] Please refer to Fig.12, a spacer isolation layer may be deposited on the middle semiconductor element. An etching process such as an anisotropic dry etching process may be performed to remove some portions of the spacer isolation layer and simultaneously form two first upper gate spacers 223 and two second upper gate spacers 323. For example, the spacer isolation layer may be silicon oxide, silicon nitride, or the like.

[0208] Please refer to Fig. 9 and Fig.13 In step S17, a plurality of recesses 701 may be formed so as to pass through the layer of the second semiconductor material 405, the layer of the first isolation material 403, the layer of the first semiconductor material 401, and the substrate 101. An etching process such as an anisotropic etching process is performed, which uses the first dummy structure 501 and the second dummy structure 601 as masks to remove the layer of the second semiconductor material 405, the layer of the first isolation material 403, the layer of the first semiconductor material 401, and some portions of the substrate 101, and simultaneously forms a plurality of recesses 701. After the etching process, the layer of the second semiconductor material 405 may be transformed into the first channel layer 211 and the second channel layer 311. The layer of the first isolation material 403 may be transformed into the first lower gate dielectric 209 and the second lower gate dielectric 309. The etching process may use multiple steps and use a variety of different etchants.

[0209] Please refer to Fig. 9 and Fig.14 In step S19, a lateral etching process may be performed to remove portions of the layer of the first semiconductor material 401 and form a plurality of lateral recesses 703. The lateral etching process may have an etching selectivity relative to the first semiconductor material 401. The selectivity of an etching process is generally expressed as a ratio of etching rates. For example, if one material is etched 25 times faster than the other material, the etching process may be described as having a selectivity of 25:1, or simply 25. In this regard, a higher ratio or value indicates a more selective etching process. In the lateral etching process, an etching rate for the first semiconductor material 401 may be greater than an etching rate for the substrate 101, an etching rate for the first isolation material 403, an etching rate for the second semiconductor material 405, and an etching rate for the plurality of insulating structures 107. The selectivity of the lateral etching process may be greater than or equal to approximately 10, greater than or equal to approximately 12, greater than or equal to approximately 15, greater than or equal to approximately 20, or greater than or equal to approximately 25.

[0210] Please refer to Fig. 9 and Fig.15In step S21, two first lower gate spacers 207 and two second lower gate spacers 307 may be formed in the plurality of lateral recesses 703. An isolation material or an energy material may be deposited to fill the plurality of lateral recesses 703 and some portions of the plurality of recesses 701. The isolation material may be silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. An etching process may be performed to remove the filling material in the plurality of recesses 701 and simultaneously form the two first lower gate spacers 207 and the two second lower gate spacers 307 in the plurality of lateral recesses 703.

[0211] Please refer to Fig. 9 and Fig.16 In step S23, two first source / drain regions 225 and two second source / drain regions 325 may be formed in the plurality of recesses 701. The two first source / drain regions 225 and the two second source / drain regions 325 may be simultaneously formed in the plurality of recesses 701 using an epitaxial growth process. In some embodiments, the two first source / drain regions 225 and the two second source / drain regions 325 may be separately formed using a suitable mask.

[0212] Please refer to Fig. 9 and Fig.17 In step S25, a first isolation layer 109 may be formed on the substrate 101. The first isolation layer 109 may be formed on the intermediate semiconductor element. A planarization process such as chemical mechanical polishing may be performed until the upper surface of the first intermediate dummy layer 505 and the upper surface of the second intermediate dummy layer 6054 are exposed to provide a substantially flat surface for subsequent processing steps.

[0213] Please refer to Fig. 9 and Fig.18 In step S27, a first trench 705 may be formed in the first dummy structure 501, and a second trench 707 may be formed in the second dummy structure 601. An etching process such as an anisotropic dry etching process may be performed to remove the first middle dummy layer 505, the first lower dummy layer 503, the second middle dummy layer 605, and the second lower dummy layer 603, and simultaneously form the first trench 705 and the second trench 707 in appropriate locations. A portion of the upper surface of the first channel layer 211 may be exposed through the first trench 705. A portion of the upper surface of the second channel layer 311 may be exposed through the second trench 707.

[0214] Please refer to Fig. 9 and Figure 19 to Figure 24 In step S29, a first upper gate structure 213 and a second upper gate structure 313 may be formed on the substrate 101. Fig.19, a layer of the third isolation material 407, a layer of the fourth isolation material 409, and a layer of the fifth isolation material 411 may be formed on the first isolation layer 109 and in the first trench 705 and the second trench 707. For example, the third isolation material 407 may be the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. For example, the fourth isolation material 409 may be an isolation material having a dielectric constant of about 4.0 or greater. For example, the fifth isolation material 411 may be the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like.

[0215] Please refer to Fig. 20 , a first mask layer 801 may be formed to mask the first region 103. The layer of the fifth isolation material 411 formed in the second region 105 may be removed by an etching process. After the etching process, the first mask layer 801 may be removed. Please refer to Fig.21 , a layer of lower work function material 413 and a layer of upper work function material 415 may be sequentially formed on the layer of the fifth isolation material 411 and on the layer of the fourth isolation material 409. For example, the lower work function material 413 may be made of the following materials: aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium aluminum carbide, titanium aluminum nitride, titanium silicon aluminum, tantalum nitride, tantalum carbide, tantalum silicon nitride, manganese, zirconium or tungsten nitride. For example, the upper work function material 415 may be made of the following materials: titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride or ruthenium.

[0216] Please refer to Fig. 22 A second mask layer 803 may be formed to mask the second region 103. The layer of the upper work function material 415 formed in the second region 105 may be removed by an etching process. After the etching process, the second mask layer 803 may be removed. Fig.23 , a layer of filling material 417 may be formed on the layer of lower work function material 413 and the layer of upper work function material 415 and deposited to completely fill the first trench 705 and the second trench 707. Please refer to Fig.24 A planarization process such as chemical mechanical polishing may be performed until the upper surface of the first isolation layer 109 is exposed to remove excess material, thereby providing a substantially flat surface for subsequent processing steps and simultaneously forming the first upper gate structure 213 and the second upper gate structure 313.

[0217] Please refer to Fig. 9 , Fig.25 and Fig.26 In step S31, two first contacts 227 may be formed on the two first source / drain regions 225, and two second contacts 327 may be formed on the two second source / drain regions 325. Fig.25, a second isolation layer 805 may be formed on the first isolation layer 109. The second isolation layer 805 may be made of the same material as the first isolation layer 109, but is not limited thereto. A photolithography process may be performed to define the positions of the two first contact points 227 and the two second contact points 327. After the photolithography process, an etching process such as an anisotropic dry etching process may be performed to remove some portions of the second isolation layer 805 and the first isolation layer 109, and simultaneously form a plurality of contact openings 709. Some portions of the upper surfaces of the two first source / drain regions 225 and the two second source / drain regions 325 may be exposed through the plurality of contact openings 709.

[0218] Please refer to Fig.25 , a layer of metal may be sequentially deposited into the plurality of contact openings 709. For example, the metal may be the following materials: titanium, nickel, platinum, tantalum or cobalt. A heat treatment may be performed. During the heat treatment, the metal atoms of the layer of metal may chemically react with the silicon atoms of the two first source / drain regions 225 and the two second source / drain regions 325 to form two first conductive layers 229 and two second conductive layers 329, respectively. The heat treatment may be a dynamic surface annealing process. After the heat treatment, a cleaning process may be performed to remove unreacted metal. The cleaning process may use an etchant, such as hydrogen peroxide and a standard cleaner-1 (SC-1) solution.

[0219] Please refer to Fig.26 , a conductive material may be deposited into the plurality of contact openings 709 by a deposition process, and the conductive material may be, for example, polysilicon, metal, or metal nitride. After the deposition process, a planarization process, such as chemical mechanical polishing, may be performed until the upper surface of the first isolation layer 109 is exposed to remove excess material, thereby providing a substantially flat surface for subsequent processing steps, and simultaneously forming two first contact points 227 and two second contact points 327. In some embodiments, the planarization process may be performed until the second isolation layer 805 is exposed. That is, the second isolation layer 805 may remain in place and may be used as a capping layer for the first upper gate structure 213 and the second upper gate structure 313 to protect the first upper gate structure 213 and the second upper gate structure 313 from damage during subsequent semiconductor processes.

[0220] An embodiment of the present disclosure provides a semiconductor element, comprising a substrate, including a first region; and a first transistor, located in the first region. The first transistor comprises a first lower gate structure, a first channel layer, a first upper gate structure, and two first source / drain regions, wherein the first lower gate structure is located on the substrate, the first channel layer is located on the first lower gate structure, the first upper gate structure is located on the first channel layer, and the two first source / drain regions are located on both sides of the first channel layer.

[0221] Another embodiment of the present disclosure provides a method for preparing a semiconductor element. The method includes: providing a substrate; forming a first lower gate structure on the substrate; forming a first channel layer on the first lower gate structure; forming a first upper gate structure on the first channel layer; and forming two first source / drain regions on both sides of the first channel layer.

[0222] Due to the design of the semiconductor device disclosed in the present invention, the conductive state of the first channel layer can be controlled by the first lower gate structure and the first upper gate structure at the same time. As a result, the leakage current in the first channel layer can be reduced. In addition, the first upper gate dielectric and the second upper gate dielectric having different thicknesses can have different threshold voltages and can provide different functions; therefore, the applicability of the semiconductor device can be increased.

[0223] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure defined in the claims. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

[0224] Furthermore, the scope of the present invention is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present invention.

Claims

1. A semiconductor element, comprising: a substrate including a first region; and a first transistor located in the first region; The first transistor includes a first lower gate structure, a first channel layer, a first upper gate structure and two first source / drain regions, wherein the first lower gate structure is located on the substrate, the first channel layer is located on the first lower gate structure, the first upper gate structure is located on the first channel layer, and the two first source / drain regions are located on both sides of the first channel layer; The first upper gate structure includes a first upper gate dielectric, a first lower work function layer and a first filling layer, wherein the first upper gate dielectric is located on the first channel layer, the first lower work function layer is located on the first upper gate dielectric, and the first filling layer is located on the first lower work function layer; The first lower work function layer has a thickness between arrive between; Also included is a first upper work function layer located between the first lower work function layer and the first filling layer; The first upper work function layer has a thickness between arrive between; The two first source / drain regions are made of a material that is different from the material of the first channel layer, and the first channel layer includes a strained channel; The first lower gate structure is disposed on the first region and is located between an adjacent pair of insulating structures disposed in the first region; the first lower gate structure has a first lower gate electrode, two first lower gate spacers and a first lower gate dielectric; Two first lower gate spacers are arranged on both sides of the first lower gate electrode, the two first lower gate spacers have a skeleton and a plurality of empty spaces, and the plurality of empty spaces are arranged between the skeletons; the plurality of empty spaces are interconnected and filled with air; the first lower gate dielectric is arranged on the first lower gate electrode and the two first lower gate spacers. 2 . The semiconductor device as claimed in claim 1 , further comprising two first upper gate spacers located on two sides of the first upper gate dielectric. 3 . The semiconductor device as claimed in claim 2 , further comprising two first contact points located on the two first source / drain regions. 4 . The semiconductor device as claimed in claim 3 , further comprising two first conductive layers located between the two first contact points and the two first source / drain regions. 5 . The semiconductor device as claimed in claim 4 , wherein each first conductive layer has a thickness ranging from 2 nm to 20 nm. 6 . The semiconductor device as claimed in claim 3 , further comprising a first lower isolation layer located below the first lower gate structure. 7 . The semiconductor device as claimed in claim 6 , further comprising a first channel separation layer located below the first lower isolation layer, wherein the first channel separation layer is doped with phosphorus, arsenic, antimony or boron. 8 . The semiconductor device as claimed in claim 6 , further comprising a first buffer layer located below the first lower isolation layer, wherein the first buffer layer has a lattice constant different from a lattice constant of the substrate.

9. The semiconductor element as described in claim 1 further includes a second transistor located in a second region of the substrate, wherein the second transistor includes a second lower gate structure, a second channel layer and a second upper gate structure, the second lower gate structure is located on the substrate, the second channel layer is located on the second lower gate structure, and the second upper gate structure is located on the second channel layer, wherein the second channel layer and the first channel layer are located on the same vertical plane. 10 . The semiconductor device as claimed in claim 9 , wherein the second upper gate structure comprises a second upper gate dielectric located on the second channel layer, and the second upper gate dielectric has a thickness smaller than a thickness of the first upper gate dielectric.

11. A method for preparing a semiconductor element, comprising: providing a substrate; forming a first lower gate structure on the substrate; forming a first channel layer on the first lower gate structure; forming a first upper gate structure on the first channel layer; as well as forming two first source / drain regions on both sides of the first channel layer; The first upper gate structure includes a first upper gate dielectric, a first lower work function layer and a first filling layer, wherein the first upper gate dielectric is located on the first channel layer, the first lower work function layer is located on the first upper gate dielectric, and the first filling layer is located on the first lower work function layer; The first lower work function layer has a thickness between arrive between; Also included is a first upper work function layer located between the first lower work function layer and the first filling layer; The first upper work function layer has a thickness between arrive between; The two first source / drain regions are made of a material that is different from the material of the first channel layer, and the first channel layer includes a strained channel; The first lower gate structure is disposed on the first region and is located between an adjacent pair of insulating structures disposed in the first region; the first lower gate structure has a first lower gate electrode, two first lower gate spacers and a first lower gate dielectric; Two first lower gate spacers are arranged on both sides of the first lower gate electrode, the two first lower gate spacers have a skeleton and a plurality of empty spaces, and the plurality of empty spaces are arranged between the skeletons; the plurality of empty spaces are interconnected and filled with air; the first lower gate dielectric is arranged on the first lower gate electrode and the two first lower gate spacers. 12 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein the first channel layer is made of the following materials: silicon, germanium, silicon germanium, indium gallium arsenide, indium arsenide, antimony gallium, antimony indium or a combination thereof.

13. The method for manufacturing a semiconductor device as claimed in claim 12, wherein the step of forming the first lower gate structure comprises: forming a layer of first semiconductor material, a layer of first isolation material and a layer of second semiconductor material on the substrate; forming a first dummy structure on the layer of second semiconductor material; Performing an etching process to form a plurality of recesses and transform the first isolation material layer into a first lower gate dielectric and the second semiconductor material layer into the first channel layer; performing a lateral etching process to form a plurality of lateral recesses and transform the layer of first semiconductor material into the first lower gate electrode; as well as forming two first lower gate spacers in the plurality of lateral recesses; The first lower gate electrode, the two first lower gate spacers and the first lower gate dielectric together form the first lower gate structure. 14 . The method for fabricating a semiconductor device as claimed in claim 13 , wherein the two first lower gate spacers comprise silicon oxide, a low dielectric material or methyl silicate. 15 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein the two first lower gate spacers have a porosity ranging from 10% to 100%.

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