Solid-state multi-switch devices

Abstract

A solid-state switch assembly includes a substrate and an electrically insulating layer secured to the substrate. First, second, third, and fourth power traces are secured to the electrically insulating layer. A first semiconductor device is disposed on the first power trace to control power flow between the first power trace and the second power trace, a second semiconductor device is disposed on the second power trace to control power flow between the second power trace and the third power trace, and a third semiconductor device is disposed on the third power trace to control power flow between the third and fourth power traces. A first signal conductor communicates with the first semiconductor device. A second signal conductor communicates with the second semiconductor device. A third signal conductor communicates with the third semiconductor device.

Description

Background Art

[0001] The onboard battery system may employ multiple battery packs arranged to supply high voltage DC power to the electrified powertrain. The battery packs may be arranged in parallel to supply power to the electrified powertrain for operation, and in series during recharging.

[0002] Existing gate driver circuits are designed for inverter applications, have high power consumption, are large, and are not suitable for integration into solid-state switches. If the power source has significant inductance, the solid-state switch cannot absorb high energy during disconnection under short circuit or overload conditions. Therefore, there is a need to develop low-power and compact gate drivers and protection circuits for solid-state switches. In addition, there is a need for a switching device that can deliver power for electrified powertrain operation and charging, is compact in size, lightweight, can manage temperature, has fast switching speeds, and is quiet. Summary of the invention

[0003] Concepts described herein relate to electronic solid-state switch assemblies, including electronic solid-state switch assemblies that can be employed in high-voltage battery systems including multiple battery packs. The disclosed switch assemblies are intended to be lightweight, fast switching, and quiet in operation. In addition, the disclosed switch assemblies can achieve one or more desired benefits, including continuous delivery of at least 400 amperes of direct current with a voltage drop of less than 1 volt; scalable; having fast fault interrupt capability; having current limiting in fault conditions; and having repeatability and reliability.

[0004] An electronic solid-state switch assembly (multi-switch device) is described, comprising a substrate and an electrically insulating layer fixed to the substrate. A first power trace is fixed to the electrically insulating layer, wherein the first power trace includes a positive power supply terminal; a second power trace is fixed to the electrically insulating layer, wherein the second power trace includes a first power node; a third power trace is fixed to the electrically insulating layer, wherein the third power trace includes a second power node; and a fourth power trace is fixed to the electrically insulating layer, wherein the fourth power trace includes a negative power supply terminal. A first group of power semiconductor devices is arranged on the first power trace to control power flow between the first power trace and the second power trace via a first plurality of electrical junctions, a second group of power semiconductor devices is arranged on the second power trace to control power flow between the second power trace and the third power trace via a second plurality of electrical junctions, and a third group of power semiconductor devices is arranged on the third power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions. A first signal conductor is fixed to the electrically insulating layer between the first and second power traces, wherein the first signal conductor communicates with the first group of power semiconductor devices. A second signal conductor is secured to the electrical insulation layer between the second and third power traces, wherein the second signal conductor communicates with the second group of power semiconductor devices. A third signal conductor is secured to the electrical insulation layer between the third and fourth power traces, wherein the third signal conductor communicates with the third group of power semiconductor devices.

[0005] Another aspect of the present disclosure includes that the first, second, third, and fourth power traces are electrically isolated conductive planar elements on the substrate.

[0006] Another aspect of the present disclosure includes that the first, second, third, and fourth power traces are electrically conductive rectangular planar elements arranged in parallel and electrically isolated on the substrate.

[0007] Another aspect of the present disclosure includes that the conductive planar elements of the first, second, third, and fourth power traces are made of a metallic material selected from the group consisting of copper, aluminum, and alloys thereof.

[0008] Another aspect of the present disclosure includes that the electrically insulating layer is thermally conductive.

[0009] Another aspect of the present disclosure includes a heat sink thermally connected to a substrate.

[0010] Another aspect of the present disclosure includes each power semiconductor device being configured to block electrical power having a magnitude between 650 volts and 1200 volts.

[0011] Another aspect of the present disclosure includes an electronic solid-state switch assembly configured to continuously deliver at least 400 amperes of direct current with a voltage drop of less than 1 volt when controlled to a conductive state.

[0012] Another aspect of the present disclosure includes a substrate having a thickness between two millimeters and three millimeters, and the plurality of semiconductor dies are electrically connected in parallel to each other.

[0013] Another aspect of the present disclosure includes a solder layer disposed between a substrate and an electrically insulating layer, wherein the electrically insulating layer includes a ceramic material, and wherein the substrate includes copper, aluminum, molybdenum, alloys thereof, or a thermally conductive metal matrix composite material such as AlSiC or copper graphite foam.

[0014] Another aspect of the present disclosure includes a conductive trace comprising a metallic material, wherein the metallic material is selected from the group consisting of copper, aluminum, and alloys thereof.

[0015] Another aspect of the present disclosure includes the first, second, and third pluralities of power semiconductor devices being metal oxide silicon field effect transistors (MOSFETs).

[0016] Another aspect of the present disclosure includes an electronic solid-state switch assembly, the assembly including a substrate and an electrically insulating layer fixed to the substrate. A first power trace is fixed to the electrically insulating layer, wherein the first power trace includes a positive power supply terminal. A second power trace is fixed to the electrically insulating layer, wherein the second power trace includes a first power node. A third power trace is fixed to the electrically insulating layer, wherein the third power trace includes a second power node. A fourth power trace is fixed to the electrically insulating layer, wherein the fourth power trace includes a third power node. A fifth power trace is fixed to the electrically insulating layer, wherein the fifth power trace includes a negative power supply terminal. A first group of power semiconductor devices is arranged on the first power trace to control power flow between the first power trace and the second power trace via a first plurality of electrical junctions. A second group of power semiconductor devices is arranged on the second power trace to control power flow between the second power trace and the third power trace via a second plurality of electrical junctions. A third group of power semiconductor devices is arranged on the fourth power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions. A fourth group of power semiconductor devices is arranged on a fourth power trace to control power flow between the fourth power trace and the fifth power trace via a fourth plurality of electrical junctions. A first signal conductor is secured to the electrical insulation layer between the first and second power traces, wherein the first signal conductor communicates with the first group of power semiconductor devices, and a second signal conductor is secured to the electrical insulation layer between the second and third power traces, wherein the second signal conductor communicates with the second group of power semiconductor devices. A third signal conductor is secured to the electrical insulation layer between the third and fourth power traces, wherein the third signal conductor communicates with the third group of power semiconductor devices. A fourth signal conductor is secured to the electrical insulation layer between the fourth and fifth power traces, wherein the fourth signal conductor communicates with the fourth group of power semiconductor devices.

[0017] Another aspect of the present disclosure includes a reconfigurable battery system, including: a high voltage bus including a positive high voltage bus and a negative high voltage bus; a first battery pack and a second battery pack electrically connected between the positive high voltage bus and the negative high voltage bus; and an electronic solid-state switch assembly, including: a first power trace including a positive power supply terminal, a second power trace including a first power node, a third power trace including a second power node, and a fourth power trace including a negative power supply terminal. The positive power supply terminal of the electronic solid-state switch assembly is electrically connected to the positive high voltage bus. The first power node of the electronic solid-state switch assembly is electrically connected to an anode of the first battery pack. The second power node of the electronic solid-state switch assembly is electrically connected to a cathode of the second battery pack. The negative power supply terminal of the electronic solid-state switch assembly is electrically connected to the negative high voltage bus. The cathode of the first battery pack is electrically connected to the negative high voltage bus. The anode of the second battery pack is electrically connected to the positive high voltage bus. An electronic solid-state switch assembly includes a substrate, an electrically insulating layer secured to the substrate, a first group of power semiconductor devices arranged to control power flow between a first power trace and a second power trace, a second group of power semiconductor devices arranged to control power flow between the second power trace and a third power trace, and a third group of power semiconductor devices arranged to control power flow between the third power trace and a fourth power trace.

[0018] The present invention provides the following technical solutions:

[0019] 1. An electronic solid-state switch assembly, comprising:

[0020] substrate;

[0021] an electrically insulating layer secured to the substrate;

[0022] a first power trace secured to the electrically insulating layer, wherein the first power trace includes a positive power terminal;

[0023] a second power trace secured to the electrically insulating layer, wherein the second power trace includes a first power node;

[0024] a third power trace secured to the electrically insulating layer, wherein the third power trace includes a second power node;

[0025] a fourth power trace secured to the electrically insulating layer, wherein the fourth power trace includes a negative power terminal;

[0026] a first set of power semiconductor devices arranged on the first power trace to control power flow between the first power trace and the second power trace via a first plurality of electrical junctions;

[0027] a second set of power semiconductor devices arranged on the second power trace to control power flow between the second power trace and the third power trace via a second plurality of electrical junctions;

[0028] a third group of power semiconductor devices arranged on the third power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions;

[0029] a first signal conductor secured to the electrically insulating layer between the first and second power traces, wherein the first signal conductor communicates with the first set of power semiconductor devices;

[0030] a second signal conductor secured to the electrically insulating layer between the second and third power traces, wherein the second signal conductor communicates with the second set of power semiconductor devices; and

[0031] A third signal conductor is secured to the electrically insulating layer between the third and fourth power traces, wherein the third signal conductor communicates with the third group of power semiconductor devices.

[0032] 2. An electronic solid-state switch assembly according to technical solution 1, wherein the first, second, third and fourth power traces include conductive planar elements electrically isolated on the substrate.

[0033] 3. An electronic solid-state switch assembly according to technical solution 2, wherein the first, second, third and fourth power traces further include conductive rectangular planar elements arranged in parallel and electrically isolated on the substrate.

[0034] 4. An electronic solid-state switch assembly according to technical solution 2, wherein the conductive planar elements of the first, second, third and fourth power traces are made of a metal material selected from the group consisting of: copper, aluminum and alloys thereof.

[0035] 5. An electronic solid-state switch assembly according to Technical Solution 1, wherein the electrical insulation layer is thermally conductive.

[0036] 6. The electronic solid-state switch assembly according to Technical Solution 1 further includes a heat sink thermally connected to the substrate.

[0037] 7. An electronic solid-state switch assembly according to technical solution 1, wherein each power semiconductor device in the first group, the second group and the third group of power semiconductor devices is configured to block power of at least 650 volts to 1200 volts.

[0038] 8. An electronic solid-state switch component according to technical solution 1, wherein the electronic solid-state switch component is configured to: when controlled to a conductive state, continuously deliver at least 400 amperes of direct current with a voltage drop of less than 1 volt.

[0039] 9. An electronic solid-state switch component according to technical solution 1, wherein the thickness of the substrate is between two millimeters and three millimeters, a first group of power semiconductor devices arranged on the first power trace are electrically connected in parallel to each other, a second group of power semiconductor devices arranged on the second power trace are electrically connected in parallel to each other, and a third group of power semiconductor devices arranged on the third power trace are electrically connected in parallel to each other.

[0040] 10. The electronic solid-state switch assembly according to technical solution 1 further comprises a solder layer arranged between the substrate and the electrical insulation layer, wherein the electrical insulation layer comprises a ceramic material, and wherein the substrate comprises copper.

[0041] 11. The electronic solid-state switch assembly according to technical solution 1, wherein the conductive trace comprises a metal material selected from the group consisting of: copper, aluminum and alloys thereof.

[0042] 12. An electronic solid-state switch assembly according to technical solution 1, wherein the first, second and third groups of power semiconductor devices include metal oxide silicon field effect transistor devices (MOSFETs).

[0043] 13. A reconfigurable battery system comprising:

[0044] A high voltage bus, comprising a positive high voltage bus and a negative high voltage bus;

[0045] a first battery pack and a second battery pack electrically connected between the positive high voltage bus and the negative high voltage bus; and

[0046] An electronic solid-state switch assembly comprising: a first power trace including a positive power supply terminal, a second power trace including a first power node, a third power trace including a second power node, and a fourth power trace including a negative power supply terminal;

[0047] wherein the positive power supply terminal of the electronic solid-state switch assembly is electrically connected to the positive high voltage bus;

[0048] wherein the first power node of the electronic solid-state switch assembly is electrically connected to the anode of the first battery pack;

[0049] wherein the second power node of the electronic solid-state switch assembly is electrically connected to the cathode of the second battery pack;

[0050] wherein the negative power supply terminal of the electronic solid-state switch assembly is electrically connected to the negative high voltage bus;

[0051] wherein the cathode of the first battery group is electrically connected to the negative high voltage bus;

[0052] wherein the anode of the second battery pack is electrically connected to the positive high voltage bus; and

[0053] Wherein, the electronic solid-state switch component comprises:

[0054] substrate,

[0055] an electrically insulating layer secured to the substrate,

[0056] a first set of power semiconductor devices arranged to control power flow between the first power track and the second power track,

[0057] a second set of power semiconductor devices arranged to control power flow between the second power trace and the third power trace, and

[0058] A third group of power semiconductor devices is arranged to control power flow between the third power trace and the fourth power trace.

[0059] 14. The reconfigurable battery system according to technical solution 13 further comprises:

[0060] a first plurality of signal conductors secured to the electrically insulating layer;

[0061] a first plurality of electrical junctions electrically connecting the first plurality of signal conductors to the first set of power semiconductor devices;

[0062] a second plurality of signal conductors secured to the electrically insulating layer;

[0063] a second plurality of electrical junctions electrically connecting the second plurality of signal conductors to the second set of power semiconductor devices;

[0064] a third plurality of signal conductors secured to the electrically insulating layer; and

[0065] A third plurality of electrical bonds electrically connects the third plurality of signal conductors to the third group of power semiconductor devices.

[0066] 15. A reconfigurable battery system according to technical solution 14, wherein the reconfigurable battery system is deployed to supply power to an electrified powertrain system.

[0067] 16. A reconfigurable battery system according to technical solution 14, wherein the first, second, third and fourth power traces include electrically isolated conductive planar elements on the substrate.

[0068] 17. A reconfigurable battery system according to technical solution 16, wherein the first, second, third and fourth power traces further include conductive rectangular planar elements arranged in parallel and electrically isolated on the substrate.

[0069] 18. A reconfigurable battery system according to technical solution 17, wherein the conductive planar elements of the first, second, third and fourth power traces are made of a metal material selected from the group consisting of copper, aluminum and alloys thereof.

[0070] 19. A reconfigurable battery system according to technical solution 13, wherein each power semiconductor device in the first group, the second group and the third group of power semiconductor devices is configured to block power of at least 650 volts to 1200 volts.

[0071] 20. An electronic solid-state switch assembly comprising:

[0072] substrate;

[0073] an electrically insulating layer secured to the substrate;

[0074] a first power trace secured to the electrically insulating layer, wherein the first power trace includes a positive power terminal;

[0075] a second power trace secured to the electrically insulating layer, wherein the second power trace includes a first power node;

[0076] a third power trace secured to the electrically insulating layer, wherein the third power trace includes a second power node;

[0077] a fourth power trace secured to the electrically insulating layer, wherein the third power trace includes a third power node;

[0078] a fifth power trace secured to the electrically insulating layer, wherein the fourth power trace includes a negative power terminal;

[0079] a first set of power semiconductor devices arranged on the first power trace to control power flow between the first power trace and the second power trace via a first plurality of electrical junctions;

[0080] a second set of power semiconductor devices arranged on the second power trace to control power flow between the second power trace and the third power trace via a second plurality of electrical junctions;

[0081] a third group of power semiconductor devices arranged on the third power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions;

[0082] a fourth group of power semiconductor devices arranged on the fourth power trace to control power flow between the fourth power trace and the fifth power trace via a fourth plurality of electrical junctions;

[0083] a first signal conductor secured to the electrically insulating layer between the first and second power traces, wherein the first signal conductor communicates with the first set of power semiconductor devices;

[0084] a second signal conductor secured to the electrically insulating layer between the second and third power traces, wherein the second signal conductor communicates with the second set of power semiconductor devices;

[0085] a third signal conductor secured to the electrically insulating layer between the third and fourth power traces, wherein the third signal conductor communicates with the third group of power semiconductor devices; and

[0086] A fourth signal conductor is secured to the electrically insulating layer between the fourth and fifth power traces, wherein the fourth signal conductor communicates with the fourth group of power semiconductor devices.

[0087] The above features and advantages and other features and advantages of the present teachings are readily apparent from the following detailed description of some of the best modes and other embodiments for carrying out the present teachings when taken in conjunction with the accompanying drawings as defined in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] Figure 1 is a schematic diagram of a reconfigurable battery system including an electronic solid-state switch assembly according to the present disclosure.

[0089] Figure 2 yes Figure 1 A schematic diagram of one embodiment of an electronic solid-state switch assembly.

[0090] Figure 3 yes Figure 1 Schematic top view of one embodiment of an electronic solid-state switch assembly.

[0091] Figure 4 yes Figure 1 Schematic diagram of a second embodiment of an electronic solid-state switch assembly.

[0092] Figure 5 yes Figure 1 Schematic top view of a second embodiment of an electronic solid-state switch assembly.

[0093] The accompanying drawings are not necessarily drawn to scale and may present somewhat simplified representations of various preferred features of the present disclosure as disclosed herein, including, for example, specific dimensions, orientations, locations and shapes. The details associated with these features will be determined in part by the specific intended application and use environment. DETAILED DESCRIPTION

[0094] As described and illustrated herein, the components of the disclosed embodiments can be arranged and designed in various configurations. Therefore, the following detailed description is not intended to limit the scope of the disclosure claimed for protection, but merely represents its possible embodiments. In addition, although many specific details are set forth in the following description to provide a thorough understanding of the embodiments disclosed herein, some embodiments can be practiced without these details. In addition, for the sake of clarity, some technical materials understood in the relevant art are not described in detail to avoid unnecessarily obscuring the disclosure. Only for convenience and clarity, directional terms, such as top, bottom, left, right, on, above, above, below, below, rear and front can be used with reference to the accompanying drawings. These and similar directional terms should not be interpreted as limiting the scope of the disclosure. In addition, as shown and described herein, the disclosure can be implemented without elements not specifically disclosed herein.

[0095] Embodiments of the present disclosure may be described herein in terms of functional and / or logical block components and various processing steps. It should be understood that such block components may be implemented by multiple hardware, software, and / or firmware components configured to perform specified functions. For example, embodiments of the present disclosure may employ various integrated circuit components, such as memory elements, digital signal processing elements, logic elements, lookup tables, etc., which may perform various functions under the control of one or more microprocessors or other control devices. In addition, those skilled in the art will appreciate that embodiments of the present disclosure may be implemented in conjunction with multiple systems, and the systems described herein are merely exemplary embodiments of the present disclosure.

[0096] For the sake of brevity, technologies related to signal processing, data fusion, signaling, control, and other functional aspects of the system (as well as the various operating components of the system) are not described in detail herein. In addition, the connecting lines shown in the various figures contained herein are intended to represent example functional relationships and / or physical connections between various elements. It should be noted that alternative or additional functional relationships or physical connections may exist in the embodiments of the present disclosure.

[0097] Figure 1A reconfigurable battery system 100 is schematically shown, which includes a first battery pack 10, a second battery pack 20, and an embodiment of a DC electronic solid-state multi-switch device (multi-switch device) 40. The operation of the reconfigurable battery system 100 is monitored and controlled by a switch controller 45 and / or a vehicle charging controller 35. The reconfigurable battery system 100 is arranged between a positive high-voltage bus (HV+) 32 and a negative high-voltage bus (HV-) 34, which are elements of the high-voltage bus 30. In one embodiment, the reconfigurable battery system 100 is deployed to supply power to an electrified powertrain system of a vehicle. The positive high-voltage bus (HV+) 32 and the negative high-voltage bus (HV-) 34 are electrically connected to a DC power source (not shown) and can be electrically connected to a charging receptacle 36. The first battery pack 10 and the second battery pack 20 are configured as electrochemical devices that are rechargeable and capable of storing electrical energy, such as supercapacitors, batteries, battery packs, battery cells, or any combination thereof.

[0098] The multi-switch device 40 is arranged between the first and second battery groups 10, 20. The multi-switch device 40 includes a plurality of switches, including, in one embodiment, a power semiconductor device S1 50, a power semiconductor device S2 60, and a power semiconductor device S3 70. The power semiconductor devices S1 50, S2 60, and S3 70 are arranged in series between a first power supply terminal 46' and a second power supply terminal 49', interposing first and second power nodes 47', 48', respectively. In one embodiment, and as described herein, the first power supply terminal 46' is connected to HV+ 32, and the second power supply terminal 49' is connected to HV- 34. The activation and deactivation of the power semiconductor device S1 50, the power semiconductor device S2 60, and the power semiconductor device S3 70 are controlled by the switch controller 45. The first power supply terminal 46' is electrically connected to the anode 22 of the second battery group 20, and supplies power to the semiconductor device S1 50. The power semiconductor device S150 is arranged to electrically connect the first power terminal 46' and the anode 12 of the first battery group 10 at the first power node 47'. The power semiconductor device S3 70 is arranged to electrically connect the cathode 21 of the second battery group 20 and the second power terminal 49' at the second power node 48'. The power semiconductor device S2 60 is arranged to electrically connect the anode 12 of the first battery group 10 and the cathode 21 of the second battery group 20. The cathode 11 of the first battery group 10 is electrically connected to the first power terminal 46', and the anode 22 of the second battery group 20 is electrically connected to the first power terminal 46'.

[0099] The reconfigurable battery system 100 facilitates a first arrangement in which the power semiconductor device S1 50 and the power semiconductor device S3 70 are closed and the power semiconductor device S2 60 is open, resulting in the first and second battery packs 10, 20 being electrically connected in parallel between HV+ 32 and HV- 34. The reconfigurable battery system 100 facilitates a second arrangement in which the power semiconductor device S1 50 and the power semiconductor device S3 70 are open and the power semiconductor device S2 60 is closed, resulting in the first and second battery packs 10, 20 being electrically connected in series between HV+ 32 and HV- 34. This can facilitate fast charging events. The reconfigurable battery system 100 facilitates a third arrangement in which the power semiconductor device S1 50 and the power semiconductor device S2 60 are open and the power semiconductor device S3 70 is closed, resulting in the first battery pack 10 being isolated and offline and the second battery pack 20 being electrically connected between HV+ 32 and HV- 34. This facilitates fault-tolerant operation in the event of a fault associated with the first battery pack 10 being detected. The reconfigurable battery system 100 facilitates a fourth arrangement in which the power semiconductor device S2 60 and the power semiconductor device S3 70 are open, and the power semiconductor device S1 50 is closed, resulting in the second battery pack 20 being isolated and offline, and the first battery pack 10 being electrically connected between HV+ 32 and HV- 34. This facilitates fault-tolerant operation in the event of a fault associated with the second battery pack 20 being detected.

[0100] The power semiconductor devices S1 50, S2 60 and S3 70 are low-loss switching devices. In the present disclosure, the term "low-loss switching device" refers to a solid-state relay that has no moving parts; instead, the solid-state relay uses the electrical and optical properties of solid-state semiconductors to perform its input-to-output isolation and switching functions. As non-limiting examples, the solid-state relay includes a MOS-controlled thyristor (MCT), a gallium nitride (GaN) field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), a silicon carbide junction field effect transistor (SiC JFET), an insulated gate bipolar transistor (IGBT), or any other suitable low-loss device with suitable voltage and current ratings.

[0101] The reconfigurable battery system 100 of the present disclosure provides flexible and fast charging of a battery system, such as can be used on an electrified vehicle (e.g., a hybrid vehicle or an electric vehicle). By adopting the reconfigurable battery system 100, the charging time can be minimized when connected to a high-power direct current (DC) fast charging station (not shown). The voltage of the high-power DC fast charging station can be 800 volts. The charging station includes a charging port capable of supplying a DC voltage or an alternating current (AC) voltage or both to the reconfigurable battery system 100 via a charging socket 36. The charging socket 36 is configured to receive a charging port to charge the reconfigurable battery system 100, and can receive AC charging power and / or DC charging power. In addition, the charging socket 36 can be configured to communicate with the charging station directly or through a charging port. In this way, the charging socket 36 can receive and send communication and port verification signals from the charging port.

[0102] Figure 2 and 3 The electrical arrangement and physical layout of the multi-switch device 40 are shown, including a power semiconductor device S1 50, a power semiconductor device S2 60, and a power semiconductor device S3 70, which are electrically connected in series between a first power supply terminal 46' and a second power supply terminal 49'. When arranged as a MOSFET device, the power semiconductor device S1 50 includes a drain 51, a source 52, and a gate 53; the power semiconductor device S2 60 includes a drain 61, a source 62, and a gate 63; and the power semiconductor device S3 70 includes a drain 71, a source 72, and a gate 73. The first power node 47' is disposed between the power semiconductor device S1 50 and the power semiconductor device S2 60, and the second power node 48' is disposed between the power semiconductor device S2 60 and the power semiconductor device S3 70. In one embodiment, and as described with reference to Figure 1 and 2 As described, the power semiconductor device S1 50 is arranged to electrically connect HV+ 32 and the anode 12 of the first battery group 10 at the first power node 47'. The power semiconductor device S3 70 is arranged to electrically connect the cathode 21 of the second battery group 20 and HV- 34 at the second power node 48'. The power semiconductor device S2 60 is arranged to electrically connect the anode 12 of the first battery group 10 and the cathode 21 of the second battery group 20. The first power supply terminal 46' is electrically connected to HV+ 32, and the second power supply terminal 49' is electrically connected to HV- 34.

[0103] The multi-switch device 40 is contained in a housing (not shown) configured to hold and encapsulate the hardware and may be made in whole or in part of an electrically insulating and rigid material, such as a rigid polymer material. Due to the configuration described herein, the mass of the multi-switch device 40 does not exceed 400 grams.

[0104] Reference Figure 2 and 3 As shown, the multi-switch device 40 includes a substrate 41, which has mounting holes on opposite sides thereof. The substrate 41 has a maximum thickness BT between two millimeters and three millimeters to minimize the overall size of the multi-switch device 40. In addition, the substrate 41 has a substantially planar shape and is therefore a flat configuration. In addition, the substrate 41 can be made of a thermally conductive material, such as a metal or a metal-based composite material, in whole or in part. For example, the substrate 41 can be made of copper, aluminum, molybdenum, or an alloy thereof, or a metal-based composite material (such as AlSiC or copper-graphite foam), in whole or in part, and can be mounted to a heat sink. The substrate 41 can include a pin fin of an optimal shape.

[0105] The multi-switch device 40 includes an electrical insulation layer 42 disposed on a substrate 41. In one embodiment, the electrical insulation layer 42 is also thermally conductive. The electrical insulation layer 42 may be made of ceramic or polymer materials in whole or in part. Suitable ceramic materials for the electrical insulation layer 42 include, but are not limited to, aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum silicon carbide (AlSiC), silicon nitride (Si3N4), diamond, gallium oxide, etc. The polymer material may include polyester film, Kapton, etc.

[0106] The multi-switch device 40 may include a solder layer (not shown) disposed between the substrate 41 and the electrical insulating layer 42 to connect the substrate 41 to the electrical insulating layer 42. The term "solder" refers to a low melting point alloy, particularly an alloy based on lead and tin or (for higher temperatures) based on brass or silver, for connecting less fusible metals. The solder layer is disposed directly on the substrate 41 to facilitate and enhance the connection between the solder layer and the substrate 41. Each of the substrate 41, the electrical insulating layer 42, and the solder layer has a planar shape to minimize the size of the multi-switch device 40 connected.

[0107] The multi-switch device 40 also includes a metal sheet (not shown) directly coupled to the electrically insulating layer 42 to form a directly bonded substrate. The thickness of the directly bonded substrate is between 0.1 mm and 0.8 mm to minimize the size of the multi-switch device 40. The metal sheet can be directly bonded to the electrically insulating and thermally conductive layer to form a directly bonded substrate. The metal sheet can be made of copper in whole or in part, and thus form a directly bonded copper (DBC) substrate together with the electrically insulating layer 42. The metal sheet can be made of aluminum in whole or in part to form a directly bonded aluminum (DBA) substrate together with the electrically insulating layer 42. The metal sheet can be directly coupled (and directly disposed on) the solder layer to enhance the structural integrity of the multi-switch device 40. In this way, the metal sheet is disposed on top of the electrically insulating layer 42 (e.g., a ceramic layer). In other words, the metal sheet is bonded to the electrically insulating layer 42.

[0108] The multi-switch device 40 includes a first conductive trace (first power trace) 46, a second conductive trace (second power trace) 47, a third conductive trace (third power trace) 48, and a fourth conductive trace (fourth power trace) 49. The first power trace 46 includes a first power terminal 46', the second power trace 47 includes a first power node 47', the third power trace 48 includes a second power node 48', and the fourth power trace 49 includes a second power terminal 49'. The first power trace 46, the second power trace 47, the third power trace 48, and the fourth power trace 49 are directly disposed on the electrical insulation layer 42 to minimize the size occupied by the multi-switch device 40.

[0109] The first power trace 46, the second power trace 47, the third power trace 48 and the fourth power trace 49 are directly disposed on the electrical insulation layer 42 and directly bonded or otherwise fixed to the electrical insulation layer 42 to enhance the structural integrity of the multi-switch device 40. The first power trace 46, the second power trace 47, the third power trace 48 and the fourth power trace 49 each have a planar shape to minimize their size. The first power trace 46, the second power trace 47, the third power trace 48 and the fourth power trace 49 are each made of a metal material in whole or in part, such as copper or aluminum or an alloy thereof.

[0110] The multi-switch device 40 also includes a first gate signal conductor 56 and an associated first gate signal terminal 56', a first source signal conductor 57 and an associated first source signal terminal 57'; a second gate signal conductor 66 and an associated second gate signal terminal 66', a second source signal conductor 67 and an associated second source signal terminal 67'; a third gate signal conductor 76 and an associated third gate signal terminal 76', and a third source signal conductor 77 and an associated third source signal terminal 77'; all of which are directly disposed on the electrically insulating layer 42, are made in whole or in part of a metal material, such as copper or aluminum or an alloy thereof, and are directly bonded to the electrically insulating layer 42 (e.g., a ceramic layer).

[0111] The control inputs delivered via the signal conductors 56 , 57 , 66 , 67 , 76 , 77 draw near zero power (ie, less than 0.5 Watts) to maintain the multi-switch device 40 in either the ON state or the OFF state.

[0112] The multi-switch device 40 includes a plurality of power semiconductor devices, including a first group of power semiconductor devices 50, a second group of power semiconductor devices 60, and a third group of power semiconductor devices 70. In one embodiment, each power semiconductor device is configured as a metal oxide semiconductor field effect transistor (MOSFET) and includes a source terminal S, a gate terminal G, and a drain terminal D. This includes a first group of power semiconductor devices 50, each power semiconductor device 50 having a source terminal S 52, a gate terminal G 53, and a drain terminal D 51. This includes a second group of power semiconductor devices 60, each having a source terminal S 62, a gate terminal G 63, and a drain terminal D 61. This includes a third group of power semiconductor devices 50, each power semiconductor device 50 having a source terminal S 72, a gate terminal G 73, and a drain terminal D 71. In one embodiment, each power semiconductor device has a minimum area of ​​20 square millimeters to share and deliver a current of 400 amperes.

[0113] The first group of power semiconductor devices 50 is disposed directly on the first power trace 46 to facilitate or control current flow between the first power trace 46 and the second power trace 47 via a first electrical junction 55 .

[0114] The second set of power semiconductor devices 60 is disposed directly on the second power trace 47 to facilitate or control current flow between the second power trace 47 and the third power trace 48 via a second electrical junction 65 .

[0115] The third group of power semiconductor devices 70 is disposed directly on the third power trace 48 to facilitate or control current flow between the third power trace 48 and the fourth power trace 49 via a third electrical junction 75 .

[0116] Each of the first, second and third electrical bonds 55, 65, 75 may be made of single or multiple high current aluminum or copper ribbon bonds or foil bonds to minimize parasitic inductance and resistance.

[0117] The depicted embodiment shows an amount of eight of a first group of power semiconductor devices 50 arranged in parallel, an amount of eight of a second group of power semiconductor devices 60 arranged in parallel, and an amount of eight of a third group of power semiconductor devices 70 arranged in parallel, each of the multiple switching devices 40 may include between four and sixteen (each having a rated voltage from 650 volts to 1200 volts) to deliver current, thereby enhancing scalability.

[0118] Each power semiconductor device includes a semiconductor material such as silicon, silicon carbide, gallium oxide and gallium nitride, graphene, or diamond.

[0119] The power semiconductor devices are arranged in a predetermined pattern to maintain substantially equal current and temperature distribution. The spacing and terminal positions are selected to maintain substantially equal current and temperature distribution therebetween. In one embodiment, each power semiconductor device has a resistance of less than 3.5 to 4.5 m-Ωcm 2 The placement of the power semiconductor devices and the pattern of the directly bonded substrate are selected to achieve equal current distribution and low parasitic inductance. The multi-switch device 40 may include a plurality of damping resistors, each damping resistor electrically connected to the gate terminal of a corresponding one of the power semiconductor devices in series to prevent or at least minimize power oscillations. The power semiconductor devices are electrically connected in parallel to achieve a scalable current rating (e.g., multiples of 100A), and the multi-switch device 40 includes an electrically insulating layer 42 (e.g., a ceramic layer) having a predetermined thermal stack height and pattern. For optimal thermal management, the spacing P between adjacent power semiconductor devices is greater than 1 mm and less than 3 mm. The term "pitch" refers to the distance between an edge of one of the power semiconductor devices and the nearest edge of an adjacent one of the power semiconductor devices.

[0120] The power semiconductor device may be capable of blocking a voltage DC between 650 volts and 1200 volts (e.g., at least 1200 volts) and may have different stack lengths. In this way, the multi-switch device 40 can continuously deliver a scalable current in the ON state with a low ON state resistance. The multi-switch device 40 includes power semiconductor devices electrically connected in parallel for scalability with an isolation resistance greater than 50 Mohm and a minimum package size of different stack lengths. The electrical insulation layer 42 (e.g., a ceramic layer) may have a predetermined thermal stack height and pattern to provide the required thermal capacity.

[0121] The gate terminal 53 of each first power semiconductor device 50 is electrically connected to the first gate signal terminal 56' via the first gate signal conductor 56, the gate terminal 63 of each second power semiconductor device 60 is electrically connected to the second gate signal terminal 66' via the second gate signal conductor 66, and the gate terminal 73 of each third power semiconductor device 70 is electrically connected to the third gate signal terminal 76' via the third gate signal conductor 76.

[0122] The first, second and third gate signal terminals 56 ′, 66 ′ and 76 ′ are connected to the switch controller 45 (refer to Figure 1 The multi-switch device 40 may optionally include one or more thermistors (not shown) directly connected to the directly bonded substrate to measure the temperature of the multi-switch device 40.

[0123] The multi-switch device 40 has an OFF state and an ON state. Due to its configuration, the multi-switch device 40 is capable of blocking at least 650 to 1200 volts in a single direction during the OFF state. Due to its configuration, the multi-switch device 40 continuously delivers at least 400 amperes of direct current with a voltage drop of less than 1V during the ON state. Due to its configuration, the multi-switch device 40 can have a mass equal to or less than 400 grams and an on / off time of less than 10 microseconds. Due to its configuration, the multi-switch device 40 has a maximum width of 55 to 65 mm, a maximum length of 65 mm, and a maximum height of 25 mm, thereby minimizing the size of the multi-switch device 40. Due to this configuration, the multi-switch device 40 has an isolation resistance greater than 50 megohms (MΩ). These concepts provide an architecture that includes a layout of a power semiconductor device in such a way that it functions as three power semiconductor devices, but under a single housing, only a minimum of four power terminals are used, thereby saving packaging space and cost.

[0124] Figure 4 and 5 The electrical arrangement and physical layout of another embodiment of the multi-switch device 140 are shown, including a power semiconductor device S1 150, a power semiconductor device S2 160, a power semiconductor device S3 170, and a power semiconductor device S4 180, which are electrically connected in series between a first power supply terminal 146' and a second power supply terminal 143'. When arranged as a MOSFET device, the power semiconductor device S1 150 includes a drain 151, a source 152, and a gate 153; the power semiconductor device S2 160 includes a drain 161, a source 162, and a gate 163; the power semiconductor device S3 170 includes a drain 171, a source 172, and a gate 173, and the power semiconductor device S4 180 includes a drain 181, a source 182, and a gate 183. A first power node 147 ′ is disposed between power semiconductor device S1 150 and power semiconductor device S2 160 , a second power node 148 ′ is disposed between power semiconductor device S2 160 and power semiconductor device S3 170 , and a third power node 149 ′ is disposed between power semiconductor device S3 170 and power semiconductor device S4 180 .

[0125] When the multi-switch device 140 is applied to the reference Figure 1 and Figure 4When describing the reconfigurable battery system 100, the power transistor S1 150 is arranged to electrically connect HV+ 32 and the anode 12 of the first battery pack 10 at the first power node 147'. The power transistor S4 180 is arranged to electrically connect the cathode 21 of the second battery pack 20 and HV- 34 at the third power node 149'. The power transistor S2 160 and the power transistor S3 170 are arranged to electrically connect the anode 12 of the first battery pack 10 and the cathode 21 of the second battery pack 20. The first power terminal 146' is electrically connected to HV+ 32, and the second power terminal 143' is electrically connected to HV- 34.

[0126] This arrangement provides bidirectional current blocking via power semiconductor devices S2 160 and S3 170 during series charging of the first and second battery packs 10 and 20 .

[0127] The multi-switch device 140 is contained within a housing (not shown) that is configured to hold and enclose the hardware and may be made in whole or in part of an electrically insulating and rigid material, such as a rigid polymer material.

[0128] Reference again Figure 4 and 5 , the multi-switch device 140 includes a substrate 141 having mounting holes on opposite sides thereof. The substrate 141 has a maximum thickness BT between two millimeters and three millimeters to minimize the overall size of the multi-switch device 140. In addition, the substrate 141 has a substantially planar shape and thus has a flat configuration. In addition, the substrate 141 may be made in whole or in part of a thermally conductive material, such as a metal or a metal-based composite material. For example, the substrate 141 may be made in whole or in part of copper, aluminum, molybdenum, or an alloy thereof, or a metal-based composite material, such as AlSiC or foamed copper, and may be mounted to a heat sink. The substrate 141 may preferably have nail-shaped fins.

[0129] The multi-switch device 140 includes an electrically insulating layer 142 disposed on a substrate 141. In one embodiment, the electrically insulating layer 142 is also thermally conductive. The electrically insulating layer 142 may be made in whole or in part of a ceramic material. Suitable ceramic materials for the electrically insulating layer 142 include, but are not limited to, aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum silicon carbide (AlSiC), silicon nitride (Si3N4), diamond, gallium oxide, and the like.

[0130] The multi-switch device 140 may include a solder layer (not shown) disposed between the substrate 141 and the electrical insulation layer 142 to connect the substrate 141 to the electrical insulation layer 142. The term "solder" refers to a low melting point alloy, particularly an alloy based on lead and tin or (for higher temperatures) based on brass or silver, for connecting less fusible metals. The solder layer is disposed directly on the substrate 141 to facilitate and enhance the connection between the solder layer and the substrate 141. Each of the substrate 141, the electrical insulation layer 142, and the solder layer has a planar shape to minimize the size of the multi-switch device 140 connected.

[0131] The multi-switch device 140 also includes a metal sheet (not shown) directly coupled to the electrical insulating layer 142 to form a directly bonded substrate. The thickness of the directly bonded substrate is between 0.1 mm and 0.8 mm to minimize the size of the multi-switch device 140. The metal sheet can be directly bonded to the electrical insulating and thermally conductive layer to form a directly bonded substrate. The metal sheet can be made of copper in whole or in part, and thus form a directly bonded copper (DBC) substrate together with the electrical insulating layer 142. The metal sheet can be made of aluminum in whole or in part to form a directly bonded aluminum (DBA) substrate together with the electrical insulating layer 142. The metal sheet can be directly coupled (and directly disposed on) the solder layer to enhance the structural integrity of the multi-switch device 140. In this way, the metal sheet is disposed between the solder layer and the electrical insulating layer 142 (e.g., a ceramic layer). In other words, the metal sheet is sandwiched between the solder layer and the electrical insulating layer 142.

[0132] The multi-switch device 140 includes a first conductive trace (first power trace) 146, a second conductive trace (second power trace) 147, a third conductive trace (third power trace) 148, a fourth conductive trace (fourth power trace) 149, and a fifth conductive trace (fifth power trace) 143. The first power trace 146 includes a first power terminal 146', the second power trace 147 includes a first power node 147', the third power trace 148 includes a second power node 148', the fourth power trace 149 includes a third power node 149', and the fifth power trace 143 includes a second power terminal 143'. The first power trace 146, the second power trace 147, the third power trace 148, the fourth power trace 149, and the fifth power trace 143 are directly disposed on the electrical insulation layer 142 to minimize the size occupied by the multi-switch device 140.

[0133] The first power trace 146, the second power trace 147, the third power trace 148, the fourth power trace 149, and the fifth power trace 143 are directly disposed on the electrical insulation layer 142 and directly bonded or otherwise fixed to the electrical insulation layer 142 to enhance the structural integrity of the multi-switch device 140. The first power trace 146, the second power trace 147, the third power trace 148, the fourth power trace 149, and the fifth power trace 143 each have a planar shape to minimize their size. The first power trace 146, the second power trace 147, the third power trace 148, the fourth power trace 149, and the fifth power trace 143 are each made of a metal material (e.g., copper or aluminum or an alloy thereof) in whole or in part.

[0134] The multi-switch device 140 also includes a first gate signal conductor 156 and an associated first gate signal terminal 156', a first source signal conductor 157 and an associated first source signal terminal 157'; a second gate signal conductor 166 and an associated second gate signal terminal 166', a second source signal conductor 167 and an associated second source signal terminal 167'; a third gate signal conductor 176 and an associated third gate signal terminal 176', and a third source signal conductor 177 and an associated third source signal terminal 177'; and a fourth gate signal conductor 186 and an associated fourth gate signal terminal 186', a fourth source signal conductor 187 and an associated fourth source signal terminal 187', all of which are directly disposed on the electrically insulating layer 142, made in whole or in part of a metallic material (such as copper or aluminum), and directly bonded to the electrically insulating layer 142 (e.g., a ceramic layer).

[0135] The control input delivered via the signal conductor 120 draws near zero power (ie, less than 0.5 Watts) to maintain the multi-switch device 140 in either the ON state or the OFF state.

[0136] The multi-switch device 140 includes a plurality of power semiconductor devices, including a first group of power semiconductor devices 150, a second group of power semiconductor devices 160, a third group of power semiconductor devices 170, and a fourth group of power semiconductor devices 180. In one embodiment, each power semiconductor device is configured as a metal oxide semiconductor field effect transistor (MOSFET) and includes a source terminal S, a gate terminal G, and a drain terminal D. This includes a first group of power semiconductor devices 150, each power semiconductor device 150 having a source terminal S 152, a gate terminal G 153, and a drain terminal D 151. This includes a second group of power semiconductor devices 160, each power semiconductor device 160 having a source terminal S 162, a gate terminal G 163, and a drain terminal D 161. This includes a third group of power semiconductor devices 150, each power semiconductor device 150 having a source terminal S 172, a gate terminal G 173, and a drain terminal D 171. This includes a fourth group of power semiconductor devices 180, each having a source terminal S 182, a gate terminal G 183, and a drain terminal D 181. In one embodiment, each power semiconductor device has a minimum area of ​​20 square millimeters to share and deliver 1400A of current.

[0137] The first group of power semiconductor devices 150 is disposed directly on the first power trace 146 to facilitate or control current flow between the first power trace 146 and the second power trace 147 via a first electrical junction 155 .

[0138] The second group of power semiconductor devices 160 is disposed directly on the second power trace 147 to facilitate or control current flow between the second power trace 147 and the third power trace 148 via a second electrical junction 165 .

[0139] The third group of power semiconductor devices 170 is disposed directly on the third power trace 148 to facilitate or control current flow between the third power trace 148 and the fourth power trace 149 via a third electrical junction 175 .

[0140] A fourth group of power semiconductor devices 180 is disposed directly on the fourth power trace 149 to facilitate or control current flow between the fourth power trace 149 and the fifth power trace 143 via a fourth electrical junction 185 .

[0141] Each of the first, second, third and fourth electrical bonds 155, 165, 175 and 185 may be made of a high current aluminum or copper ribbon bond or foil bond to minimize parasitic inductance and resistance.

[0142] The depicted embodiment shows an amount of eight of a first group of power semiconductor devices 150 arranged in parallel, an amount of eight of a second group of power semiconductor devices 160 arranged in parallel, an amount of eight of a third group of power semiconductor devices 170 arranged in parallel, and an amount of eight of a fourth group of power semiconductor devices 180 arranged in parallel, and each of the multiple switching devices 140 may include four to sixteen (each having a rated voltage from 650 volts to 1200 volts) to deliver current, thereby enhancing scalability.

[0143] These concepts provide an architecture that includes the layout of a power semiconductor device in such a way that it functionally operates as three power semiconductor devices, but under a single housing, requiring only a minimum of four terminals, thereby saving packaging space and cost.

[0144] The detailed description and the accompanying drawings or figures are support and description of the present teaching, but the scope of the present teaching is limited only by the claims. Although some best modes and other embodiments for implementing the present teaching have been described in detail, there are various alternative designs and embodiments for practicing the present teaching defined in the appended claims.

Claims

1. An electronic solid-state switch assembly comprising: substrate; an electrically insulating layer secured to the substrate; a first power trace secured to the electrically insulating layer, wherein the first power trace includes a positive power terminal; a second power trace secured to the electrically insulating layer, wherein the second power trace includes a first power node; a third power trace secured to the electrically insulating layer, wherein the third power trace includes a second power node; a fourth power trace secured to the electrically insulating layer, wherein the fourth power trace includes a negative power terminal; a first set of power semiconductor devices arranged on the first power trace to control power flow between the first power trace and the second power trace via a first plurality of electrical junctions; a second set of power semiconductor devices arranged on the second power trace to control power flow between the second power trace and the third power trace via a second plurality of electrical junctions; a third group of power semiconductor devices arranged on the third power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions; a first signal conductor secured to the electrically insulating layer between the first and second power traces, wherein the first signal conductor communicates with the first set of power semiconductor devices; a second signal conductor secured to the electrically insulating layer between the second and third power traces, wherein the second signal conductor communicates with the second set of power semiconductor devices; and A third signal conductor is secured to the electrically insulating layer between the third and fourth power traces, wherein the third signal conductor communicates with the third group of power semiconductor devices.

2. The electronic solid-state switch assembly of claim 1, wherein: The first, second, third and fourth power traces include electrically conductive planar elements that are electrically isolated on the substrate.

3. The electronic solid-state switch assembly of claim 2, wherein: The first, second, third and fourth power traces further include electrically conductive rectangular planar elements arranged in parallel and electrically isolated on the substrate.

4. The electronic solid-state switch assembly of claim 2, wherein: The conductive planar elements of the first, second, third and fourth power traces are made of a metallic material selected from the group consisting of: copper, aluminum and alloys thereof.

5. The electronic solid-state switch assembly of claim 1, wherein: The electrically insulating layer is thermally conductive.

6. The electronic solid state switch assembly of claim 1 further comprising a heat sink thermally connected to the substrate.

7. The electronic solid-state switch assembly of claim 1, wherein: Each of the first, second, and third groups of power semiconductor devices is configured to block electrical power having a magnitude of 650 volts to 1200 volts.

8. The electronic solid-state switch assembly of claim 1, wherein: The electronic solid-state switch assembly is configured to continuously deliver at least 400 amperes of direct current with a voltage drop of less than 1 volt when controlled to a conductive state.

9. The electronic solid-state switch assembly of claim 1, wherein: The thickness of the substrate is between two millimeters and three millimeters, a first group of power semiconductor devices arranged on the first power trace are electrically connected in parallel to each other, a second group of power semiconductor devices arranged on the second power trace are electrically connected in parallel to each other, and a third group of power semiconductor devices arranged on the third power trace are electrically connected in parallel to each other.

10. The electronic solid-state switch assembly of claim 1, further comprising a solder layer disposed between the substrate and the electrically insulating layer, wherein: The electrically insulating layer comprises a ceramic material, and wherein the substrate comprises copper.

11. The electronic solid-state switch assembly of claim 1, wherein: The first, second, third and fourth power traces include a metallic material selected from the group consisting of: copper, aluminum and alloys thereof.

12. The electronic solid-state switch assembly of claim 1, wherein: The first, second and third groups of power semiconductor devices include metal oxide silicon field effect transistor devices (MOSFETs).

13. A reconfigurable battery system comprising: A high voltage bus, comprising a positive high voltage bus and a negative high voltage bus; a first battery pack and a second battery pack electrically connected between the positive high voltage bus and the negative high voltage bus; and An electronic solid-state switch assembly comprising: a first power trace including a positive power supply terminal, a second power trace including a first power node, a third power trace including a second power node, and a fourth power trace including a negative power supply terminal; wherein the positive power supply terminal of the electronic solid-state switch assembly is electrically connected to the positive high voltage bus; wherein the first power node of the electronic solid-state switch assembly is electrically connected to the anode of the first battery pack; wherein the second power node of the electronic solid-state switch assembly is electrically connected to the cathode of the second battery pack; wherein the negative power supply terminal of the electronic solid-state switch assembly is electrically connected to the negative high voltage bus; wherein the cathode of the first battery group is electrically connected to the negative high voltage bus; wherein the anode of the second battery pack is electrically connected to the positive high voltage bus; and Wherein, the electronic solid-state switch component comprises: substrate, an electrically insulating layer secured to the substrate, a first set of power semiconductor devices arranged to control power flow between the first power track and the second power track, a second set of power semiconductor devices arranged to control power flow between the second power trace and the third power trace, and a third group of power semiconductor devices arranged to control power flow between the third power track and the fourth power track, a first plurality of signal conductors secured to the electrically insulating layer; a first plurality of electrical junctions electrically connecting the first plurality of signal conductors to the first set of power semiconductor devices; a second plurality of signal conductors secured to the electrically insulating layer; a second plurality of electrical junctions electrically connecting the second plurality of signal conductors to the second set of power semiconductor devices; a third plurality of signal conductors secured to the electrically insulating layer; and A third plurality of electrical bonds electrically connects the third plurality of signal conductors to the third group of power semiconductor devices.

14. The reconfigurable battery system according to claim 13, wherein: The reconfigurable battery system is deployed to supply power to an electrified powertrain system.

15. The reconfigurable battery system according to claim 13, wherein: The first, second, third and fourth power traces include electrically conductive planar elements that are electrically isolated on the substrate.

16. The reconfigurable battery system according to claim 15, wherein: The first, second, third and fourth power traces further include electrically conductive rectangular planar elements arranged in parallel and electrically isolated on the substrate.

17. The reconfigurable battery system according to claim 16, wherein: The conductive planar elements of the first, second, third and fourth power traces are made of a metallic material selected from the group consisting of copper, aluminum and alloys thereof.

18. The reconfigurable battery system of claim 13, wherein: Each of the first, second, and third groups of power semiconductor devices is configured to block electrical power having a magnitude of 650 volts to 1200 volts.

19. An electronic solid-state switch assembly comprising: substrate; an electrically insulating layer secured to the substrate; a first power trace secured to the electrically insulating layer, wherein the first power trace includes a positive power terminal; a second power trace secured to the electrically insulating layer, wherein the second power trace includes a first power node; a third power trace secured to the electrically insulating layer, wherein the third power trace includes a second power node; a fourth power trace secured to the electrically insulating layer, wherein the fourth power trace includes a third power node; a fifth power trace secured to the electrically insulating layer, wherein the fifth power trace includes a negative power terminal; a first set of power semiconductor devices arranged on the first power trace to control power flow between the first power trace and the second power trace via a first plurality of electrical junctions; a second set of power semiconductor devices arranged on the second power trace to control power flow between the second power trace and the third power trace via a second plurality of electrical junctions; a third group of power semiconductor devices arranged on the third power trace to control power flow between the third power trace and the fourth power trace via a third plurality of electrical junctions; a fourth group of power semiconductor devices arranged on the fourth power trace to control power flow between the fourth power trace and the fifth power trace via a fourth plurality of electrical junctions; a first signal conductor secured to the electrically insulating layer between the first and second power traces, wherein the first signal conductor communicates with the first set of power semiconductor devices; a second signal conductor secured to the electrically insulating layer between the second and third power traces, wherein the second signal conductor communicates with the second set of power semiconductor devices; a third signal conductor secured to the electrically insulating layer between the third and fourth power traces, wherein the third signal conductor communicates with the third group of power semiconductor devices; and A fourth signal conductor is secured to the electrically insulating layer between the fourth and fifth power traces, wherein the fourth signal conductor communicates with the fourth group of power semiconductor devices.

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