Line discharge circuit with low power components

Abstract

The present invention discloses a control circuit, which includes a discharge circuit, a control logic component and an output terminal. The output terminal is communicatively coupled to a control terminal of a power transistor. The control circuit also includes an input terminal communicatively coupled to an input terminal of the transistor. In a discharge operation mode, the control logic component is configured to provide a control terminal voltage to the control terminal of the power transistor via the output terminal. The control terminal voltage is configured to linearly operate the power transistor to dissipate energy stored in a capacitor connected to the input terminal of the power transistor / in a discharge mode, the discharge circuit is configured to receive a discharge current from the output terminal of the power transistor and dissipate residual energy not dissipated by the power transistor.

Description

[0001] Related patent applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 806,663, filed on February 15, 2019, the contents of which are hereby incorporated in their entirety. Technical Field

[0003] The present disclosure relates to providing power in electronic devices, and more particularly, to a line discharge circuit having low power components. Background Art

[0004] Many electronic devices use power supplies. Such power supplies may be located outside or inside the electronic device. The power supply may include a voltage regulator. The voltage regulator may be configured to generate a constant output voltage. The output voltage may be a direct current (DC) voltage. The output voltage may be generated using an input voltage. The voltage regulator may be configured to try to maintain a constant output voltage even if the input voltage or the load attached to the voltage regulator changes. If the output voltage is less than the input voltage, the voltage regulator may be said to be implemented as a buck converter or to operate in buck mode. If the output voltage is greater than the input voltage, the voltage regulator may be said to be implemented as a boost converter or to operate in boost mode. The voltage regulator may be implemented as a buck-boost converter, wherein the voltage regulator may operate in buck mode, boost mode, or in a buck-boost mode in which both the buck component and the boost component are in operation.

[0005] The capacitor may be formed at the input or output of the power supply. Some solutions may dissipate the charge accumulated in the capacitor by linear solutions such as constant current discharge or resistor discharge. However, such solutions may generate a large amount of heat energy, thereby requiring additional heat dissipation solutions to handle the heat energy generated by the dissipated capacitor. Other solutions may include a regenerative solution, in which the current that discharges the charge accumulated in the output capacitor is directed from the output capacitor to the input capacitor, or vice versa. However, since there may be large changes in the input voltage based on the capacitor, such solutions are more complicated. Still other solutions may include loss switching, in which the low-side output switch of the buck-boost regulator can be turned on and off to dissipate the charge accumulated in the output capacitor. However, such solutions may require very low frequencies to allow the inductor of the regulator to charge and discharge without becoming saturated.

[0006] As described above, embodiments of the present disclosure overcome various disadvantages of other solutions for discharging the charge accumulated in the input and / or output capacitance of the regulator. Embodiments of the present disclosure may include a power regulator that reduces the area required to dissipate power on the die. Embodiments of the present disclosure may avoid the need for tightly coupled thermal protection. Embodiments of the present disclosure may avoid significant increases in input voltage and operate without saturating the inductor. Embodiments of the present disclosure may operate without the need for additional pins on the semiconductor device that implements the power regulator. Summary of the invention

[0007] Embodiments of the present disclosure include a control circuit. The control circuit may include a discharge circuit. The discharge circuit may be implemented by any suitable combination of analog and digital circuits. The control circuit may include a control logic component. The control circuit may be implemented by any suitable combination of analog circuits, digital circuits, or instructions executed by a processor. The control circuit may include a first output terminal, the first output terminal being communicatively coupled to a control terminal of a first power transistor. The first power transistor may include the control terminal, a first terminal, and a second terminal. The first power transistor may be implemented by any suitable transistor. The control circuit may also include an input terminal, the input terminal being communicatively coupled to the second terminal of the first power transistor. The control logic component is configured to provide a first control terminal voltage to the control terminal of the first power transistor via the first output terminal in a discharge operation mode. The first control terminal voltage may be configured to operate the first power transistor in a linear operation region to dissipate energy stored in a first capacitor connected to the first terminal of the first power transistor. The discharge circuit may be configured to receive a discharge current from the second terminal of the first power transistor in a discharge operation mode, and dissipate the remaining energy not dissipated by the first power transistor.

[0008] In combination with any of the above embodiments, the first power transistor may be located outside the die including the control circuit.

[0009] In combination with any of the above embodiments, the second terminal of the first power transistor may be a source of the first power transistor.

[0010] In combination with any of the above embodiments, the discharge circuit may be configured to dissipate less energy than the first power transistor is configured to dissipate in the linear region during operation.

[0011] In conjunction with any of the above embodiments, the discharge circuit may include a current source and a pair of transistors configured to mirror a reference current to dissipate the residual energy. The current source may be connected to the pair of transistors via a switch. The switch may be driven by a discharge signal from the control logic component. The pair of transistors may include a third transistor and a fourth transistor. The third transistor may include a first terminal and a control terminal connected to the current source, and a third terminal connected to ground. The fourth transistor may include a first terminal connected to an input of the discharge circuit, a control terminal connected to the current source, and a second terminal connected to ground.

[0012] In conjunction with any of the above embodiments, the discharge circuit may include a resistor configured to dissipate excess energy. The resistor may be connected to an input of the discharge circuit. The resistor may be connected to the input of the discharge circuit via a switch. The switch may be driven by a discharge signal from the control logic component.

[0013] In conjunction with any of the above embodiments, the control circuit may include a second output communicatively coupled to a control terminal of a second power transistor, the second power transistor including a control terminal, a first terminal, and a second terminal.

[0014] The input may also be communicatively coupled to the second terminal of the second power transistor through an inductor.

[0015] The control logic component may also be configured to provide a second control terminal voltage to the control terminal of the second power transistor in a discharge operation mode, the second control terminal voltage being configured to operate the second power transistor in the linear operation region to dissipate energy stored in a second capacitor connected to the first terminal of the second power transistor. The received discharge current may include components from the output terminal of the first power transistor and from the output terminal of the second power transistor, and the discharge circuit may also be configured to dissipate remaining energy not dissipated by the second power transistor.

[0016] In conjunction with any of the above embodiments, the control circuit may include a voltage source. The control terminal voltage may be provided by the control logic component as being derived from the voltage source. The voltage source may be a separate voltage source different from the voltage source that provides the voltage to be converted or regulated by the control circuit. In another embodiment, the control circuit may include two separate such voltage sources, wherein different voltage sources are used to apply separate control terminal voltages to the first power transistor and the second power transistor.

[0017] In conjunction with any one of the embodiments described above, the control circuit may be included in a system. The system may be, for example, a microcontroller, a power regulator, a voltage regulator, a voltage source, a voltage controller, a computer, a mobile device, a tablet computer, or any other suitable electronic device. The system may include a voltage source or may be communicatively coupled to a voltage source. The control circuit may be included in a power regulator circuit in the system. The power regulator may be configured to output a specified voltage and maintain the specified voltage. The first power transistor may be an output transistor connected to the voltage output of the power regulator, or may be an input transistor connected to the voltage source of the power regulator. The output voltage may be provided to various parts of the system, such as peripherals on a microcontroller, external to the system, or provided to any suitable load. The capacitance may be an input capacitance or an output capacitance realized by a capacitor connected in parallel with the input voltage or output voltage of the power regulator.

[0018] In conjunction with any of the above embodiments, the control circuit may be connected to a fifth power transistor and a sixth power transistor. The output of the control circuit may be connected to control terminals of the fifth power transistor and the sixth power transistor. The first terminal of the fifth power transistor may be connected to an input voltage to be adjusted. The first terminal of the fifth power transistor may be connected to an adjusted output voltage. The second terminals of the fifth power transistor and the sixth power transistor may be connected together and connected to the input of the control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is an illustration of a system configured to provide power conditioning using a line discharge circuit with low power components according to an embodiment of the present disclosure.

[0020] Figure 2 is a more detailed illustration of a system configured to provide power conditioning using a line discharge circuit with low power components according to an embodiment of the present disclosure.

[0021] Figure 3 is a diagram of a specific implementation of a discharge circuit according to an embodiment of the present disclosure.

[0022] Figure 4 is a diagram of another specific implementation of a discharge circuit according to an embodiment of the present disclosure.

[0023] Figure 5 is an illustration of another system configured to provide power conditioning using a line discharge circuit with low power components according to an embodiment of the present disclosure.

[0024] Figure 6is an illustration of a method for providing power conditioning using a line discharge circuit with low power components according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Figure 1 1 is a diagram of a system 100 according to an embodiment of the present disclosure, which is configured to provide power regulation using a line discharge circuit with a low-power component. The system 100 may be implemented as, for example, a microcontroller, a mobile device, a computer, a server, or any other suitable electronic device or implemented in, for example, a microcontroller, a mobile device, a computer, a server, or any other suitable electronic device. The system 100 may be configured to provide power to various peripheral devices 106 from a source, such as a V source 102. The V source 102 may include, for example, a DC voltage source. The voltage of the V source 102 may be fixed or programmable. The peripheral device 106 may be implemented by any suitable circuit, electronic device, or subsystem requiring a power supply. The voltage required for a given peripheral device 106 may be different from the voltage available from the V source 102. Therefore, the system 100 may include a power regulator 104, which is configured to convert a voltage level VIN at the input of the power regulator from the V source 102 to a different voltage level VOUT at the output of the power regulator. The voltage from VOUT may be provided to the peripheral device 106. VIN may be provided by any suitable power source or any other suitable portion of system 100 .

[0026] The voltage regulator 104 may be configured to discharge an input capacitor or an output capacitor connected to the voltage regulator. The voltage regulator 104 may include a line discharge circuit configured to discharge an input capacitor or an output capacitor connected thereto. The discharge circuit may be implemented in the silicone or die of the voltage regulator 104. The voltage regulator 104 may implement, for example, a four-switch buck-boost power controller or regulator, a universal serial bus (USB) power controller, another USB application, or a switch mode power supply (SMPS).

[0027] The voltage regulator 104 can be implemented as a buck-boost converter and can be configured to provide a VOUT higher or lower than VIN, depending on the needs of the peripheral device 106. The voltage regulator 104 can include an inductor 110, a high-side output transistor 112, a low-side output transistor 114, a high-side input transistor 116, and a low-side input transistor 118. Transistors 112, 114, 116, 118 can be implemented as, for example, n-channel power metal oxide semiconductor field effect transistors (MOSFETs), n-channel vertical MOSFETs, bipolar junction transistors (BJTs), or any other suitable transistors or devices. In one embodiment, the voltage regulator 104 can include a control circuit 120.

[0028] The drain or first terminal of the high-side output transistor 112 may be connected to VOUT, the source or second terminal of the high-side output transistor 112 may be connected to the drain of the low-side output transistor 114, to the first side of the inductor 110, and to the input 122 of the control circuit 120. The gate (or control terminal) of the high-side output transistor 112 may be connected to the corresponding output of the control circuit 120. The source of the low-side output transistor 114 may be grounded, and the gate (or control terminal) of the low-side output transistor 114 may be connected to the corresponding output of the control circuit 120. The drain or first terminal of the high-side input transistor 116 may be connected to VOUT, the source or second terminal of the high-side input transistor 116 may be connected to the drain of the low-side input transistor 118 and the second side of the inductor 110, and the gate (or control terminal) of the high-side input transistor 116 may be connected to the control circuit 120. The source of the low-side input transistor 118 may be grounded, and the gate (or control terminal) of the low-side input transistor 118 may be connected to a corresponding output of the control circuit 120. In one embodiment, the source or second terminal of the high-side input transistor 116 may be connected to another input 124 of the control circuit 120.

[0029] The system 100 may include an input capacitor CIN 106 connected between VIN and ground of the power regulator 104. In one embodiment, CIN 106 may be included in the power regulator 104. In another embodiment, CIN 106 may be implemented external to the power regulator 104. The system 100 may include an output capacitor COUT 108 connected between VOUT and ground of the power regulator 104. In one embodiment, COUT 108 may be included in the power regulator 104. In another embodiment, COUT 108 may be implemented external to the power regulator 104.

[0030] In one embodiment, the power regulator 104 may be configured to dissipate power or charge in CIN 106. In another embodiment, the power regulator 104 may be configured to dissipate power or charge in COUT 108. Although shown as a single entity, the power regulator 104 may be implemented in a single entity or in more than one entity to dissipate power or charge in CIN 106 and COUT 108 individually or in combination.

[0031] Since other solutions may require additional power components (such as resistors or dedicated transistors that may dissipate more power), the power regulator 104 may be configured to reduce the larger area required for power dissipation compared to other solutions. Such additional power components require space on the semiconductor die for the power regulator 104 to be implemented, and may require additional heat dissipation components or heat reduction components. In addition, compared to other solutions, the power regulator 104 can be configured to dissipate power without significantly increasing the input voltage or without the risk of saturating the inductor 110. In addition, compared to other solutions, the power regulator 104 can be configured to dissipate power without additional pins. For example, in other solutions, a resistor or dedicated transistor in which power is to be dissipated may not be included in the power regulator 104, but may be connected to the power regulator 104 from the outside.

[0032] In one embodiment, the control circuit 120 can be configured to operate the power regulator 104 to dissipate power in the high-side transistors (such as the high-side transistors 112, 116) of the power regulator 104. The control circuit 120 can be configured to operate the power regulator 104 to dissipate power from COUT 108 in the high-side output transistor 112. In addition, the control circuit 120 can be configured to operate the power regulator 104 to dissipate power from CIN 106 in the high-side input transistor 116. Since the control circuit 120 is configured to discharge a capacitor present on an input line or an output line of the power regulator 104, the control circuit 120 can be a line discharge circuit. The control circuit 120 can be configured to drain power from the capacitor by connecting the respective gates (or control terminals) of the high-side transistors 112, 116 to a suitable low voltage source. The low voltage source connected to the respective gates (or control terminals) of the high-side transistors 112, 116 may cause current to be drawn from the capacitor connected to the respective drains or first terminals of the high-side transistors 112, 116. The corresponding current may flow through the channel of the respective one of the high-side transistors 112, 116 to discharge. Therefore, most of the energy to be dissipated is dissipated in the high-side transistors 112, 116, while the remaining portion of the energy is dissipated in the control circuit 120 through the input terminal 122 or the input terminal 124.

[0033] In one embodiment, the energy from CIN 106 can be dissipated in high-side transistor 116, while the remaining portion of the energy is dissipated in control circuit 120 through input 122 after passing through inductor 110. In another embodiment, the energy from CIN 106 can be dissipated in high-side transistor 116, while the remaining portion of the energy is dissipated in control circuit 120 through input 124.

[0034] In one embodiment, energy from COUT 108 may be dissipated in high-side transistor 112, while the remainder of the energy is dissipated in control circuit 120 through input 124 after passing through inductor 110. In another embodiment, energy from COUT 108 may be dissipated in high-side transistor 112, while the remainder of the energy is dissipated in control circuit 120 through input 122.

[0035] Although transistors 112, 114, 116, 118 are discussed above as being implemented by n-channel power MOSFETs, transistors 112, 114, 116, 118 may be implemented by any suitable transistor. When transistors 112, 114, 116, 118 are implemented by other types of transistors, a given connection to, for example, a drain pin may instead be to a source pin. Other specific implementations of transistors 112, 114, 116, 118 may be, without departing from the scope and teachings of the present disclosure, Figure 1 The specific arrangement of the elements in brings about other changes.

[0036] An exemplary implementation of the power regulator 104 is as follows Figures 2 to 4 is shown in the context of .

[0037] Figure 2 is a more detailed illustration of system 100 according to an embodiment of the present disclosure. Specifically, Figure 2 106 and COUT 108. The discharge mode may include operations in which CIN 106 or COUT 108 are discharged. The system 100 may enter the discharge mode at any suitable time or according to any suitable criteria. The discharge of COUT 108 may begin when the power delivery of the power regulator 104 stops. The power delivery of the power regulator 104 may stop automatically or by an external controller. The discharge of CIN 106 may begin when the V source 102 is no longer available (such as after disconnection in a system powered by USB). In the discharge mode, CIN 106, COUT 108, or both may be discharged. Even if both CIN 106 and COUT 108 are to be discharged, they may be discharged separately. In this case, CIN 106 and COUT 108 may be discharged separately in any suitable order.

[0038] The control signals for the control circuit 120 may be generated in any suitable manner. In one embodiment, the control circuit 120 may include a control logic component 222 to generate the control signals. The control logic component 222 may be configured to generate the control signals based on any suitable criteria. The control logic component 222 may be implemented in any suitable manner such as by analog circuits, digital circuits, instructions for execution by a processor, or any combination thereof. The control logic component 222 may be configured to generate control signals such as CTL1, CTL2, CTL3, CTL4, DISCHARGE (not shown), nDISCHARGE, DISCHARGE_OUT, and DISCHARGE_IN.

[0039] The control circuit 120 may include drivers 202, 204, 206, 208 connected to the gates (or control terminals) of the transistors 116, 112, 118, 114, respectively. The drivers 202, 204, 206, 208 may be driven by control signals CTL1, CTL2, CTL3, CTL4, respectively, generated by the control logic component 222. CTL1, CTL2, CTL3, CTL4 may be enabled during the normal (non-discharge) mode or operation of the power regulator 104 to alternately activate (or close) and deactivate (or open) the transistors 116, 112, 118, 114 to provide a continuous VOUT. During the discharge operation mode, the drivers 202, 204, 206, 208 may be turned off, made inoperable, or otherwise ignored. The control circuit 120 may include any suitable mechanism for causing the control signals generated by the drivers 202, 204, 206, 208 to be turned off, inoperable, or otherwise ignored. For example, the control circuit 120 may include a control signal nDISCHARGE, which may be the logical inverse of the DISCHARGE control signal (as described above, DISCHARGE is not in Figure 2 106). When logic high or connected, the DISCHARGE control signal may specify that the control circuit 120 is to operate in a discharge operation mode to deplete power from COUT 108 or CIN 106. When logic low or turned off, the DISCHARGE control signal may specify that the control circuit 120 is to operate in a normal operation mode to control transistors 116, 112, 118, 114 to provide VOUT. Thus, when logic high or turned on, the nDISCHARGE control signal may be used to enable, power, or otherwise allow drivers 202, 204, 206, 208 to issue control signals to transistors 116, 112, 118, 114. Additionally, when the control circuit 120 is to enter a discharge operation mode, the nDISCHARGE control signal may be logic low or turned off and disable the drivers 202, 204, 206, 208.

[0040] During the discharge mode of operation, the low-side transistors 118, 114 may be turned off in response to the off state of the nDISCHARGE control signal. However, during the discharge mode of operation, the high-side transistors 116, 112 may be in various operating states, depending on the control signal provided by the control circuit 120. The control circuit 120 may be configured to issue a control signal to control the gate (or control terminal) of the high-side transistors 116, 112 during the discharge mode of operation. The control circuit 120 may include any suitable number and type of components to control the gates of the high-side transistors 116, 112.

[0041] For example, the control circuit 120 may include a first voltage source 224. The first voltage source 224 may be configured to generate a logic high signal. Such a logic high signal may be, for example, five volts. The signal generated by the first voltage source 224 may be a logic high signal that is initially generated and after passing through a diode, such as diode 214. In one embodiment, the control circuit 120 may include a single instance of a voltage source, such as the first voltage source 224, that is configured to provide a gate (or control terminal) voltage to both high-side transistors 112, 116. In another embodiment, such as Figure 2 As shown, the control circuit 120 may include a second voltage source 226. The second voltage source 226 may be configured to generate a logic high signal. Such a logic high signal may be, for example, five volts. The signal generated by the voltage source 224 may be a logic high signal initially generated and after passing through a diode (such as a diode 216). In such embodiments, the first voltage source 224 may be configured to provide a gate (or control terminal) voltage to the high-side output transistor 112, and the second voltage source 226 may be configured to provide a gate (or control terminal) voltage to the high-side input transistor 116. The voltages of the first voltage source 224 and the second voltage source 226 may be the same or different, and may be independently controlled by the control logic component 222.

[0042] The control circuit 120 may include a switch S2 212 between a second voltage source 226 and a gate (or control terminal) of the high-side input transistor 116, wherein when the switch S2 212 is closed, the connection between the voltage source 226 and the gate (or control terminal) of the high-side input transistor 116 is through a diode 216. The switch S2 212 may be controlled by a control signal DISCHARGE_IN. When CIN 106 is to be discharged in a given discharge mode, DISCHARGE_IN may be enabled by the control logic component 222. The control circuit 120 may include a switch S1 210 between a first voltage source 224 and a gate (or control terminal) of the high-side output transistor 112, wherein when the switch S1 210 is closed, the connection between the voltage source 224 and the gate (or control terminal) of the high-side output transistor 112 is through a diode 214. The switch S1 210 may be controlled by a control signal DISCHARGE_OUT. When COUT 108 is to be discharged in a given discharge mode, DISCHARGE_OUT may be enabled by the control logic component 222. When DISCHARGE_IN is enabled or logic high, switch S2 212 may be enabled, and thus the voltage is directed from the second voltage source 226 to the gate (or control terminal) of the high-side input transistor 116 through the diode 216. When DISCHARGE_OUT is enabled or logic high, switch S1 210 may be enabled, and thus the voltage is directed from the first voltage source 224 to the gate (or control terminal) of the high-side output transistor 112 through the diode 214. During the discharge mode, when the high-side input transistor 116 is enabled by applying a voltage from the second voltage source 226, the capacitor CIN 106 may be discharged. During the discharge mode, when the high-side input transistor 112 is enabled by applying a voltage from the first voltage source 224, the capacitor COUT 108 may be discharged.

[0043] Control circuit 120 may use any suitable one or more discharge modes. In one embodiment, CIN 106 may be discharged during a first discharge mode. In another embodiment, COUT 108 may be discharged during a second discharge mode. In another embodiment, both CIN 106 and COUT 108 may be discharged during a third discharge mode.

[0044] During the discharge of COUT 108, current may flow from the top plate of COUT 108 into the drain or first terminal of the high-side output transistor 112. This discharge current may be represented as IDO. IDO may be directed through the input 122 to the discharge circuit 220 included in the control circuit 120. During the discharge of CIN 106, current may flow from the top plate of CIN 106 into the drain or first terminal of the high-side input transistor 116. This discharge current may be represented as IDI. IDI may be directed through the inductor 110 and then through the input 122 into the discharge circuit 220. The current directed into the discharge circuit 220 through the input 122 is shown as ID. If the discharge mode used by the control circuit 120 is to discharge only COUT 108, then ID may be equal to IDO. If the discharge mode used by the control circuit 120 is to discharge only CIN 106, then ID may be equal to IDI. If the discharge mode used by the control circuit 120 is to discharge CIN 106 and COUT 108, then ID can be equal to the sum of IDI and IDO. Alternatively, by the symmetry of the circuit, the discharge circuit 220 can be connected only to the source of the high-side input transistor 116. Then, the discharge current IDO of COUT 108 can then flow through the transistor 112, the inductor 110 and into the discharge circuit 220.

[0045] During the discharge mode, a relatively large amount of energy may be dissipated in the high-side transistors 112, 116. The voltage to be applied to the gate of the high-side transistors 112, 116 may be selected based on the expected voltage at the drain (or first terminal) and source (or second terminal) of each respective high-side transistor in the high-side transistors 112, 116. Specifically, the voltage is selected so that the high-side transistors 112, 116 operate in a linear operating region. Operation in the linear region may dissipate a large amount of discharge energy on the high-side transistors 112, 116. The specific range of the linear operating region may depend on the specific type and model of transistors used to implement the high-side transistors 112, 116. Therefore, the voltage to be selected so that the high-side transistors 112, 116 operate in the linear operating region may depend on the specific type and model of transistors used to implement the high-side transistors 112, 116. In order to provide such a voltage to be applied to the gate of the high-side transistors 112, 116, any suitable mechanism may be used. For example, the voltage sources 224, 226 may be 5V, which may be further attenuated by one or more diodes, such as diodes 214, 216, such that a particular gate (or control terminal) voltage to be applied to the high-side transistors 112, 116 will cause the high-side transistors 112, 116 to operate in a linear operating region based on their drain voltage and source voltage.

[0046] The energy to be dissipated by the high-side transistors 112, 116 during the respective discharge modes may be large compared to the amount of energy to be dissipated by the discharge circuit 220. By utilizing the high-side transistors 112, 116 to dissipate a large amount of energy from the capacitors COUT 108, CIN 106, the discharge circuit 220 may be implemented using fewer components. The discharge circuit 220 may be implemented in any suitable manner and by any suitable number, type, and combination of components. Exemplary non-limiting implementations of the discharge circuit 220 are described in Figure 3 and Figure 4 The discharge circuit 220 may be implemented in any fixed or adjustable implementation.

[0047] However, the discharge circuit 220 may be implemented with relatively few components compared to other solutions. Specifically, the discharge circuit 220 may be implemented with dissipative elements that will not generate excessive heat within the power regulator 104 or the control circuit 120. This may be advantageous compared to prior art solutions, which may require the addition of line capacitance discharge blocks with high silicon area, additional heat sinking, additional thermal protection, or other components that also increase the cost and size of the device.

[0048] For example, in Figure 2 , VOUT may be 20V. COUT 108 may be 3000pF. During the discharge mode of COUT 108, IDO may be 110mA. Therefore, the voltage to be dissipated may be 2.2W. By operating the high-side output transistor 112 in its linear operating region, the high-side output transistor 112 may be configured to dissipate 1.925W. Therefore, the voltage at the source of the high-side output transistor 112 and the voltage at the input terminal 122 may be 2.5V. Therefore, the discharge circuit 220 may only need to dissipate 275mW. Therefore, the discharge circuit 220 may be configured to dissipate less energy than the high-side output transistor 112 during the linear operation of the high-side output transistor 112. The gate (or control terminal) voltage applied to the high-side output transistor 112 may be the voltage of the first voltage source 224, 5V, minus the voltage drop on the diode 214, 0.7V, resulting in 4.3V applied to the gate (or control terminal) of the high-side output transistor 112. The combination of a gate (or control terminal) voltage of 4.3V and a source voltage of 2.5V may cause the high-side output transistor 112 to operate in the linear region of operation. Similar operations may be performed to discharge CIN 106 to dissipate a portion of the discharge energy on the high-side input transistor 116. Diodes 214, 216 and further described below Figure 5The diodes 518 may be optional. These diodes may reduce the design and production costs of the discharge circuit 220.

[0049] Figure 3 is a diagram of a specific implementation of a discharge circuit 300 according to an embodiment of the present disclosure. The discharge circuit 300 may implement the discharge circuit 220. In one embodiment, the discharge circuit 300 may receive ID from one or more of the high-side transistors 112, 116 via the input terminal 122. In another embodiment, the discharge circuit 300 may receive ID from one or more of the high-side transistors via the input terminal 124 (not shown). The ID may represent the current to be dissipated after some portion of the energy of the capacitor has been dissipated by one or more of the high-side transistors 112, 116. The discharge circuit may include a transistor arrangement. The transistor arrangement may include transistors 306, 308.

[0050] The input ID may be connected to the drain of the first transistor 308. The source of the first transistor 308 may be grounded. The discharge circuit 300 may include a second transistor 306. The gate (or control terminal) of the first transistor 308, the gate (or control terminal) of the first transistor 306, and the drain of the second transistor 306 may each be switchably connected to a current source 302. The current source 302 may be a constant current reference represented by a value IREF. When the control circuit 120 operates in the discharge mode, the current source 302 may be applied to the transistors 306, 308. Therefore, the discharge circuit 300 may include a switch S3 304. The switch S3 304 may be controlled by the DISCHARGE signal. The discharge circuit 300 may be configured to dissipate energy defined by the voltage drop of the transistors 306, 308 when the control circuit 120 operates in the discharge mode. The transistors 306, 308 may be configured to operate in a linear region during the discharge mode. The current source 302 may flow through the second transistor 306 and be multiplied in the first transistor 308 acting as a mirror transistor. In this example, if the discharge mode is to discharge COUT 108 alone, the current flowing through the first transistor 308 may be approximately 110 mA, which is the same as ID. The combination of the high-side output transistor 112 and the first transistor 308 may form a common source and common gate structure.

[0051] This exemplary implementation of the discharge circuit 300 may use only low-power components and thus dissipate a small amount of power. Therefore, this exemplary implementation of the discharge circuit 300 may be easier to integrate in a smaller silicon area or smaller implementation of the die for the control circuit 120. The discharge circuit 300 may not require thermal protection, while still effectively discharging the line voltage in many cases. For example, in USB applications, USB power delivery may have the following worst-case conditions: a 3000pF capacitor charged to 20V must be discharged to less than 0.5V in less than 600 milliseconds. Other implementations of the discharge circuit 300, such as using a resistor to dissipate energy, may be able to dissipate a peak of 6W using only the discharge circuit 300. Yet another implementation using a constant current discharge may be able to dissipate 2.2W of heat. However, due to the energy dissipation of the high-side transistors 112, 116 in the system 100, the energy dissipation of the transistors 306, 308 in the discharge circuit 300 in the range of 200mW to 300mW may be sufficient. In some cases, the energy dissipated by the high-side transistors 112 , 116 during the discharge mode may be less energy than normal operation powered by the regulator 104 , and thus additional thermal considerations may not be required.

[0052] However, if the high-side transistors 112 , 116 are implemented on the same semiconductor device or die as the discharge circuit 300 , the energy dissipation in the discharge mode may require additional thermal protection.

[0053] Figure 4 is a diagram of another specific implementation of a discharge circuit 400 according to an embodiment of the present disclosure. The discharge circuit 400 may implement the discharge circuit 220. The discharge circuit 400 may operate similarly to the discharge circuit 300. The discharge circuit 400 may include a switch S4 402 connected to a resistor 404. The switch S4 402 may be controlled by a DISCHARGE signal.

[0054] return Figure 2 , the voltage sources 224, 226 may be adjusted as needed by the control circuit 120. The voltage sources 224, 226 may be adjusted by, for example, the control logic component 222. The voltage sources 224, 226 may be dynamically adjusted to improve the accuracy of the discharge current ID so as to dissipate a specific amount of energy in the discharge circuit 200. In addition, the voltage sources 224, 226 may be configured to be dynamically adjusted to change the energy dissipation of the transistor 308 when the discharge circuit 220 is implemented by the discharge circuit 300. Such adjustments of the voltage sources 224, 226 may be performed in response to temperature changes, disturbances, or other non-ideal changes or operations of the control circuit 120.

[0055] exist Figure 2, a single instance of the discharge circuit 220 is shown, which can be configured to dissipate energy in both CIN 106 and COUT 108. However, in various embodiments, separate instances of the discharge circuit 220 can be provided in the control circuit 120 to separately dissipate energy from CIN 106 and COUT 108, each of which has a respective input to the control circuit 120. For low frequencies (such as those that may be experienced during discharge), the inductor 110 may have a negligible voltage drop. Therefore, the discharge circuit 220 is able to dissipate the energy of CIN 106 through the inductor 110, as described above.

[0056] Thus, the control circuit 120 is configured to discharge the capacitance of the power line connected to the power supply or other device. The control circuit 120 can utilize a high-side power switch (such as one of the high-side transistors 112, 116) that already exists in the power regulation solution. The control circuit 120 can be configured to utilize the existing high-side transistors 112, 116 by using such high-side transistors 112, 116 as linear power dissipators. This technology can reduce the cost of the specific implementation by reducing the silicon area dedicated to the discharge function in the form of the discharge circuit 220. This solution reduces the power of the discharge circuit 220 that is dissipated, thereby generally eliminating the need for dedicated thermal protection. This can increase the durability of the control circuit 120. This can also avoid the disadvantages of other discharge circuits by reducing the large area required to dissipate power, avoiding the need for tightly coupled thermal protection, eliminating the risk of uncontrollably increasing the input voltage, eliminating the risk of saturating the inductor 110, and not requiring additional pins to interface with external components.

[0057] Figure 5 5 is a diagram of another system 500 according to an embodiment of the present disclosure, which is configured to provide power using a line discharge circuit with low-power components. System 500 may include an application that provides power to a USB element or device. System 500 may include a VIN from a voltage source (not shown) that will be applied to a USB element or device as VOUT. The USB power switch may be provided and implemented by transistors 506, 508. VIN may be applied to the drain of transistor 506. VOUT may be provided by the drain of transistor 508. The sources of transistors 506, 508 may be connected to each other. The gates of transistors 506, 508 may be connected to the output of control circuit 510. The sources of transistors 506, 508 may then be connected to the input of control circuit 510. Input capacitor 502 may be formed on an input power line, and output capacitor 504 may be formed on an output power line. Control circuit 510 may be configured to deplete one or more of capacitors 502, 504 in a discharge mode.

[0058] The control circuit 510 can be implemented in a similar manner to the control circuit 120. The control circuit 510 can include a control logic component 522 configured to issue control signals to various parts of the control circuit 510. The control logic 522 is configured to issue a DISCHARGE signal, an nDISCHARGE signal, and a control signal CTL. When the control circuit 510 is in a discharge mode, the DISCHARGE signal can be high. When the control circuit 510 is in a normal operating mode, the nDISCHARGE signal can be high. When the control circuit 510 is in a normal operating mode, the CTL signal can be high.

[0059] During the normal operating mode, the CTL signal may be issued to the input of the buffer 512, the output of which may in turn be directed to the gates of the transistors 506, 508. The buffer 512 may also receive at its control input an nDISCHARGE signal, which during the normal operating mode (i.e., when the nDISCHARGE signal is high) may enable the buffer 512 to provide its output to the gates of the transistors 506, 508. During the normal operating mode, the DISCHARGE signal may be inactive, low, or logic zero, and thus open the switch S1 516, which would otherwise connect the voltage source 514 to the gates of the transistors 506, 508 via the diode 518.

[0060] During the discharge mode of operation, the CTL signal may be turned off (i.e., set to low). In addition, the nDISCHARGE signal may be low or logic zero (i.e., active low) and thus disable the buffer 512. Therefore, in the discharge mode of operation, the gates of the transistors 506, 508 will not receive their inputs from the buffer 512. Instead, the DISCHARGE signal may be active, high, or logic one and close the switch S1 516. The voltage source 514 may be configured to provide its value (minus the voltage drop across the diode 518, which may serve as an isolation diode) to the gates of the transistors 506, 508 when the switch S1 516 is closed. The selection of the value of the voltage source 514 and the selection of one or more diodes (such as the diode 518) may be performed so as to operate the transistors 506, 508 in the linear operating region during the discharge mode. This may result in power dissipation in the transistors 506, 508, with the remaining power being dissipated by the discharge circuit 520 of the control circuit 510 received through the input terminal 525. The discharge circuit 520 may be implemented by, for example, the discharge circuit 220 , 300 , or 400 .

[0061] For example, assume that VIN is 20V and VOUT is also 20V. Capacitor 502 may be 3000μF and capacitor 504 may be 10μF. The current flowing from capacitor 502 through transistor 506 may be given as IDI. The current flowing from capacitor 504 through transistor 508 may be given as IDO. The discharge current ID may be the sum of IDI and IDO. The discharge current ID may be directed to the discharge circuit 520 in the control circuit 510 through the input terminal 525. When the capacitors 502, 504 are charged to a given voltage, the sum of IDI and IDO may be equal to ID, and for unmatched transistors 506, 508, it is impossible to discern the individual values ​​of the current in each transistor. Once one of the capacitors 502, 504 is discharged, the voltage on the corresponding transistor decreases until it is approximately the voltage of the source, and then Rds prevents Ids from flowing. Subsequently, the Vgs of the other transistor increases (when its source is pulled down), thereby increasing its current, until at the end of the discharge, the currents tend to separate, such as 502 and 504 both have similar voltages, and discharge continues in a self-matching manner. If the power supply 514 is configured to provide 5V and the diode 518 provides a 0.7V voltage drop, the gate (or control terminal) voltage at the transistors 506, 508 will be 4.3V, and the voltage drop of the transistors 506, 508 can be 17.5V, which means that ID is applied to the discharge circuit 520 at 2.5V. At about 100mA, the gate voltage of the transistors 506, 508 can be 4.3V, and the Vgs of the transistors 506, 508 can be 1.8V. Therefore, the source of the transistors 506, 508 can be at 2.5V, and the Vds can therefore be 17.5V. The gate (or control terminal) and source voltages can cause the transistors 506, 508 to operate in the linear operating region. The combined power to be dissipated from capacitors 502, 504 may be 2.2 W. Transistors 506, 508 may dissipate 1.925 W. Discharge circuit 520 may dissipate 0.275 W.

[0062] Figure 6 is an illustration of a method 600 for providing power using a line discharge circuit with low power components according to an embodiment of the present disclosure. The method 600 may be implemented using any suitable mechanism, such as Figures 1 to 5 Method 600 may begin at any suitable point, such as at step 605. Method 600 may use Figure 6 Various steps of method 600 may be omitted, repeated, or performed in parallel with other steps of method 600. For example, steps 640 and 635 may be performed simultaneously. Method 600 may optionally be repeated or terminated according to any suitable criteria or control mechanism.

[0063] At step 605, it may be determined whether the method is to perform a discharge operation or a normal power operation in the power conditioner. Normal operation may include switching power or providing a constant power level to a load. Discharge operation may include exhausting or dissipating energy formed on line capacitance at the input, output, or both. If normal operation is used, the method 600 may proceed to step 610. If discharge operation is used, the method 600 may proceed to step 615.

[0064] At step 610, power may be provided from the source to the load. Power may be provided in any suitable manner or mode, such as buck, boost, or buck-boost. Power may continue to be provided until a criterion is met (such as time, accumulated power, or an external signal indicating that the operating mode should be changed). Method 600 may return to step 605.

[0065] At step 615, a disable signal may be sent to a power switch gate (or control terminal) selector in the regulator. The disable signal may cause normal operation of providing power from the input terminal to the output terminal to cease. In one embodiment, as described above with respect to Figure 2 and Figure 5 As described above, the disable signal can be achieved by setting nDISCHARGE to a low level.

[0066] At step 620, a voltage source may be directed to the gate of one or more high-side switches of the power regulator. The voltage source may be selected so as to operate the switches in a linear region of operation. The voltage source value may be attenuated, for example, by passing the voltage source voltage through one or more diodes and then applying the result to the gate of the switch. In one embodiment, as described above with respect to Figure 2 and Figure 5 As described above, the voltage source may be directed in response to an active high DISCHARGE signal.

[0067] At step 625 , the high-side switches receiving the voltage source to their respective gates may be operated in a linear region.

[0068] At step 630 , line capacitance on the input, output, or both may be drained by the respective high-side switches operating in their linear regions.

[0069] At step 635 , power may be dissipated in the high-side switch according to linear region operation.

[0070] At step 640 , any remaining power to be dissipated may be dissipated in an internal discharge circuit.

[0071] The output value of the voltage source may be adjusted, if necessary, at step 645. Such values ​​may be adjusted to ensure that the switch is operated in the linear region in the future, or to account for changes caused by disturbances, temperature changes, or other non-ideal conditions.

[0072] Method 600 may return to step 605, or may optionally terminate based on any suitable criteria.

[0073] Although example embodiments have been described above, other modifications and embodiments may be made by this disclosure without departing from the spirit and scope of these embodiments.

Claims

1. A control circuit, comprising: Discharge circuit; Control logic components; a first output terminal communicatively coupled to a control terminal of a first power transistor, the first power transistor comprising the control terminal, a first terminal, and a second terminal; as well as an input communicatively coupled to the second terminal of the first power transistor; Among them, in the discharge operation mode: the control logic component being configured to provide a first control terminal voltage to the control terminal of the first power transistor via the first output terminal, the first control terminal voltage being configured to operate the first power transistor in a linear operation region to dissipate energy stored in a first capacitance connected to the first terminal of the first power transistor; and The discharge circuit is configured as follows: receiving a discharge current from the second terminal of the first power transistor via the input; and The remaining energy not dissipated by the first power transistor is dissipated. 2 . The control circuit of claim 1 , wherein the first power transistor is located external to a die including the control circuit. 3 . The control circuit according to claim 1 , wherein the second terminal of the first power transistor is a source of the first power transistor. 4 .

4. The control circuit of any one of claims 1 to 2, wherein the discharge circuit is configured to dissipate less energy than the first power transistor is configured to dissipate in the linear region during operation.

5. The control circuit according to any one of claims 1 to 2, wherein the discharge circuit comprises a current source and a pair of transistors configured to mirror a reference current to dissipate excess energy.

6. The control circuit according to any one of claims 1 to 2, wherein the discharge circuit comprises a resistor configured to dissipate excess energy.

7. The control circuit of any one of claims 1 to 2, further comprising a second output terminal communicatively coupled to a control terminal of a second power transistor, the second power transistor comprising the control terminal, the first terminal, and a second terminal; in: The input is also communicatively coupled to the second terminal of the second power transistor through an inductor; and In the discharge mode of operation: The control logic component is further configured to provide a second control terminal voltage to the control terminal of the second power transistor, the second control terminal voltage being configured to operate the second power transistor in the linear operating region to dissipate energy stored in a second capacitance connected to the first terminal of the second power transistor; The received discharge current includes a component from an output terminal of the first power transistor and an output terminal of the second power transistor; and The discharge circuit is further configured to dissipate remaining energy not dissipated by the second power transistor.

8. The control circuit according to any one of claims 1 to 2, further comprising a voltage source, wherein the control terminal voltage is provided by the control logic component and originates from the voltage source.

9. A system for providing power, comprising: Voltage source; A power regulator circuit, the power regulator circuit being configured to convert a voltage from the voltage source into a voltage output, the power regulator circuit comprising: a first power transistor comprising a control terminal, a first terminal, and a second terminal; and A control circuit, the control circuit comprising: Discharge circuit; Control logic components; a first output communicatively coupled to the control terminal of the first power transistor; and an input communicatively coupled to the second terminal of the first power transistor; Among them, in the discharge operation mode: the control logic component being configured to provide a first control terminal voltage to the control terminal of the first power transistor via the first output terminal, the first control terminal voltage being configured to operate the first power transistor in a linear operation region to dissipate energy stored in a first capacitance connected to the first terminal of the first power transistor; and The discharge circuit is configured as follows: receiving a discharge current from the second terminal of the first power transistor via the input; and The remaining energy not dissipated by the first power transistor is dissipated.

10. The system of claim 9, wherein the first power transistor is external to a die including the control circuit.

11. The system of any one of claims 9 to 10, wherein the second terminal of the first power transistor is a source of the first power transistor.

12. The system of any one of claims 9 to 10, wherein the discharge circuit is configured to dissipate less energy than the first power transistor is configured to dissipate in the linear region during operation.

13. The system of any one of claims 9 to 10, wherein the discharge circuit comprises a current source and a pair of transistors configured to mirror a reference current to dissipate excess energy.

14. The system of any one of claims 9 to 10, wherein the discharge circuit comprises a resistor configured to dissipate the residual energy.

15. The system of any one of claims 9 to 10, wherein the control circuit further comprises a second output, the second output being communicatively coupled to a control terminal of a second power transistor, the second power transistor comprising the control terminal, the first terminal, and a second terminal; in: The input is also communicatively coupled to the second terminal of the second power transistor through an inductor; and In the discharge mode of operation: The control logic component is further configured to provide a second control terminal voltage to the control terminal of the second power transistor, the second control terminal voltage being configured to operate the second power transistor in the linear operating region to dissipate energy stored in a second capacitance connected to the first terminal of the second power transistor; The received discharge current includes a component from an output terminal of the first power transistor and an output terminal of the second power transistor; and The discharge circuit is further configured to dissipate remaining energy not dissipated by the second power transistor.

16. The system of any one of claims 9 to 10, wherein the control terminal voltage is provided by the control logic component and is derived from the voltage source.

17. A method of providing power, comprising: providing a first output, the first output being communicatively coupled to a control terminal of a first power transistor, the first power transistor comprising the control terminal, a first terminal, and a second terminal; providing an input communicatively coupled to the second terminal of the first power transistor; In discharge mode of operation: providing a first control terminal voltage to the control terminal of the first power transistor via the first output terminal, the first control terminal voltage being configured to operate the first power transistor in a linear operation region to dissipate energy stored in a first capacitance connected to the first terminal of the first power transistor; as well as receiving a discharge current from the second terminal of the first power transistor via the input; as well as The remaining energy not dissipated by the first power transistor is dissipated. 18 . The method of claim 17 , wherein the remaining energy that is not dissipated is less than the energy that the first power transistor is configured to dissipate in the linear region during operation.

19. The method of any one of claims 17 to 18, further comprising providing a second output communicatively coupled to a control terminal of a second power transistor, the second power transistor comprising the control terminal, the first terminal, and a second terminal; in: The input is also communicatively coupled to the second terminal of the second power transistor through an inductor; and In the discharge mode of operation: The method further includes providing a second control terminal voltage to the control terminal of the second power transistor, the second control terminal voltage being configured to operate the second power transistor in the linear operating region to dissipate energy stored in a second capacitance connected to the first terminal of the second power transistor; The received discharge current includes a component from an output terminal of the first power transistor and an output terminal of the second power transistor; and The method also includes dissipating remaining energy not dissipated by the second power transistor.

20. The method of any one of claims 17 to 18, wherein the control terminal voltage is provided by the control logic component and originates from a voltage source.

21. A method of providing power, the method comprising operating any of the systems of control circuits according to claims 1 to 16.

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