Imaging device and comparator

Abstract

The solid-state image sensor of the present invention includes: an input transistor, which is configured to output a drain voltage from the drain according to the input voltage when the input voltage input to the source is substantially consistent with a predetermined reference voltage input to the gate; and an output transistor, which is configured to output a signal indicating whether the difference between the input voltage input to the source and the drain voltage input to the gate exceeds a predetermined threshold voltage as a comparison result between the input voltage and the reference voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Japanese Priority Patent Application JP 2019-028965, filed February 21, 2019, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] The present technology relates to a solid-state image sensor. Specifically, the present technology relates to a solid-state image sensor that performs analog-to-digital conversion using a comparator. Background Art

[0004] Due to its simple structure, a single-slope analog-to-digital converter (ADC) has been used for analog-to-digital (AD) conversion in solid-state image sensors and the like. The single-slope ADC is generally composed of a comparator and a counter that counts based on the comparison result of the comparator. For example, a solid-state image sensor has been proposed that includes a p-channel metal oxide semiconductor (pMOS) transistor and an inverter arranged within the comparator, wherein the pMOS transistor has a pixel signal input to the source and a reference signal input to the gate (for example, see Patent Document 1). The pMOS transistor outputs its drain voltage as the comparison result of the pixel signal and the reference signal to the counter via the inverter.

[0005] [Citation List]

[0006] [Patent Document]

[0007] [Patent Document 1]: US 2018 / 0103222 A Summary of the Invention

[0008] [Technical Issues]

[0009] In the above-mentioned solid-state image sensor, the comparator shares the pixel circuit's power supply, thereby reducing power consumption, compared to a configuration in which the comparator has a power supply independent of the pixel circuit. However, in this connection configuration of the solid-state image sensor, when the pixel signal and the reference signal are substantially consistent, the drain voltage of the pMOS transistor varies depending on the pixel signal level. Consequently, when the pixel signal and the reference signal are substantially consistent, the timing of inversion of the comparison result may deviate from the ideal time. This inversion timing error can lead to errors or nonlinearities in the digital signal obtained by A / D conversion of the pixel signal, resulting in degradation of the image data quality.

[0010] The present technology has been made in view of the above-described circumstances, and it is desirable to suppress an error in the inversion timing of a comparison result in a solid-state image sensor that compares a reference signal and a pixel signal.

[0011] [Solution to the problem]

[0012] According to an embodiment of the present technology, an imaging device is provided, including: a pixel circuit configured to output a pixel signal; a pixel signal line connected to the pixel circuit; a reference signal generating circuit configured to output a reference signal; and a comparator, the comparator including: a first transistor, wherein the gate of the first transistor is connected to the reference signal generating circuit and the source of the first transistor is connected to the pixel signal line, and a second transistor, wherein the gate of the second transistor is connected to the drain of the first transistor and the source of the second transistor is electrically connected to the pixel signal line.

[0013] Furthermore, in one embodiment, the source of the first transistor and the source of the second transistor may be configured to receive a voltage corresponding to the pixel signal.

[0014] Furthermore, in one embodiment, the comparator may include a third transistor, wherein a drain of the third transistor is connected to the pixel signal line, and a source of the third transistor is connected to a power supply terminal.

[0015] Furthermore, in one embodiment, the gate of the third transistor can be configured to receive a bias voltage.

[0016] Furthermore, in one embodiment, the comparator may include a third transistor, wherein a gate of the third transistor is connected to a drain of the first transistor, and a source of the third transistor is connected to the pixel signal line.

[0017] Furthermore, in one embodiment, the gate of the third transistor may be connected to the drain of the third transistor.

[0018] Furthermore, in one embodiment, the bottom gate of the third transistor may be connected to the source of the third transistor.

[0019] Furthermore, in one embodiment, the comparator may include a fourth transistor, wherein a drain of the fourth transistor is connected to the pixel signal line, and a source of the fourth transistor is connected to the drain of the third transistor.

[0020] Furthermore, in one embodiment, the gate of the fourth transistor can be configured to receive a bias voltage.

[0021] Furthermore, in one embodiment, the bottom gate of the first transistor may be connected to the source of the first transistor, and the bottom gate of the second transistor may be connected to the source of the second transistor.

[0022] Furthermore, in one embodiment, the pixels may be arranged in a first substrate, and the comparator may be arranged in a second substrate bonded to the first substrate.

[0023] Furthermore, in one embodiment, the first substrate and the second substrate may be electrically connected through through silicon vias.

[0024] Furthermore, in one embodiment, the first substrate and the second substrate may be electrically connected by direct bonding.

[0025] According to another embodiment of the present technology, a comparator is provided, including: a first input terminal, which is configured to receive a pixel signal; a second input terminal, which is configured to receive a reference signal; a first transistor, wherein the gate of the first transistor is connected to the second input terminal, and the source of the first transistor is connected to the first input terminal; and a second transistor, wherein the gate of the second transistor is connected to the drain of the first transistor, and the source of the second transistor is electrically connected to the first input terminal.

[0026] Furthermore, in one embodiment, the source of the first transistor and the source of the second transistor may be configured to receive a voltage corresponding to the pixel signal.

[0027] Furthermore, in one embodiment, the comparator may include a third transistor, wherein a drain of the third transistor is connected to the first input terminal and a source of the third transistor is connected to the power supply terminal.

[0028] Furthermore, in one embodiment, the gate of the third transistor can be configured to receive a bias voltage.

[0029] Furthermore, in one embodiment, the comparator may include a third transistor, wherein a gate of the third transistor is connected to the drain of the first transistor, and a source of the third transistor is connected to the first input terminal.

[0030] Furthermore, in one embodiment, the gate of the third transistor may be connected to the drain of the third transistor.

[0031] Furthermore, in one embodiment, the bottom gate of the third transistor may be connected to the source of the third transistor.

[0032] Furthermore, in one embodiment, the comparator may include a fourth transistor, wherein a drain of the fourth transistor is connected to the first input terminal, and a source of the fourth transistor is connected to the drain of the third transistor.

[0033] Furthermore, in one embodiment, the gate of the fourth transistor can be configured to receive a bias voltage.

[0034] Furthermore, in one embodiment, the bottom gate of the first transistor may be connected to the source of the first transistor, and the bottom gate of the second transistor may be connected to the source of the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology.

[0036] Figure 2A and Figure 2B is a block diagram showing a configuration example of a solid-state image sensor according to a first embodiment of the present technology.

[0037] Figure 3 is a circuit diagram showing a configuration example of a pixel circuit according to the first embodiment of the present technology.

[0038] Figure 4 : is a block diagram showing a configuration example of a column signal processing unit according to the first embodiment of the present technology.

[0039] Figure 5 is a circuit diagram showing a configuration example of a comparator according to the first embodiment of the present technology.

[0040] Figure 6 : is a timing chart showing an example of changes in input and output signals of the comparator according to the first embodiment of the present technology.

[0041] Figure 7 is a graph showing an example of characteristics of a pMOS transistor according to the first embodiment of the present technology.

[0042] Figure 8 is a circuit diagram showing a configuration example of a comparator according to a first comparative example.

[0043] Figure 9 : is a timing chart showing an example of changes in input and output signals of the comparator according to the first comparative example.

[0044] Figure 10 is a circuit diagram showing a configuration example of a comparator according to a second comparative example.

[0045] Figure 11 is a flowchart illustrating an operation example of the solid-state image sensor according to the first embodiment of the present technology.

[0046] Figure 12 is a circuit diagram showing a configuration example of a comparator according to a modification example of the first embodiment of the present technology.

[0047] Figure 13 is a circuit diagram showing a configuration example of a comparator according to a second embodiment of the present technology.

[0048] Figure 14 is a timing chart showing an example of changes in input and output signals of a comparator according to the second embodiment of the present technology.

[0049] Figure 15is a circuit diagram showing a configuration example of a comparator according to a third embodiment of the present technology.

[0050] Figure 16 is a timing chart showing a change example of input and output signals of a comparator according to a third embodiment of the present technology.

[0051] Figure 17 is a circuit diagram showing a configuration example of a comparator according to a fourth embodiment of the present technology.

[0052] Figure 18 : is a timing chart showing a change example of input and output signals of a comparator according to a fourth embodiment of the present technology.

[0053] Figure 19 is a circuit diagram showing a configuration example of a comparator according to a fifth embodiment of the present technology.

[0054] Figure 20 is a timing chart showing a change example of input and output signals of a comparator according to a fifth embodiment of the present technology.

[0055] Figure 21 is a circuit diagram showing a configuration example of a comparator according to a sixth embodiment of the present technology.

[0056] Figure 22 is a circuit diagram showing a configuration example of a comparator according to a seventh embodiment of the present technology.

[0057] Figure 23 is a circuit diagram showing a configuration example of a comparator according to an eighth embodiment of the present technology.

[0058] Figure 24 is a circuit diagram showing a configuration example of a comparator according to a ninth embodiment of the present technology.

[0059] Figure 25 This is a circuit diagram showing a configuration example of a comparator according to a modification example of the ninth embodiment of the present technology.

[0060] Figure 26 is a circuit diagram showing a configuration example of a comparator according to a tenth embodiment of the present technology.

[0061] Figure 27 is a circuit diagram showing a configuration example of a comparator according to an eleventh embodiment of the present technology.

[0062] Figure 28 is a circuit diagram showing a configuration example of a comparator according to a modification example of the eleventh embodiment of the present technology.

[0063] Figure 29 is a circuit diagram showing a configuration example of a comparator according to a twelfth embodiment of the present technology.

[0064] Figure 30 is a timing chart showing a change example of input and output signals of a comparator according to a twelfth embodiment of the present technology.

[0065] Figure 31 is a circuit diagram showing a configuration example of a comparator according to a thirteenth embodiment of the present technology.

[0066] Figure 32 It is a block diagram showing a schematic configuration of a vehicle control system.

[0067] Figure 33 is an explanatory diagram illustrating an example of an installation position of an imaging unit. DETAILED DESCRIPTION

[0068] Hereinafter, a form for implementing the present technology (hereinafter, referred to as an embodiment) will be described. The description will be given according to the following order.

[0069] 1. First Embodiment (Example of Supplying Drain-Source Voltage to Output Transistor)

[0070] 2. Second Embodiment (Example of Supplying Drain-Source Voltage to the Output Transistor and Providing a Clamp Transistor on the Input Side)

[0071] 3. Third Embodiment (Example of Supplying Drain-Source Voltage to Output Transistor and Self-Setting Gate Voltage of Current Source Transistor)

[0072] 4. Fourth Embodiment (Example of Supplying Drain-Source Voltage to Cascode-Connected Output Transistors)

[0073] 5. Fifth Embodiment (Example in which a drain-source voltage is supplied to an output transistor and an auto-zero switch is provided on the output side)

[0074] 6. Sixth Embodiment (Example of Supplying Drain-Source Voltage to Output Transistor and Adding Logic Gates in the Later Stage)

[0075] 7. Seventh Embodiment (Example of Supplying Drain-Source Voltage to Output Transistor and Providing Two-Stage Clamp Transistors)

[0076] 8. Eighth Embodiment (Example of Supplying Drain-Source Voltage to Output Transistor and Adding a Current Source)

[0077] 9. Ninth Embodiment (Example of Supplying Drain-Source Voltage to Output Transistor and Providing N-Type Clamp Transistor)

[0078] 10. Tenth Embodiment (Example in which a drain-source voltage is supplied to an output transistor and a buffer is provided)

[0079] 11. Eleventh Embodiment (Example in which a drain-source voltage is supplied to an output transistor and a clamp transistor is provided on the output side)

[0080] 12. Twelfth Embodiment (Example of Supplying Drain-Source Voltage to Output Transistor and Providing a Clamp Switch)

[0081] 13. Thirteenth Embodiment (Example in which a drain-source voltage is supplied to an output transistor and a resistance element is provided)

[0082] 14. Application examples of mobile objects

[0083] <1. First Implementation Method>

[0084] [Configuration Example of Imaging Device]

[0085] Figure 1 This is a block diagram illustrating an example configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for imaging image data and includes an optical unit 110, a solid-state image sensor 200, and a digital signal processing (DSP) circuit 120. Furthermore, the imaging device 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. Assume that the imaging device 100 is a camera mounted on a smartphone, an in-vehicle camera, or the like.

[0086] The optical unit 110 collects light from a subject and guides the light to the solid-state image sensor 200 . The solid-state image sensor 200 generates image data by photoelectric conversion and supplies the generated image data to the DSP circuit 120 via a signal line 209 .

[0087] The DSP circuit 120 performs predetermined signal processing on the image data and outputs the processed image data to the frame memory 160 or the like via the bus 150 .

[0088] The display unit 130 displays image data. For example, a liquid crystal panel or an organic electroluminescence (EL) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal according to a user's operation.

[0089] The bus 150 is a common path for the optical unit 110 , the solid-state image sensor 200 , the DSP circuit 120 , the display unit 130 , the operation unit 140 , the frame memory 160 , the storage unit 170 , and the power supply unit 180 to mutually exchange data.

[0090] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state image sensor 200, the DSP circuit 120, the display unit 130, and the like.

[0091] [Configuration Example of Solid-State Image Sensor]

[0092] Figure 2A and Figure 2B This is a block diagram illustrating an example configuration of a solid-state image sensor 200 according to a first embodiment of the present technology. The solid-state image sensor 200 includes a vertical scanning circuit 210, a timing control unit 220, a digital-to-analog converter (DAC) 230, a pixel array unit 240, a column signal processing unit 260, and a horizontal scanning circuit 270. The solid-state image sensor 200 can be integrated into a single chip or implemented as a stacked structure. In a stacked structure, the various illustrated components can be formed separately on multiple substrates, then stacked, bonded, or laminated, and connected to each other via connectors.

[0093] exist Figure 2B In the example shown, the first substrate 201 includes a pixel array unit 240, and the second substrate 202 includes a vertical scanning circuit 210; a timing control unit 220; a DAC 230; a pair of counter areas 261, a pair of latch areas 262, and a pair of comparator areas 300 (which can be components of the column signal processing unit 260); a horizontal scanning circuit 270; and an interface (I / F) 290. In this example, the first substrate 201 and the second substrate 202 each include a plurality of pads 205 and a plurality of connecting portions 280. The connecting portions 280 can be Cu-Cu connections (CCCs), through silicon vias (TSVs), continuous wiring, etc. Figure 2B As shown, the comparator 300 is arranged adjacent to the connection portion 280 .

[0094] In another example, the pixel array unit 240 and the control circuit including the vertical scanning circuit 210 and the timing control unit 220 can be arranged in the first substrate; and the signal processing circuit including the DAC 230, the column signal processing unit 260, and the horizontal scanning circuit 270 can be arranged in the second substrate. In another example, the pixel array unit 240 can be arranged in the first substrate; the control circuit including the vertical scanning circuit 210 and the timing control unit 220 can be arranged in the second substrate; and the signal processing circuit including the DAC 230, the column signal processing unit 260, and the horizontal scanning circuit 270 can be arranged in the third substrate.

[0095] In the pixel array unit 240, a plurality of pixel circuits 250 are arranged in a two-dimensional lattice. Hereinafter, a set of pixel circuits 250 arranged in a predetermined horizontal direction is referred to as a "row," and a set of pixel circuits 250 arranged in a vertical direction relative to the row is referred to as a "column."

[0096] The vertical scanning circuit 210 sequentially drives each row so that the pixel circuits 250 output signals.

[0097] The timing control unit 220 controls the operation timing of each of the vertical scanning circuit 210, the DAC 230, the column signal processing unit 260, and the horizontal scanning circuit 270 in synchronization with the vertical synchronization signal VSYNC. The vertical synchronization signal VSYNC is a periodic signal having a predetermined frequency (such as 60 Hz) indicating an imaging timing.

[0098] The DAC 230 generates a predetermined reference signal through digital-to-analog (DA) conversion. For example, a sawtooth ramp signal is used as the reference signal. The DAC 230 supplies the reference signal to the column signal processing unit 260. Note that the DAC 230 is an example of a reference signal supply unit described in the claims.

[0099] The pixel circuit 250 generates an analog pixel signal through photoelectric conversion and supplies the analog pixel signal to the column signal processing unit 260 .

[0100] The column signal processing unit 260 performs signal processing such as AD conversion processing and correlated double sampling (CDS) processing on the pixel signal for each column and supplies image data including the processed digital signal to the DSP circuit 120 via the signal line 209 .

[0101] The horizontal scanning circuit 270 controls the column signal processing unit 260 to sequentially output digital signals.

[0102] [Configuration Example of Pixel Circuit]

[0103] Figure 3 This is a circuit diagram showing an example configuration of a pixel circuit 250 according to the first embodiment of the present technology. The pixel circuit 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplifier transistor 255, and a selection transistor 256. Furthermore, in the pixel array unit 240, a vertical signal line VSL is wired along the vertical direction for each column.

[0104] The photoelectric conversion element 251 performs photoelectric conversion on incident light to generate electric charge, and the transfer transistor 252 transfers the electric charge from the photoelectric conversion element 251 to the floating diffusion layer 254 in accordance with the drive signal TRG from the vertical scanning circuit 210 .

[0105] The reset transistor 253 extracts and initializes charges from the floating diffusion layer 254 according to the driving signal RST from the vertical scanning circuit 210 .

[0106] The floating diffusion layer 254 accumulates electric charges and generates a voltage corresponding to the amount of electric charges. The amplifier transistor 255 amplifies the voltage of the floating diffusion layer 254.

[0107] The selection transistor 256 outputs the amplified voltage signal as a pixel signal to the column signal processing unit 260 via the vertical signal line VSL in accordance with the drive signal SEL from the vertical scanning circuit 210 .

[0108] Note that the pixel circuit 250 is not limited to Figure 3 The circuit shown is sufficient as long as the pixel circuit 250 can generate a pixel signal through photoelectric conversion.

[0109] [Configuration Example of Column Signal Processing Unit]

[0110] Figure 4 1 is a block diagram illustrating a configuration example of the column signal processing unit 260 according to the first embodiment of the present technology. In the column signal processing unit 260, a comparator 300, a counter 261, and a latch 262 are arranged for each column. When the number of columns is N (N is an integer), N comparators 300, N counters 261, and N latches 262 are arranged.

[0111] The comparator 300 compares the reference signal from the DAC 230 with the pixel signal from the corresponding column. Hereinafter, the voltage of the reference signal is referred to as the reference voltage V RMP , and the voltage of the pixel signal input via the vertical signal line VSL is referred to as the input voltage V VSL The comparator 300 will reference the voltage V RMP and input voltage V VSL The comparison result COMP therebetween is supplied to the counter 261 of the corresponding column.

[0112] In addition, in the following, the input voltage V when the pixel circuit 250 is initialized is VSL is referred to as the “reset level” and, hereinafter, the input voltage V when the charge is transferred to the floating diffusion layer 254 VSL It is called "signal level".

[0113] The counter 261 counts the count value until the comparison result COMP is inverted. For example, the counter 261 counts down until the comparison result COMP with the reset level is inverted, and counts up until the comparison result COMP with the signal level is inverted. This counting realizes CDS processing for obtaining the difference between the reset level and the signal level.

[0114] The counter 261 then causes the latch 262 to hold a digital signal indicating the count value. The AD conversion process for converting the analog pixel signal into a digital signal is implemented by the comparator 300 and the counter 261. That is, the comparator 300 and the counter 261 function as an ADC. An ADC using a comparator and a counter in this manner is generally referred to as a single-slope ADC.

[0115] Note that the CDS process is implemented by up-counting and down-counting. However, the CDS process is not limited to this configuration. The following configuration may be adopted, in which the counter 261 performs only up-counting or down-counting, and the CDS process for obtaining the difference is performed by the subsequent circuit.

[0116] The latch 262 holds the digital signal and outputs the held digital signal to the DSP circuit 120 under the control of the horizontal scanning circuit 270 .

[0117] [Comparator Configuration Example]

[0118] Figure 5 3 is a circuit diagram showing a configuration example of a comparator 300 according to the first embodiment of the present technology. The comparator 300 includes capacitors 311 and 314, an input transistor 312, an auto-zero switch 313, an output transistor 315, an input-side current source 320, and an output-side current source 330.

[0119] The capacitor 311 is inserted between the DAC 230 and the gate of the input transistor 312 .

[0120] The source of the input transistor 312 is connected to the vertical signal line VSL, and the input voltage V VSL is input to the source. In addition, the reference voltage V RMP The voltage V is input to the gate of the input transistor 312 via the capacitor 311. VSL The reference voltage V RMP At the time point when the input transistor 312 is substantially consistent, the voltage state of the input transistor 312 becomes the same as the voltage state at the time of auto-zeroing, and according to the input voltage V VSL and reference voltage V RMP The drain voltage Vd is output from the drain. Here, "substantially consistent" means that the voltage changes during each auto-zero period are completely consistent, or the difference falls within a predetermined allowable value. For example, a pMOS transistor is used as the input transistor 312.

[0121] Furthermore, in order to suppress the bottom gate effect, it is desirable to short-circuit the bottom gate and source of the input transistor 312 .

[0122] The auto-zero switch 313 is used to short-circuit the gate and drain of the input transistor 312 according to the control signal AZSW1 from the timing control unit 220 .

[0123] Input-side current source 320 is inserted between the drain of input transistor 312 and a predetermined reference terminal (such as a ground terminal). Input-side current source 320 supplies a fixed current Id1. Input-side current source 320 is implemented using an n-channel MOS (nMOS) transistor, etc. The circuit configuration of input-side current source 320 will be described later.

[0124] The capacitor 314 is inserted between the source and drain of the input transistor 312 .

[0125] The source of the output transistor 315 is connected to the vertical signal line VSL, and the input voltage V VSL is input to the source. In addition, the gate of the output transistor 315 is connected to the drain of the input transistor 312, and the drain voltage Vd is input to the gate of the output transistor 315. For example, a pMOS transistor is used as the output transistor 315. In addition, it is desirable to short-circuit the bottom gate and source of the output transistor 315.

[0126] The output transistor 315 outputs an input voltage V from the drain to the source. VSL The comparison result COMP is supplied to the counter 261 as a signal indicating whether the difference between the voltage Vd and the drain voltage Vd input to the gate exceeds a predetermined threshold voltage.

[0127] The output-side current source 330 is inserted between the drain of the output transistor 315 and a predetermined reference terminal (such as a ground terminal) and supplies a fixed current Id2. The output-side current source 330 is implemented by an nMOS transistor or the like. The circuit configuration of the output-side current source 330 will be described later.

[0128] Figure 6 : is a timing chart showing an example of changes in input and output signals of the comparator 300 according to the first embodiment of the present technology.

[0129] At time T0 just before AD conversion starts, the control signal AZSW1 is input during a predetermined auto-zero period. As a result, the gate and drain of the input transistor 312 are short-circuited, and auto-zero of the comparator 300 is performed.

[0130] Next, the DAC 230 gradually reduces the reference voltage V during a fixed period starting from time T2. RMP On the other hand, the pixel circuit 250 is initialized, and the input voltage V VSL (i.e., reset level) is set to V VSLp .

[0131] Then, at time T3, it is assumed that the reference voltage V RMP and reset level V VSLp Generally consistent.

[0132] The drain voltage Vd of the input transistor 312 at this time T3 is set to Vdp. When a level lower than Vdp is set to a low level and a level equal to or higher than Vdp is set to a high level, the drain voltage Vd of the input transistor 312 is reversed from a low level to a high level at time T3.

[0133] Next, the DAC 230 initializes the reference voltage and gradually decreases the reference voltage V during a fixed period starting from time T5. RMP On the other hand, the charge is transferred to the floating diffusion layer 254, and the input voltage V VSL (i.e., signal level) is set to V VSLd Assuming that the signal level V VSLd than the reset level V VSLp Low ΔV.

[0134] Then, at time T6, it is assumed that the reference voltage V RMP With signal level V VSLd The drain voltage Vd of the input transistor 312 at time T6 is set to Vdd. The drain voltage Vdd is a value ΔV lower than the drain voltage Vdp. That is, the drain voltage Vdd at time T6 changes with the input voltage (signal level V VSLd ) becomes low and becomes low.

[0135] Since the drain voltage Vdd of the input transistor 312 decreases by ΔV from the drain voltage Vdp when it switches to the reset level, in the prior art, the time when the drain voltage Vd is reversed is determined to be time T7 after time T6. Therefore, if the drain voltage Vd is used as the comparison result COMP, the inversion time T7 of the comparison result COMP is ΔV from the reference voltage Vdp. RMP With signal level V VSLd The ideal time T6 when the two signals are substantially aligned shifts. As a result, linearity errors and deviations occur in the ADC, and the image quality of the image data may be degraded due to these errors.

[0136] However, as described above, the output transistor 315 is provided at the subsequent stage of the input transistor 312, and the source and drain of the input transistor 312 are connected to the source and gate of the output transistor 315. Through this connection, the drain-source voltage Vds of the input transistor 312 is input as the gate-source voltage of the output transistor 315.

[0137] like Figure 6 As shown, when the reference voltage VRMP With input voltage V VSL At the same time T3 and T6, the input voltage V VSL The voltage drop ΔV is the same as the voltage drop in drain voltage Vd. Therefore, at these times, drain-source voltage Vd has the same value. At this time (i.e., at times T3 and T6), the value of drain-source voltage Vds is the same as the value at the time of auto-zero. Since drain-source voltage Vds is the gate-source voltage of output transistor 315, the drain voltage of output transistor 315 reverses at times T3 and T6.

[0138] Since the inversion timing of the comparison result COMP is the reference voltage V RMP With signal level V VSLd The ideal timing when the comparison result COMP is substantially the same as the ideal timing when the comparison result COMP is substantially the same is achieved, thereby suppressing the error in the inversion timing. As a result, the linear error and deviation can be reduced compared to the case where the drain voltage Vd is used as the comparison result COMP, and the image quality of the image data can be improved.

[0139] Next, the voltage drop amount ΔV of the drain voltage Vd of the input transistor 312 becomes equal to the input voltage Vd input to the source at time T3 and T6. VSL The voltage drops by the same amount for the same reason.

[0140] Figure 7 is a graph showing an example of the characteristics of the pMOS transistor according to the first embodiment of the present technology. Figure 7 , the vertical axis represents the drain current, and the horizontal axis represents the drain-source voltage. In addition, the single-dot chain line shows the boundary between the linear region and the saturation region.

[0141] As a general rule, the operating point of the pMOS transistor is determined so as to operate in the saturation region at the time of auto-zeroing. The drain current Id in this saturation region is expressed by the following equation.

[0142] Id=(1 / 2)·μC OX (W / L)·(V GS -Vth) 2 (1+λVds)……Equation 1

[0143] In the above formula, μ represents electron mobility, and the unit is, for example, square meter per volt second (m 2 / V·s). C OX"V" represents the capacitance per unit area of ​​the MOS capacitor, and its unit is, for example, farad per meter (F / m). "W" represents the gate width, and its unit is, for example, meter (m). "L" represents the gate length, and its unit is, for example, meter (m). "Vth" represents the threshold voltage, and its unit is, for example, volt (V). "λ" represents a predetermined coefficient. Furthermore, "drain-source voltage Vds" represents, for example, volt (V), and "drain current Id" represents, for example, ampere (A).

[0144] Since the input transistor 312 is a pMOS transistor, Equation 1 holds true in the saturation region. At this time, the drain current Id is a fixed value (i.e., Id1) supplied from the input side current source 320. In addition, the electron mobility μ and the unit capacitance C OX , gate width W, gate length L, threshold voltage Vth and coefficient λ are fixed values.

[0145] In addition, when the reference voltage V is input to the gate and source of the input transistor 312 RMP With input voltage V VSL When they are roughly consistent with each other, the gate-source voltage V GS It is a fixed value determined during auto zeroing.

[0146] Therefore, when the reference voltage V is input to the gate and source of the input transistor 312 RMP and input voltage V VSL When they are substantially consistent with each other, the drain-source voltage Vds is also a fixed value according to Formula 1. When the fixed drain-source voltage is Vds1, the following formula holds true at the above-mentioned times T3 and T6.

[0147] Vds1=V VSLp -Vdp……Equation 2

[0148] Vds1=V VSLd -Vdd……Formula 3

[0149] When the drain-source voltage Vds1 is eliminated from Equations 2 and 3, the following equation is obtained.

[0150] V VSLp -V VSLd =Vdp-Vdd...Formula 4

[0151] Note that in the case of determining the operating point of the pMOS transistor to operate in the linear region at the time of auto-zeroing, Equation 1 takes a different form, but Equation 4 also holds true.

[0152] According to Equation 4, the voltage drop ΔV of the drain voltage Vd of the input transistor 312 becomes equal to the input voltage V VSL The voltage drop is the same. Therefore, we get Figure 6The timing diagram shown.

[0153] Next, a first comparative example in which the output transistor 315 is not provided will be considered.

[0154] Figure 8 is a circuit diagram illustrating an example configuration of a comparator according to a first comparative example. In this first comparative example, an inverter is provided after the input transistor, instead of output transistor 315. The inverter inverts the drain voltage of the input transistor and outputs the drain voltage as the comparison result COMP. Essentially, the drain voltage of the input transistor is used as the comparison result COMP.

[0155] Figure 9 : is a timing chart showing an example of changes in input and output signals of a comparator according to the first comparative example. The input voltage V in the first comparative example VSL , reference voltage V RMP and the change of drain voltage Vd with Figure 6 The variations in the first embodiment shown are similar.

[0156] As described above, according to Equation 4, the voltage drop amount of the drain voltage Vd of the input transistor becomes equal to the input voltage V VSL The voltage drop is the same as the reference voltage. Therefore, the time T7 at which the drain voltage Vd reverses shifts from the ideal time T6, when the reference voltage and the signal level are substantially aligned. Because the inverter in the first comparative example inverts the drain voltage Vd as is, the timing of the inversion of the comparison result COMP also shifts from the ideal time T6. This timing error degrades the image quality of the image data.

[0157] Next, a second comparative example using a differential amplifier circuit will be considered.

[0158] Figure 10 2 is a circuit diagram showing a configuration example of a comparator according to a second comparative example. A differential amplifier circuit is arranged in the second comparative example. In addition, in the load MOS circuit, a current source is also connected to the vertical signal line VSL.

[0159] Since the differential amplifier circuit is used in the second comparative example, unlike the first comparative example, the comparison result COMP is inverted at the ideal timing when the reference voltage and the signal level are substantially consistent. Figure 10 As shown in the figure, a current source is required in the load MOS circuit and a power supply is required in the comparator. Therefore, the power consumption increases.

[0160] In summary, since the output transistor 315 is not provided in the first comparative example, the image quality of the image data is degraded compared to the first embodiment. The second comparative example of the differential amplification type can solve the problem of image quality degradation of the image data, but the second comparative example is not advantageous due to its greater power consumption compared to the first embodiment.

[0161] [Operation example of solid-state image sensor]

[0162] Figure 11 1 is a flowchart showing an example of the operation of the solid-state image sensor according to the first embodiment of the present technology. For example, this operation is started when a predetermined application for capturing image data is executed.

[0163] In the solid-state image sensor 200 , the vertical scanning circuit 210 sequentially selects and drives rows (step S901 ). The column signal processing unit 260 performs AD conversion on the reset level for each column (step S902 ) and performs AD conversion on the signal level (step S903 ).

[0164] The solid-state image sensor 200 determines whether the readout of all rows has been completed (step S904). If the readout of all rows has not been completed (step S904: No), the solid-state image sensor 200 repeats the processing of step S901 and subsequent steps. On the other hand, if the readout of all rows has been completed (step S904: Yes), the solid-state image sensor 200 terminates the operation for imaging the image data. When imaging a plurality of image data sequentially, steps S901 to S904 are repeatedly executed in synchronization with the vertical synchronization signal VSYNC.

[0165] As described above, according to the first embodiment of the present technology, input transistor 312 supplies a drain-source voltage between the gate and source of output transistor 315, thereby inverting the comparison result at the timing when the input voltage matches the reference voltage. As a result, noise caused by errors in inversion timing can be reduced, and the image quality of the image data can be improved.

[0166] [Modification]

[0167] In the first embodiment described above, the input side current source 320 is connected to the drain of the input transistor 312. However, in this configuration, the input voltage V VSL The voltage Vd decreases significantly, the drain voltage Vd drops, the transistor constituting the input-side current source 320 becomes non-conductive, and the supply of the drain current Id1 can be stopped. The comparator 300 according to the modification of the first embodiment differs from the comparator 300 according to the first embodiment in that the supply of the current Id1 is prevented from being stopped by adding an input-side clamp transistor.

[0168] Figure 12 3 is a circuit diagram showing a configuration example of a comparator 300 according to a modification of the first embodiment of the present technology. The comparator 300 of the modification of the first embodiment differs from the first embodiment in that it further includes an input-side clamp transistor 341.

[0169] The input side clamp transistor 341 is inserted between the vertical signal line VSL (ie, the source of the input transistor 312) and the power supply terminal. An nMOS transistor is used as the input side clamp transistor 341, and a fixed bias voltage V clamp is applied to the gate of the input-side clamp transistor 341. The input-side clamp transistor 341 can limit the drain voltage Vd to a predetermined lower limit voltage or higher. With this configuration, the transistor constituting the input-side current source 320 can remain in an on state and prevent the supply of the current Id1 from being stopped.

[0170] As described above, according to the modification example of the first embodiment of the present technology, the input-side clamp transistor 341 suppresses a decrease in the drain voltage Vd, thereby preventing the supply of the current Id1 from being stopped.

[0171] <2. Second Implementation Plan>

[0172] In the above-described variation of the first embodiment, the input-side clamp transistor 341 is inserted between the power supply terminal and the vertical signal line VSL to suppress a decrease in the drain voltage Vd. However, in this configuration, when current flows through the input-side clamp transistor 341, the current flowing through the vertical signal line VSL is reduced by the amount of current flowing through the input-side clamp transistor 341, and there is a possibility that the settling time of the vertical signal line VSL will be prolonged. The comparator 300 according to the second embodiment differs from the variation of the first embodiment in that the input-side clamp transistor is inserted between the source and drain of the input transistor 312.

[0173] Figure 13 2 is a circuit diagram showing a configuration example of a comparator 300 according to a second embodiment of the present technology. The comparator 300 receives a pixel signal V from the pixel circuit 250 via the connection portion 280. VSL The connection portion 280 may be a Cu-Cu connection (CCC), a through-silicon via (TSV), a continuous wiring, or the like. The comparator 300 according to the second embodiment differs from the modified example of the first embodiment in that an input-side clamp transistor 342 is included instead of the input-side clamp transistor 341. Furthermore, an initialization switch 343 may be further included.

[0174] The input-side clamp transistor 342 is inserted between the source and drain of the input transistor 312. A pMOS transistor is used as the input-side clamp transistor 342, and the gate of the input-side clamp transistor 342 is short-circuited to the drain of the input-side clamp transistor 342. Furthermore, it is desirable to short-circuit the bottom gate and source of the input-side clamp transistor 342. The input-side clamp transistor 342 can suppress a decrease in the drain voltage Vd when the input transistor 312 is in a non-conductive state. Furthermore, since the input-side clamp transistor is not connected to the power supply terminal, the current of the vertical signal line VSL is not reduced, and the settling time can be shortened compared to the modified example of the first embodiment.

[0175] Furthermore, the initialization switch 343 opens and closes the path between the gate and the drain of the output transistor 315 according to the control signal GDSW from the timing control unit 220 .

[0176] Figure 14 : is a timing chart showing an example of changes in input and output signals of the comparator 300 according to the second embodiment of the present technology.

[0177] The timing control unit 220 supplies a control signal GDSW during a pulse period starting at time T4, between the reset-level AD conversion period and the signal-level AD conversion period, to close the output transistor 315. This control suppresses the drain voltage Vd from approaching the lower limit voltage immediately before the signal-level AD conversion via the vertical signal line VSL and the input-side clamp transistor 342. As a result, the drain voltage Vd is stabilized, reducing errors in the signal-level AD conversion, and minimizing skew and linearity errors.

[0178] As described above, according to the second embodiment of the present technology, the input side clamp transistor 342 is inserted between the source and the drain of the input transistor 312 , and thus a decrease in the current of the vertical signal line VSL can be suppressed.

[0179] <3. Third Implementation Plan>

[0180] In the second embodiment described above, only the output of the output-side current source 330 is connected to the drain of the output transistor 315. However, in this configuration, the voltage of the comparison result COMP may become unstable due to variations in the characteristics of the components constituting the circuit. The comparator 300 according to the third embodiment differs from the second embodiment in that the gate voltage of the output transistor 315 is set based on the input-side current Id1 during auto-zero.

[0181] Figure 153 is a circuit diagram showing a configuration example of a comparator 300 according to a third embodiment of the present technology. The comparator 300 according to the third embodiment differs from the second embodiment in that an auto-zero switch 331, a capacitor 332, and a current source transistor 333 are arranged within the output-side current source 330. Furthermore, the current source transistor 321 and the capacitor 322 are arranged within the input-side current source 320 of the second embodiment. For example, nMOS transistors are used as the current source transistors 321 and 333.

[0182] The current source transistor 321 is inserted between the drain of the input transistor 312 and a reference terminal (such as a ground terminal). bias1 is applied to the gate of the current source transistor 321. The capacitor 322 is inserted between the gate of the current source transistor 321 and the reference terminal. Note that the bias voltage V bias1 The voltage may be sampled by a switch (not shown) in the initial state and held in the capacitor 322 .

[0183] Furthermore, a current source transistor 333 is inserted between the drain of the output transistor 315 and the reference terminal. A capacitor 332 is inserted between the gate of the current source transistor 333 and the reference terminal. The auto-zero switch 331 opens and closes the path between the gate and drain of the current source transistor 333 in response to a control signal AZSW2 from the timing control unit 220. Note that the auto-zero switch 331 is an example of the first auto-zero switch described in the claims.

[0184] Figure 16 This is a timing diagram illustrating an example of changes in the input and output signals of the comparator 300 according to the third embodiment of the present technology. In addition to the control signal AZSW1, the timing control unit 220 also supplies the control signal AZSW2 during the auto-zero period starting at time T0. The auto-zero switch 331 is closed by the control signal AZSW2.

[0185] The gate voltage of the current source transistor 333 is automatically set based on the input side current Id1 under the control of the auto-zero switch 331. As a result, the voltage of the comparison result COMP is stabilized regardless of variations in the elements.

[0186] As described above, according to the third embodiment of the present technology, the auto-zero switch 331 short-circuits the gate and drain of the current source transistor 333, and thus the gate voltage of the current source transistor 333 absorbs the error due to the variation and can stabilize the voltage of the comparison result COMP.

[0187] <4. Fourth Implementation Plan>

[0188] In the third embodiment described above, the gate voltage of the output current source transistor 333 is automatically set during the auto-zero period. However, in this configuration, if the drain voltages of the input transistor 312 and the output transistor 315 are not uniform, there is a possibility that the current ratio between the input current Id1 and the output current Id2 will deviate from the expected value. The comparator 300 according to the fourth embodiment differs from the third embodiment in that the cascode connection of the transistors reduces the deviation in the current ratio.

[0189] Figure 17 1 is a circuit diagram showing a configuration example of a comparator 300 according to a fourth embodiment of the present technology. The comparator 300 according to the fourth embodiment differs from the third embodiment in that it further includes an input-side cascode connection transistor 345, an output-side cascode connection transistor 347, and cascode control switches 344 and 346. For example, pMOS transistors are used as the input-side cascode connection transistor 345 and the output-side cascode connection transistor 347.

[0190] The input side cascode connection transistor 345 is cascode-connected to the input transistor 312. The input side cascode connection transistor 345 is inserted between the drain of the input transistor 312 and the input side current source 320. In addition, the gate of the input side cascode connection transistor 345 is connected to the gate of the output side cascode connection transistor 347.

[0191] The output side cascode connection transistor 347 is cascode-connected to the output transistor 315. The output side cascode connection transistor 347 is inserted between the drain of the output transistor 315 and the output side current source 330.

[0192] The cascode control switch 344 opens and closes a path between the gate and the drain of the input-side cascode connection transistor 345 according to a control signal CASEN from the timing control unit 220 .

[0193] The cascode control switch 346 opens and closes the path between the gates of the input side cascode connection transistor 345 and the output side cascode connection transistor 347 and the reference terminal according to XCASEN which is the inverted control signal CASEN.

[0194] Figure 18This is a timing diagram illustrating an example of changes in the input and output signals of the comparator 300 according to the third embodiment of the present technology. The timing control unit 220 supplies control signals CASEN and XCASEN for a fixed period starting at time T0. These control signals CASEN and XCASEN control the cascode control switch 344 to be closed, and the cascode control switch 346 to be open. As a result, the drain voltage of the input transistor 312 and the drain voltage of the output transistor 315 are easily aligned, and the current ratio of current Id1 to current Id2 can be reduced in deviation from the assumed value.

[0195] However, if the cascode connection is maintained, the dynamic range may be reduced. Therefore, at time T1 after the auto-zero period has elapsed, the cascode control switch 344 is controlled to be in an open state and the cascode control switch 346 is controlled to be in a closed state by the control signals CASEN and XCASEN. As a result, the cascode connection is released, and a reduction in the dynamic range can be prevented.

[0196] As described above, according to the fourth embodiment of the present technology, the transistors are cascaded to the input transistor 312 and the output transistor 315, and thus the drain voltages of the transistors can be made uniform. As a result, the current ratio of the current Id1 to the current Id2 can be made less deviated from the assumed value.

[0197] <5. Fifth Implementation Plan>

[0198] In the second embodiment described above, the input-side current source 320 and the output-side current source 330 are provided. However, when these current sources independently generate currents Id1 and Id2 using bias voltages, the current values ​​may vary. The solid-state image sensor 200 according to the fifth embodiment differs from the second embodiment in that current variations are suppressed by adding an auto-zero switch on the output side.

[0199] Figure 19 1 is a circuit diagram illustrating a configuration example of a comparator 300 according to a fifth embodiment of the present technology. The comparator 300 according to the fifth embodiment differs from the second embodiment in that it further includes a capacitor 348 and an auto-zero switch 349. Furthermore, a sample-and-hold switch 334, a capacitor 332, and a current source transistor 333 are disposed within the output-side current source 330 according to the fifth embodiment. Furthermore, a current source transistor 321 and a capacitor 322 are disposed within the input-side current source 320 according to the fifth embodiment. For example, nMOS transistors are used as the current source transistors 321 and 333.

[0200] The current source transistor 321 is inserted between the drain of the input transistor 312 and the reference terminal.bias1 is applied to the gate of the current source transistor 321. The capacitor 322 is inserted between the gate of the current source transistor 321 and the reference terminal.

[0201] In addition, the current source transistor 333 is inserted between the drain of the output transistor 315 and the reference terminal. The capacitor 332 is inserted between the gate of the current source transistor 333 and the reference terminal. The sample hold switch 334 switches the predetermined bias voltage V to the reference terminal according to the control signal ISBH from the timing control unit 220. bias2 Applied to capacitor 332 and the gate of current source transistor 333.

[0202] Furthermore, a capacitor 348 is inserted between the drain of the input transistor 312 and the gate of the output transistor 315. The auto-zero switch 349 short-circuits the gate and drain of the output transistor 315 in accordance with a control signal AZSW2 from the timing control unit 220. Note that the auto-zero switch 349 is an example of a second auto-zero switch described in the claims.

[0203] Furthermore, the initialization switch 343 of the fifth embodiment opens and closes the path between the drain of the input transistor 312 and the drain of the output transistor 315 according to the control signal GDSW.

[0204] As described above, in each of the input-side current source 320 and the output-side current source 330 , the currents Id1 and Id2 are individually generated by the bias voltage.

[0205] Figure 20 2 is a timing diagram illustrating an example of changes in the input and output signals of the comparator 300 according to the fifth embodiment of the present technology. In addition to the control signals AZSW1 and AZSW2, the timing control unit 220 also supplies the control signal ISBH during the auto-zero period starting at time T0. The output-side auto-zero switch 349 is closed by the control signal AZSW2. Furthermore, the sample-and-hold switch 334 within the output-side current source 330 is closed by the control signal ISBH.

[0206] It is possible to suppress the influence of the variation of the currents Id1 and Id2 when the output-side deviation is reduced by the output-side auto-zero switch 349 and the currents Id1 and Id2 are generated solely by the bias voltage.

[0207] As described above, according to the fifth embodiment of the present technology, the auto-zero switch 349 is added to the output side, and thus the influence of the variation of the currents Id1 and Id2 when they are generated solely by the bias voltage can be suppressed.

[0208] <6. Sixth Implementation Plan>

[0209] In the second embodiment described above, the drain voltage of the output transistor 315 is outputted as the comparison result COMP as is. However, a logic gate such as an inverter may be added after the output transistor 315. The comparator 300 according to the sixth embodiment differs from the second embodiment in that a logic gate is added.

[0210] Figure 21 1 is a circuit diagram showing a configuration example of a comparator 300 according to a sixth embodiment of the present technology. The comparator 300 according to the sixth embodiment differs from the second embodiment in that it further includes a NOR gate 350 and an inverter 351.

[0211] The NOR gate 350 outputs the NOR of the drain of the output transistor 315 and the control signal XEN to the inverter 351. The inverter 351 inverts the output of the NOR gate 350 and outputs the inverted output as the comparison result COMP to the counter 261. Note that the NOR gate 350 and the inverter 351 are examples of logic gates described in the claims.

[0212] With the above configuration, the voltage of the signal path (comparison result COMP) can be set to the power supply voltage level of the logic circuit. Furthermore, the logic of the output of NOR gate 350 is fixed between the auto-zero period or the period between AD conversion of the reset level and the period between AD conversion of the signal level. As a result, even when the drain voltage of output transistor 315 is at an intermediate voltage, through-current can be prevented from flowing through third-stage NOR gate 350.

[0213] Note that the sixth embodiment can be applied to each embodiment other than the second embodiment and modifications of each embodiment.

[0214] As described above, according to the sixth embodiment of the present technology, the NOR gate 350 and the inverter 351 are added to the subsequent stage of the output transistor 315 , and thus the logic of the output can be fixed during auto-zero or the like.

[0215] <7. Seventh Implementation Plan>

[0216] In the second embodiment described above, only one stage of input-side clamp transistors is arranged. However, with this configuration, the output amplitude of input transistor 312 may be insufficient. The comparator 300 according to the seventh embodiment differs from the second embodiment in that the input-side clamp transistors are arranged in two stages.

[0217] Figure 22 3 is a circuit diagram showing a configuration example of a comparator 300 according to a seventh embodiment of the present technology. The comparator 300 according to the seventh embodiment differs from the second embodiment in that it further includes an input-side clamp transistor 352.

[0218] A pMOS transistor is used as the input side clamp transistor 352. The input side clamp transistors 342 and 352 are connected in series between the drain and source of the input transistor 312.

[0219] By adding the input-side clamp transistor 352, the output amplitude of the input transistor 312 becomes larger than that of the case where only the input-side clamp transistor 342 is provided. With this configuration, the delay time until the comparison result COMP is inverted becomes longer, and noise can be reduced.

[0220] Note that the seventh embodiment can be applied to each embodiment other than the second embodiment and modifications of each embodiment.

[0221] As described above, according to the seventh embodiment of the present technology, the input-side clamp transistors 342 and 352 are connected in series between the drain and the source of the input transistor 312 , and thus the output amplitude of the input transistor 312 can be made large.

[0222] <8. Eighth Implementation Plan>

[0223] In the second embodiment described above, currents Id1 and Id2 are supplied from the input-side current source 320 and the output-side current source 330. However, in this configuration, these current amounts may become excessive. The comparator 300 according to the eighth embodiment differs from the second embodiment in that a current source is added to suppress the current amounts of currents Id1 and Id2.

[0224] Figure 23 1 is a circuit diagram showing a configuration example of a comparator 300 according to an eighth embodiment of the present technology. The comparator 300 according to the eighth embodiment is different from that of the second embodiment in that a pixel-side current source 353 is further included.

[0225] The pixel-side current source 353 is connected between the vertical signal line VSL and the reference terminal. The current amounts of the currents Id1 and Id2 can be reduced by the current amount supplied by the pixel-side current source 353.

[0226] Note that the eighth embodiment can be applied to each embodiment other than the second embodiment and modifications of each embodiment.

[0227] As described above, according to the eighth embodiment of the present technology, the pixel side current source 353 is connected to the vertical signal line VSL, and therefore the current amounts of the currents Id1 and Id2 can be suppressed.

[0228] <9. Ninth Implementation Plan>

[0229] In the second embodiment described above, a pMOS transistor is used as the input-side clamp transistor. However, an nMOS transistor may also be used. The comparator 300 according to the ninth embodiment differs from the second embodiment in that an nMOS transistor is used as the input-side clamp transistor.

[0230] Figure 24 1 is a circuit diagram illustrating a configuration example of a comparator 300 according to a ninth embodiment of the present technology. The comparator 300 of the ninth embodiment differs from the second embodiment in that it includes an input-side clamp transistor 354 in place of the input-side clamp transistor 342. An nMOS transistor is used as the input-side clamp transistor 354. The gate and drain of the input-side clamp transistor 354 are short-circuited.

[0231] Note that the ninth embodiment can be applied to each embodiment other than the second embodiment and modifications of each embodiment.

[0232] As described above, according to the ninth embodiment of the present technology, the input side clamp transistor 354 is an nMOS transistor, and therefore the lower limit of the drain voltage Vd can be limited by the nMOS transistor.

[0233] [Modification]

[0234] In the ninth embodiment described above, the gate and drain of the input-side clamp transistor 354 are short-circuited. However, in this configuration, the lower limit voltage limited by the input-side clamp transistor 354 is determined based on the voltage of the vertical signal line VSL. This requires increasing the margin for the lower limit voltage to suppress the supply of current Id1, and the dynamic range may be reduced by this margin. Furthermore, since the output amplitude of the input transistor 312 is small, noise tends to increase. The comparator 300 according to this variation of the ninth embodiment differs from the ninth embodiment in that the lower limit of the drain voltage Vd is limited by a bias voltage.

[0235] Figure 25 1 is a circuit diagram showing a configuration example of a comparator 300 according to a modification of the ninth embodiment of the present technology. The comparator 300 according to the modification of the ninth embodiment is different from the ninth embodiment in that the bias voltage V bias3 is applied to the gate of the input side clamp transistor 354 .

[0236] By bias voltage V bias3 The application of , regardless of the voltage of the vertical signal line VSL, limits the lower limit of the drain voltage Vd and can directly prevent the supply of the drain current Id1 from being stopped.

[0237] Note that in cases where dynamic range and noise issues do not arise, e.g. Figure 24As shown in FIG, a configuration that does not use a bias voltage can be adopted. Figure 24 In the configuration of , the lower limit voltage to be limited is associated with the voltage of the vertical signal line VSL, and therefore, Figure 25 Compared with the configuration in , the dependence of the maximum amplitude of the gate-source voltage of the output transistor 315 on the signal level is suppressed, and the linearity error and the gain error can be reduced.

[0238] As described above, according to the modification of the ninth embodiment, the lower limit of the drain voltage Vd is limited by the bias voltage, and thus a reduction in the dynamic range and degradation of noise can be suppressed.

[0239] <10. Tenth Implementation Plan>

[0240] In the second embodiment described above, the input transistor 312 in the comparator 300 is connected to the DAC 230 via the capacitor 311. However, in this configuration, a kickback from the comparator 300 in a certain column to the DAC 230 may interfere with adjacent columns via the signal line for transmitting a reference signal. The comparator 300 according to the tenth embodiment differs from the second embodiment in that a buffer is added between the capacitor 311 and the DAC 230.

[0241] Figure 26 1 is a circuit diagram showing a configuration example of a comparator 300 according to a tenth embodiment of the present technology. The comparator 300 according to the tenth embodiment is different from that of the second embodiment in that a buffer 355 is further included.

[0242] The buffer 355 is inserted between the DAC 230 and the capacitor 311. Note that the buffer 355 is arranged for each column, but the arrangement is not limited to this configuration. For example, the buffer 355 may be arranged for each of a plurality of columns.

[0243] The buffer 355 can make the load of the comparator 300 invisible to the DAC 230. In addition, the kickback from the comparator 300 in a column can be prevented from interfering with the columns adjacent to the column via the signal line for transmitting the reference signal.

[0244] Note that the tenth embodiment can be applied to each embodiment other than the second embodiment and modifications of each embodiment.

[0245] As described above, according to the tenth embodiment of the present technology, the buffer 355 is inserted between the DAC 230 and the capacitor 311 , and thus it is possible to prevent the kickback of a specific column from interfering with the adjacent column.

[0246] <11. Eleventh Implementation Plan>

[0247] In the second embodiment described above, the lower limit of the drain voltage Vd of the input transistor 312 is limited by the input-side clamp transistor 342. However, the state of the transistor constituting the output-side current source 330 becomes non-conductive due to the decrease in the drain voltage of the output transistor 315, and the supply of the current Id2 can be stopped. The comparator 300 according to the eleventh embodiment differs from the second embodiment in that an output-side clamp transistor is added to limit the lower limit of the drain voltage of the output transistor 315.

[0248] Figure 27 1 is a circuit diagram showing a configuration example of a comparator 300 according to an eleventh embodiment of the present technology. The comparator 300 according to the eleventh embodiment differs from the second embodiment in that it further includes an output-side clamp transistor 356.

[0249] The output-side clamp transistor 356 is inserted between the source and drain of the output transistor 315. A pMOS transistor is used as the output-side clamp transistor 356, and the gate of the output-side clamp transistor 356 is short-circuited with the drain of the output-side clamp transistor 356. Furthermore, it is desirable to short-circuit the bottom gate and source of the output-side clamp transistor 356. By adding the output-side clamp transistor 356, a decrease in the drain voltage of the output transistor 315 is suppressed, and the supply of the drain current Id2 can be prevented from being stopped.

[0250] Note that the eleventh embodiment can be applied to each embodiment other than the second embodiment and modifications of each embodiment.

[0251] As described above, the output-side clamp transistor 356 suppresses a decrease in the drain voltage of the output transistor 315 , and thus can prevent the supply of the drain current Id2 from being stopped.

[0252] [Modification]

[0253] In the above-described eleventh embodiment, a pMOS transistor is used as the output-side clamp transistor. However, an nMOS transistor may also be used. The comparator 300 according to the modified example of the eleventh embodiment differs from the eleventh embodiment in that an nMOS transistor is used as the output-side clamp transistor.

[0254] Figure 28 1 is a circuit diagram showing a configuration example of a comparator 300 according to a modification of the eleventh embodiment of the present technology. The comparator 300 according to the modification of the eleventh embodiment differs from the eleventh embodiment in that it includes an output-side clamp transistor 357 instead of the output-side clamp transistor 356.

[0255] An nMOS transistor is used as the output side clamp transistor 357. In addition, a predetermined bias voltage V bias4is applied to the gate of the output-side clamp transistor 357.

[0256] Notice, Figure 28 The gate and drain of the output side clamp transistor 357 can be like Figure 24 The input side clamp transistor 354 is short-circuited as shown in FIG.

[0257] As described above, since the output-side clamp transistor 357 is an nMOS transistor in the modification of the eleventh embodiment of the present technology, the lower limit of the drain voltage of the output transistor 315 can be restricted by the nMOS transistor.

[0258] <12. Twelfth Implementation Plan>

[0259] In the first embodiment described above, the input-side current source 320 is connected to the drain of the input transistor 312. However, in this configuration, when the input transistor 312 is in a non-conductive state, the drain voltage Vd decreases, and the state of the transistor constituting the input-side current source 320 becomes a non-conductive state, and the supply of the drain current Id1 can be stopped. The comparator 300 according to the twelfth embodiment differs from the comparator 300 according to the first embodiment in that the supply of the drain current Id1 is prevented from being stopped by adding a clamp switch.

[0260] Figure 29 1 is a circuit diagram showing a configuration example of a comparator 300 according to a twelfth embodiment of the present technology. The comparator 300 according to the twelfth embodiment is different from the first embodiment in that a clamp switch 358 is further included.

[0261] The clamp switch 358 supplies a predetermined lower limit voltage V to the connection node between the DAC 230 and the capacitor 311 according to the control signal clampSW from the timing control unit 220. ref .

[0262] Figure 30 1 is a timing chart showing an example of changes in the input and output signals of the comparator 300 according to the twelfth embodiment of the present technology. The timing control unit 220 supplies the control signal clampSW during the pulse period starting from time T4. The clamp switch 358 is controlled to be in a closed state by the control signal clampSW. As a result, the lower limit voltage V is supplied. ref , regardless of the input voltage V VSL In any case, the input transistor 312 is turned on, and the decrease in the drain voltage Vd can be suppressed.

[0263] As described above, according to the twelfth embodiment of the present technology, the clamp switch 358 suppresses a decrease in the drain voltage Vd, thereby preventing the supply of the drain current Id1 from being stopped.

[0264] <13. Thirteenth Implementation Plan>

[0265] In the second embodiment described above, the input-side clamp transistor 342 is inserted between the source and drain of the input transistor 312 to limit the lower limit of the drain voltage Vd. However, it may be difficult to adjust the lower limit voltage using only the input-side clamp transistor 342. The comparator 300 according to the thirteenth embodiment differs from the second embodiment in that the lower limit voltage is adjusted using a resistor element.

[0266] Figure 31 13 is a circuit diagram showing a configuration example of a comparator 300 according to a thirteenth embodiment of the present technology. The comparator 300 according to the thirteenth embodiment is different from the comparator 300 according to the second embodiment in that a resistor element 359 is further included.

[0267] Input-side clamp transistor 342 and resistor 359 are connected in series between the source and drain of input transistor 312. Resistor 359 may be a variable resistor. When used as a variable resistor, the resistance value of the variable resistor is stored in a register, etc. By adjusting the resistance value of resistor 359, the lower limit voltage to be clamped can be set to an optimal value. Furthermore, resistor 359 can be implemented by using an active element as the resistor.

[0268] Note that the thirteenth embodiment can be applied to each embodiment other than the second embodiment and modifications of each embodiment.

[0269] As described above, according to the thirteenth embodiment of the present technology, the resistance element 359 is added, and therefore the lower limit voltage can be set to an optimal value by adjusting the resistance value of the resistance element 359 .

[0270] <14. Application Examples of Mobile Objects>

[0271] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can also be implemented as a device installed on any type of mobile object such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, a robot, etc.

[0272] Figure 32 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0273] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 32In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as functional components of integrated control unit 12050, a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0274] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates the vehicle's drive force, a drive force transmission mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates the vehicle's braking force.

[0275] The main system control unit 12020 controls the operation of various devices attached to the vehicle body according to various programs. For example, the main system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, instead of key presses, radio waves transmitted from a portable device or signals from various switches can be input to the main system control unit 12020. The main system control unit 12020 receives the input of radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0276] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing such as people, cars, obstacles, signs, text on the road, and the like, or distance detection processing.

[0277] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal based on the amount of light received. Imaging unit 12031 can output the electrical signal as an image or as distance measurement information. Furthermore, the light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0278] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 for detecting the driver's state is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that captures the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or can determine whether the driver is drowsy.

[0279] For example, the microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on the information inside and outside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output control instructions to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of the vehicle, tracking driving based on the distance between vehicles, vehicle speed maintenance driving, vehicle collision warning, and vehicle lane departure warning.

[0280] In addition, the microcomputer 12051 can perform coordinated control by controlling the driving force generating device, steering mechanism, braking device, etc. based on the information about the vehicle's surroundings obtained in the vehicle-external information detection unit 12030 or the vehicle-inside information detection unit 12040, so as to achieve automatic driving in which the vehicle travels autonomously without relying on the driver's operation.

[0281] Furthermore, the microcomputer 12051 can output a control command to the main system control unit 12020 based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 performs coordinated control by controlling the headlights and switching the high beam to the low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0282] The sound and image output unit 12052 transmits at least one of a sound and an image output signal to an output device that can visually or auditorily notify the vehicle occupants or the outside of the vehicle of information. Figure 32 In the example of FIG, as output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0283] Figure 33 is a diagram showing an example of the installation position of the imaging unit 12031.

[0284] exist Figure 33, imaging units 12101 , 12102 , 12103 , 12104 , and 12105 are included as imaging unit 12031 .

[0285] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are disposed at locations such as the front of the vehicle 12100, the side-view mirrors, the rear bumper, the rear door, and the upper side of the windshield inside the vehicle. Imaging unit 12101 disposed at the front of the vehicle and imaging unit 12105 disposed at the upper side of the windshield inside the vehicle primarily obtain images of the front of the vehicle 12100. Imaging units 12102 and 12103 disposed at the side-view mirrors primarily obtain images of the sides of the vehicle 12100. Imaging unit 12104 disposed at the rear bumper or rear door primarily obtains images of the rear of the vehicle 12100. Imaging unit 12105 disposed at the upper side of the windshield inside the vehicle is primarily used to detect vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0286] Notice, Figure 33 The figure shows examples of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located at the front of the vehicle. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, which are located at the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 can be obtained.

[0287] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or an imaging element having pixels for phase difference detection.

[0288] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 determines the distance to three-dimensional objects within imaging ranges 12111-12114 and the temporal change in distance (relative speed to vehicle 12100), thereby extracting a three-dimensional object located on the driving route, particularly one closest to vehicle 12100 and traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher), as the leading vehicle. Furthermore, microcomputer 12051 can set a predetermined distance between vehicles ahead of the leading vehicle and perform automatic braking control (including tracking travel stop control), automatic acceleration control (including tracking travel start control), and other functions. In this way, coordinated control such as autonomous driving, in which the vehicle travels autonomously without relying on driver input, can be performed.

[0289] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 can classify the 3D object data to be extracted into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other 3D objects such as utility poles, and can use this data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as those visually recognizable by the driver of vehicle 12100 and those difficult for the driver to visually recognize. Microcomputer 12051 then determines a collision risk, indicating the degree of risk of collision with each obstacle. If the collision risk is at or above a set value and a collision is possible, microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via audio speaker 12061 or display unit 12062 and by initiating forced deceleration or evasive steering via drive system control unit 12010.

[0290] At least one of the imaging units 12101-12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may determine whether a pedestrian is present in the images captured by the imaging units 12101-12104, thereby identifying the pedestrian. For example, pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which function as infrared cameras, and performing pattern matching on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio and video output unit 12052 causes the display unit 12062 to superimpose and display a rectangular outline on the identified pedestrian for emphasis. Furthermore, the audio and video output unit 12052 may cause the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0291] An example of a vehicle control system to which the technology of the present disclosure is applicable has been described. The technology of the present disclosure is applicable to the imaging unit 12031 in the above-mentioned configuration. Specifically, Figure 1 The imaging device 100 in can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a captured image that is easy to view can be obtained, and thus the driver's fatigue can be reduced.

[0292] Note that the above embodiments illustrate examples for embodying the present technology, and that the matters in the embodiments and the matters used to specify the technology in the claims each have a corresponding relationship. Similarly, the matters used to specify the technology in the claims and the matters in the embodiments of the present technology with the same names each have a corresponding relationship. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the main purpose of the present technology.

[0293] Note that the effects described in this specification are merely examples and are not restrictive, and other effects may be exhibited.

[0294] Note that the present technology may also have the following configurations.

[0295] (1) A solid-state image sensor comprising:

[0296] an input transistor configured to output a drain voltage from a drain in accordance with an input voltage input to a source when the input voltage input to a gate substantially coincides with a predetermined reference voltage input to the gate; and

[0297] An output transistor configured to output a signal indicating whether a difference between the input voltage input to the source and the drain voltage input to the gate exceeds a predetermined threshold voltage as a comparison result between the input voltage and the reference voltage.

[0298] (2) The solid-state image sensor according to (1), further comprising:

[0299] an input-side current source connected to the drain of the input transistor; and

[0300] An input-side clamp transistor is configured to limit a lower limit of the drain voltage.

[0301] (3) The solid-state image sensor according to (2), wherein

[0302] The input-side clamp transistor is inserted between the source of the input transistor and a power supply terminal.

[0303] (4) The solid-state image sensor according to (2), wherein

[0304] The input-side clamp transistor is inserted between the source and drain of the input transistor.

[0305] (5) The solid-state image sensor according to any one of (2) to (4), wherein

[0306] The input-side clamp transistor is a P-type transistor.

[0307] (6) The solid-state image sensor according to any one of (2) to (4), wherein

[0308] The input side clamp transistor is an N-type transistor, and

[0309] The gate and drain of the input-side clamp transistor are short-circuited.

[0310] (7) The solid-state image sensor according to any one of (2) to (4), wherein

[0311] The input side clamp transistor is an N-type transistor, and

[0312] A bias voltage is applied to the gate of the input-side clamp transistor.

[0313] (8) The solid-state image sensor according to (2), wherein

[0314] The input-side clamp transistor includes a plurality of transistors connected in series between a source and a drain of the input transistor.

[0315] (9) The solid-state image sensor according to any one of (2) to (8), further comprising:

[0316] Resistive element, where

[0317] The input-side clamp transistor and the resistance element are connected in series between the source and drain of the input transistor.

[0318] (10) The solid-state image sensor according to any one of (1) to (9), further comprising:

[0319] an output-side current source connected to the drain of the output transistor; and

[0320] An output-side clamp transistor is configured to limit a lower limit of a drain voltage of the output transistor.

[0321] (11) The solid-state image sensor according to (10), wherein

[0322] The output-side clamping transistor is a P-type transistor.

[0323] (12) The solid-state image sensor according to (10), wherein

[0324] The output-side clamping transistor is an N-type transistor.

[0325] (13) The solid-state image sensor according to (1), further comprising:

[0326] a reference voltage supply unit configured to supply the reference voltage to the gate of the input transistor via a predetermined connection node; and

[0327] The clamp switch is configured to supply a predetermined lower limit voltage to the connection node according to a predetermined control signal.

[0328] (14) The solid-state image sensor according to any one of (1) to (13), further comprising:

[0329] An initialization switch is configured to open and close a path between the gate and the drain of the output transistor.

[0330] (15) The solid-state image sensor according to any one of (1) to (14), further comprising:

[0331] an output-side current source connected to the drain of the output transistor, wherein

[0332] The output-side current source comprises:

[0333] a current source transistor inserted between the drain of the output transistor and a predetermined reference terminal,

[0334] capacitor, which is connected to the gate of the current source transistor, and

[0335] A first auto-zero switch is configured to open and close a path between the gate and the drain of the current source transistor.

[0336] (16) The solid-state image sensor according to (15), further comprising:

[0337] an input-side cascode-connected transistor having its cascode connected to the drain of the input transistor; and

[0338] The output-side cascode-connected transistor has a cascode connected to the drain of the output transistor.

[0339] (17) The solid-state image sensor according to (1), further comprising:

[0340] a capacitor inserted between the drain of the input transistor and the gate of the output transistor; and

[0341] A second auto-zero switch is configured to short-circuit a path between the gate and the drain of the output transistor.

[0342] (18) The solid-state image sensor according to any one of (1) to (17), further comprising:

[0343] Logic gates, which are configured to perform predetermined logical operations, wherein

[0344] The output transistor outputs the comparison result via the logic gate.

[0345] (19) The solid-state image sensor according to any one of (1) to (18), further comprising:

[0346] a pixel circuit configured to input the input voltage to a source of the input transistor via a predetermined vertical signal line; and

[0347] A pixel-side current source is connected to the vertical signal line.

[0348] (20) The solid-state image sensor according to any one of (1) to (19), further comprising:

[0349] a reference voltage supply unit configured to supply the reference voltage; and

[0350] A buffer is inserted between the gate of the input transistor and the reference voltage supply unit.

[0351] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made according to design requirements and other factors within the scope of protection of the appended claims or their equivalents.

[0352] [Reference Signs List]

[0353] 100 Imaging Device

[0354] 110 optical unit

[0355] 120 DSP circuit

[0356] 130 display units

[0357] 140 operating units

[0358] 150 bus

[0359] 160 frame memory

[0360] 170 storage units

[0361] 180 Power Supply Unit

[0362] 200 solid-state image sensor

[0363] 205 pads

[0364] 210 vertical scanning circuit

[0365] 220 Timing Control Unit

[0366] 230 DAC

[0367] 240 pixel array unit

[0368] 250 pixel circuit

[0369] 251 Photoelectric conversion element

[0370] 252 pass transistor

[0371] 253 Reset transistor

[0372] 254 floating diffusion layer

[0373] 255 amplifier transistor

[0374] 256 select transistors

[0375] 260 columns of signal processing units

[0376] 261 Counter

[0377] 262 latch

[0378] 270 horizontal scanning circuit

[0379] 280 connection

[0380] 290 interface

[0381] 300 Comparator

[0382] 311, 314, 322, 332, 348 capacitors

[0383] 312 Input transistor

[0384] 313, 331, 349 Auto-zero switch

[0385] 315 output transistor

[0386] 320 Input side current source

[0387] 321, 333 Current Source Transistors

[0388] 330 Output side current source

[0389] 334 Sample and Hold Switch

[0390] 341, 342, 352, 354 Input-side clamp transistors

[0391] 343 Initialization switch

[0392] 344, 346 Cascode Control Switch

[0393] 345 Input-side cascode transistor

[0394] 347 Output-side cascode transistor

[0395] 350 NOR gate

[0396] 351 Inverter

[0397] 353 pixel side current source

[0398] 355 Buffer

[0399] 356, 357 Output side clamp transistors

[0400] 358 Clamp Switch

[0401] 359 Resistor

[0402] 12031 Imaging Unit

Claims

1. An imaging device comprising: a pixel circuit configured to output a pixel signal; a pixel signal line connected to the pixel circuit; a reference signal generating circuit configured to output a reference signal; and A comparator, the comparator comprising: a first transistor, wherein a gate of the first transistor is connected to the reference signal generating circuit to receive a reference voltage corresponding to the reference signal, and a source of the first transistor is connected to the pixel signal line to receive an input voltage corresponding to the pixel signal, and a second transistor, wherein a gate of the second transistor is connected to the drain of the first transistor to receive a drain voltage, and a source of the second transistor is connected to the pixel signal line to receive an input voltage corresponding to the pixel signal, The second transistor is configured to output a signal from its drain indicating whether the difference between the input voltage input to its source and the drain voltage input to its gate exceeds a predetermined threshold voltage, and supply the signal as a comparison result to the subsequent stage of the second transistor.

2. The imaging device according to claim 1, wherein the comparator comprises: a third transistor, wherein a drain of the third transistor is connected to the pixel signal line, and a source of the third transistor is connected to a power supply terminal.

3. The imaging device according to claim 2, wherein The gate of the third transistor is configured to receive a bias voltage.

4. The imaging device according to claim 1 , wherein the comparator comprises: a third transistor, wherein a gate of the third transistor is connected to the drain of the first transistor, and a source of the third transistor is connected to the pixel signal line.

5. The imaging device according to claim 4, wherein The gate of the third transistor is connected to the drain of the third transistor.

6. The imaging device according to claim 4, wherein The bottom gate of the third transistor is connected to the source of the third transistor.

7. The imaging device according to claim 4, wherein the comparator further comprises: a fourth transistor, wherein a drain of the fourth transistor is connected to the pixel signal line, and a source of the fourth transistor is connected to the drain of the third transistor.

8. The imaging device according to claim 7, wherein The gate of the fourth transistor is configured to receive a bias voltage.

9. The imaging device according to claim 1, wherein The bottom gate of the first transistor is connected to the source of the first transistor, and the bottom gate of the second transistor is connected to the source of the second transistor.

10. The imaging device according to claim 1, wherein The pixels are arranged in a first substrate, and the comparator is arranged in a second substrate bonded to the first substrate.

11. The imaging device according to claim 10, wherein The first substrate and the second substrate are electrically connected through through-silicon vias.

12. The imaging device according to claim 10, wherein The first substrate and the second substrate are electrically connected by direct bonding.

13. A comparator comprising: a first input terminal configured to receive a pixel signal; a second input configured to receive a reference signal; a first transistor, wherein a gate of the first transistor is connected to the second input terminal to receive a reference voltage corresponding to the reference signal, and a source of the first transistor is connected to the first input terminal to receive an input voltage corresponding to the pixel signal; and a second transistor, wherein a gate of the second transistor is connected to the drain of the first transistor to receive the drain voltage, and a source of the second transistor is connected to the first input terminal to receive an input voltage corresponding to the pixel signal, The second transistor is configured to output a signal from its drain indicating whether the difference between the input voltage input to its source and the drain voltage input to its gate exceeds a predetermined threshold voltage, and supply the signal as a comparison result to the subsequent stage of the second transistor.

14. The comparator according to claim 13, comprising: a third transistor, wherein a drain of the third transistor is connected to the first input terminal, and a source of the third transistor is connected to the power supply terminal.

15. The comparator according to claim 14, wherein The gate of the third transistor is configured to receive a bias voltage.

16. The comparator according to claim 13, comprising: a third transistor, wherein a gate of the third transistor is connected to the drain of the first transistor, and a source of the third transistor is connected to the first input terminal.

17. The comparator according to claim 16, wherein: The gate of the third transistor is connected to the drain of the third transistor.

18. The comparator according to claim 16, wherein: The bottom gate of the third transistor is connected to the source of the third transistor.

19. The comparator according to claim 16, further comprising: a fourth transistor, wherein a drain of the fourth transistor is connected to the first input terminal, and a source of the fourth transistor is connected to the drain of the third transistor.

20. The comparator of claim 19, wherein a gate of the fourth transistor is configured to receive a bias voltage.

21. The comparator according to claim 13, wherein The bottom gate of the first transistor is connected to the source of the first transistor, and the bottom gate of the second transistor is connected to the source of the second transistor.

Images