Flip Conductor Patch Lamination for Ultra-Fine Line Substrate Formation

Abstract

The present invention discloses a laminated circuit board structure, which includes a printed circuit board substrate (16) having conductive wiring traces (not shown) on at least a first wiring surface, a prepreg layer (18) formed above the first wiring surface, and a patch (10) having an area of less than 1,000 mm<supgt;2< / supgt>. The patch includes conductive wiring traces (14a-14d) formed on a wiring surface and is laminated above the prepreg layer to the printed circuit board substrate. The patch is oriented such that the wiring surface contacts the prepreg layer and is pressed into the prepreg layer. A portion of the prepreg layer fills the gaps between the conductive wiring traces.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates to substrates for circuit components. More particularly, the present invention relates to a laminated structure providing an extremely fine conductive trace layer for use on a printed circuit board substrate.

[0002] As die sizes shrink (but the number of pins typically increases), there is a need to develop packaging interconnect technologies to interface with these evolving dies while meeting the demand for size reduction. Wire bonding the connection of die pads to a carrier substrate has been an excellent interfacing method, but more recently chip scale packages (CSP dies or "flip chips") are more often directly connected to the substrate, thus shifting the "fan out" problem of the traces to the printed circuit board (PCB) substrate.

[0003] Etched fine line traces / gaps on the PCB have become a problem, mainly because as the width of the conductive traces becomes smaller, etching reaches its process limit and the adhesion of the copper traces and connection pads to the substrate is greatly reduced.

[0004] Some PCB and die packaging enterprises have developed methods with extremely fine trace layers on the outside of their substrates. PCB and IC companies such as Kyocera, Toshiba, and Cicor have developed processes to add ultra-fine line capabilities to integrate their IC and PCB laminated structures and products. These methods are generally more expensive and do not provide the flexibility required for some designs that incorporate different elements of the design, such as dies, SMT components, and PCBs that are typically purchased separately and not necessarily from the same source.

[0005] As dies begin to be integrated into the substrate itself, the process is no longer a straightforward substrate design, and manufacturing and assembly become integrated (and often proprietary) activities that require methods different from simply providing a PCB and assembling components onto it. These activities generally involve proprietary additive processes rather than subtractive etching processes, but are still limited in terms of where and how these processes can be introduced into the design (usually at the outer layer).

[0006] One problem is the ability to provide the capability to include ultra-fine trace layers in a PCB laminated structure, where such trace layers are not part of a normal PCB construct. Another problem is the difficulty in providing small vias in a laminated PCB structure. Yet another problem is minimizing the lateral area required to make connections between the lower and upper layers of a laminated PCB assembly. Still another problem is that the layers laminated onto the PCB substrate undergo non-linear and uncontrolled stretching, making layer registration difficult. SUMMARY OF THE INVENTION

[0007] According to one aspect of the present invention, a laminated circuit board structure includes a printed circuit board substrate having wiring traces on at least its first wiring surface, a prepreg layer formed above the first wiring surface of the printed circuit board substrate, and a chip formed of a non-conductive substrate and having wiring traces formed on the wiring surface of the non-conductive substrate. The chip is laminated onto the printed circuit board substrate above the prepreg layer. The chip is oriented such that its wiring surface contacts the prepreg layer and is pressed into the prepreg layer, and a portion of the prepreg layer fills the gaps between the wiring traces on the chip.

[0008] According to one aspect of the present invention, the laminated circuit board structure further includes at least one opening formed through the non-conductive substrate of the chip and communicating with at least one wiring trace on the wiring surface of the chip, and a conductive material disposed in each of the at least one opening and in electrical contact with at least one wiring trace on the wiring surface of the chip.

[0009] According to one aspect of the present invention, the conductive material disposed in each of the at least one opening and in contact with the exposed at least one wiring trace is a solder bump.

[0010] According to one aspect of the present invention, the conductive material disposed in each of the at least one opening and in contact with the exposed at least one wiring trace is a conductive ink layer.

[0011] According to one aspect of the present invention, the laminated circuit board structure further includes solder bumps disposed on the wiring traces on the chip, solder bumps disposed on the wiring traces on the first wiring surface of the printed circuit board substrate at positions aligned with the solder bumps disposed on the wiring traces on the chip, and a z-axis tape layer disposed between the printed circuit board substrate and the chip, at least between the solder bumps disposed on the chip and the solder bumps disposed on the printed circuit board substrate.

[0012] According to one aspect of the present invention, the laminated circuit board structure further includes solder bumps disposed on the wiring traces on the chip, an integrated circuit die having at least one connection pad at a position aligned with the solder bumps disposed on the wiring traces on the chip, and a z-axis tape layer disposed between the integrated circuit die and the chip, at least between the solder bumps disposed on the chip and the connection pads disposed on the integrated circuit die. The at least one connection pad may be a solder bump.

[0013] According to one aspect of the present invention, the laminated circuit board structure further includes conductive traces on a second wiring surface of a printed circuit board substrate, a first conductive via formed through the printed circuit board substrate to establish electrical contact between one of the wiring traces on the first wiring surface of the printed circuit board substrate and one of the wiring traces on the second wiring surface of the printed circuit board substrate, and a second conductive via formed through a prepreg layer and in electrical contact with the wiring traces on the chip. The second conductive via is in electrical contact with the wiring traces on the first wiring surface of the printed circuit board substrate. The laminated circuit board structure may further include an upper prepreg layer disposed above the solder bump integrated circuit die, and a top printed circuit board disposed above the upper prepreg layer.

[0014] According to one aspect of the present invention, the chip further includes a plurality of pre-formed openings in the chip, each pre-formed opening communicating with at least one wiring trace on a wiring surface of the chip; a solder printing area formed in the pre-formed opening; and at least one surface mount component electrically connected to the solder printing area formed in the pre-formed opening.

[0015] According to one aspect of the present invention, the non-conductive substrate of the chip is formed of polyimide.

[0016] According to one aspect of the present invention, the chip has an area of less than 1000 mm 2 ².

[0017] According to one aspect of the present invention, a method for forming a chip for a laminated circuit board structure includes providing a non-conductive material layer having a conductive electroplating seed layer formed on its surface; applying a photoresist layer above the surface of the conductive electroplating seed layer; defining wiring channels in the photoresist resist layer using photolithography and etching processes; electroplating a first layer of conductive material in the wiring channels; electroplating a second layer of conductive material above the first layer in the wiring channels; adhering a non-conductive layer above the photoresist layer and the plated conductive material in the wiring channels; and removing the non-conductive layer and the conductive electroplating seed layer.

[0018] According to one aspect of the present invention, providing a non-conductive material layer having a conductive electroplating seed layer formed on its surface includes providing a polyester material layer having a conductive electroplating seed layer formed on its surface.

[0019] According to one aspect of the present invention, electroplating the first layer includes electroplating a gold layer in the wiring channels.

[0020] According to one aspect of the present invention, electroplating the second layer includes electroplating a nickel layer above the first layer in the wiring channels.

[0021] According to one aspect of the present invention, laminating a non-conductive layer over a photoresist layer and an electroplated layer of conductive material in a wiring channel includes attaching a layer of one of polyester or polyimide over the photoresist layer and the plated conductive material in the wiring channel using a transfer adhesive.

[0022] According to one aspect of the present invention, a patch includes a non-conductive thin substrate having an area of less than 1000 mm 2 The non-conductive flexible substrate has a wiring surface. A layer of conductive material is formed on the wiring surface of the non-conductive substrate, and areas of the conductive material layer are etched away to define a plurality of wiring traces on the wiring surface of the non-conductive flexible substrate, with at least some of the wiring traces having a width no wider than 50 μ.

[0023] According to one aspect of the present invention, areas of the conductive material are etched away to form areas of conductive material that are disposed between the wiring traces and insulated from the wiring traces. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will be explained in more detail below with reference to embodiments and the drawings, in which:

[0025] Figures 1A to 1I is a cross-sectional schematic view showing the formation of a patch circuit assembly structure according to an exemplary embodiment of the present invention;

[0026] Figure 2 is a schematic top view showing an exemplary patch according to the present invention;

[0027] Figures 3A to 3E are a cross-sectional view and a top view of an exemplary embodiment of the present invention, in which the patch is foldable to provide bottom-to-top connection of a laminated structure; and

[0028] Figures 4A to 4G is a cross-sectional schematic view showing the formation of a patch according to other exemplary embodiments of the present invention. DETAILED DESCRIPTION

[0029] Those of ordinary skill in the art will recognize that the following description is merely illustrative and not limiting in any way. Other embodiments will be readily apparent to those skilled in the art.

[0030] First, refer to Figure 1A, The cross-sectional view shows a substrate "patch" 10, which can be used to provide an extremely fine conductive trace layer for use on a printed circuit board substrate. According to one aspect of the present invention, the patch can be formed of a flexible material. A non-conductive substrate 12 formed of a material layer (such as a polyimide layer) that can withstand the temperatures encountered during the PCB lamination process is shown, and a conductive layer 14 is formed above the wiring surface of the non-conductive substrate 12 by known processes such as deposition or etching. In one aspect of the present invention, the conductive layer 14 is a copper layer. According to one aspect of the present invention, the non-conductive substrate 12 is "thin". According to the present invention, the "thin" non-conductive substrate 12 has a thickness of less than about 100 μ and preferably between about 10 μ and about 50 μ. According to one aspect of the present invention, portions of the conductive layer 14 are etched away using conventional lithography and etching techniques to form a pattern of conductive wiring traces, including exemplary traces 14a, 14b, 14c, and 14d as shown in the cross-sectional schematic diagram of Figure 1B . According to one aspect of the present invention, at least some of the wiring traces have a width no wider than 50 μ.

[0031] The non-conductive substrate 12 having defined conductive traces 14a, 14b, 14c, and 14d is oriented such that its conductive traces 14a, 14b, 14c, and 14d face downward and are placed on the surface of a PCB substrate 16 on which a prepreg layer 18 has been formed. A prepreg layer (short for "pre-impregnated") is a substrate fabric impregnated with a resin (an example of which is the NEMA grade name FR4), such as fiberglass. The resin is pre-dried but not hardened, so when the resin is heated under pressure during the lamination process, it flows, adheres, and covers the conductive traces 14a, 14b, 14c, and 14d and fills all the gaps between the conductive traces 14a, 14b, 14c, and 14d.

[0032] As previously pointed out, the etched fine-line tracks / gaps on prior art PCBs become a problem, mainly because when the line width of the tracks becomes smaller and etching reaches its process limit, the adhesion of the copper tracks / pads to the substrate is greatly reduced. A typical conductive trace used in the present invention can be about 24 μ wide and about 12 μ high. It is conceivable that the present invention can be implemented using conductive traces having a width as small as about 1 μ and a thickness of about 1 μ. During the lamination process, the prepreg layer 18 forms around the conductive traces 14a, 14b, 14c, and 14d and provides dimensional stability for these conductive traces, filling all the gaps between them.

[0033] Figure 1Cis a cross-sectional schematic view of a laminated structure, which shows a structure obtained after laminating a patch 10 including a non-conductive substrate 12 having conductive traces 14a, 14b, 14c, and 14d to a PCB substrate 16 and a prepreg layer 18 by pressing and heating to laminate the prepreg layer 18, as is known in the art. Figure 1C shows that the conductive traces 14a, 14b, 14c, and 14d are firmly embedded in the prepreg layer 18 of the hybrid laminated substrate, which includes the PCB substrate 16 and the patch 10, and the patch includes the non-conductive substrate 12 and the conductive traces 14a, 14b, 14c, and 14d.

[0034] Now refer to Figure 1D , which shows a cross-sectional schematic view of the laminated structure after small holes 18 (e.g., with a diameter down to about 20 μm or less) have been formed in the non-conductive substrate 12. This can be done using, for example, laser ablation. Larger holes (e.g., hole 20) for more time-consuming surface mount technology (SMT) components (e.g., components of 0201 size and above) can be formed in the non-conductive substrate 12 by laser ablation, for example as a laser-cut opening through which Sn / Cu paste can be printed and then sintered according to the ordinary surface mount technology (SMT) solder attachment assembly process. Figure 1D shows the laminated structure after holes 18 and 20 have been formed in the non-conductive substrate 12 to expose the copper conductive traces 14a, 14b, 14c, and 14d.

[0035] Now refer to Figure 1E , which shows a cross-sectional schematic view of the laminated structure after solder bumps 22 have been formed in the small holes 18 and larger solder bumps 24 have been formed in the larger holes 20. The solder bumps 22 are used to connect to chip-scale package (CSP) die pads and are also used for small SMT components, such as resistors or capacitors of 01005 (about 10 mils × 5 mils), 0201 (about 20 mils × 10 mils), or 008004 (about 8 mils × 4 mils) size. Figure 1F is a cross-sectional schematic view of a laminated structure, which shows a solder pad integrated circuit die 26 combined with the solder bumps 22 previously formed in the holes 18 and an SMT component 30, and one lead 32 of the SMT component 30 is shown combined with the larger solder bumps 24 previously formed in the holes 20. According to one aspect of the present invention, the holes 18 can be filled with conductive ink. Placing and connecting the solder pad integrated circuit die 26 and the SMT component 30 on the laminated structure using fiducial points by existing pick-and-place equipment is known in the art.

[0036] Prior art lamination processes for producing PCBs use sheets or panels of FR4 or similar material that are typically 24" x 18" (approximately 600mm x 450mm). Registration of pre-etched layers for lamination onto an existing pre-etched panel is extremely difficult at this scale, and the registration problem is exacerbated by the fact that the materials involved will stretch differently, especially when they are not of the same type. Even if the two pre-etched layers can be aligned within the target tolerance, any differences in the coefficients of thermal expansion of these materials will cause a host of problems across the 600 x 450mm panel. Mechanical registration of the different layers using drilled tool holes at these opposing scales is simply not an option. This has given rise to PCB manufacturing practices where the PCB manufacturing machine will build onto an existing core, etching new layers after registering them to the existing underlying pattern using, among other things, computerized adjustments for stretching.

[0037] The present invention contemplates the use of relatively smaller patches 10 compared to the prior art. The patch circuit area is relatively small and can be placed in a step-and-repeat pattern across an FR4 panel. A non-limiting example of such a patch according to the present invention is a 9mm×9mm patch "component" formed on a 50μ thick flexible polyimide substrate using a 50μ wide track (having a thickness of approximately 9μ) formed from 1 / 4 ounce copper. It is currently contemplated that a 15μ track having a thickness of approximately 7.5μ is possible using the etching concepts of the present invention. Such small patch components can be very accurately machine placed locally on a PCB using reference points using existing pick-and-place equipment as is known in the art. Generally speaking, the area of a patch according to the present invention is no greater than approximately 500mm 2 About 1,000mm 2 When the area of the patch increases above this value, registration and stretching issues start to become untenable, leading to assembly issues.

[0038] Interlayer vias are also important in printed circuit board assemblies, and efforts have been made to make them as small as possible, given the thickness of the layers that form them. The technology of the present invention includes another way to form interlayer vias using via filling materials (Sn / Cu paste sintered in the lamination). Since the patches can be accurately placed using SMT equipment, the vias on different layers and the small pads for printing solder bumps can be accurately matched. Figure 1G and Figure 1H This aspect of the invention is shown.

[0039] Figure 1G is a cross-sectional view of an exemplary laminated PCB assembly according to another aspect of the present invention. Figure 1GThe exemplary laminated PCB assembly depicted in [Figure 0] shows a solder pad 28 of an integrated circuit die 26 connected to a conductive trace 36 on a second wiring surface of a PCB substrate 16 through solder bumps 22, a conductive trace 14d of a chip 10, a via 40 formed in a prepreg layer 18, a conductive trace 38 on a first wiring surface of the PCB substrate 16, and a via 34 formed through the PCB substrate 16. Those of ordinary skill in the art will understand that Figure 1G The specific circuit connections shown are entirely arbitrary and are simply shown to illustrate how multi - layer vias can be incorporated into a laminated printed circuit board assembly according to the present invention.

[0040] Figure 1H is a cross - sectional view of an exemplary laminated PCB assembly according to another aspect of the present invention. The PCB substrate 16 is shown having a via 34 formed between a conductive trace 36 on a second wiring surface of the PCB substrate 16 and a conductive trace 38 on a first wiring surface of the PCB substrate 16. A prepreg layer 18 is formed above the first wiring surface of the PCB substrate 16, and as previously described, a chip 10 including a non - conductive substrate 12 having conductive wiring traces on its surface is laminated face - down into the prepreg layer 18. A via opening is laser - cut through the non - conductive substrate 12 of the chip 10 in the prepreg layer 18. The prepreg layer 18 acts as an insulating layer, and vias leading to conductive traces on the chip 10 and / or on the underlying PCB substrate 16 are formed by printing Sn / Cu paste into the pre - laser - treated prepreg openings. Vias 42 connected to wiring traces 44 on the chip 10 are sintered during the lamination process. Vias 42 are formed by via filling before laminating the chip 10 onto the prepreg layer 18. Vias 42 establish electrical connections with wiring traces 44 on the chip 10. A second sintered via 46 is shown, which establishes an electrical connection between a wiring trace 38 on the first wiring surface of the PCB 16 and a wiring trace 48 on the non - conductive substrate 12 of the chip 10. Those of ordinary skill in the art will observe that the specific connections established by vias 42 and 46 are merely exemplary and simply show that connections can be made to the chip 10 or to the underlying PCB substrate 16, and these connections can be formed in the same process as Sn / Cu alloy vias (such as Figure 1G the via 40 shown).

[0041] Figure 1H The exemplary circuit depicted in [Figure 12] shows leads 32 of SMT components 30 connected to vias 42 and 46 using solder paste areas 50 during the assembly process. Those of ordinary skill in the art will understand that Figure 1H The specific circuit connections shown are entirely arbitrary and are simply shown to illustrate how multi - layer vias can be incorporated into a laminated printed circuit board assembly according to the present invention.

[0042] Now refer to Figure 1I, The cross-sectional view shows an exemplary laminated printed circuit board assembly according to another aspect of the present invention. The PCB substrate 16 is shown to have vias 34 formed between the conductive traces 36 on the bottom surface of the PCB substrate 16 and the conductive traces 38 on the first wiring surface of the PCB substrate 16.

[0043] In Figure 1I the exemplary embodiment shown, solder bumps 52 have been formed on the conductive traces 38 on the first wiring surface of the PCB substrate 16. Solder bumps 54 have also been formed on the conductive traces 14d of the chip 10. A sheet of z-axis tape 56 is placed in alignment with the solder bumps 52 and 54 in the void formed in the prepreg layer 18 before the chip 10 is placed above the prepreg layer 18. The z-axis tape 56 will form an electrical connection between the conductive traces 14d and the conductive traces 38 through the solder bumps 52 and 54 during the lamination process.

[0044] After the lamination process, small holes will be formed in the non-conductive substrate 12 and these holes will be filled with solder bumps 22, as previously described. An integrated circuit die 58 having solder bump connections (one of the solder bump connections is identified by reference numeral 60) can be bonded to the solder bumps 22 using a z-axis tape layer 62 in the voids that can be formed in the prepreg layers 64 and 66. Then the second PCB substrate 68 can be laminated onto the underlying structure. For illustrative purposes, the second PCB substrate 68 is shown to include vias 70 formed between the conductive traces 72 on the bottom surface of the PCB substrate 68 and the conductive traces 74 formed on the first wiring surface of the PCB substrate 68. One or more additional prepreg layers 76 are placed above the die 58 and the prepreg layers 64 and 66 to maintain electrical and mechanical integrity laminated to the die 58 due to being embedded therein. Similar to the exemplary circuit formed by the Figure 1H laminated structure shown, those of ordinary skill in the art will understand that Figure 1I the specific circuit connections shown are entirely arbitrary and are simply shown to illustrate how multiple unique and successive overlays of a laminated circuit substrate structure can be formed to meet the needs of a wide variety of designs, including embedding very fine pitch CSP dies into a multi-layer laminated printed circuit board assembly according to the present invention.

[0045] Now referring to Figure 2 , the top view of the exemplary chip 10 shows another aspect of the present invention. The thin flexible material non-conductive substrate 12 on which the chip is formed will be very easily bendable, so copper regions 90 are included in all the gaps between the conductive traces to facilitate pick-and-place of the chip 10, thereby forming a desired flat surface after lamination.

[0046] The patch 10 includes a plurality of connection pads 82. The connection pads 82 are electrically connected to the I / O pins (one of the I / O pins is shown by reference numeral 84) of the integrated circuit die 86 by copper traces (one of the copper traces is shown by reference numeral 88) formed on a thin flexible material non-conductive substrate 12. An unetched solid copper area 90 is shown remaining in the area of the thin flexible material non-conductive substrate 12 between the I / O pads 82, the area occupied by the integrated circuit die 86, and the conductive trace 88 to provide dimensional stability to the patch 10.

[0047] Figures 3A to 3D are a top view and a cross-sectional view of an exemplary embodiment of the present invention, where the patch is foldable to provide bottom-to-top connection of the laminated structure.

[0048] Now refer to Figure 3A , the cross-sectional schematic diagram shows a folded patch 90 that includes a flexible non-conductive substrate 92 having conductive traces 94 formed on one of its surfaces. The solder pad integrated circuit die 96 has been bonded by one of its I / O pads 98 to a solder pad 100 in communication with the conductive trace 94. Figure 3A The exemplary example of shows the patch 90 laminated to the PCB substrate 102 using a prepreg layer 104. As pointed out in the previously disclosed embodiments, the conductive traces 106 on the bottom surface of the PCB substrate 102 are electrically connected through vias 110 to the conductive traces 108 on the first wiring surface of the PCB substrate 102. As previously disclosed, the wiring traces 94 on the patch 90 are shown to be electrically connected to the conductive traces 108 on the first wiring surface of the PCB substrate 102 using a piece of z-axis tape placed in a void in the prepreg layer 104 indicated by reference numeral 112.

[0049] In Figure 3AIn the illustrated embodiment, the patch 90 is folded over the solder pad integrated circuit die 96. The upper PCB substrate 114 is laminated to the top surface of the folded patch 90 by the prepreg layer 116 and includes conductive traces 118 on its bottom surface (second wiring surface), which are electrically connected to conductive traces 120 on its top surface (first wiring surface) through preformed vias 122 in the PCB substrate 114. The via 124 from the conductor 118 to the conductive trace 94 is formed by filling the holes in the laser-formed prepreg layer 116 with Sn / Cu paste, and the Sn / Cu paste is sintered during lamination to form an Sn / Cu alloy, as previously discussed. The SMT component 126 is shown to be coupled to the upper PCB substrate 114 by its solder bump I / O connections (one of the solder bump I / O connections is shown by reference numeral 128). The folded patch 90 is shown to be placed in a void formed by apertures in one or more other prepreg layers generally indicated by the dashed line to the right of the folded patch 90 by reference numeral 130 in order to maintain a sufficiently flat surface for laminating the upper PCB substrate 114 thereon.

[0050] Figure 3A An advantageous feature of the folded patch is that connections to the SMT component 126 can be established from the I / O pads of the solder pad integrated circuit die 96 without the need for vias that must be laterally disposed outside the perimeter of the solder pad die 96, thereby increasing the footprint of this portion of the circuit. This feature of the present invention is illustrated by the connection through the conductive trace 94 of the folded patch. Those of ordinary skill in the art will understand that Figure 3A is a cross-section of this structure and additional conductive traces of the folded patch can be used to route connections from other I / O pads of the solder pad integrated circuit die 96 to the top PCB substrate 114 and / or from the lower PCB substrate 102 located at a position outside the plane of the cross-section shown Figure 3A .

[0051] Now referring to Figure 3B , Figure 3C , Figure 3D and Figure 3E , a method for forming a folded patch including portions 90a and 90b is shown. Figure 3A Figure 3B , Figure 3C and Figure 3D are cross-sectional views showing the formation of the folded patch 90 Figure 3A . Figure 3B , Figure 3C and Figure 3D The cross-sections depicted in Figure 3E are taken at line A-A of Figure 3E , and

[0052] Now refer to Figure 3B , the cross-sectional view shows a substrate that is prepared to receive a patch (including portions 90a and 90b) where folding will occur. The fixture 132 includes positioning pins, and one of the positioning pins is shown by reference numeral 134. The substrate on which the folded patch 90 will be formed is shown by reference numeral 136. The substrate 136 includes a cavity 138 in which the patch will be placed before the folded patch (including portions 90a and 90b). At this time, the patch (including portions 90a and 90b) is substantially flat.

[0053] The metal slide 140 is positioned above the substrate 136 and includes a slot 142 that aligns with the positioning pin 134. The orifice 144 in the slide 140 ( Figure 3E as shown in) is positioned above the cavity 138.

[0054] Now refer to Figure 3C , the patch (including portions 90a and 90b) is placed in the cavity 138 and held in place by a thin layer of adhesive z-axis tape ( Figure 3C shown by reference numeral 146 in) to establish a connection with the pads on the PCB substrate 132. The portion of the patch 90 on which the integrated circuit die 96 is placed is shown by reference numeral 90a and lies flat within the cavity 138, and the edge of the cavity 138 and / or the edge of the orifice 144 in the sliding metal plate 140 forces the portion of the patch 90 to the right of the cavity 138, shown by reference numeral 90b, upward at an angle. The substrate 136 includes a groove 148 ( Figure 3B shown in, in which a drop of adhesive ( Figure 3C and Figure 3D shown by reference numeral 150 in) is placed).

[0055] Then the metal slide 140 is moved laterally towards the portion 90b of the patch, thereby folding the patch as shown in Figure 3D , which depicts the position of the metal slide after it has been engaged by the end of the slot 142 to prevent its lateral movement. The drop of adhesive 150 holds the distal edge of the portion 90b of the patch in its folded position when cured, thereby allowing further processing of the resulting laminated structure.

[0056] It should be noted that more than one folded patch 90a and 90b can be formed simultaneously. Figure 3E The top view of

[0057] Now refer to Figures 4A to 4F , the cross-sectional schematic view shows the formation of a patch according to another exemplary embodiment of the present invention.Figures 4A to 4E An advantage of the embodiments depicted is that an ultra-fine trace layer having a width of about 5 μm can be formed using a continuous process.

[0058] Now referring to Figure 4A , a carrier layer 160 (such as a polyester sheet) having a conductive electroplated seed layer 162 (such as graphite) deposited on one of its surfaces is preferably formed into a roll (indicated at the curled end 164). The use of a roll is not necessary to practice the present invention, but it allows for the use of a somewhat continuous roll-to-roll process in accordance with one aspect of the present invention.

[0059] As Figure 4B shown, the carrier layer 160 having the conductive electroplated seed layer 162 is cut into panels. Then, a photoresist layer 166 is formed on the surface of the metal layer on each panel and the photoresist layer is cured.

[0060] As Figure 4C shown, after the photoresist layer 166 is formed on the surface of the metal layer and the photoresist layer is cured, the photoresist layer is masked, exposed (shown by arrow 168), and etched to remove the photoresist in the desired areas as is well known in the lithography art, thereby exposing portions of the underlying conductive electroplated seed layer 162 in the wiring channels 170. The geometry of the wiring channels 170 defines the conductive traces to be formed on the finished patch.

[0061] Now referring to Figure 4D , metal is electroplated into the wiring channels 170 using the graphite conductive seed layer 162 as the cathode. Figure 4D Two metal layers are shown, namely a first metal layer 172 and a second layer 174. In one particular embodiment, the first metal layer 172 can be an Au layer (which can have a thickness of, for example, about 0.03 μm) and the second metal layer 174 can be a Ni layer (which can have a thickness of, for example, about 5 μm). Those of ordinary skill in the art will understand that in other embodiments, different metals can be employed or a single metal layer (e.g., Cu) can be used. In this additive electroplating process, conductive traces having a minimum size of about 1 μm in width and 1 μm in thickness can also be envisioned.

[0062] Now referring to Figure 4E , a patch substrate 176 (as previously noted, which can be a layer of material having an adhesive backing (such as polyester or polyimide)) is adhered to the top of the photoresist layer 166 and the top surface of the exposed second metal layer 174. The patch substrate 176 can include an adhesive backing layer 178 as a transfer adhesive and can conveniently but not necessarily be in the form of a roll as indicated by the curled edge at reference numeral 180.

[0063] Now referring to Figure 4F, the carrier layer 160 and its conductive electroplated seed layer 162 have been stripped by peeling it from the assembly layer to expose the top surface of the second metal layer 174 and the panel has been cut into the final size patches 182.

[0064] Now refer to Figure 4G , another embodiment is shown after the carrier layer 160 and its conductive electroplated seed layer 162 have been stripped by peeling it from the assembly layer and the patch has been cut into the final size panel. In this embodiment, only a single plated metal layer 184 (formed of, for example, Cu) is used. The manufacturing process is the same as that of Figures 4A to 4F the embodiment shown, except that Figures 4D to 4F the two plated metal layers 172 and 174 shown have been replaced by a single plated metal layer 184.

[0065] Various embodiments of the present invention propose small, thin and flexible patch components with ultra-fine conductive tracks, and the patch components can be very accurately machine-placed locally using fiducial points. When flipped to be laminated to a PCB substrate, the conductive tracks are embedded in the prepreg layer and the central CSP pad opening can be laser ablated through the non-conductive substrate layer 12. The thin flexible material non-conductive substrate 12 is easily bendable, so copper regions are included to fill the gaps between the conductive tracks and enable pick-and-place of the patch, thereby forming the required flat surface after lamination.

[0066] Laser ablation openings are cost-effective for small CSP and 01005 component pads. Components of about 0201 size and above can utilize different strategies while "printing and filling" the vias with a via filling material that "sinter" into a Sn / Cu alloy during lamination. For these larger component pads, the patch according to the embodiments of the present invention can have laser-cut openings (faster and cheaper than ablation), and Sn / Cu paste is printed under these openings, and the Sn / Cu paste is sintered during lamination to form component pads for ordinary SMT solder attachment. Various embodiments of the present invention enable the formation of small interlayer vias. Since the patches according to the present invention can be accurately placed using SMT equipment, the small pads (for vias) on different layers and on the solder bumps can be accurately paired.

[0067] The ultra-fine and precision tracks are laminated downward into the prepreg layer of the underlying structure including the PCB substrate, where these tracks are completely fixed, thus eliminating the low peel strength of the fine conductive tracks. The non-conductive substrate 12 becomes the "solder mask" layer of the component assembly. This eliminates the entire set of processes that would otherwise be required to add a resist layer, since the conductive tracks are accompanied by the included resist.

[0068] Due to the small size of the patches, the patches can be placed by machine with extremely high accuracy to register to the PCB substrate, thus eliminating alignment and stretching issues across the entire component panel. The use of small patches also minimizes any thermal mismatch or material delamination issues within the laminated substrate.

[0069] The present invention is particularly applicable to printed vias in PCB substrates because these connections are also "sintered" under temperature and pressure during the lamination process.

[0070] Although embodiments and applications of the present invention have been shown and described, it will be apparent to those skilled in the art that many more modifications can be made without departing from the inventive concept herein. Therefore, the invention is not limited except as by the substance of the appended claims.

Claims

1. A laminated circuit board structure, the laminated circuit board structure comprising: A printed circuit board substrate including conductive traces on at least its first wiring surface; A prepreg layer formed above the first wiring surface of the printed circuit board substrate; And A patch, the patch including: A flexible non-conductive substrate having a wiring surface; and Conductive traces formed on the wiring surface of the flexible non-conductive substrate, A solder bump disposed on one of the conductive traces on the flexible non-conductive substrate, The patch is laminated to the prepreg layer, wherein the wiring surface of the flexible non-conductive substrate faces the first wiring surface of the printed circuit board substrate, and the wiring surface of the flexible non-conductive substrate contacts and is pressed into the prepreg layer, wherein a portion of the prepreg layer fills the gap between the conductive traces on the wiring surface of the flexible non-conductive substrate, A solder bump disposed on one of the conductive traces on the first wiring surface of the printed circuit board substrate at a position aligned with the solder bump disposed on one of the conductive traces on the flexible non-conductive substrate; and A z-axis tape layer disposed between the printed circuit board substrate and the patch, at least between the solder bump disposed on one of the conductive traces on the flexible non-conductive substrate and the solder bump disposed on one of the conductive traces on the first wiring surface of the printed circuit board substrate.

2. The laminated circuit board structure according to claim 1, the laminated circuit board structure further comprising; At least one opening formed through the flexible non-conductive substrate of the patch and communicating with at least one conductive trace on the wiring surface of the flexible non-conductive substrate; and A conductive material disposed in each of the at least one opening and in electrical contact with the at least one conductive trace on the wiring surface of the flexible non-conductive substrate.

3. The laminated circuit board structure according to claim 2, wherein the conductive material is a solder bump.

4. The laminated circuit board structure according to claim 2, wherein the conductive material is a conductive ink layer.

5. The laminated circuit board structure according to claim 1, the laminated circuit board structure further comprising: A solder bump disposed on one of the conductive traces on the flexible non-conductive substrate and extending in an opening in the flexible non-conductive substrate; An integrated circuit die having at least one connection pad at a position aligned with the solder bump; And A z-axis tape layer disposed between the integrated circuit die and the patch, at least between the solder bump and the connection pad.

6. The laminated circuit board structure according to claim 5, wherein the at least one connection pad is a solder bump.

7. The laminated circuit board structure according to claim 1, the laminated circuit board structure further comprising: Conductive traces on the second wiring surface of the printed circuit board substrate; A first conductive via that is formed through the printed circuit board substrate to establish electrical contact between one of the conductive traces on the first wiring surface of the printed circuit board substrate and one of the conductive traces on the second wiring surface of the printed circuit board substrate; And A second conductive via that is formed through the prepreg layer and is in electrical contact with one of the conductive traces on the flexible non-conductive substrate.

8. The laminated circuit board structure according to claim 7, wherein the second conductive via is in electrical contact with one of the conductive traces on the first wiring surface of the printed circuit board substrate.

9. The laminated circuit board structure according to claim 5, the laminated circuit board structure further comprising: An upper prepreg layer disposed above the integrated circuit die; And A top printed circuit board disposed above the upper prepreg layer.

10. The laminated circuit board structure according to claim 1, the laminated circuit board structure further comprising: A plurality of pre-formed openings in the flexible non-conductive substrate, each pre-formed opening communicating with at least one of the conductive traces on the wiring surface of the flexible non-conductive substrate; A solder printing area formed in the pre-formed opening; And At least one surface mount component electrically connected to the solder printing area formed in the pre-formed opening.

11. The laminated circuit board structure according to claim 1, wherein the flexible non-conductive substrate is formed of polyimide.

12. The laminated circuit board structure according to claim 1, wherein the patch has an area of less than 1000 mm 2 .

13. A method for forming a patch of a laminated circuit board structure, the method comprising: Providing a non-conductive material layer having a conductive electroplating seed layer formed on its surface; Applying a photoresist layer above the surface of the conductive electroplating seed layer; Defining a wiring channel in the photoresist layer using a photolithography and etching process; Electroplating a first layer of conductive material in the wiring channel; Electroplating a second layer of conductive material above the first layer in the wiring channel; Adhering a non-conductive layer above the photoresist layer and the electroplated conductive material in the wiring channel; Removing the non-conductive material layer and the conductive electroplating seed layer; And Setting solder bumps on the second layer of conductive material.

14. The method according to claim 13, wherein the providing the non-conductive material layer having the conductive electroplating seed layer formed on its surface includes providing a polyester material layer having a conductive electroplating seed layer formed on its surface.

15. The method according to claim 13, wherein the electroplating the first layer includes electroplating a gold layer in the wiring channel.

16. The method according to claim 13, wherein the electroplating the second layer includes electroplating a nickel layer above the first layer in the wiring channel.

17. The method according to claim 13, wherein the adhering of the non-conductive layer above the photoresist layer and the electroplated layer of the conductive material in the wiring channel includes attaching a layer of one of polyester or polyimide above the photoresist layer and the electroplated conductive material in the wiring channel using a transfer adhesive.

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