Processing system, integrated circuit, device and method with queued serial peripheral interface

Abstract

Embodiments of the present disclosure relate to processing systems, integrated circuits, devices, and methods with queued serial peripheral interfaces. The embodiment processing system includes a queued SPI circuit, which includes a hardware SPI communication interface, an arbitrator, and a plurality of interface circuits. Each interface circuit includes a transmit FIFO memory, a receive FIFO memory, and an interface control circuit. The interface control circuit is configured to receive a first data packet and store it in the transmit FIFO memory. The interface control circuit sequentially reads the first data packet from the transmit FIFO memory, extracts at least one transmit data word, and provides the extracted word to the arbitrator. The interface control circuit receives the receive data word from the arbitrator, and stores the second data packet including the received receive data word in the receive FIFO memory. The interface control circuit sequentially reads the second data packet from the receive FIFO memory and transmits it to the digital processing circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Application No. 102020000006322, filed on March 25, 2020, which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to queued communication interfaces and associated methods, and in particular, to serial peripheral interfaces (SPIs) including multiple queues and associated methods. Background Art

[0004] Figure 1 A typical electronic system, such as that of a vehicle, is shown, comprising a plurality of processing systems 10, such as embedded systems or integrated circuits, for example field programmable gate arrays (FPGAs), digital signal processors (DSPs) or microcontrollers (eg, specific to the automotive market).

[0005] For example, in Figure 1 1 shows three processing systems 101, 102 and 103 connected by an appropriate communication system 20. For example, the communication system may include a vehicle control bus (such as a controller area network (CAN) bus) and possibly a multimedia bus (such as a media oriented system transport (MOST) bus) connected to the vehicle control bus via a gateway. Typically, the processing system 10 is located in different locations in the vehicle and may include, for example, an engine control unit (ECU), a transmission control unit (TCU), an anti-lock braking system (ABS), a body control module (BCM) and / or a navigation and / or multimedia audio system.

[0006] Future generations of processing systems, especially microcontrollers dedicated to automotive applications, will show a significant increase in complexity, mainly due to the increasing number of functionalities (such as new protocols, new functions, etc.) and stricter constraints on system operating conditions (such as lower power consumption, increased computing power and speed, etc.).

[0007] Figure 2 A block diagram of an exemplary digital processing system 10, such as a microcontroller, is shown that can be used as Figure 1 Any processing system 10.

[0008] In the example considered, the processing system 10 comprises at least one processing unit 102, such as a microprocessor, typically a central processing unit (CPU), programmed via software instructions. Typically, the software executed by the processing unit 102 is stored in a program memory 104, such as a non-volatile memory, such as a flash memory or an EEPROM. Typically, the memory 104 may be integrated with the processing unit 102 in a single integrated circuit, or the memory 104 may be in the form of a separate integrated circuit and connected to the processing unit 102, for example via traces of a printed circuit board. Thus, typically, the memory 104 contains firmware for the processing unit 102, wherein the term firmware includes software for a microprocessor and programming data for a programmable logic circuit such as an FPGA.

[0009] In the example considered, the processing unit 102 may have associated one or more (hardware) resources 106 selected from the following group:

[0010] one or more communication interfaces IF, for example, for exchanging data via the communication system 20, such as a universal asynchronous receiver / transmitter (UART), a serial peripheral interface bus (SPI), an inter-integrated circuit (I 2 C), Controller Area Network (CAN) bus and / or Ethernet interface and / or debug interface; and / or

[0011] - one or more analog-to-digital converters AD and / or digital-to-analog converters DA; and / or

[0012] - one or more dedicated digital components DC, such as hardware timers and / or counters, or cryptographic co-processors; and / or

[0013] - one or more analog components AC, such as comparators, sensors such as temperature sensors, etc.; and / or

[0014] - One or more mixed signal components MSC, such as PWM (Pulse Width Modulation) drivers.

[0015] Thus, different functionalities may be supported by the digital processing system 10. For example, the behavior of the processing unit 102 is determined by firmware stored in the memory 104, such as software instructions to be executed by the microprocessor 102 of the microcontroller 10. Thus, by installing different firmware, the same hardware (microcontroller) may be used for different applications.

[0016] Figure 3An example of communication between two processing systems 101 and 102 via a serial peripheral interface (SPI) is shown, i.e., the communication interface IF of the processing system 10 is a SPI communication circuit 30. For example, such an SPI communication interface is often used to connect the microcontroller 10 to peripheral electronic devices, such as those mounted on the same printed circuit board (PCB) or connected to the microcontroller 10 via a cable.

[0017] As is well known in the art, in SPI communication, one of the devices (e.g., device 101) is a master device, the other device (e.g., 102) is a slave device, and the communication between devices 101 and 102 is based on a bus 20 having four signals (e.g., these signals are applied to corresponding pads / pins of corresponding dies / integrated circuit packages and exchanged via corresponding conductors (such as wires or traces of a PCB)), in particular:

[0018] - a clock signal SCK provided by the master device 101;

[0019] A first data signal SOUT provided by the master device 101, usually referred to as “master output slave input”, indicating the data output of the master device 101 and the data input of the slave device 102;

[0020] - a second data signal SIN provided by the slave device 102, usually referred to as "master input slave output", indicating the data input of the master device 101 and the data output of the slave device 101;

[0021] - The peripheral chip select signal PCS provided by the master device 101, usually called "slave select".

[0022] Therefore, SPI is a full-duplex serial communication protocol.

[0023] For example, Figure 4Schematically illustrates possible SPI communication. At a given time t0, the slave selection signal PCS is de-asserted as invalid, and is set to a first logic level (e.g., high) indicating that the communication / slave device is disabled (idle state). At time t1, the master device 101 sets the signal PCS to a second logic level (e.g., low) indicating that the communication / slave device is enabled. Then, in the transmission phase device between time t2 and time t3, the master device 101 generates a given first number of pulses in the clock signal SCK, and for each clock pulse in the signal SCK, the signal SOUT is set to a high level or a low level, thereby sequentially transmitting a transmission data word consisting of a bit sequence. Therefore, the slave device 102 can, for example, sample the signal SOUT in response to the clock signal SCK. Optionally, the master device 101 can then wait for the slave device 12 to complete a given operation (such as, in response to the transmitted command). During the receiving phase between time t4 and time t5, the master device 101 can then generate a given second number of pulses in the clock signal SCK. In response to the clock pulse, the slave device 102 sets the logic level of the signal SIN to a high level or a low level, thereby sequentially transmitting the received data word consisting of the bit sequence to the master device 101. Therefore, the master device 101 can sample the signal SIN, for example, in response to the clock signal SCK. Once the transmission is completed, the master device 101 sets the signal PCS to a first logic level (e.g., high) indicating that the communication / slave device is disabled at time t6. Typically, since the communication is full-duplex, the master device and the slave device can also transmit data simultaneously.

[0024] Figure 5 It is shown that multiple slave devices 102, 103 and 104 can also be connected to the same master device 101, in particular the same communication interface 30, wherein each slave device 102, 103 and 104 includes terminals for exchanging signals SCK, SOUT and SIN with the master device 101, that is, the signals SCK, SOUT and SIN are shared, and each slave device 102, 103 and 104 can include a slave selection terminal PCS connected to a corresponding slave selection terminal of the master device 101, that is, the master device 101 generates multiple slave selection signals PCS1, PCS2, PCS3, and each slave device 102, 103 and 104 has a slave selection signal, that is, the slave selection signal PCS is a dedicated signal. Generally, the slave selection signals PCS1, PCS2, PCS3 can be generated directly by the interface circuit 30 and / or via software commands executed by the processing circuit 102, for example, by using a general purpose I / O pin (GPIO) of the processing system.

[0025] Although SPI communications are well known in the art, unfortunately, a large number of implementation variations have been used. For example, one or more of the following parameters may often vary between various slave devices:

[0026] - the number of bits transmitted from the master device 101 to the slave device 102, i.e. the length of the transmitted data word (which may also vary depending on the command transmitted to the slave device) and / or the number of bits received by the master device 101 from the slave device 102, i.e. the length of the received data word (which may also vary depending on the command sent to the slave device);

[0027] - The clock frequency or clock frequency range supported by the signal SCK;

[0028] - Clock polarity, i.e. the logic level of the clock signal SCK in the idle state; and

[0029] - Clock phase, that is, whether the slave device transmits data in response to the rising edge or the falling edge of the clock signal SCK.

[0030] Therefore, when multiple slave devices 102 , 103 , and 104 are connected to the master device 101 , each data transfer may require corresponding reconfiguration of the interface 30 of the master device 101 in order to correctly exchange data with the corresponding slave device 102 , 103 , or 104 .

[0031] Typically, the SPI communication interface 30 includes an interface 32 through which the processing circuit 102 can exchange data with the SPI interface 32. Such an interface 32 is often a register interface, wherein the interface 32 is associated with a given address in the memory range of the processing circuit 102.

[0032] In the past, a so-called queued serial peripheral interface (QSPI) has also been proposed, in which the interface 32 includes a data queue for transmitting data across the SPI bus 20. Typically, in this case, the interface 32 includes: a first (transmit, TX) memory 320, such as a first-in-first-out (FIFO) memory, in which the data to be transmitted is stored; and a second (receive, RX) memory 322, such as a FIFO memory, in which the received data is stored. Therefore, in this case, the processing circuit 102 can exchange data with the slave device via the interface 32 by configuring the SPI interface 30, (sequentially) storing data to the TX memory 320, and optionally (sequentially) reading received data from the RX memory 322.

[0033] Therefore, as Figure 6 As shown, the SPI interface 30 can be used to communicate with multiple slave devices 102 ... 106. Due to the possibly different characteristics and / or generation of the corresponding slave select signals, the individual communications must be managed by the master device 101. Therefore, from the perspective of the implementation of the SPI interface 30, the communication with multiple different slave devices 102 ... 106 can be quite complex.

[0034] Furthermore, the inventors have observed that it is generally preferred to manage the communication with a given slave device 102 ... 106 via a corresponding software module / task, such as tasks SWT1 ... SWT5 for communicating with the slave devices 102 ... 106. Generally, each task may refer to an activity of an operating system OS or an application APP, for example, executed by such an operating system OS.

[0035] However, when using a single SPI communication interface 30 , different software tasks executed by processing circuit 102 may have to exchange data with interface 32 , such as memories 320 and 322 .

[0036] The inventors have observed that this problem can be solved by providing multiple SPI interfaces within the processing system 10. However, this solution may not be feasible because each SPI interface requires four pins of the processing system 10.

[0037] Figure 7 A typical software architecture is shown in this regard. Typically, the software executed by the microprocessor 102 includes an operating system OS, which is configured to execute at least one application APP. Typically, the operating system OS includes a driver DRV, which allows the use of given hardware resources HW of the processing system 10, such as resources 106, such as the SPI communication interface 30. For example, the driver DRV can manage the communication with the SPI interface 30, for example, by providing given software functions to the operating system OS and / or (one or more) application APP, which allows the configuration of the SPI interface 30, the transmission of data and the reading of received data. These software commands can then be converted by the driver DRV into commands for accessing the interface 32 of the SPI communication interface, for example, in order to program the registers of the corresponding register interface 32.

[0038] The inventor has observed that such a hardware driver DRV of an operating system OS executed by the processing circuit 102 can therefore manage different virtual software interfaces for upper software layers (such as an operating system OS or an application APP), and then use a single hardware SPI interface IF to perform configuration and data exchange. However, this has several disadvantages. For example, on the one hand, this can involve security issues, because, for example, each software task SWT can access the registers of the SPI interface 30, so that data associated with another task SWT can be read. In addition, each software task SWT is able to exchange data with all slave devices, while in some cases, it is preferred that a given software task SWT can only exchange data with a given slave device. On the other hand, the driver DRV must be able to manage parallel write / read requests. For example, a parallel transmission request implies that a decision must be made: which task SWT can transmit the first data. However, when using, for example, a queued SPI 30, the interface 32 includes only a single transmission queue 320. Therefore, in order to also manage different communication priorities, the driver DRV will need to manage additional virtual queues. Therefore, all these software simulation interfaces will require additional processing power and memory space. Summary of the invention

[0039] In view of the above, an object of various embodiments of the present disclosure is to provide an improved solution for an SPI communication interface.

[0040] According to one or more embodiments, one or more of the above objects are achieved by means of a processing system comprising a queued serial peripheral device interface having the features specified in the following claims. Embodiments also relate to related integrated circuits, devices and methods.

[0041] The claims are an integral part of the technical teaching of the present disclosure provided herein.

[0042] As previously mentioned, various embodiments of the present disclosure relate to a processing system, such as a microcontroller, comprising a digital processing circuit and an SPI circuit, the digital processing circuit preferably being programmable according to firmware stored in a non-volatile memory. In various embodiments, the SPI circuit comprises a hardware SPI communication interface, an arbitrator, and a plurality of interface circuits.

[0043] In various embodiments, the hardware SPI communication interface includes: one or more shift registers configured to generate a first serial data signal according to a transmit data word and a receive data word by sampling a second serial data signal; and a control circuit configured to generate a clock signal for the one or more shift registers. In various embodiments, the arbiter is configured to provide the transmit data word to the hardware SPI communication interface and receive the receive data word from the hardware SPI communication interface.

[0044] In various embodiments, each interface circuit includes a transmit FIFO memory, a receive FIFO memory, and an interface control circuit. Specifically, the interface control circuit is configured to receive one or more first data packets from the digital processing circuit, and store the received one or more first data packets in the transmit FIFO memory. Next, the interface control circuit sequentially reads one or more first data packets from the transmit FIFO memory, extracts at least one transmit data word from the one or more first data packets, and provides the extracted at least one transmit data word to the arbitrator. Then, the interface control circuit receives the receive data word from the arbitrator, and stores one or more second data packets in the receive FIFO memory, and the one or more second data packets include the received receive data word. Finally, the interface control circuit sequentially reads one or more second data packets from the receive FIFO memory, and transmits the one or more second data packets to the digital processing circuit.

[0045] In various embodiments, the one or more first data packets include a command followed by at least one transfer data word, wherein the command includes a field for storing data indicating a data transfer count, the data transfer count identifying the number of transfer data words following the command. In this case, the interface control circuitry may be configured to extract the command from the one or more first data packets, determine the data transfer count, extract the number of transfer data words indicated by the data transfer count from the one or more first data packets, and provide the extracted transfer data words to the arbitrator.

[0046] For example, in various embodiments, the SPI circuit includes a set of global configuration registers for specifying a plurality of transmission attribute items, wherein each transmission attribute item includes a corresponding field for storing a data transfer count, and wherein the command includes a field indicating one of the transmission attribute items. In this case, each transmission attribute item may also include one or more fields for storing at least one of the following: data indicating the timing of a clock signal; data indicating an inactive state of the clock signal; data indicating whether one or more shift registers generate a first serial data signal and / or sample a second serial data signal in response to a rising edge or a falling edge of the clock signal; and data indicating the number of bits of a transmission data word to be transmitted via the first serial data signal.

[0047] In various embodiments, the command may also include other configuration data. For example, in various embodiments, the control circuit is configured to generate multiple slave select signals, and the command may include data indicating which slave select signal should be set during the transmission of the corresponding transmission data word. In various embodiments, the command may also include data indicating the priority of the corresponding extracted transmission data word provided to the arbitrator. In contrast, in other embodiments, each interface circuit includes a corresponding set of separate configuration registers, wherein each set of separate configuration registers includes one or more fields for storing data indicating the priority of the corresponding extracted transmission data word provided to the arbitrator.

[0048] Thus, in various embodiments, the SPI circuit may include a global configuration register for configuring the hardware SPI communication interface and / or the arbiter, and each interface circuit may include a corresponding set of individual configuration registers for configuring the corresponding interface circuit. In this case, a corresponding memory address range in the address range of the digital processing circuit may be associated with the set of global configuration registers and the set of individual configuration registers, and the processing system may be configured to restrict access to the memory address range for a given software task executed by the digital processing circuit.

[0049] For example, in various embodiments, the digital processing circuit is configured to execute (and therefore may also execute) a hypervisor that provides multiple execution environments, each of which is configured to execute a respective operating system. Thus, in this case, the hypervisor may be configured to restrict access to the memory address range of the execution environment.

[0050] In various embodiments, the SPI circuit can also exchange data with the digital processing unit via a DMA request. For example, in various embodiments, the processing system includes: a memory connected to the digital processing circuit; and a DMA controller configured to read data from the memory according to a data read request received via a first DMA channel, and store the data to the memory according to a data write request received via a second DMA channel. In this case, the SPI circuit may include a DMA interface configured to communicate with the DMA controller, and the interface control circuit of at least one interface circuit may be configured to receive one or more first data packets by sending a data read request to the DMA controller via the DMA interface, and to transmit one or more second data packets by sending a data write request to the DMA controller via the DMA interface.

[0051] Specifically, in various embodiments, at least one interface circuit includes a corresponding set of separate configuration registers for configuring a first threshold of free entries in a transmit FIFO memory and a second threshold of fill entries in a receive FIFO memory. In this case, the interface control circuit of at least one interface circuit can be configured to determine whether the number of free entries in the transmit FIFO memory exceeds the first threshold, and when the number of free entries in the transmit FIFO memory exceeds the first threshold, send a data read request to the DMA controller via the DMA interface. Similarly, the interface control circuit of at least one interface circuit can be configured to determine whether the number of fill entries in the receive FIFO memory exceeds the second threshold, and when the number of fill entries in the receive FIFO memory exceeds the second threshold, send a data write request to the DMA controller via the DMA interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting examples only, in which:

[0053] Figure 1 An example of an electronic system including multiple processing systems is shown;

[0054] Figure 2 An example of a processing system such as a microcontroller is shown;

[0055] Figure 3 An example of SPI communication between a master device and a slave device is shown;

[0056] Figure 4 shows an example of data exchanged via SPI communications;

[0057] Figure 5 An example of SPI communication between a master device and multiple slave devices is shown;

[0058] Figure 6 An example of multiple software tasks is shown that use the same SPI communication interface to communicate with multiple slave devices;

[0059] Figure 7 An example of software layers of software executed by a processing system is shown;

[0060] Figure 8 An embodiment of an SPI communication interface according to the present disclosure is shown;

[0061] Fig. 9 A first embodiment of a software layer of software executed by a processing system is shown;

[0062] Fig.10A second embodiment of a software layer of software executed by a processing system is shown;

[0063] Fig.11 An embodiment of a processing system according to the present disclosure is shown;

[0064] Fig.12 A third embodiment of a software layer of software executed by a processing system is shown;

[0065] Fig.13 Another embodiment of a processing system according to the present disclosure is shown;

[0066] Figures 14 to 18 , Figures 20 to 37 and Fig.39 Various configuration registers of an embodiment of an SPI communication interface are shown;

[0067] Fig.19 An embodiment of the configuration of the properties of SPI communication is shown;

[0068] Fig.38 , Fig.40 and Fig.41 An embodiment of data packets provided to and received from a SPI communication interface is shown; and

[0069] Fig.42 An embodiment of the operation of the control circuit of the SPI communication interface is shown. DETAILED DESCRIPTION

[0070] In the following description, many specific details are given to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or more of the specific details or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0071] Throughout the specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0072] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0073] In the following Figures 8 to 42 In, reference has been made Figure 1 and Figure 7The described parts, elements or components are indicated by the same reference numerals used previously in these figures; in order to avoid burdening this detailed description, the description of these aforementioned elements will not be repeated below.

[0074] As mentioned above, various embodiments of the present disclosure relate to the SPI communication interface. Specifically, in various embodiments, the SPI communication interface provides multiple interfaces to the processing circuit 102, thereby allowing each software task SWT that needs to use the SPI interface to use a corresponding interface of the SPI communication interface.

[0075] Figure 8 1 shows a first embodiment of a SPI interface circuit 30a according to the present disclosure. Specifically, in the embodiment considered, the SPI interface 30a comprises a given number (n+1) (eg, n=7) of interfaces 320 . . . 32 n , wherein each interface 32 comprises: a corresponding transmission queue 3200 . . . 320 n , used to store the corresponding transmission data packets TX0...TX n , such as corresponding FIFO memories; and corresponding receive queues 3220 . . . 322 n , used to store received data packets RX0...RX n , such as a corresponding FIFO memory.

[0076] In the embodiment considered, the transmit queues 3200 . . . 320 n and receive queue 3220…322 n 34, which is configured to determine which transmission data should be provided to the hardware SPI communication interface 36. For example, in various embodiments, the hardware SPI communication interface 36 includes at least one register 360 for storing data to be transmitted via the signal SOUT and data received via the signal SIN. For example, the at least one register 360 may include one or more shift registers. Specifically, in the embodiment considered, a single shift register 360 is used, wherein the serial input of the shift register 360 is connected to the signal SIN, and the serial output of the shift register 360 is connected to the signal SOUT. Preferably, the parallel interface of the (one or more) shift registers 360 is used to exchange data between the (one or more) registers 360 and the queues 320 and 322 (via the arbitrator 34).

[0077] In the embodiment considered, the hardware SPI communication interface 36 further comprises a control circuit 362 configured to generate a (serial) clock signal SCK and a given number (m+1) (e.g. m=12) of slave selection signals PCS0 . . . PCS m, the following also uses the data vector PCS[m:0] (eg PCS[11:0]) to identify the slave selection signals PCS0…PCS m .

[0078] Thus, in the embodiment under consideration, the arbitrator 34 may determine the interfaces 320 . . . 32 n Which interface is selectively connected to the hardware SPI communication interface 36. For example, the first data packet TX 0,1 Provided to the queue 3200. In various embodiments, the data packets exchanged via the various signals TX and RX have a given first number of bits, such as 8, 16, 32 or 64 bits, and the register 360 has a given second number of bits, such as 8, 16, 32 or 64 bits. Preferably, the first number and the second number correspond, the second number is a multiple of the first number, or the first number is a multiple of the second number.

[0079] In various embodiments, the arbiter 34 is configured to determine a transfer request for this purpose. For example, the arbiter 34 may automatically determine a transfer request by monitoring a fill status of a transfer queue, such as an empty signal indicating whether the FIFO memory is empty or includes at least one element. Additionally or alternatively, the circuit requesting the transfer may set a corresponding transfer request signal, such as a hardware or software transfer request trigger signal.

[0080] Therefore, in response to the transmit request, the arbiter 34 connects the queue to the register 360, thereby transmitting the first data packet TX 0,1 stored in register 360. Typically, only a portion or a plurality of data packets may be read from queue 3200 in order to fill register 360. However, as previously described, preferably register 360 has a size for each data packet stored to queue 320 / 322 that preferably corresponds to the word length of processing circuit 102.

[0081] Therefore, once the data has been stored in the register 360, the control circuit 362 may generate the clock signal SCK and set at least one slave selection signal PCS[m:0], preferably via a parallel write access to the register 360. To this end, as will be described in more detail below, the control circuit 362 may have the following items associated:

[0082] - a set of global configuration registers common to all interfaces 320 ... 32n; and / or

[0083] - A separate set of configuration registers for each interface 320...32n.

[0084] For example, individual registers of a given interface 320 . . . 32n may include data identifying requested attributes of the clock signal SCK, the slave select signal PCS[m:0] to be set, and / or the number of bits to be transferred.

[0085] Thus, in response to this configuration, the control circuit 362 may generate a given first number of clock pulses for sequentially transmitting the bit levels of data stored via the signal SOUT to the register 360. If requested, the control circuit 362 may then generate a given second number of clock pulses to sample the bit levels of the signal SIN and sequentially store the received bits to the register(s) 360.

[0086] For example, assuming that the SPI transmission using a given slave device is based on a request including 16 bits, which are used to request data having 16 bits, the interface 30a can be configured to transmit a data word having 16 bits. Next, the first transmission data packet can include the request, and the second transmission data packet can include default data, such as a bit sequence with all bits set to "1" or "0". Therefore, in response to the transmission of two transmission data packets, the SPI interface 36 will provide a first reception data packet including default data (such as a bit sequence set to "1" or "0") and a second reception data packet including data determined according to the transmitted request.

[0087] Once the received data is stored in the register (s) 360, the arbiter 34 can store the data in the receive queue 3220. Specifically, since SPI communication is based on master-slave communication, data is only received by the interface 36 in response to a previous request, which can also be implied by setting the slave select signal. Therefore, the received data is uniquely linked to a given transfer request executed by a given interface 32.

[0088] in this regard, Fig. 9 An embodiment of a modified software architecture is shown. Specifically, also in this case, the software executed by the microprocessor 102 includes an operating system OS configured to execute at least one application APP. Also in this case, the operating system OS may include a driver DRV that allows the use of a given hardware resource 106 of the processing system 10, such as a resource 106, including the SPI communication interface 30a, such as one or more drivers DRV for one or more resources 106. x .

[0089] However, in this case, the driver DRV may include a plurality of drivers DRV0 . . . DRV n , where each driver DRV0…DRV nconfigured to manage the communication with the corresponding interfaces 320 . . . 320 , for example by providing a given software functionality to the operating system OS and / or the application(s) APP, which allows the configuration of the SPI interface 30 . n These software commands can then be converted by the corresponding driver DRV into access to the corresponding interface 320…32 n Thus, in the embodiment considered, each driver DRV0 ... DRV n Only compatible with corresponding interfaces 320…32 n communication.

[0090] Therefore, various software tasks, such as application APP0...APP n , you can use the corresponding dedicated drivers DRV0...DRV n .

[0091] Fig.10 A second embodiment of a modified software architecture is shown. Specifically, in this case, the software executed by the microprocessor 102 comprises a hypervisor HYP, such as a hypervisor operating system.

[0092] Such a hypervisor HYP can provide multiple execution environments, such as an execution environment EEH and one or more execution environments EEa, EEb, etc. Specifically, each execution environment allows the execution of a corresponding operating system. For example, the execution environments EEH, EEa, and EEb can execute operating systems OSH, OSa, and OSb, respectively. For example, the execution environment EEH can be used to execute a host operating system, which is used to manage the operation of the hypervisor HYP. Conversely, the execution environments EEa and EEb can be used to execute corresponding guest operating systems OSa and OSb. Therefore, each operating system EEH, EEa, and EEb may also include corresponding driver layers DRVH, DRVa, and DRVb. Similarly, the hypervisor HYP may also include a driver layer HYP_DRV.

[0093] Thus, in various embodiments, the hypervisor HYP may be configured, for example via the host environment EEH, to connect the interfaces 320 . . . 32 n A given subset of is assigned to each execution environment EEH, EEa and EEb. For example, by using interfaces 320 . . . 324 addressable by processing unit 102 n , a hardware memory protection unit of the processing system 10, or a software memory protection unit implemented, for example, within the hypervisor HYP, may be used to ensure that each execution environment can only access interfaces 320 . . . 32 enabled for a given execution environment. nThus, in this way, a given software task, such as an application, can use only the interfaces 320 . . . 32 assigned to the corresponding execution environment. n .

[0094] Furthermore, in various embodiments, the hypervisor HYP may also configure the interfaces 320 . . . 324 , for example via the host environment EEH. n part, so that for example for each interface 320 . . . 32 n Indicates which slave select signal PCS can be set, thereby specifying which slave device a given execution environment can communicate with.

[0095] In this regard, Fig.11 A possible embodiment of a processing system 10a is shown, in particular the data flow between a processing circuit 102, such as a microprocessor, and an interface 30a. Without loss of generality, only two interfaces 320 and 321 are shown.

[0096] In particular, in the embodiment under consideration, the processing circuit 102 may communicate with the memory 104 , such as a RAM, in any suitable manner, for example by using address signals ADR and data signals DAT transmitted via the bus system 112 .

[0097] In the embodiment under consideration, the memory 104 may comprise a respective memory area, for example B0 and B1, for each interface 32. Furthermore, each memory area comprises a respective transfer sub-area / buffer B0 for storing data to be transferred. TX and a receiving sub-area / buffer B for storing received data RX , for example B0 TX / B1 TX and B0 RX / B1 RX Therefore, the processing circuit 102 (or another resource 106 of the processing system 10) may store the data to be transmitted to the transmission sub-region B. TX A transmission sub-area (for example, B0 TX ) data, and can receive data from the corresponding sub-area B RX (For example, B0 RX ) to read the received data.

[0098] In the embodiment under consideration, the memory 104 is also connected to the interface 30a, in particular the transmit and receive queues, via suitable communication channels. Specifically, in various embodiments, each transmit memory sub-area (e.g. B0 TX and B1 TX) are connected to corresponding transmit queues (e.g., 3200 and 3201) via corresponding direct memory access (DMA) channels (e.g., CH01 and CH11), and each receive memory sub-area (e.g., B0 RX and B1 RX ) are connected to corresponding receive queues (eg, 3220 and 3221) via corresponding DMA channels (eg, CH02 and CH12). Therefore, in various embodiments, data exchange between the memory 104 and the interface 30a is based on separate DMA channels.

[0099] like Fig.11 As shown, in various embodiments, the processing circuit 102 may also communicate with one or more configuration registers REGG, REG0, and REG1 of the interface 30a. For example, the communication with these registers may be performed via the above-mentioned bus 112, for example, by using the address signal ADR and the data signal DAT. For example, in various embodiments, a given address range may be associated with the memory 104 (particularly the memory sub-area B). TX and B RX ) and the registers of interface 30a. Specifically, in the embodiment considered, the address range associated with the registers includes:

[0100] a first address range associated with a plurality of registers REGG for global / common configuration and / or status data of the exchange interface 30a; and

[0101] -For interfaces 320…32 n For each interface in, a corresponding address range is associated with a plurality of corresponding registers (eg, REG0 and REG1) for exchanging configuration and / or status data with the corresponding interface (eg, 320 and 321).

[0102] Therefore, the memory controller of the processing circuit 102 (such as for generating the address signal ADR and the data signal DAT) or the hypervisor HYP and / or the operating system OS executed by the processing circuit 102 may limit the access to the interfaces 320 . . . 32 n Access to memory sub-area B is restricted by TX and B RX , global register REGG and individual registers (REG0 and REG1) associated with the address or address range.

[0103] For example, Fig.12An embodiment of the organization of the address ranges is shown. In particular, in the embodiment considered, the processing circuit 102 again uses the address signal ADR and the data signal DAT to access the global register REGG and the individual registers, such as the eight registers REG0 ... REG7 in the example considered. For example, in the embodiment considered, the following addresses are used: 0x0000 ... 0x00FF for register REGG, 0x0100 ... 0x01FF for register REG0, 0x0200 ... 0x02FF for register REG1, 0x0300 ... 0x03FF for register REG2, etc. Typically, fixed offsets may also be added to these addresses.

[0104] Thus, by restricting the memory accesses of each execution environment to a given address range, each global register REGG and individual registers can be assigned to a given driver, e.g. the aforementioned drivers HYP_DRV, DRVH, DRVa and DRVb, such as:

[0105] - the hypervisor HYP has (privileged) access rights and can access the address range associated with the global register REGG (e.g. 0x0000 ... 0x00FF) and optionally also the address range associated with the individual registers (e.g. 0x0100 ... 0x08FF);

[0106] - Each execution environment or even each software task executed by an execution environment may not be able to access the address range associated with the global register REGG (e.g. 0x0000…0x00FF), but may only have access to a subset of the address range associated with the corresponding subset of individual registers (e.g. 0x0100…0x01FF and 0x0300…0x3FF), while being prohibited from accessing the address ranges of other interfaces 32.

[0107] As mentioned previously, access control can be enhanced by hardware or software memory protection, which can be configured via:

[0108] a) A hypervisor, optionally via a host environment for configuring the hypervisor so as to restrict access to a given interface 321 . . . 32 of the execution environments EEH, EEa, EEb n access, and / or

[0109] b) an operating system OSH, OSa, OSb executed by a given execution environment EEH, EEa, EEb, thereby restricting a given interface 321 ... 322 to the software tasks executed by the respective operating system OSH, OSa, OSb n of visits.

[0110] As previously described (see, for example, Figure 8 ), multiple interfaces 321…32 n The same hardware SPI communication interface 36 may be used by exchanging data with the hardware SPI communication interface 36 via the arbiter / scheduler 34 .

[0111] As mentioned above, preferably, arbitration is performed based on priority. In various embodiments, the priority can be specified, for example, in at least one of the following ways:

[0112] - by storing the first priority data in the global register REGG, thereby providing for each interface 321 . . . 32 via the hypervisor HYP, for example n Specify priorities;

[0113] - by storing the second priority data in separate registers REG1 ... REG7, where for each interface 321 ... 32 n Specifying a priority; for example, a driver executed via a given operating system; and

[0114] - by storing the third priority data together with the corresponding data to be transmitted in the transmission buffer B TX In which, for example via a driver executed by a given operating system, a priority is assigned to each data packet or sequence of data packets to be transmitted.

[0115] Therefore, in various embodiments, in a conventional software environment with a single operating system ( Fig. 9 ) and virtual / hypervisor environments ( Fig.10 ) In both, the proposed SPI interface circuit 32a can be used by independent software tasks. In various embodiments, the separate interfaces 321 ... 32 can be controlled for each execution environment and / or each software task. n Furthermore, priority processing may be performed directly on the hardware layer 34, for example, based on data identifying an execution environment, a software task (eg, linking to a given slave device), or even a single transfer requesting a data transfer.

[0116] In various embodiments, with a given interface 321 . . . 32 n The associated registers and the global register REGG are grouped in a continuous address range, which simplifies the implementation of memory accesses to these corresponding registers.

[0117] In the following, a possible detailed implementation of the SPI communication interface circuit 32a is now described. Such a circuit 32a may have one or more of the following features:

[0118] - Interface 32a can be configured as a master device or a slave device;

[0119] - Support up to a given number of transport groups / interfaces 32, such as eight interfaces 320 ... 327, where each transport group / interface 32 may support one or more of the following:

[0120] - Buffering operation with a given number of entries in the TX and RX FIFOs 320 and 322;

[0121] - DMA interface to TX and RX queues 320 and 322;

[0122] - the transfer may be initiated via software control and / or based on at least one (programmable) hardware trigger generated by another hardware resource of the processing system (e.g. a pin / pad or resource 106);

[0123] - may provide the status of the received data, which may include one or more of the following: parity error, CRC error, end-of-queue status, chip select signal used, timestamp;

[0124] - can support burst mode, where a transmission frame includes multiple data packets to be transmitted;

[0125] - Priority-based arbitration between transmission groups for determining the next frame to be transmitted;

[0126] -Programmable global and / or individual SPI transfer properties such as:

[0127] -Programmable clock polarity and phase;

[0128] - programmable delays, for example the delay between the signal PCS and the clock signal SCK (the delay between the instants t1 and t2 and / or between t5 and t6), and / or the delay between data packets within a frame;

[0129] - A programmable size of data packets of frames to be transmitted / received, such as between 4 and 32 bits.

[0130] Fig.13 An embodiment of an SPI communication interface 30a is shown, which again comprises a given number of interfaces 320 . . . 32 n , and an arbiter 34 and a hardware SPI transmitter / receiver circuit 36, wherein each interface 320 . . . 32 n It includes a transmit queue 320 and a receive queue 322 .

[0131] As previously mentioned, the SPI interface circuit 32a is connected to the processing circuit 102 via an appropriate communication interface. For example, in the embodiment considered, the SPI interface circuit 32a includes:

[0132] a DMA interface 300 configured to manage a plurality of DMA channels DMA_Tx and DMA_Rx, wherein each transmit queue 320 and receive queue 322 may have an associated respective DMA channel; and

[0133] A bus slave interface 302 configured to connect the SPI interface 30 a to the bus system 112 of the processing system 10 , for example for connection to the processing system 102 .

[0134] For example, in various embodiments, the bus slave interface 302 and the DMA interface 300 follow the Advanced Microcontroller Bus Architecture (AMBA), where the DMA interface 300 is connected to the AMBA or AMBA high-performance bus (AHB) 112 via the DMA controller 108, and the bus slave interface 302 is an advanced peripheral bus (APB) slave device connected to the APB bus, which in turn is connected to the AMBA or AHB bus via the bridge circuit 110. In this case, the processing circuit 102 is connected to the AMBA or AHB bus 140. Similarly, one or more memories 104 can be connected to the bus 112 via one or more memory controllers 104a. For example, the memory can be a non-volatile program memory of the processing circuit 102 or a volatile memory 104b, such as a random access memory (RAM).

[0135] In the embodiment considered, each interface 320 . . . 32 n Including corresponding transmission queues 3200...320 n and the corresponding receiving queues 3220…322 n In various embodiments, each interface 320 . . . 32 n Also includes corresponding interface control circuits 3240 . . . 324 n , which is configured to manage data exchanges with the arbiter 34. Specifically, as will be described in more detail below, each control circuit 324 is configured to read the contents of the corresponding transmission queue 320 and extract the command CMD and the corresponding data DATA to be transmitted, that is, (such as, via the DMA controller 108 and the DMA interface 300) the processing circuit 102 (or any other circuit requesting the transmission of data) provides one or more data packets to the corresponding interface 32, which are stored in the corresponding transmission queue 320, wherein the one or more data packets include the command CMD and the corresponding data DATA. Therefore, the control circuit 324 can be configured to extract the command and data and provide this information to the arbiter 34. For example, this Fig.13 Schematically shown in FIG. 3 , wherein interfaces 320 . . . 32 n The command signals CMD0...CMD n and data signals DATA0…DATA n34. Conversely, the arbiter 34 supplies the selected command CMD and the data DATA to the hardware SPI interface 36. The hardware SPI interface thus transmits the data DATA according to the command CMD and optionally receives corresponding data RXDATA, which are forwarded to the arbiter 34. In the embodiment considered, the arbiter 34 thus supplies the received data RXDATA to the interface 320 ... 32 n .

[0136] In various embodiments, the hardware SPI interface 36 may be connected to pins / pads of the processing system 10 via routing circuitry 114 , such as a configurable crossbar switch.

[0137] In various embodiments, each interface 320 . . . 32 n It may also include a trigger management circuit 3260 ... 326 n , which is configured as follows:

[0138] - receiving a trigger signal TIN from another circuit of the processing system 10 and signaling a transfer request to the arbitrator; and / or

[0139] - In response to the completion of transmission / reception, a trigger signal TOUT is generated.

[0140] In various embodiments, each interface 320 . . . 32 n A timestamp management circuit 3280 . . . 328 may also be included n Specifically, the timestamp management circuit 328 may be configured to store the timestamp signal TIME in response to the start of a transmission (as signaled by the trigger management circuit 326 or preferably the actual start of a transmission as signaled by the arbiter 34) or the end of data reception (as signaled by the arbiter 34).

[0141] Typically, the above operation applies when the circuit 32a is configured as a master device. However, in various embodiments, the circuit 32a may also be configured as a slave device. Therefore, in this case, the hardware SPI interface 36 may generate an enable signal EN, which indicates that data RXDATA has been received and that the data should be stored in a predetermined queue, such as queue 3200. For example, when operated in slave mode, the hardware SPI communication circuit 36 ​​may monitor the slave select signal PCS[0] and the signal SCK, and when enabled via the slave select signal PCS[0], the SPI communication circuit 36 ​​may store the logic level of the signal SIN in response to the clock signal SCK.

[0142] Thus, in the embodiment considered, the circuit 30a provides a plurality of queue interfaces 320 . . . 321 for buffering SPI sequences. n. Each queue represents a transmission group and implements data transmission and reception between the FIFO and an external device. As will be described in more detail below, the TX FIFO 320 can be configured to store SPI commands and data to be transmitted, while the RX FIFO 322 buffers incoming serial data. In various embodiments, the number of entries of the queue and / or the number of bits per entry can be configurable.

[0143] In various embodiments, longer SPI sequences may also be stored in a memory external to the SPI interface circuit 30a, such as the memory 104b. In this case, data transfer between the memory and the SPI interface circuit 30a may be automatically accomplished by the DMA controller 108 and / or software instructions executed by the processing circuit 102.

[0144] Specifically, in various embodiments, the SPI interface 30a supports master mode and slave mode. In master mode, the interface 32a starts and controls serial communication. In this mode, the clock signal SCK and the slave selection signal PCS[m:0] are configured to be output by the interface 30a, and are configured to be generated by the interface 30a. In the SPI master mode, each SPI frame to be transmitted may include a command CMD associated with the corresponding data DATA, which allows a given transmission attribute to be specified frame by frame. On the contrary, the data DATA of the frame is loaded from the transmission FIFO 320 into the transmission shift register 360 and is shifted out on the serial output pin SOUT. At the same time, the serial data input on the serial input pin SIN is shifted in the receiving shift register 360 (it may also correspond to the transmission shift register) and is stored in the receiving FIFO 322 as a data entry.

[0145] In contrast, in various embodiments, the slave mode can allow the SPI interface 30a to communicate with the SPI bus master. In this mode, the SPI interface 30a responds to externally controlled serial transmissions. The SCK signal and a given slave select signal (e.g., PCS[0]) are configured as inputs and driven by the SPI bus master. In this case, certain transmission properties (such as clock polarity, clock phase, and frame size) can also be programmable.

[0146] Thus, in various embodiments, when operating as a master device, transmit FIFO 320 is configured to receive a frame including:

[0147] - a first entry comprising a command CMD; and

[0148] - One or more entries containing the data to be transferred.

[0149] In various embodiments, in both the master mode and the slave mode, the receive FIFO 322 is configured to receive a frame including one or more entries including received data. As will be described in more detail below, each frame or each received data packet may also optionally include a last entry including a status RxSTATUS indicating the status of the received data.

[0150] As described above, in various embodiments, the SPI interface 30a may include a set of global registers REGG and a set of individual registers REG0 ... REGn to control the operation of the SPI interface 30a (particularly the arbiter 34 and the hardware SPI communication interface). Preferably, these registers are accessible from the interface 302 via the bus (e.g., via corresponding addresses).

[0151] For example, in various embodiments, the global register REGG may include one or more of the following registers:

[0152] -MCR: module configuration register;

[0153] -HW_CONFIG_STATUS: Hardware configuration status register;

[0154] -GLOBAL_STATUS: global status register;

[0155] -GLOBAL_IRQ_CTRL: global interrupt control register;

[0156] -GLOBAL_IRQ_STATUS: global interrupt status register;

[0157] -TAC[k:0]: a set of transfer attribute control registers, where one or more registers TAC (such as two registers TAC_L and TAC_H) are associated with each interface 320...32 n associated with; and

[0158] -MONITOR_SLAVE_SELECT: Monitor slave select register.

[0159] Instead, each interface 320...32 n There may be associated individual registers REG0...REGn, which may include queue control, status and (optionally) interrupt registers. For example, the queue control, status and interrupt registers may include one or more of the following registers:

[0160] -Q_SETUP: Queue setup register;

[0161] -Q_HW_CFG: Queue hardware configuration register;

[0162] -Q_STATUS: Queue status register;

[0163] -Q_CTRL: queue control register;

[0164] -Q_IRQ_CTRL: Queue interrupt control register; and

[0165] -Q_IRQ_STATUS: Queue interrupt status register;

[0166] In various embodiments, each interface 320 . . . 32 n It may also have associated other optional individual registers REG0...REG n , such as one or more of the following registers:

[0167] - Queue FIFO push / pop registers;

[0168] -queue debug registers; and

[0169] - Queue CRC register.

[0170] For example, in various embodiments, the queue FIFO push register Q_TxFIFO_PUSH and the queue FIFO pop register Q_RxFIFO_POP may be used to temporarily store data to be stored in the transmit FIFO 320 (received via the interface 300) and data to be read from the receive FIFO memory 322 (to be transmitted via the interface 300). For debugging purposes, access to these registers may therefore be useful.

[0171] Typically, these registers may also be used to transmit data packets directly to a given interface 32 (e.g., by storing data in register Q_TxFIFO_PUSH and then writing the data to the corresponding transmit FIFO 320), and to read data packets from a given interface 32 (e.g., by reading data from register Q_RxFIFO_POP and then refilling the register by reading a new data packet from receive FIFO 322). Thus, in various embodiments, data exchange (of data frames to be transmitted or received) between processing circuit 102 and interface 30a may be accomplished directly via registers Q_TxFIFO_PUSH and Q_RxFIFO_POP of a given queue, or indirectly via the corresponding buffer B TX and B RX And it is done using DMA transfer.

[0172] Instead, the queue debug registers may include one or more of the following registers:

[0173] -Q_TxFIFO_PTR: Queue transmit FIFO pointer register;

[0174] -Q_RxFIFO_PTR: Queue receive pointer register.

[0175] Additionally or alternatively, full debugging of FIFO memories 320 and 322 is also possible, which may include read and / or write access to each entry of FIFO memories 320 and / or 322. For example, in various embodiments, the queue debug registers may also include the following registers:

[0176] -Q_DEBUG_PTR: Queue debug pointer register;

[0177] - Q_DEBUG_TxFIFO_DATA: queue debug data for transmit registers (selected via signal pointer Q_DEBUG_PTR); and

[0178] - Q_DEBUG_RxFIFO_DATA: Queue debug data for receive registers (selected via signal pointer Q_DEBUG_PTR).

[0179] In various embodiments, the queue debug registers may also include a queue command register Q_DEBUG_TxFIFO_CMD indicating a last or ongoing command CMD.

[0180] As previously mentioned, in various embodiments, the hardware SPI interface may also be configured to selectively perform error verification operations, such as parity or CRC verification of received data. In this case, the queue CRC registers may include one or more of the following registers:

[0181] -Q_CRC_CFG: Queue CRC configuration register;

[0182] -Q_CRC_INIT: Queue CRC initialization register;

[0183] - Q_CRC_POLY: Queue CRC polynomial register;

[0184] - Q_CRC_TX: Queue CRC transmit register; and

[0185] - Q_CRC_RX: Queue CRC receive register.

[0186] The possible implementation of the above-mentioned registers will be described below. In general, this description is only for the purpose of illustration, so as to show how the configuration of a given function of the SPI interface 30a can be implemented. However, one or more configuration registers or their fields may be purely optional (because the corresponding configuration may also be fixed at the hardware level), the configuration may also be implemented with other registers, or the fields of these registers may be organized in different ways. Similarly, which entries are readable and / or writable (indicated horizontally with "R" and "W"), and the possible reset values ​​of the corresponding bits indicated with "Reset" will be shown by way of example.

[0187] For example, Fig.14 An embodiment of a module configuration register MCR is shown. In the embodiment considered, the register MCR comprises the following fields (processed accordingly by the interface 30a):

[0188] -MSTR: allows selection of whether the SPI interface 30a operates in master or slave mode;

[0189] -CONT_SCKE: allows to select whether the clock signal SCK is discontinuous (i.e. generated only during frame transmission) or continuous;

[0190] - PCS_DEFAULT_LEVEL: allows selection of the inactive level of each slave select signal, e.g. PCS[x] inactive level is 0 or 1;

[0191] -SAFE_SPI_MODE: allows to select whether to enable SafeSPI mode;

[0192] -SAMPLE_POINT: allows to specify when the SPI master samples the signal SIN and generates the signal SOUT;

[0193] -MTFE: allows to specify whether to enable or disable modified timing format;

[0194] -DEBUG_FREEZE: allows to specify whether to stop the transmission / reception operation of the SPI interface 30a in response to a debug request;

[0195] -LOOPBACK_EN: allows enabling or disabling the internal loopback, where the signal SIN is selectively (internally) connected to the signal SOUT;

[0196] -CRC_ERR_STOP: allows to specify whether to interrupt data transmission when a CRC error occurs;

[0197] -PAR_ERR_STOP: allows to specify whether to interrupt data transmission when a parity error occurs;

[0198] -MODULE_EN: allows enabling or disabling the SPI interface 30a.

[0199] As previously mentioned, the field SAMPLE_POINT allows the transmission format of the signals SIN and SOUT to be specified. For example, in various embodiments (described below), the transmission format of the signals SIN and SOUT may be specified via a transmission format for each interface 300 . . . 30 n The corresponding fields CPOL and CPHA of the SAMPLE_POINT register may specify the clock polarity and phase, for example via corresponding flags in register TAC_H (described in more detail below). In this case, the field SAMPLE_POINT may only specify the properties of the signals SIN and SOUT. For example, when for a given 300 ... 30 n , when the flag CPHA is set to low, the hardware SPI interface 36 can sample the signal SIN and drive the signal SOUT according to the following bit values ​​of the field SAMPLE_POINT:

[0200] -00: sample SIN on even SCK edges and drive SOUT on odd SCK edges; and

[0201] -01: ​​SIN is sampled one system clock before the even SCK edge, and SOUT is driven one system clock after the odd SCK edge.

[0202] On the contrary, when for a given 300…30 n When the flag CPHA is set high, the hardware SPI interface 36 can sample the signal SIN and drive the signal SOUT according to the following bit values ​​of the field SAMPLE_POINT:

[0203] -00: sample SIN on odd SCK edges and drive SOUT on even SCK edges;

[0204] -01: ​​SIN is sampled one system clock before the odd SCK edge, and SOUT is driven one system clock after the even SCK edge.

[0205] Fig.15 An embodiment of a hardware configuration status register HW_CONFIG_STATUS is shown. In the embodiment considered, the register HW_CONFIG_STATUS comprises the following (read-only) fields (generated accordingly by the interface 30a):

[0206] -NUM_TAC: Provides the number of transfer attribute control (TAC) registers fixed during design;

[0207] -NUM_QUEUES: Provides interfaces 320…32 fixed at design time n The number of.

[0208] Fig.16 An embodiment of a global status register GLOBAL_STATUS is shown. In the embodiment considered, the register GLOBAL_STATUS comprises the following (read-only) fields (which are generated accordingly by the interface 30a):

[0209] -QUEUE_NUM: 320…32 for each interface n Specifies whether to report the status (1) or not report the status (0);

[0210] -SPIQ_STATUS: Provides status messages such as:

[0211] -IDLE(000): All queues are in idle state.

[0212] -RUNNING(001): SPI transmission is in progress

[0213] -WAIT_TRIGGER(010): No SPI transfer in progress, all enabled queues are waiting for trigger

[0214] -SUSPENDED(011): All queues are in suspended state;

[0215] -ERROR (111): At least one queue is reporting an error status (such as UNDERFLOW, STALLED, FIFO underrun, FIFO overflow, parity error, CRC error, trigger overflow error).

[0216] Fig.17 An embodiment of a global interrupt control register GLOBAL_IRQ_CTRL is shown. In the embodiment considered, the register GLOBAL_IRQ_CTRL comprises the following fields (which are processed accordingly by the interface 30a):

[0217] -ERR_IRQ_EN: allow 320…32 for each individual interface n Enable or disable error interrupts;

[0218] -STATUS_IRQ_EN: allow 320…32 for each individual interface n Enable or disable status interrupts.

[0219] Fig.18 An embodiment of a global interrupt status register GLOBAL_IRQ_STATUS is shown. In the embodiment considered, the register GLOBAL_IRQ_STATUS comprises the following (read-only) fields (which are generated accordingly by the interface 30a):

[0220] -ERR_IRQ_STATUS: 320…32 for each individual interface n Provides error interrupt value;

[0221] -STATUS_IRQ: 320…32 for each individual interface n Provides a status interrupt value.

[0222] As mentioned above, in various embodiments, the configuration of the hardware SPI interface is based on given transmission properties. Specifically, Fig.19 As shown, in various embodiments, instead of specifying all transfer attributes in the command field CMD, the SPI interface 30a includes multiple registers TAC[k:0] with stored given transfer attributes, and the command field CMD only includes the field TAC_NUM that has stored the number i of one of the registers TAC[k:0], that is, i=0…k.

[0223] For example, in various embodiments, each register TAC[k:0] is implemented by two addressable registers TAC_L[k:0] and TAC_H[k:0].

[0224] Fig. 20 and 21 An embodiment of registers TAC_L[k:0] and TAC_H[k:0] is shown. In the embodiment considered, each register TAC_L[k:0] comprises the following fields (which are processed accordingly by the interface 30a):

[0225] -DBR, PBR and BR: allow to specify the baud rate, i.e. the frequency of the clock signal SCK;

[0226] -PLD and LD: allow to specify the delay between the assertion of the slave select signal PCS and the first edge of SCK, for example in the number of cycles of the signal SCK;

[0227] -PTD and TD: allow to specify the delay between the last edge of the signal SCK and the negation of the slave selection PCS, for example in the number of cycles of the signal SCK;

[0228] - PNFD and NFD: allow to specify the delay between the negation of the slave selection signal PCS at the end of a frame and the assertion of the slave selection signal PCS at the beginning of the next frame, for example in the number of cycles of the signal SCK;

[0229] -PIWD and IWD: allow to specify the delay between the transmission of the last bit of a word and the first bit of the next word in a continuous PCS selection mode, for example in the number of cycles of the signal SCK.

[0230] In the embodiment considered, each register TAC_H[k:0] comprises the following fields:

[0231] -CPOL: allows selection of the inactive state of the serial communication clock (SCK), i.e. high or low;

[0232] - CPHA: allows selection of which edge of the signal SCK causes the data to be changed and which edge of the signal SCK causes the data to be captured, i.e., the clock signal of the register(s) 360, e.g., a low may indicate that the signal SIN is captured at the leading / rising edge of the signal SCK and the signal SOUT is changed at the following (falling) edge, while a high may indicate that the signal SOUT is changed at the leading / rising edge of the signal SCK and the signal SIN is captured at the following (falling) edge;

[0233] -LSBFE: allows selection of the shift direction of register(s) 360, i.e., whether data is transferred MSB first (0) or LSB first (1);

[0234] - SCK_DISABLE_CYCLES: allows to specify a delay between setting the polarity of the signal SCK and assertion of the slave select signal PCS, for example in the number of cycles of the signal SCK;

[0235] -FMSZ: allows you to select the number of bits transmitted per frame, for example between 4 and 32 bits;

[0236] -DTC: allows to specify the data transfer count per command entry, i.e. the number of data words following the command, e.g. between 1 and 65536.

[0237] Fig. 22 Also shown is an embodiment of register TAC_H (e.g., register TAC_H[0]) when the SPI interface 30a operates as a slave device, which is hereinafter identified as TAC_H_SLAVE. Fig.21 In contrast, in this case the fields LSBFE, SCH_DISABLE_CYCLES and DTC are not used, but the register may include the following fields:

[0238] -PE: allows to select whether to enable or disable per-frame parity bit transmission and reception;

[0239] -PP: allows specifying the polarity of the parity, for example, whether the number of bits set to "1" is even or odd, wherein, when the parity calculated based on the received frame does not correspond to the field PP, the control circuit 362 can set the corresponding flag in the field Q_IRQ_STATUS to the state PAR_ERR.

[0240] Fig.23An embodiment of a monitor slave selection register MONITOR_SLAVE_SELECT is shown. Specifically, this register can be used to specify whether a monitor SPI (such as an error logging module) is connected to one of the slave selection lines together with the corresponding slave selection number. For example, in the embodiment considered, each register MONITOR_SLAVE_SELECT includes the following fields:

[0241] -MONITOR_SPI_CONNECTED: allows to specify whether the monitor SPI module is connected;

[0242] -MONITOR_SPI_SLAVE_SELECT: Allows to specify for each slave select line PCS[k:0] whether to connect the monitor SPI module to the corresponding slave select line.

[0243] For example, the content of the register MONITOR_SLAVE_SELECT may be used by the processing circuit 102 or the error detection / collection module of the processing system 10 to automatically send status and / or error messages to an external monitor SPI module.

[0244] Thus, the preceding registers essentially allow the global configuration of the hardware SPI communication circuit 36 ​​and a series of predetermined transfer configurations TAC[k:0] to be specified. Optionally, the registers may also provide additional status and configuration information. In addition to these registers, each interface 320 . . . 32 n There may also be associated individual registers REG0 . . . REGn.

[0245] For example, Fig.24 An embodiment of a queue setting register Q_SETUP is shown. For example, in the embodiment considered, each register Q_SETUP comprises the following fields (which are processed accordingly by the interface 30a):

[0246] -PRIORITY: Allows you to specify interfaces 320…32 n A priority, for example between 0 (lowest) and n (highest);

[0247] -TIMESTAMP_NOT_TRANSFER_CNT: allows to specify whether the SPI interface 30a samples the timestamp TIME in response to the reception of data (see also the description of the timestamp management circuit 328) and stores the timestamp in the status field RxSTATUS, or stores the transfer count in the status field RxSTATUS;

[0248] - Rx_STATUS_EN: allows to specify whether the field RxSTATUS is added to the receive FIFO 322 after each reception of data;

[0249] - HW_TRIG_OUT_WIDTH: allows to specify the properties of the trigger signal TOUT generated via the circuit 326 of the corresponding queue, such as the number of clock cycles during which the trigger signal is set high;

[0250] - RxDMA_EN: allows to specify whether the receive FIFO 322 should generate DMA requests via the DMA controller 300 when the number of entries in the receive FIFO 322 exceeds a given threshold RxFIFO_THRESHOLD;

[0251] -RxFULL_STALL_EN: allows to specify whether the transmission operation of the hardware SPI interface 36 should be paused when the receive FIFO 322 is full;

[0252] -RxFIFO_THRESHOLD: threshold for allowing the operation of the flag RxDMA_EN;

[0253] - TxDMA_EN: allows specifying whether the transmit FIFO 320 should generate DMA requests via the DMA controller 300 when the number of entries in the transmit FIFO 320 drops below a given threshold TxFIFO_THRESHOLD;

[0254] - HW_TRIG_EDGE: allows to specify whether the data transmission is triggered on the rising edge or the falling edge of the signal TIN (see the description of the trigger circuit 326);

[0255] - HW_TRIG_EN: allows to specify whether the transfer of the queue is started via software trigger or via hardware trigger (ie via signal TIN).

[0256] -TxFIFO_THRESHOLD: allows to specify the threshold for the TxDMA_EN flag to operate.

[0257] Therefore, in various embodiments, each interface 320 . . . 32 n New data to be transferred may be automatically requested and / or received data may be transferred via a DMA request generated by interface 300, i.e., each interface 320 . . . 32 n Data to be transmitted may be read directly from memory 104 / 104 b , and received data may be written to memory 104 / 104 b , without intervention by processing circuitry 102 .

[0258] Fig.25 An embodiment of the queue hardware configuration registers Q_HW_CFG is shown. For example, in the embodiment considered, each register Q_HW_CFG comprises the following (read-only) fields (which are generated accordingly by the interface 30a):

[0259] - RxFIFO_DEPTH: indicates the number of entries in the receive FIFO 322, such as 2 to 32 words;

[0260] - TxFIFO_DEPTH: Indicates the number of entries in the transmit FIFO 320, such as 2 to 32 words.

[0261] Fig.26 An embodiment of a queue status register Q_STATUS is shown. For example, in the embodiment considered, each register Q_STATUS includes the following (read-only) fields:

[0262] - TRANSFER_COUNT: indicates the value of the SPI transfer counter, which is incremented by the hardware SPI interface 36 each time the last bit of an SPI frame is transmitted and is reset to zero at the beginning of a frame when the field CLR_COUNTER is set in the corresponding command field CMD;

[0263] -Q_STATUS: Indicates the status of the queue, such as IDLE, RUNNING, WAIT_TRIGGER, SUSPENDED, UNDERFLOW, or STALLED;

[0264] Fig. 27 An embodiment of a queue control register Q_CTRL is shown. For example, in the embodiment considered, each register Q_CTRL comprises the following fields (which are processed accordingly by the interface 30a):

[0265] -Q_FLUSH: allows resetting queues 320 and 322 and status register Q_STATUS;

[0266] - Q_SW_TRIG: allows a software command executed via the processing circuit 102 to initiate a transfer, ie, this flag indicates a software trigger.

[0267] Fig.28 An embodiment of the queue interrupt control register Q_IRQ_CTRL is shown. For example, in the embodiment considered, each register Q_IRQ_CTRL includes the following fields (ie, the interface 30a can be configured to detect one or more corresponding events):

[0268] -PARITY_ERR_IRQ_EN: allows enabling or disabling the generation of an interrupt based on the detection of a parity error;

[0269] - CRC_ERR_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to a detected CRC error;

[0270] -TRIG_OVERRUN_ERR_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detecting a trigger overflow;

[0271] - COMM and _ERR_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to the detection of a command error (i.e. a command CMD comprising invalid data);

[0272] -EOS_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detecting the end of a sequence consisting of multiple frames;

[0273] -FRAME_END_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detection of the end of a frame;

[0274] - RXFIFO_OVERRUN_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detection of a receive FIFO overflow;

[0275] - RXFIFO_UNDERRUN_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detection of a receive FIFO underrun;

[0276] -RXFIFO_FULL_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to the detection of a full receive FIFO;

[0277] - RXFIFO_EMPTY_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to the detection of an empty receive FIFO;

[0278] - RXFIFO_THRESH_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detecting that the number of entries in the receive FIFO exceeds the threshold described previously;

[0279] -TXFIFO_OVERRUN_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detection of a transmit FIFO overflow;

[0280] -TXFIFO_UNDERRUN_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detecting a transmit FIFO underrun;

[0281] -TXFIFO_FULL_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detection of a full transmit FIFI;

[0282] -TXFIFO_EMPTY_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detection of an empty transmit FIFO; and

[0283] - TXFIFO_THRESH_IRQ_EN: allows enabling or disabling the generation of an interrupt in response to detecting that the number of entries in the transmit FIFO is below the threshold described previously.

[0284] Fig.29 An embodiment of the queue interrupt status register Q_IRQ_STATUS is shown. For example, in the embodiment considered, each register Q_IRQ_STATUS includes the following fields (ie, the interface 30a can be configured to generate one or more of the following interrupts based on the enable flag of the register Q_IRQ_CTRL):

[0285] - PARITY_ERR: SPI parity error flag, which is set when an SPI frame with a parity error has been received (detected by the SPI interface 36);

[0286] - CRC_ERR: SPI CRC error flag, which is set when a SPI frame with a CRC mismatch has been received (detected by the SPI interface 36);

[0287] -TRIG_OVERRUN_ERR: Hardware trigger overflow error flag, which is set when a hardware trigger occurs while the previous hardware trigger is already pending;

[0288] -COMM and _ERR: Command error, for example, it is set when the value TAC_NUM of the command entry field CMD is greater than the corresponding hardware parameter configuration.

[0289] - EOS: end of sequence flag, which is set, for example, when the last bit of a frame has a command field CMD (which includes an end of sequence indication) in the field EOS;

[0290] -FRAME_END: ​​frame end interrupt, which is set at the end of each frame;

[0291] -RXFIFO_OVERRUN_ERR: This flag is set when the receive FIFO 322 is full and new data is ready to be written to the FIFO 322;

[0292] -RXFIFO_UNDERRUN_ERR: This flag is set when the read interface tries to read data from an empty receive FIFO320;

[0293] -RXFIFO_FULL: This flag is set when the receive FIFO 322 is full.

[0294] -RXFIFO_EMPTY: This flag is set when the receive FIFO 322 is empty.

[0295] -RXFIFO_THRESH: This flag is set when the number of entries in the receive FIFO 322 is greater than or equal to the receive FIFO threshold.

[0296] -TXFIFO_OVERRUN_ERR: This flag is set when the transmit FIFO 320 is full and another word is written to the register TxFIFO_PUSH;

[0297] -TXFIFO_UNDERRUN_ERR: This flag is set when the transmit FIFO 320 is empty and a queue is selected for the next word transmission;

[0298] -TXFIFO_FULL: This flag is set when the transmit FIFO 320 is full.

[0299] -TXFIFO_EMPTY: This flag is set when the transmit FIFO 320 is empty.

[0300] -TXFIFO_THRESH: This flag is set when the number of free entries in the transmit FIFO 320 is greater than or equal to the transmit FIFO threshold.

[0301] As previously described, in various embodiments, communication with the transmit FIFO 320 and the receive FIFO 322 is performed by storing data into and reading data from the FIFO push register Q_TxFIFO_PUSH and the queue FIFO pop register Q_RxFIFO_POP, respectively, for example via the interface 302 or the DMA interface 302.

[0302] In various embodiments, each transmit FIFO 320 may therefore manage a write pointer TxFIFO_WR_PTR that is incremented when data is transferred from register Q_TxFIFO_PUSH to the transmit FIFO 320, and a read pointer TxFIFO_RD_PTR that is incremented when data is transferred to the arbiter 34. Based on these pointers, the transmit FIFO 320 may also generate a signal TxFIFO_ACTIVE_ENTRIES that indicates the number of entries in the transmit FIFO 320 that have not yet been transferred.

[0303] Similarly, in various embodiments, each receive FIFO can manage a write pointer RxFIFO_WR_PTR that is incremented when data is transferred from the arbiter 34 to the receive FIFO 322, and a read pointer RxFIFO_RD_PTR that is incremented when data is transferred from the receive FIFO 320 to the register Q_RxFIFO_POP. Based on these pointers, the receive FIFO 322 can also generate a signal RxFIFO_ACTIVE_ENTRIES that indicates the number of entries in the receive FIFO 320 that have not yet been read.

[0304] As previously mentioned, in various embodiments, one or more of these registers and parameters may be readable for debugging purposes. For example, Fig.30 and Fig.31 An embodiment of a Q_TxFIFO_PTR and a Qn_RxFIFO_PTR associated with each interface 32 is shown, which allows the following data to be read:

[0305] -TxFIFO_ACTIVE_ENTRIES;

[0306] -TxFIFO_WR_PTR;

[0307] -TxFIFO_RD_PTR;

[0308] -RxFIFO_ACTIVE_ENTRIES;

[0309] - RxFIFO_WR_PTR; and

[0310] -RxFIFO_RD_PTR.

[0311] Typically, as previously described, these registers are related to the actual parameters used by the transmit and receive FIFOs. In various embodiments, the interface 30a may also support a debug interface that allows the FIFOs (320, 322) to be provided with corresponding read pointers in order to read the corresponding contents of the FIFOs. For example, the queue debug registers mentioned above may be used for this purpose.

[0312] Finally, as previously mentioned, in various embodiments, the interface 30a, in particular the hardware SPI interface 36, may also be configurable to perform error checking operations, such as parity checking or CRC checking. However, when performing a CRC check, a reference polynomial is typically used to calculate the CRC code. In order to properly manage the CRC calculation, the interface 30a may therefore include the aforementioned registers Q_CRC_CFG, Q_CRC_INT, Q_CRC_POLY, Q_CRC_TX, and Q_CRC_RX (which are handled accordingly by the interface 30a).

[0313] Fig.32 An embodiment of a queue CRC configuration register Q_CRC_CFG is shown. For example, in the embodiment considered, each register Q_CRC_CFG includes the following fields:

[0314] - INV_OUT: allows to specify whether the calculated final CRC value should be inverted;

[0315] -CRC_SIZE: Allows specification of the dimensions of the CRC field, such as 3 bits to 32 bits.

[0316] Fig.32 An embodiment of a queue CRC configuration register CRC initialization register is shown, which allows to specify an initial value CRC_INI (based on the dimension selected via the field CRC_SIZE) for the calculation of the CRC.

[0317] Fig.34 An embodiment of a queue CRC polynomial register Q_CRC_POLY is shown which allows the polynomial CRC_POLY (based on the dimension selected via the field CRC_SIZE) to be set by setting the corresponding bit high or low. For example, the polynomial x3+x+1 may correspond to the sequence "1011".

[0318] Therefore, if Fig.35 and 36 As shown, the interface 30a may also provide corresponding registers Q_CRC_TX and Q_CRC_RX that have stored the current CRC calculated value for each interface 32. Therefore, the control circuit 362 may include a CRC processing circuit configured to calculate the values ​​Q_CRC_TX and Q_CRC_RX based on the initial value Q_CRC_INT, the polynomial CRC_POLY and the transmitted or received data, respectively.

[0319] Thus, in various embodiments, the previously described registers allow configuration of the interface 36 and the interface 32 to be performed, in particular with respect to the transfer attribute TAC[k:0]. In addition, the registers may optionally be used to perform debugging of the interface 36 and / or the interface 32 (e.g., the queues 320 and 322). In this regard, in various embodiments, the transmission of data occurs by storing a frame including a command CMD and data DATA into the transmit FIFO 320 of the interface 32.

[0320] Specifically, in various embodiments, each queue includes:

[0321] - For example, a 32-bit transfer command and data FIFO 320, wherein the number of bits to be transferred of the data DATA stored in the FIFO 320 may be configurable, for example, between 1 and 32;

[0322] - a receive data FIFO having, for example, 32 bits, wherein the number of bits of the received data RXDATA stored in the FIFO 322 may be configurable, for example between 1 and 32;

[0323] - an optional hardware trigger input TIN managed by circuit 326;

[0324] - an optional hardware trigger output TOUT managed by circuit 326;

[0325] - a transmit DMA interface managed by the DMA interface 300, which can be configured to generate a DMA request signal when the transmit FIFO has a given number of free entries;

[0326] - a receive DMA interface managed by the DMA interface 300, which can be configured to generate a DMA request signal when the receive FIFO has a given number of filled entries;

[0327] - An optional timestamp input managed by circuit 328, which can be configured to store a timestamp into the status RxStatus.

[0328] Specifically, each transmit FIFO 320 has a given number of (fixed) entries, which may also be stored in the Q_HW_CONFIG register or specified in the manual. The (such as 32-bit) entries written to the transmit FIFO form part of a frame, which includes a series of data packets including a command CMD and one or more data values ​​DATA. As previously described, in various embodiments, each command entry CMD points to a transmit attribute control (TAC) register having a data transfer count (DTC) field. This field determines the number of data entries used for the corresponding frame, for example, DTC=0 may specify that the command CMD has one data word associated with it, and DTC=i may imply i+1 data entries for each command entry. Typically, instead of specifying the field DTC in the TAC register, the field DTC may also constitute part of the command field CMD.

[0329] For example, Fig.37 An embodiment of a command CMD is shown. For example, in the embodiment considered, each command CMD comprises the following fields (which are processed accordingly by the interface 30a):

[0330] - CONT_PCS and DEASSERT_PCS_AFTER_DTC: allows to specify whether the slave select signal PCS shall be deasserted after the end of a frame and / or every data word per frame, which may be useful for transmitting a sequence of frames, where the slave select signal is deasserted only at the end of the transmission;

[0331] -TAC_NUM: allows to specify which of the transfer attribute control registers TAC[k:0] will be used for data transfer in master mode (in slave mode, a given TAC, such as TAC[0], may be used);

[0332] -EOS: enables the generation of interrupt EOS in register Q_IRQ_STATUS, i.e. this flag indicates that the current SPI frame is the last one in the sequence;

[0333] -CLR_COUNTER: allows resetting the transfer counter field TRANSFER_COUNT in register Q_STATUS;

[0334] -PARITY_EN: allows enabling or disabling the generation of parity bits for transmission and verification based on received data;

[0335] - PARITY_POLARITY: allows to specify the polarity of the transmitted and checked parity bit (see also the description of the flag PARITY_ERR in register Q_IRQ_STATUS);

[0336] - TRIG_OUT_CONDITION and TRIG_OUT_EN: allow to specify if and when the trigger signal TOUT is generated, for example at the beginning or end of the data transmission of a frame;

[0337] - SW_TRIGGER and WAIT_TRIGGER: allow specifying whether the transfer starts immediately or based on the configuration of the field HW_TRIG_EN in the register Q_SETUP, in response to a hardware trigger signaled via the signal TIN or a separate software trigger caused by programming the field Q_SW_TRIG in the register Q_CTRL;

[0338] - DATA_IN_RXFIFO: allows to specify whether received data should be stored in the receive FIFO memory 322;

[0339] - BURST_MODE_EN: allows enabling of the burst mode, which signals to the arbiter 34 that a sequence of multiple frames should not be interrupted by the arbiter 34;

[0340] - CUMMULATIVE_CRC_DTC, CRC_TRANSMIT and CRC_EN: allow to specify whether the CRC should be calculated, whether and when the calculated CRC should be transmitted, e.g. for each word, frame and / or sequence of frames;

[0341] - CRC_RST: allows to specify whether the CRC calculation should start from the value stored to field CRC_INIT; and

[0342] - PCS_EN: Allows selection of which slave select signal should be asserted, for example, by specifying the value of the corresponding bit for each slave select signal PCS[m:0].

[0343] As mentioned above, for security purposes, a given interface 32 may also be configured to exchange data only with a given slave device. Therefore, in this case, a corresponding field PCS_EN may be associated with each interface 32, and these fields may be stored in a global register.

[0344] For example, in various embodiments, the corresponding field PCS_EN is stored in each transmission attribute TAC[k:0]. In this case, the interface 30a can also be configured to limit the use of the transmission attribute TAC[k:0] of one or more interfaces, for example, by storing a field indicating which interface 32 can use the corresponding transmission attribute TAC in each transmission attribute TAC[k:0].

[0345] Fig.38 In this regard, an example of an entry stored to the transmit FIFO 320 is shown. Specifically, in the example considered, the FIFO 320 comprises a first frame comprising a first command CMD0, which specifies a transmit attribute TAC[0] via TAC_NUM. The transmit attribute TAC[0] indicates 1 data word, for example DTC=0. Therefore, the interface 32 expects a frame comprising one data word D0, which is stored in an entry in the FIFO 320, after the command CMD0, i.e. the interface 32 reads the entry from the FIFO 320, which is provided to the arbiter 34 for transmission. The data word D0 is followed by a second frame, which comprises a second command CMD1, which specifies a transmit attribute TAC[2] via TAC_NUM. The transmit attribute TAC[2] indicates two data words, for example DTC=1. Thus, the interface 32 expects that the frame includes two data words D1 and D2, which are stored in entries in the FIFO 320, after the command CMD1, i.e. the interface 32 sequentially reads two entries from the FIFO 320, which are provided to the arbiter 34 for transmission. Similarly, the subsequent frame may include the command CMD2, which includes the number TAC_NUM referring to the transmission attribute TAC[1], for example specifying the transmission of three data words.

[0346] As previously described, in various embodiments, the interface 30a may be configured to store only received data or the corresponding status entry RxFIFO after each data word to the receive FIFO 322. For example, Fig.39 An embodiment of a data packet RxFIFO is shown. For example, in the embodiment considered, each status packet RxFIFO comprises the following fields (which are generated accordingly by the interface 30a):

[0347] -PAR_ERR: Indicates whether the received data word has a parity error;

[0348] -CRC_ERR: indicates whether the received data word has a CRC error;

[0349] -EOS: EOS is set when a data packet has been received in response to a command CMD with the flag EOS set;

[0350] - PCS_NUM: indicates the slave select signal set for the received data word;

[0351] - TIMESTAMP_OR_TRANSFER_COUNT: Indicates the timestamp or the transfer count of the received data word (eg specified via the flag TIMESTAMP_NOT_TRANSFER_COUNT in register Q_SETUP).

[0352] Therefore, the embodiments described herein have the following advantages: various interfaces 32 can be used independently and can also have different configurations. For example, in various embodiments, the processing circuit 102 can be configured, for example via software instructions, to configure the SPI interface 30a via the following steps:

[0353] 1. Configure the global registers to set the operation mode (master or slave) and one or more transfer attributes of register TAC[k:0];

[0354] 2. Optionally configure DMA thresholds for one or more transmit and receive FIFOs in corresponding queue setup registers;

[0355] 3. Enabling the interface 30a, for example by setting the field MODULE_EN in the register MCR;

[0356] 4. Once the module is enabled, the processing circuit 102 can exchange data with the registers Q_TxFIFO_PUSH and Q_RxFIFO_POP, or the interface 32 automatically generates a DMA request to read data from the buffer B. TX Read data and perform SPI transmission based on the read commands and data;

[0357] 5. To mark the end of a specific queue, the flag EOS of the command field CMD of the last frame should be set.

[0358] For example, Fig.40An example is shown, where the interface 30a comprises at least two interfaces 320 and 321, and where:

[0359] - the interface 320 is configured to use the status message RxSTATUS and to transmit two separate frames, each frame comprising a respective command CMD0, CMD1, wherein the command CMD0 uses a transmission attribute indicating the transmission of one data word TxData0 and the command CMD1 uses a transmission attribute indicating the transmission of one data word TxData1; and

[0360] The interface 321 is configured not to use the status message RxSTATUS and to transmit two separate frames, each frame comprising a respective command CMD0 , CMD1 , wherein command CMD0 uses transmission attributes indicating the transmission of one data word TxData0 and command CMD1 uses transmission attributes indicating the transmission of one data word TxData1 .

[0361] on the contrary, Fig.41 An example is shown, where the interface 30a again comprises at least two interfaces 320 and 321, and where:

[0362] - the interface 320 is configured to use the status message RxSTATUS and to transmit a sequence of link frames, each link frame comprising a respective command CMD0, CMD1, wherein the command CMD0 uses a transmission attribute indicating the transmission of two data words TxData0, TxData1 and the command CMD1 uses a transmission attribute indicating the transmission of two subsequent data words TxData2, TxData3; and

[0363] - The interface 321 is configured not to use the status message RxSTATUS and to transmit a sequence of link frames, each link frame comprising a respective command CMD0, CMD1, wherein command CMD0 uses a transmission attribute indicating the transmission of three data words TxData0, TxData1, TxData2 and command CMD1 uses a transmission attribute indicating the transmission of a subsequent data word TxData3 and so on.

[0364] Fig.42 The operation of various embodiments of the interface control circuit 324 of each interface 32 is summarized.

[0365] After the start step 1000, the interface control circuit 324 receives one or more first data packets in step 1002. As previously described, the circuit receives data via the register TxFIFO_PUSH. Optionally, the interface control circuit 324 may transmit a data read request to the DMA controller 108 via the DMA interface 300 in step 1002, and the DMA controller 108 in turn stores the received data in the register TxFIFO_PUSH. Typically, in order to generate a DMA read request, the interface control circuit 324 may monitor the fill status of the corresponding transmit FIFO 320.

[0366] Next, in step 1004 , the interface control circuit 324 stores the received one or more first data packets into the corresponding transmit FIFO memory 320 , that is, transfers the data packets from the register TxFIFO_PUSH to the write interface of the FIFO 320 .

[0367] Once the data is stored in the transmit FIFO 320, the interface control circuit 324 sequentially reads one or more first data packets from the transmit FIFO memory 320 (via the read interface of the transmit FIFO 320) in step 1006 and extracts at least one transmit data word DATA and optionally also a word command CMD from the one or more first data packets.

[0368] Therefore, in the optional verification step 1008, the interface control circuit 324 can verify whether the transmission is enabled, for example, based on a hardware or software trigger. For example, in the case that the transmission is disabled (output "N" of the verification step 1008), the interface control circuit 324 returns to step 1008. Conversely, in the case that the transmission is enabled (output "Y" of the verification step 1008), the interface control circuit 324 proceeds to step 1010. Generally, this step is completely optional, because the transmission of data can always be enabled.

[0369] In step 1010, the interface control circuit 326 provides at least one extracted transfer data word DATA to the arbiter 34. As previously described, the arbiter 34 selects which data word provided by the interface 32 must be transferred, for example based on the priority associated with the data, and provides the selected data word (or data word sequence) to the hardware SPI interface 36.

[0370] Thus, at a given time, the hardware SPI interface 36 transmits at least one transmission data word DATA. To this end, the hardware SPI interface 36 may include one or more shift registers 360, which are configured to generate a first serial data signal SOUT according to the transmission data word DATA, and generate a reception data word RXDATA by sampling the second serial data signal SIN. In addition, the hardware SPI interface 36 may also include a control circuit 362, which is configured to generate a clock signal SCK for one or more shift registers 360. As previously described, the parameters for transmission can be specified via the global register REGG, the corresponding individual registers REG0...REGn and / or the command CMD. Therefore, generally, although preferred, the command field is completely optional, because fixed transmission attributes TAC can also be defined for each interface 32 (globally).

[0371] Therefore, once the hardware SPI interface 36 has transmitted at least one transmit data word DATA and received a receive data word RXDATA, the hardware SPI interface 36 provides the receive data word RXDATA to the arbitrator 34, that is, the arbitrator 34 receives the receive data word RXDATA from the hardware SPI communication interface 36 and forwards the receive data word RXDATA to the interface 32 associated with the transmitted at least one transmit data word DATA.

[0372] Therefore, in step 1012 , the interface control circuit 326 receives the receive data word (RXDATA) from the arbiter 34 .

[0373] Next, the interface control circuit 326 stores one or more second data packets into the receive FIFO memory 322 via the write interface of the receive FIFO 322 in step 1014 , wherein the one or more second data packets include the received receive data word RXDATA.

[0374] Therefore, once the data is available, the interface control circuit 326 can sequentially transmit the one or more second data packets to the receive FIFO memory 322 in step 1016. As previously described, the circuit 326 can read at least one second data packet from the receive FIFO 322 via the read interface of the receive FIFO 322, and transmit the at least one second data packet to the register RxFIFO_PULL. Next, the interface control circuit 326 can transmit the at least one second data packet stored in the register RxFIFO_PULL, for example:

[0375] - in response to a read request to register RxFIFO_PULL; or

[0376] - By transmitting a data write request to the DMA controller 108 via the DMA interface 300 .

[0377] Once the transmission / reception of data is completed, the interface control circuit 326 may return to step 1002 to transmit a new request.

[0378] Usually, although Fig.42 Although shown as sequential operations, the various steps may actually be performed in parallel, for example via corresponding hardware subcircuits such as:

[0379] - Steps 1002 and 1004 relating to the operation of the write interface of FIFO 320;

[0380] - Steps 1006-1014 relating to the operation of the read interface of FIFO 320 and the write interface of FIFO 322; and

[0381] - Step 1016 related to the operation of the read interface of the FIFO 322 .

[0382] As previously described, when multiple queues request to transmit corresponding frames or sequences of frames (in burst mode), the arbiter 34 must decide which frame to transmit first.

[0383] For example, as described above, in various embodiments, the transmission of a frame may be requested (eg, selectively) directly based on the command field CMD, a software trigger, or a hardware trigger.

[0384] Thus, in various embodiments, the arbiter 34 is configured to determine the queue for which the transfer of data has been requested. In various embodiments, the priority of the transfer request is based on the priority set for a given interface 32, which is specified in the field PRIORITY of the corresponding register Q_SETUP. However, as mentioned above, the priority may also be specified directly in the command field CMD.

[0385] For example, in various embodiments, once the priority associated with a given transfer request is determined, arbiter 34 is configured to select the transfer request having the highest priority (eg, having the highest (or, alternatively, lowest) value).

[0386] Therefore, the arbiter 34 connects the transmit queue 320 and the receive queue 322 of the corresponding interface 32 to the hardware SPI communication interface, thereby initiating the transmission of data based on the global configuration, the corresponding individual configuration, and (optionally) the configuration stored to the command field CMD.

[0387] In this regard, as previously described, in the case of storing multiple frames to a given transmit FIFO 320, the burst mode flag BURST_MODE_EN may specify whether the transmission of a sequence of frames may be interrupted by transmitting another frame having a higher priority. For example, in various embodiments, the arbiter 34 is configured to interrupt the transmission of frames in the sequence of frames and transmit one or more frames having a higher priority when one of the following conditions is met:

[0388] - BURST_MODE_EN = 0 and CONT_PCS = 0

[0389] - BURST_MODE_EN = 0 and (CONT_PCS = 1 and DTC>0 and DEASSERT_PCS_AFTER_DTC = 1).

[0390] like Fig.13 As schematically shown in FIG. 1 , in various embodiments, interfaces 320 . . . 32 n One or more interfaces in the SPI interface 30a may also include an auxiliary receive queue 330 (in addition to the receive queue 322). For example, in various embodiments, the auxiliary receive queue 330 is provided only for the interface 320, which is also the interface used when the SPI interface 30a is operated in the slave mode. For example, in various embodiments, the queue configuration register may include a flag that specifies whether the received data should be stored in the receive FIFO 320 and / or the auxiliary receive queue 330. The auxiliary receive queue 330, such as an additional FIFO memory, may be useful for providing the corresponding data directly to another hardware circuit of the processing system 10 via the signal AuxData, for example via a FIFO read interface, thereby bypassing the DMA interface 300. In this case, the auxiliary receive queue 330 may have corresponding configuration data associated with the receive FIFO 322, such as at least one of the following: a threshold value (AuxFIFO_THRESHOLD), a field indicating the FIFO position (AuxFIFO_DEPTH), corresponding interrupt enable flags (AUXFIFO_OVERRUN_IRQ_EN, AUXFIFO_UNDERRUN_IRQ_EN, AUXFIFO_FULL_IRQ_EN, AUXFIFO_FULL_IRQ_EN, AUXFIFO_THRESH_IRQ_EN), interrupt flags (AUXFIFO_OVERRUN_ERR, AUXFIFO_UNDERRUN_ERR, AUXFIFO_UNDERRUN_ERR, AUXFIFO_EMPTY, AUXFIFO_THRESH) and debug registers.

[0391] Thus, the present disclosure is directed to various aspects that provide improvements over known SPI interfaces, which aspects may be used separately or in combination.

[0392] In general, the SPI circuit 30 a of the present disclosure may be used with any digital processing circuit 102 , preferably a digital processing circuit 102 that is programmable according to firmware stored in a non-volatile memory 104 , such as a microprocessor.

[0393] In various embodiments, the SPI circuit 30a includes a hardware SPI communication interface 36, an arbiter 34, and a plurality of interface circuits 320 . . . 32 n .

[0394] In various embodiments, the hardware SPI communication interface 36 includes one or more shift registers 360, which are configured to generate a first serial data signal SOUT according to a transmission data word DATA and a reception data word RXDATA by sampling a second serial data signal SIN. The hardware SPI communication interface 36 also includes a control circuit 362, which is configured to generate a clock signal SCK for the one or more shift registers 360.

[0395] In various embodiments, the arbiter 34 is configured to provide transmit data words DATA to the hardware SPI communication interface 36 , and to receive receive data words RXDATA from the hardware SPI communication interface 36 .

[0396] In various embodiments, each interface circuit 320 . . . 32 n The digital processing circuit 102 includes a transmission FIFO memory 320, a reception FIFO memory 322, and an interface control circuit 324. Specifically, in various embodiments, the interface control circuit 324 is configured to receive one or more first data packets from the digital processing circuit 102, and store the received one or more first data packets in the transmission FIFO memory 320. Next, the interface control circuit 324 sequentially reads the one or more first data packets from the transmission FIFO memory 320, extracts at least one transmission data word DATA from the one or more first data packets, and provides the extracted at least one transmission data word DATA to the arbiter 34. The interface control circuit 324 also receives the reception data word RXDATA from the arbiter 34, and stores one or more second data packets in the reception FIFO memory 322, wherein the one or more second data packets include the received reception data word RXDATA. Finally, the interface control circuit 324 sequentially reads the one or more second data packets from the reception FIFO memory 322, and transmits the one or more (read) second data packets to the digital processing circuit 102.

[0397] According to the first aspect of the present disclosure, the interface control circuit 324 extracts not only at least one transmission data word DATA from one or more first data packets, but also extracts a command CMD. Specifically, in various embodiments, the command indicates the attributes of the SPI communication to be used to transmit the at least one transmission data word DATA. More specifically, in various embodiments, the command includes a reference to one of a plurality of configurable transmission attributes TAC.

[0398] According to a second aspect of the present disclosure, the SPI circuit 30a includes a plurality of configuration registers, wherein the global register REGG is used to configure the hardware SPI communication interface 36 and / or the arbiter 34, and the individual registers REG0...REGn are used to configure each interface circuit 320...32 n In various embodiments, the processing system is configured to restrict access to these registers via a hardware and / or software memory access controller.

[0399] According to a third aspect of the present disclosure, the processing system 10 includes: a memory 104 (or 104b) connected to the digital processing unit 102; and a DMA controller 108, which is configured to read data from the memory 104 according to a data read request received via a first DMA channel DMA_Tx and store data to the memory 104 according to a data write request received via a second DMA channel DMA_Rx. In this case, the SPI circuit 30a may include a DMA interface 300 configured to communicate with the DMA controller 108. In addition, the interface control circuit 324 may be configured to receive one or more first data packets by transmitting a data read request to the DMA controller 108 via the DMA interface 300, and to transmit one or more second data packets by transmitting a data write request to the DMA controller 108 via the DMA interface 300. Therefore, in this case, the digital processing unit 102 can exchange data with the SPI circuit 30a indirectly via the memory 104 (or 104b). In various embodiments, processing system 10 is configured to restrict access to a memory region arranged to store the first data packet and the second data packet via a hardware and / or software memory access controller.

[0400] Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what is described and illustrated herein purely by way of example, without thereby departing from the scope of the invention, which is defined by the appended claims.

Claims

1. A processing system comprising: digital processing circuitry programmable according to firmware stored in non-volatile memory; as well as Serial peripheral interface SPI circuit, including: Hardware SPI communication interface, including: one or more shift registers configured to generate a first serial data signal based on a transmit data word and a receive data word by sampling a second serial data signal; and a first control circuit configured to generate a clock signal for the one or more shift registers; an arbiter configured to provide the transmit data word to the hardware SPI communication interface and to receive the receive data word from the hardware SPI communication interface; and A plurality of interface circuits, wherein each interface circuit comprises a transmit first-in-first-out FIFO memory, a receive FIFO memory and an interface control circuit, wherein the interface control circuit is configured to: receiving one or more first data packets from the digital processing circuit; storing the received one or more first data packets in the transmit FIFO memory; sequentially reading the one or more first data packets from the transmit FIFO memory; extracting at least one transmitted data word from the one or more first data packets; providing the extracted at least one transmit data word to the arbiter; receiving the receive data word from the arbiter; storing one or more second data packets in the receive FIFO memory, wherein the one or more second data packets include the received receive data words; sequentially reading the one or more second data packets from the receive FIFO memory; and transmitting the one or more second data packets to the digital processing circuit; wherein the SPI circuit comprises a global set of configuration registers for configuring the hardware SPI communication interface and / or the arbiter, and wherein each interface circuit comprises a respective set of individual configuration registers for configuring the respective interface circuit, and wherein a respective memory address range in the address range of the digital processing circuit is associated with the global set of configuration registers and the individual sets of configuration registers, and wherein the processing system is configured to restrict access to the memory address range for a given software task executed by the digital processing circuit.

2. The processing system of claim 1 , wherein the one or more first data packets comprise a command followed by at least one transfer data word, wherein the command comprises a field for storing data indicating a data transfer count, the data transfer count identifying the number of transfer data words following the command, and wherein the interface control circuit is configured to: extracting the command from the one or more first data packets; determining the data transmission count; extracting the number of transmitted data words indicated by the data transfer count from the one or more first data packets; and The extracted transfer data word is provided to the arbiter.

3. The processing system of claim 2, wherein the interface control circuit is configured to generate a plurality of slave select signals, and wherein the command includes data indicating which slave select signal should be set during transfer of the corresponding transfer data word.

4. The processing system of claim 2 , wherein the set of global configuration registers is configured to specify a plurality of transmission attribute items, wherein each transmission attribute item includes a corresponding field for storing the data transfer count, and wherein the command includes a field indicating one of the transmission attribute items.

5. The processing system of claim 4, wherein each transmission attribute item includes one or more fields for storing at least one of: data indicative of the timing of the clock signal; data indicating an inactive state of the clock signal; indicating whether the one or more shift registers generate the first serial data signal and / or data sampling the second serial data signal in response to a rising edge or a falling edge of the clock signal; or Data indicating the number of bits of the transmission data word to be transmitted via the first serial data signal.

6. The processing system of claim 1, wherein each individual configuration register set includes one or more fields for storing data indicative of a priority of a corresponding extracted transfer data word provided to the arbiter.

7. The processing system of claim 1 , wherein the digital processing circuit is configured to execute a hypervisor that provides a plurality of execution environments, wherein each execution environment is configured to execute a respective operating system, and wherein the hypervisor is configured to restrict access to the memory address range for the execution environment.

8. The processing system of claim 1, further comprising: A first memory connected to the digital processing circuit; and a direct memory access DMA controller configured to read data from the first memory according to a data read request received via a first DMA channel, and to store data to the first memory according to a data write request received via a second DMA channel, wherein the SPI circuit further comprises a DMA interface configured to communicate with the DMA controller, and wherein the interface control circuit of at least one interface circuit is configured to: receiving the one or more first data packets by sending a data read request to the DMA controller via the DMA interface, and The one or more second data packets are transferred by sending a data write request to the DMA controller via the DMA interface.

9. The processing system of claim 8, wherein each individual configuration register set is configured to a first threshold of free entries in the transmit FIFO memory, and a second threshold of filled entries in the receive FIFO memory, and wherein the interface control circuitry of the at least one interface circuitry is configured to: determining whether the number of free entries in the transmit FIFO memory exceeds the first threshold, and sending the data read request to the DMA controller via the DMA interface when the number of free entries in the transmit FIFO memory exceeds the first threshold; and It is determined whether the number of fill entries in the receive FIFO memory exceeds the second threshold, and when the number of fill entries in the receive FIFO memory exceeds the second threshold, the data write request is sent to the DMA controller via the DMA interface.

10. The processing system of claim 1, wherein the processing system is disposed on an integrated circuit.

11. An electronic device, comprising: Serial peripheral interface SPI slave device; as well as A processing system configured to exchange data with the SPI slave device via an SPI circuit, the processing system comprising: digital processing circuitry programmable according to firmware stored in the non-volatile memory; and The SPI circuit comprises: Hardware SPI communication interface, including: one or more shift registers configured to generate a first serial data signal based on a transmit data word and a receive data word by sampling a second serial data signal; and a first control circuit configured to generate a clock signal for the one or more shift registers; an arbiter configured to provide the transmit data word to the hardware SPI communication interface and to receive the receive data word from the hardware SPI communication interface; A plurality of interface circuits, wherein each interface circuit comprises a transmit first-in-first-out FIFO memory, a receive FIFO memory and an interface control circuit, wherein the interface control circuit is configured to: receiving one or more first data packets from the digital processing circuit; storing the received one or more first data packets in the transmit FIFO memory; sequentially reading the one or more first data packets from the transmit FIFO memory; extracting at least one transmitted data word from the one or more first data packets; providing the extracted at least one transmit data word to the arbiter; receiving the receive data word from the arbiter; storing one or more second data packets in the receive FIFO memory, wherein the one or more second data packets include the received receive data words; sequentially reading the one or more second data packets from the receive FIFO memory; and transmitting the one or more second data packets to the digital processing circuit; wherein the SPI circuit comprises a global set of configuration registers for configuring the hardware SPI communication interface and / or the arbiter, and wherein each interface circuit comprises a respective set of individual configuration registers for configuring the respective interface circuit, and wherein a respective memory address range in the address range of the digital processing circuit is associated with the global set of configuration registers and the individual sets of configuration registers, and wherein the processing system is configured to restrict access to the memory address range for a given software task executed by the digital processing circuit.

12. The electronic device of claim 11, wherein the device is a vehicle.

13. An electronic device according to claim 11, wherein each interface circuit includes a corresponding set of separate configuration registers, each set of separate configuration registers includes one or more fields, and the one or more fields are used to store data indicating the priority of the corresponding extracted transmitted data word provided to the arbitrator.

14. A method of operating a processing system, the processing system comprising: digital processing circuitry programmable according to firmware stored in non-volatile memory; and a serial peripheral interface (SPI) circuit, comprising: a hardware SPI communication interface, comprising: one or more shift registers, configured to generate a first serial data signal according to a transmit data word and a receive data word by sampling a second serial data signal; and a first control circuit, configured to generate a clock signal for the one or more shift registers; an arbiter, configured to provide the transmit data word to the hardware SPI communication interface, and to receive the receive data word from the hardware SPI communication interface; and a plurality of interface circuits, each of which comprises a transmit first-in-first-out FIFO memory, a receive FIFO memory, and an interface control circuit, wherein the SPI circuit comprises a global configuration register set for configuring the hardware SPI communication interface and / or the arbiter, and wherein each interface circuit comprises a respective individual configuration register set for configuring the respective interface circuit, and wherein a respective memory address range in the address range of the digital processing circuit is associated with the global configuration register set and the individual configuration register set, and wherein the processing system is configured to restrict access to the memory address range for a given software task executed by the digital processing circuit, and the method comprises: receiving one or more first data packets from the digital processing circuit; storing the received one or more first data packets in the transmit FIFO memory; sequentially reading the one or more first data packets from the transmit FIFO memory; extracting at least one transmitted data word from the one or more first data packets; providing the extracted at least one transmit data word to the arbiter; receiving the receive data word from the arbiter; storing one or more second data packets in the receive FIFO memory, the one or more second data packets comprising the received receive data words; sequentially reading the one or more second data packets from the receive FIFO memory; and The one or more second data packets are transmitted to the digital processing circuit.

15. The method of claim 14, wherein the one or more first data packets comprise a command followed by at least one transmit data word, wherein the command comprises a field for storing data indicating a data transfer count, the data transfer count identifying the number of transmit data words following the command, the method further comprising: extracting the command from the one or more first data packets; determining the data transmission count; extracting the number of transmitted data words indicated by the data transfer count from the one or more first data packets; as well as The extracted transfer data word is provided to the arbiter.

16. The method according to claim 15, further comprising: A plurality of slave select signals are generated, the command including data indicating which slave select signal should be set during transmission of a corresponding one of the transmit data words.

17. The method of claim 14, wherein the processing system further comprises: A first memory connected to the digital processing circuit; and a direct memory access (DMA) controller configured to read data from the first memory according to a data read request received via a first DMA channel, and to store data to the first memory according to a data write request received via a second DMA channel, the SPI circuit further comprising a DMA interface configured to communicate with the DMA controller, and for at least one interface circuit, the method further comprises: receiving the one or more first data packets by sending a data read request to the DMA controller via the DMA interface, and The one or more second data packets are transferred by sending a data write request to the DMA controller via the DMA interface.

18. The method of claim 17, wherein the at least one interface circuit comprises a respective set of separate configuration registers for configuring a first threshold of free entries in the transmit FIFO memory and a second threshold of filled entries in the receive FIFO memory, and the method further comprises: determining whether the number of free entries in the transmit FIFO memory exceeds the first threshold, and in response to the number of free entries in the transmit FIFO memory exceeding the first threshold, sending the data read request to the DMA controller via the DMA interface; as well as It is determined whether the number of fill entries in the receive FIFO memory exceeds the second threshold, and in response to the number of fill entries in the receive FIFO memory exceeding the second threshold, the data write request is sent to the DMA controller via the DMA interface.

Images