Storage controllers, memory and storage systems

Abstract

The present invention discloses a storage controller, a memory and a storage system. The storage controller includes a command processor. When the storage controller executes an access command, the command processor generates a column address information to the memory between generating an activation command to the memory and generating a read or write command to the memory. The command processor generates the column address information and the activation command based on the access command. Therefore, compared with the prior art, the memory can use the column address information to quickly turn on the corresponding bit switch.

Description

Technical Field

[0001] The present invention relates to a memory controller, a memory and a memory system, and more particularly to a memory controller, a memory and a memory system capable of reducing the time interval between a memory receiving a read command (or a write command) and turning on a corresponding bit switch. Background Art

[0002] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a dynamic random access memory (DRAM) controller 10 disclosed in the prior art. Figure 1 As shown, one side of the dynamic random access memory controller 10 can be coupled to multiple hosts H1-Hn through an advanced eXtensible interface (AXI) bus 102 of the dynamic random access memory controller 10, and the other side of the dynamic random access memory controller 10 can be coupled to multiple memories M1-Mm through a port physical layer (PHY) interface 112 of the dynamic random access memory controller 10, wherein the multiple memories M1-Mm can be double data rate (Double Data Rate, (DDR~DDR4 or higher) memory, low power (low Power) double data rate (LPDDR~LPDDR4 or higher) memory, etc. In addition, n and m are integers greater than 1.

[0003] like Figure 1 As shown, the dynamic random access memory controller 10 further includes an arbitration and mapping unit 104, a physical queue 106, a sequence engine 108, a command processor 110, and a double data rate PHY interface (DFI) bus 111. The arbitration and mapping unit 104 can determine the priority of multiple access commands (or commands) generated from multiple hosts H1-Hn, and map the multiple commands from the advanced extensible interface (AXI) address to the memory address. Then, the physical queue 106 can store the multiple commands into a command queue 202 (such as the command queue 202) according to the priority of the mapped memory address (corresponding to the priority of the multiple commands). Figure 2 For example, Figure 2As shown, the command queue 202 has 16 queues 0-15 (corresponding to commands C0-C15, respectively), wherein each queue has 36 bits, and the 36 bits include command bits, bank address data, row address data, and column address data. In addition, each command in commands C0-C15 may correspond to an 8-bit read or write command from a dynamic random access memory. The physical queue 106 may then sequentially transmit multiple commands C0-C15 to the sorting engine 108. For example, the physical queue 106 may sequentially transmit commands C0-C2 to registers FIFO00-FIFO02 (such as Figure 3 That is, commands C0-C2 are stored in registers FIFOO0-FIFOO2 in sequence. Figure 3 As shown, the finite state machine 1082 included in the sorting engine 108 can execute the commands C0-C2 stored in the registers FIFOO0-FIFOO2 according to the order of the corresponding registers FIFOO0-FIFOO2. For example, the finite state machine 1082 first executes the command C0 stored in the register FIFOO0 (with order 1), and then sequentially executes the command C1 stored in the register FIFOO1 (with order 2) and the command C2 stored in the register FIFOO2 (with order 3). After that, the command processor 110 also processes the command C0, command C1 and command C2 in sequence, wherein the operation timing of the command processor 110 processing the command C0, command C1 and command C2 can be referred to Figure 4 .like Figure 4 As shown, taking the memory M1 as an example, the command C0 is a read command corresponding to the row 11 and column 11 address (K0_row11 / col11) of the block 0 of the memory M1, the command C1 is a read command corresponding to the row 22 and column 22 address (K7_row22 / col22) of the block 7 of the memory M1, and the command C2 is a read command corresponding to the row 33 and column 33 address (K5_row33 / col33) of the block 5 of the memory M1. When the finite state machine 1082 executes the command C0, the finite state machine 1082 first checks whether the row 11 of the block 0 is activated. If the row 11 of the block 0 is not activated and the other rows of the block 0 are activated, the finite state machine 1082 enters a precharge state and controls the command processor 110 (in Figure 4 At time t1) shown in FIG. 1 , a precharge command PRECH_K0 is generated. Figure 4As shown, after the command processor 110 generates the precharge command PRECH_K0, the command processor 110 may generate an activation command ACT_K0_R11 (eg, Figure 4 The time t4 shown in the figure is used to select the row 11 of the block 0, wherein the address of the row 11 will be received by the memory M1 simultaneously with the activation command ACT_K0_R11. After the time interval tRCD (defined by the double data rate memory specification of the Joint Electronic Device Engineering Council) after the command processor 110 generates the activation command ACT_K0_R11, the command processor 110 may generate a read command RD_K0_C11 to select the column 11 of the block 0 (as shown in the figure). Figure 4 At time t6 shown in the figure, the address of row 11 will also be received by the memory M1 simultaneously with the read command RD_K0_C11. After the memory M1 receives the read command RD_K0_C11, the data stored in the memory cells of row 11 and column 11 of block 0 coupled to the memory M1 will be read. However, if the command C0 is to write data to the memory cells of row 11 and column 11 of block 0 coupled to the memory M1, then the command processor 110 will generate a write command corresponding to row 11 and column 11 of block 0 (not shown). Figure 4 ) to the memory M1. Then the memory M1 writes the data into the storage unit of row 11 and column 11 of block 0 coupled to the memory M1 according to the write command.

[0004] During the time interval tRP and the time interval tRCD, the command processor 110 may process part of the command C1 and / or the command C2 based on some lookahead rules. For example, before the activation command ACT_K0_R11 corresponding to the command C0 is generated, the finite state machine 1082 may control the command processor 110 to generate the precharge command PRECH_K7 corresponding to the command C1 (e.g., Figure 4 The time t2 shown in FIG. 1 and the activation command ACT_K5_R33 corresponding to the command C2 is generated thereafter (eg, Figure 4 In addition, during the time interval tRCD, the finite state machine 1082 can control the command processor 110 to generate an activation command ACT_K7_R22 corresponding to the command C1 (eg, Figure 4 In addition, it is worth noting that at Figure 4In the operation sequence of , unlike command C0 and command C1, because the block 5 to be read or written according to command C2 may have been precharged before time t1 (or has been executed with an auto-refresh command or a pre-charge all command), the command processor 110 does not generate a precharge command corresponding to command C2 between time t1-T3. In addition, when the read command RD_K0_C11 corresponding to command C0 is issued, the command C1 stored in register FIFOO1 will be transferred and stored in register FIFOO0, the command C2 stored in register FIFOO2 will be transferred and stored in register FIFOO1, and register FIFOO2 will store a new command (e.g., command C3) from the command queue 202 in the physical queue 106.

[0005] Also, please refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram illustrating the operation timing of the command processor 110 issuing activation commands ACT_K0_R11, ACT_K5_R33, ACT_K7_R22 and read commands RD_K0_C11, RD_K7_C22, RD_K5_C33 in the prior art. Figure 5 As shown, a time interval tRCD must exist between the activation command ACT_K0_R11 and the read command RD_K0_C11 (that is, the time interval between the activation command ACT_K0_R11 and the read command RD_K0_C11 is not less than the time interval tRCD), and a time interval tCCD (defined by the double data rate memory specification of the Joint Council of Electron Device Engineering) must exist between the read command RD_K0_C11 and the read command RD_K7_C22 (that is, the time interval between the read command RD_K0_C11 and the read command RD_K7_C22 is not less than the time interval tCCD), wherein in the double data rate memory specification of the Joint Council of Electron Device Engineering, when one clock cycle of the internal clock applied to the memory M1-Mm is equal to 1 nanosecond (1ns), the time interval tCCD is not less than 4 nanoseconds (4ns). In addition, the time interval tCCD must also exist between the read command RD_K7_C22 and the read command RD_K5_C33. In addition, when the command processor 110 processes the command C3 in sequence, the command processor 110 may issue a read command RD_K6_C44 according to the command C3, wherein Figure 5 As shown, the time interval tCCD (11 nanoseconds) between the read command RD_K6_C44 and the read command RD_K5_C33 is greater than 4 nanoseconds.

[0006] Please refer to the following Figure 6 , Figure 6 FIG. 1 is a schematic diagram of a data structure of a command disclosed in the prior art and a read or write command generating circuit 1101 in a command processor 110. Figure 6 As shown in (a), taking command C0 as an example, command C0 has 36 bits B0-B35, of which bits B0-B10 store column address data CAD, bits B11-B26 store row address data RAD, bits B27-B29 store block address data BAD, bits B32-B34 store command codes CC, and bits B30, B31, and B35 are reserved bits R. For example, the column address data CAD represents column 11, the row address data RAD represents row 11, the block address data BAD represents block 0 of the memory M1, and the command code CC represents command C0 corresponding to a read command (that is, the read command RD_K0_C11). In addition, the data structure of each command in commands C1 and C2 is the same as the data structure of command C0, so it will not be repeated here. Figure 6 As shown in (b), the read or write command generating circuit 1101 can generate a read command RD_K0_C11 according to the block address data BAD, the column address data CAD, and / or a read or write command confirmation signal RWSS, wherein the block address data BAD and the column address data CAD are transmitted from the sorting engine 108. In addition, the command processor 110 can transmit the read command RD_K0_C11 to the memory M1 via the double data rate physical layer interface bus 111 and the physical layer interface 112.

[0007] Please refer to the following Figure 7 , Figure 7 FIG. 1 is a schematic diagram of the operation sequence of the finite state machine 1082 controlling the command processor 110 disclosed in the prior art. Figure 7 As shown, regarding the read commands RD_K0_C11, RD_K7_C22, and a write command WR_K5_C33, when a first finite state machine controller 10822 included in the finite state machine 1082 controls the command processor 110 to generate the read commands RD_K0_C11, RD_K7_C22, and the write command WR_K5_C33, a time interval tRCD should be satisfied between the command processor 110 generating the activation command ACT_K0_R11 and the read command RD_K0_C11, a time interval tCCD should be satisfied between the command processor 110 generating the read command RD_K0_C11 and the read command RD_K7_C22, and a time interval tRTW (defined by the double data rate memory specification of the Joint Council of Electron Device Engineering) should be satisfied between the command processor 110 generating the read command RD_K7_C22 and the write command WR_K5_C33. In addition, as Figure 7As shown, regarding the activation commands ACT_K5_R33, ACT_K0_R11, ACT_K7_R22 and a precharge command PRECH_K5, when a second finite state machine controller 10824 included in the finite state machine 1082 controls the command processor 110 to generate the activation commands ACT_K5_R33, ACT_K0_R11, ACT_K7_R22 and the precharge command PRECH_K5, a time interval tRRD (defined by the double data rate memory specification of the Joint Council of Electronic Device Engineering) should be met between the command processor 110 generating two different activation commands, and a time interval tWR (defined by the double data rate memory specification of the Joint Council of Electronic Device Engineering) should be met before the command processor 110 generates the precharge command PRECH_K5, wherein as Figure 7 As shown, the time interval tWR exists between the precharge command PRECH_K5 and the turn-on time LBSTON of a last bit switch corresponding to the write command WR_K5_C33.

[0008] like Figure 8 As shown, taking command C0 as an example, after the memory M1 receives the read command RD_K0_C11, a time interval T1 is a time for a decoder 802 in the memory M1 to receive and decode the read command RD_K0_C11, wherein the decoder 802 operates according to a clock signal CLK (RD or WR) applied to the memory M1. Afterwards, a time interval T2 (i.e., a delay chain) is a time for a column address latch 806 to latch / output the address of column 11, and also a time for a column redundancy comparison 808 and a column address pre-decoder 810 to be ready according to the address of column 11 and a one-bit switch enable signal BS_ENABLE_PLS generated from the decoder 802. Then a time interval T3 is a time for a column bit-switch decoder 812 to decode a corresponding bit switch according to the address of column 11. In addition, as Figure 8 As shown, an address XADD[0:N] includes the address of block 0, the address of row 11 and the address of column 11, and an address latch 804 is used to latch the address of block 0, the address of row 11 and the address of column 11, wherein the address latch 804 also operates according to the clock signal CLK (RD or WR).

[0009] However, if Figure 4As shown, in the command processor 110, command C0 already includes the address information of row 11 and column 11 of block 0, command C1 also includes the address information of row 22 and column 22 of block 7, and command C2 also includes the address information of row 33 and column 33 of block 5. In addition, as Figure 4 As shown, since the unoccupied time still exists between the read command RD_K0_C11 and the activation command ACT_K0_R11 corresponding to the command C0 and the address of the column 11 stored in the register FIFOO0 is known, how to use the unoccupied time and the known address of the column 11 to remove the time interval T2 (that is, the delay chain) has become an important issue for the designer of the dynamic random access memory controller 10. Summary of the invention

[0010] The present invention discloses a storage controller, a memory and a storage system. Because the storage controller can generate a pre-column address command to the memory between generating a read command (or a write command) and generating an activate command, the memory can use the pre-column address command to quickly turn on a corresponding bit switch compared to the prior art.

[0011] An embodiment of the present invention discloses a memory controller applied to a memory. The memory controller includes a command processor. When the memory controller executes an access command, the command processor generates a column address information to the memory before generating a read or write command to the memory, wherein the column address information and the read or write command are generated based on the access command.

[0012] According to another embodiment of the present invention, the command processor generates the column address information to the memory between generating an activate command and generating the read or write command, wherein the activate command is generated based on the access command.

[0013] According to another embodiment of the present invention, the command processor is further configured to generate a precharge command based on the access command before generating the activate command.

[0014] According to another embodiment of the present invention, the command processor is also used to generate a pre-column address command to the memory before the memory receives the read or write command, the command processor generates the pre-column address command based on the access command, and there is a predetermined time between the pre-column address command and the read or write command.

[0015] According to another embodiment of the present invention, the column address information and the pre-column address command are generated to the memory within one clock cycle or simultaneously.

[0016] According to another embodiment of the present invention, after another read or write command corresponding to another access command is generated, the pre-column address command and the column address information corresponding to the access command are generated, wherein the storage controller executes the other access command before the access command.

[0017] According to another embodiment of the present invention, the storage controller further includes a sorting engine, wherein the sorting engine is coupled to the command processor, wherein the access command is stored in the sorting engine, and the sorting engine controls the command processor to sequentially generate the column address information and the read or write command according to the access command.

[0018] Another embodiment of the present invention discloses a memory capable of receiving an access command from a memory controller. The memory includes a first decoder. The first decoder is used to decode a read or write command corresponding to the access command; before receiving the read or write command, the memory receives a column address information corresponding to the access command.

[0019] According to another embodiment of the present invention, the memory further includes a second decoder, wherein the second decoder is used to decode an activation command corresponding to the access command, and the memory receives the column address information at a falling clock edge or a rising clock edge after receiving the activation command.

[0020] According to another embodiment of the present invention, the memory further includes a third decoder, wherein the third decoder is used to decode a pre-column address command corresponding to the access command, and the pre-column address command is received by the memory before the memory receives the read or write command.

[0021] According to another embodiment of the present invention, the memory receives the column address information and the pre-column address command within one clock cycle or simultaneously.

[0022] According to another embodiment of the present invention, the memory further comprises a column address latch, wherein the third decoder decodes the pre-column address command and generates a latch signal to the column address latch to latch the column address information before the memory receives the read or write command.

[0023] According to another embodiment of the present invention, the memory further includes a fourth decoder, wherein the fourth decoder is used to decode a precharge command corresponding to the access command, and the memory receives a row of address information after receiving the precharge command and before receiving the activate command.

[0024] According to another embodiment of the present invention, the memory receives the row address information and a pre-row address command within one clock cycle or simultaneously.

[0025] According to another embodiment of the present invention, the memory further comprises a fifth decoder, wherein the fifth decoder is used to decode the advance row address command corresponding to the access command, and the advance row address command is received by the memory before the memory receives the activation command.

[0026] According to another embodiment of the present invention, the memory further comprises a row address latch, wherein the fifth decoder decodes the pre-row address command and generates a latch signal to the row address latch to latch the row address information before the memory receives the activate command.

[0027] Another embodiment of the present invention discloses a storage system. The storage system includes a storage controller and a memory. The storage controller includes a command processor. The memory is coupled to the storage controller. When the storage controller executes an access command, the command processor generates a column address information to the memory before generating a read or write command to the memory; wherein the command processor generates the column address information and the read or write command based on the access command.

[0028] According to another embodiment of the present invention, the command processor is further used to generate a pre-column address command to the memory to latch the column address information before the memory receives the read or write command.

[0029] According to another embodiment of the present invention, the column address information and the pre-column address command are generated to the memory within one clock cycle or simultaneously.

[0030] According to another embodiment of the present invention, after another read or write command corresponding to another access command is generated, the pre-column address command and the column address information corresponding to the access command are generated, wherein the storage controller executes the other access command before the access command. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of a dynamic random access memory controller disclosed in the prior art.

[0032] Figure 2 is a diagram illustrating a command queue.

[0033] Figure 3 is a schematic diagram illustrating a sorting engine.

[0034] Figure 4The present invention is a schematic diagram illustrating the operation sequence of a command processor in a dynamic random access memory controller based on the prior art.

[0035] Figure 5 The present invention is a schematic diagram for explaining the operation timing of a command processor issuing an activation command and a read command in the prior art.

[0036] Figure 6 The present invention is a schematic diagram of a data structure of a command disclosed in the prior art and a read or write command generating circuit in a command processor.

[0037] Figure 7 It is a schematic diagram of the operation sequence of the finite state machine controlling the command processor disclosed in the prior art.

[0038] Figure 8 is a schematic diagram illustrating the operation of the memory after the memory receives a read command.

[0039] Fig. 9 It is a schematic diagram of a storage controller disclosed in an embodiment of the present invention.

[0040] Fig. 10A , 10B is a diagram illustrating a command processor.

[0041] Figure 11-14 2 is a schematic diagram illustrating the operation timing of the command processor generating an activation command and a corresponding read command.

[0042] Fig.15 It is a schematic diagram of the operation sequence of a finite state machine controlling a command processor disclosed in an embodiment of the present invention.

[0043] Fig.16 is a schematic diagram illustrating the operation of the memory after the memory receives a read command.

[0044] Fig.17 The present invention is a schematic diagram illustrating an operation sequence of a memory based on a pre-column address command and an operation sequence of a memory based on the prior art.

[0045] The reference numerals are described as follows:

[0046] 10 Dynamic Random Access Memory Controller

[0047] 100 Storage Controller

[0048] 102 Advanced eXtensible Interface Bus

[0049] 104 Arbitration and Mapping Unit

[0050] 106 Physical Queue

[0051] 108 Sorting Engine

[0052] 110, 150, 160 Command Processor

[0053] 111 Double Data Rate Physical Layer Interface Bus

[0054] 112 Physical layer interface

[0055] 1082 Finite State Machine

[0056] 10822 First Finite State Machine Controller

[0057] 10824 Second Finite State Machine Controller

[0058] 10826 Third Finite State Machine Controller

[0059] 1101, 1110 read or write command generation circuit

[0060] 1102 Activation command generation circuit

[0061] 1104 Precharge command generation circuit

[0062] 1106 Advance row address command generation circuit

[0063] 1108 Pre-column address command generation circuit

[0064] 802, 1602 decoder

[0065] 804 Address Latch

[0066] 806 Column Address Latch

[0067] 808 column redundant comparators

[0068] 810 Column Address Pre-Decoder

[0069] 812 Column Switch Decoder

[0070] ACT_K0_R11, ACT_K5_R33, ACT_K7_R22 activation command

[0071] ASS activation confirmation signal A13 pin BS_ENABLE_PLS bit switch enable signal BAD block address data C0-C15 commands col11, col22, col33 column addresses CLK(RD or WR), CLK(PCA) clock signals CC command code CAD column address data Delay chain FIFOO0-FIFOO2 Registers H1-Hn Host K0, K7, K5 block addresses LBSTON ON TIME M1-Mm Memory PRECH_K0, PRECH_K7, PRECH_K5 precharge commands PCSS precharge confirmation signal PRASS Pre-row address confirmation signal PCASS Pre-column address confirmation signal

[0072] PRA0 Advance row address command

[0073] PCA_K0_C11, PCA_K7_C22, Pre-column address command

[0074] PCA_K5_C33, PCA_K6_C44

[0075] PRE_COL_ADD_EN Pre-column address enable signal

[0076] Q Data

[0077] R Reserved bit

[0078] RD_K0_C11, RD_K7_C22, read command

[0079] RD_K5_C33, RD_K6_C44

[0080] Rd Read

[0081] row11, row22, row33 row addresses

[0082] RAD row address data

[0083] RWSS Read or write command confirmation signal tRCD, tRP, T1-T3, tRRD, tPCA2C, time interval

[0084] tCCD, tRTW, tWR t1-t6 time

[0085] WR_K5_C33, WR_K66_C44 write command

[0086] XADD[0:N] Address DETAILED DESCRIPTION

[0087] Please refer to Fig. 9 , Fig. 9 1 is a schematic diagram of a storage controller 100 disclosed in an embodiment of the present invention. Fig. 9 As shown, the storage controller 100 includes at least an advanced eXtensible interface (AXI) bus 102, an arbitration and mapping unit 104, a physical queue 106, a sorting engine 108, a command processor 150, a double data rate physical layer interface bus 111, and a physical layer interface 112, wherein Fig. 9 The advanced extensible interface bus 102, arbitration and mapping unit 104, physical queue 106, sequencing engine 108, double data rate physical layer interface bus 111 and physical layer interface 112 and Figure 1 The ASE bus 102, arbitration and mapping unit 104, physical queue 106, sorting engine 108, double data rate physical layer interface bus 111 and physical layer interface 112 are the same as shown, so they are not repeated here. In addition, the difference between the memory controller 100 and the dynamic random access memory controller 10 is that Fig. 9 The command processor 150 in the Figure 1 In addition, the coupling relationship between the AEIB 102, the arbitration and mapping unit 104, the physical queue 106, the sorting engine 108, the command processor 150, the double data rate physical layer interface bus 111 and the physical layer interface 112 can be referred to. Figure 1 In addition, because other circuits in the storage controller 100 other than the above components are not the technical features of the present invention, they are not described here.

[0088] In addition, the data structure of each command in the commands C0-C2 stored in the registers (eg, registers FIFO00-FIFO02) in the sequencing engine 108 can be referred to as Figure 6 Therefore, when the command processor 150 starts to execute the command C0, all the address information (including the row address data RAD and the column address data CAD) has been stored in the sorting engine 108 and can be transmitted to the command processor 150.

[0089] Also, please refer to Fig. 10A , 10B , Fig. 10A is a schematic diagram illustrating the command processor 150 and Fig. 10B is a schematic diagram illustrating the command processor 160. Fig. 10A As shown, the command processor 150 includes an active command generating circuit 1102, a pre-charge command generating circuit 1104, a pre-column address command generating circuit 1108, and a read or write command generating circuit 1110. Now, taking command C0 as an example, the active command generating circuit 1102 can generate an active command ACT_K0_R11 according to the block address data BAD of block 0 of the memory M1, the row address data RAD of block 0, and an active confirmation signal ASS, wherein the block address data BAD and the row address data RAD can be transmitted from the sorting engine 108; the pre-charge command generating circuit 1104 can generate a pre-charge command PRECH_K0 according to the block address data BAD and a pre-charge confirmation signal PCSS, wherein the block address data BAD can be transmitted from the sorting engine 108. The pre-column address command generating circuit 1108 may generate a pre-column address command PCA_K0_C11 according to the block address data BAD, the column address data CAD, and a pre-column address confirmation signal PCASS, wherein the block address data BAD and the column address data CAD may be transmitted from the sorting engine 108; the read or write command generating circuit 1110 may generate a read command RD_K0_C11 according to the block address data BAD and the read or write command confirmation signal RWSS, wherein the block address data BAD may be transmitted from the sorting engine 108. In addition, the command processor 150 may transmit a pre-charge command PRECH_K0, a pre-column address command PCA_K0_C11, a read command RD_K0_C11, and an activation command ACT_K0_R11 to the memory M1 through the double data rate physical layer interface bus 111 and the physical layer interface 112, wherein a fourth decoder in the memory M1 is used to decode the pre-charge command PRECH_K0 corresponding to the command C0. In addition, in another embodiment of the present invention (such as Fig. 10BAs shown in FIG. 1 , the difference between the command processor 160 and the command processor 150 is that the command processor 160 further includes a pre-row address command generating circuit 1106, wherein the pre-row address command generating circuit 1106 can generate a pre-row address command PRA0 according to the block address data BAD, the row address data RAD, and a pre-row address confirmation signal PRASS, the block address data BAD and the row address data RAD can be transmitted by the sorting engine 108, and a fifth decoder in the memory M1 is used to decode a pre-row address command PRA0 corresponding to the command C0. In addition, the command processor 160 can transmit the pre-row address command PRA0, the pre-charge command PRECH_K0, the pre-column address command PCA_K0_C11, the read command RD_K0_C11, and the activation command ACT_K0_R11 to the memory M1 through the double data rate physical layer interface bus 111 and the physical layer interface 112, wherein the command processor 160 generates the pre-row address command PRA0 before generating the activation command ACT_K0_R11.

[0090] In one embodiment of the present invention, command C0 stored in register FIFO00 corresponds to sequence 1, command C1 stored in register FIFO01 corresponds to sequence 2, and command C2 stored in register FIFO02 corresponds to sequence 3. The finite state machine 1082 in the sequencing engine 108 can control the command processor 150 to execute command C0. At this time, the finite state machine 1082 can pre-execute parts of command C1 and command C2 to effectively send available address information to the command processor 150 so that the command processor 150 generates the pre-column address command PCA_K0_C11 and / or the pre-row address command PRA0 at the appropriate time.

[0091] In addition, in the present invention, each command (such as command C0, command C1, or command C2) corresponds to a read command or a write command, and only the read command is used as an example to illustrate the present invention. Fig.11 As shown, command C0 corresponds to reading the memory cell of row 11 and column 11 of block 0 coupled to memory M1, command C1 corresponds to reading the memory cell of row 22 and column 22 of block 7 coupled to memory M1, and command C2 corresponds to reading the memory cell of row 33 and column 33 of block 5 coupled to memory M1 as an example, Fig.11 and Figure 5The difference is that because command C0 contains column address information (that is, column 11), the finite state machine 1082 can also control the command processor 150 to generate a pre-column address command PCA_K0_C11 between generating the activation command ACT_K0_R11 and the read command RD_K0_C11, wherein the command processor 150 can generate the pre-column address command PCA_K0_C11 to the memory M1 at the falling edge or the rising edge of the internal clock applied to the memory M1-Mm, and a second decoder in the memory M1 can be used to decode the activation command ACT_K0_R11 corresponding to command C0. For example, the command processor 150 may generate a pre-column address command PCA_K0_C11 to the memory M1 before generating a read command RD_K0_C11 to the memory M1, wherein there is a predetermined time (i.e., a time interval tPCA2C) between the pre-column address command PCA_K0_C11 and the read command RD_K0_C11, and in one embodiment of the present invention, the time interval tPCA2C is not less than 4 clock cycles (4clks) of the internal clock applied to the memories M1-Mm. Therefore, according to the example Fig.11 In the operation timing shown, because the command processor 150 can generate the pre-column address command PCA_K0_C11 with the column 11 address information before generating the read command RD_K0_C11, the memory M1 can decode the column 11 address information according to the pre-column address command PCA_K0_C11 before receiving the read command RD_K0_C11, resulting in a saving of about 2 nanoseconds (ns) in a read access time (e.g., CAS latency defined by the double data rate memory specification of the Joint Council for Electronic Device Engineering) or in a write recovery time (e.g., tWR defined by the double data rate memory specification of the Joint Council for Electronic Device Engineering). Similarly, as Fig.11As shown, the command processor 150 may generate a pre-column address command PCA_K7_C22 having the address information of column 22 before generating a read command RD_K7_C22 to the memory M1, wherein a time interval tPCA2C exists between the pre-column address command PCA_K7_C22 and the read command RD_K7_C22; the command processor 150 may generate a pre-column address command PCA_K5_C33 having the address information of column 33 before generating a read command RD_K5_C33 to the memory M1, wherein a time interval tPCA2C exists between the pre-column address command PCA_K5_C33 and the read command RD_K5_C33; the command processor 150 may generate a pre-column address command PCA_K6_C44 having the address information of column 44 before generating a read command RD_K6_C44 to the memory M1, wherein a time interval tPCA2C exists between the pre-column address command PCA_K6_C44 and the read command RD_K6_C44.

[0092] In addition, in the double data rate memory specification of the Joint Council on Electron Devices Engineering, pins A0-A13 of the memory M1 can be used to decode address information, but pins A13 and A11 are not originally used to decode column address information. Therefore, in the present invention, pins A13, A0-A9 (or pins A11, A0-A9, or pins A13, A11, A0-A9) of the memory M1 can be used to decode the column address information contained in the pre-column address commands PCA_K0_C11, PCA_K7_C22, PCA_K5_C33, wherein in one embodiment of the present invention, the column address information contained in the pre-column address commands PCA_K0_C11, PCA_K7_C22, PCA_K5_C33 corresponds to pins A0-A9 of the memory M1. However, the present invention is not limited to the memory M1 using the above pin configuration to decode the column address information contained in the pre-column address commands PCA_K0_C11, PCA_K7_C22, PCA_K5_C33.

[0093] Next, take pins A13, A0-A9 as an example. Fig.12 As shown, when the pin A13 in the column address information has a high level, the command processor 150 may generate a pre-column address command PCA_K0_C11, PCA_K7_C22, PCA_K5_C33, or PCA_K6_C44, where Fig.12As shown, the generated pre-column address commands PCA_K0_C11, PCA_K7_C22, and / or PCA_K5_C33 correspond to the read commands RD_K0_C11, RD_K7_C22, RD_K5_C33, respectively, and the pre-column address command PCA_K6_C44 corresponds to the read command RD_K6_C44 (or the write command WR_K6_C44). In addition, the time interval between a pre-column address command and a corresponding read command (or a corresponding write command) is not less than the time interval tPCA2C, and the time interval between two adjacent read commands is not less than the time interval tCCD.

[0094] In addition, the present invention is not limited to the pre-column address command generating circuit 1108 of the command processor 150 generating the pre-column address command PCA_K0_C11 at the falling edge of the clock or the rising edge of the clock between the activation command ACT_K0_R11 and the read command RD_K0_C11. In other words, as long as the pre-column address command generating circuit 1108 can generate the pre-column address command PCA_K0_C11 before the read command RD_K0_C11, it falls within the scope of the present invention.

[0095] In addition, take the command processor 150 generating the pre-column address command PCA_K6_C44 as an example. Fig.13 As shown, in one embodiment of the present invention, the time for the command processor 150 to generate the pre-column address command PCA_K6_C44 will not exceed Fig.13 Therefore, the maximum value tPCA2CMAX of the time interval tPCA2C between the pre-column address command PCA_K6_C44 and the read command RD_K6_C44 is equal to the time interval tCCD (for example, Fig.13 As shown, the time interval tCCD between the pre-column address command PCA_K6_C44 and the read command RD_K6_C44 is equal to 11 clock cycles (11clks) or 11 nanoseconds (ns), and the minimum value tPCA2CMIN of the time interval tPCA2C between the pre-column address command PCA_K6_C44 and the read command RD_K6_C44 is equal to 4 clock cycles (4clks) of the internal clock. In addition, as Fig.13As shown, taking the pre-column address command PCA_K0_C11 as an example, when the pre-column address command PCA_K0_C11 is provided, the memory M1 can improve the read access time by about 2 nanoseconds (ns) (for example, the CAS latency "CL" set by the mode register can be changed from 12 to 10). Of course, when the pre-column address command PCA_K0_C11 corresponds to a write command, the memory M1 can also improve the write recovery time by about 2 nanoseconds (ns) (for example, the "WR" set by the mode register can also be changed from 12 to 10). In addition, Fig.13 The symbol Q shown represents data.

[0096] In addition, in another embodiment of the present invention, taking the command processor 150 generating the pre-column address command PCA_K6_C44 as an example, Fig.14 As shown, the time for the command processor 150 to generate the pre-column address command PCA_K6_C44 may exceed Fig.14 The previous read command (i.e., read command RD_K5_C33) in the operation sequence shown in FIG. 1 may not exceed the activation command (not shown) corresponding to the pre-column address command PCA_K6_C44. Fig.14 ), or if possible, it cannot exceed the precharge command corresponding to the pre-column address command PCA_K6_C44. In addition, the pre-column address command PCA_K5_C33 can exceed Fig.14 The previous read command (ie, the read command RD_K7_C22) in the operation sequence shown, but cannot exceed the activation command corresponding to the pre-column address command PCA_K5_C33, or if possible, cannot exceed the pre-charge command corresponding to the pre-column address command PCA_K5_C33.

[0097] Please refer to the following Fig.15 , Fig.15 FIG. 1 is a schematic diagram of the operation sequence of the finite state machine 1082 controlling the command processor 150 disclosed in an embodiment of the present invention, wherein two read commands and a subsequent write command are generated. Fig.15As shown, taking the case where a pre-column address command is generated between the generation of a corresponding activation command and a corresponding read command (or a corresponding write command), and the pre-column address command cannot exceed the previous read command (or the previous write command) as an example, because the command processor 150 can generate pre-column address commands PCA_K0_C11, PCA_K7_C22, PCA_K5_C33, when the second finite state machine controller 10824 included in the finite state machine 1082 controls the command processor 150 to generate a pre-charge command PRECH_K5, before the command processor 150 issues the pre-charge command PRECH_K5, the time interval tWR will be reduced to a time interval tWR-2clks, where Fig.15 As shown, the time interval tWR-2clks exists between the opening time LBSTON of the last bit switch of the precharge command PRECH_K5 and the corresponding write command WR_K5_C33. Fig.15 As shown, in Fig.15 In the embodiment of the present invention, the maximum value tPCA2CMAX of the time interval tPCA2C is equal to the time interval tCCD (between two read commands) or the time interval tRTW (between a previous read command and a next write command). When a third finite state machine controller 10826 included in the finite state machine 1082 controls the command processor 150 to generate a pre-column address command PCA_K0_C11, there is a time interval tRCD-4clks between the pre-column address command PCA_K0_C11 and the activation command ACT_K0_R11, wherein the time interval tPCA2C is equal to the minimum value tPCA2CMIN (that is, 4clks); when the third finite state machine controller 10826 controls the command processor 150 to generate a pre-column address command PCA_K7_C22, there is a time interval tCCD between the pre-column address command PCA_K7_C22 and the read command RD_K7_C22; when the third finite state machine controller 10826 controls the command processor 150 to generate a pre-column address command PCA_K5_C33, there is a time interval tRTW between the pre-column address command PCA_K5_C33 and the write command WR_K5_C33. In addition, the operating principle of the first finite state machine controller 10822 can refer to Figure 7 , so I will not go into details here. In addition, Fig.15 The operation timing shown is only for illustrating (not limiting) one embodiment of the present invention.

[0098] Next, Fig.16As shown, taking command C0 as an example, after the command processor 150 generates the pre-column address command PCA_K0_C11, based on pin A13 (or other pins not used in the traditional column address) and / or the pre-column address command PCA_K0_C11, a decoder 1602 in the memory M1 (that is, a third decoder and operates according to a clock signal CLK (PCA)) can generate a pre-column address enable signal PRE_COL_ADD_EN to the column address latch 806 in the memory M1, and the address latch 804 in the memory M1 latches the address XADD[0:N] (for example, the address of block 0, the address of row 11, and the address of column 11, wherein the address latch 804 also operates according to the clock signal CLK (PCA), so the column address latch 806 can latch the address of column 11 and output the address of column 11 to the column redundancy comparator 808 and the column address pre-decoder 810 in advance, resulting in the column redundancy comparator 808 and the column address pre-decoder 810 being ready before the memory M1 receives the read command RD_K0_C11 (or during the period when the memory M1 receives the read command RD_K0_C11), or before the decoder 802 (that is, a first decoder) of the memory M1 decodes the read command RD_K0_C11 (or during the period when the decoder 802 of the memory M1 decodes the read command RD_K0_C11).

[0099] like Fig.16 As shown, because the column redundancy comparator 808 and the column address pre-decoder 810 can be prepared before the memory M1 receives the read command RD_K0_C11 (or before the decoder 802 of the memory M1 decodes the read command RD_K0_C11), Figure 8 The delay chain shown can be Fig.16 The delay chain is removed, where the delay chain is the time for the column address latch 806 to latch the address of column 11, and the time for the column redundancy comparator 808 and the column address pre-decoder 810 to be ready. Fig.16 There is no such Figure 8 The time interval T2 is shown.

[0100] Please refer to Fig.17 , Fig.17 1 is a schematic diagram illustrating the operation timing of the memory M1 based on the pre-column address command PCA_K0_C11 and the operation timing of the memory M1 based on the prior art. Fig.17As shown in (a), in the prior art, after the memory M1 receives the read command RD_K0_C11, if the pre-column address command PCA_K0_C11 is not applied to the memory M1, then after the memory M1 receives the read command RD_K0_C11, there must be a time interval T1-T3 before the memory M1 turns on the corresponding bit switch according to the column address data CAD, wherein the time interval T1 is the time for the memory M1 to receive the read command RD_K0_C11 and decode the read command RD_K0_C11, the time interval T2 is the time for the memory M1 to latch the column address data CAD, pre-decode the column address data CAD, and execute the column redundancy comparator 808, and the time interval T3 is the time for the memory M1 to decode the corresponding bit switch according to the column address data CAD to turn on the corresponding bit switch.

[0101] However, if Fig.17 As shown in (b), after the memory M1 receives the read command RD_K0_C11, if the pre-column address command PCA_K0_C11 is applied to the memory M1, because the memory M1 has decoded the pre-column address command PCA_K0_C11 to obtain the column address data CAD, has latched the column address data CAD, has pre-decoded the column address data CAD, and has executed the column redundancy comparator 808 before the memory M1 receives the read command RD_K0_C11, there are only time intervals T1 and T3 between the memory M1 receiving the read command RD_K0_C11 and the memory M1 turning on the corresponding bit switch. That is, when the memory M1 receives the read command RD_K0_C11, the memory M1 can quickly turn on the corresponding bit switch according to the column 11.

[0102] In addition, the arbitration and mapping unit 104, the sorting engine 108, and the command processor 150 can be a field programmable gate array (FPGA) having the functions of the arbitration and mapping unit 104, the sorting engine 108, and the command processor 150, or an application-specific integrated circuit (ASIC) having the functions of the arbitration and mapping unit 104, the sorting engine 108, and the command processor 150, or a software module having the functions of the arbitration and mapping unit 104, the sorting engine 108, and the command processor 150, or an analog integrated circuit having the functions of the arbitration and mapping unit 104, the sorting engine 108, and the command processor 150.

[0103] In addition, because those skilled in the art in the field of the present invention can input the code having the above functions of the arbitration and mapping unit 104, the sequencing engine 108 and the command processor 150 into a field programmable gate array (FPGA), or use the intellectual property core (IP) having the above functions of the arbitration and mapping unit 104, the sequencing engine 108 and the command processor 150 to implement an application-specific integrated circuit (ASIC) having the above functions of the arbitration circuit 104, the sequencing engine 108 and the command processor 110, and the field programmable gate array (FPGA) and the application-specific integrated circuit (ASIC) are readily available to those skilled in the art in the field of the present invention, the circuit architecture of the arbitration and mapping unit 104, the sequencing engine 108 and the command processor 150 does not need to be disclosed.

[0104] In summary, because the unoccupied time exists between the read command (or the write command) and the activate command, the present invention can use the pre-column address command generation circuit in the command processor to generate the pre-column address command to the memory between the read command (or the write command) and the activate command. Therefore, compared with the prior art, the memory can use the pre-column address command to reduce the time interval between the memory receiving the read command (or the write command) and turning on the corresponding bit switch.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A memory controller for use in a memory, wherein the memory comprises at least a decoder and a bit switch decoder, Features Includes: a command processor; wherein when the memory controller executes an access command, the command processor generates a pre-column address command to the memory before generating a read command to the memory and after generating an activate command, wherein the pre-column address command includes a column address information; The pre-column address command and the read command are generated based on the access command, there is no delay chain circuit between the decoder and the column switch decoder, and the decoder is used to decode the read command.

2. The storage controller according to claim 1, Features : The activation command is generated based on the access command.

3. The storage controller according to claim 2, Features : The command processor is further used to generate a precharge command based on the access command before generating the activate command.

4. The storage controller according to claim 1, Features There is a predetermined time between the pre-column address command and the read command.

5. The storage controller according to claim 4, Features : The column address information and the pre-column address command are generated to the memory in one clock cycle or simultaneously.

6. The storage controller according to claim 4, Features : After another read command corresponding to another access command is generated, the pre-column address command and the column address information corresponding to the access command are generated, wherein the storage controller executes the other access command before the access command.

7. The storage controller according to claim 1, Features Also includes: A sorting engine is coupled to the command processor, wherein the access command is stored in the sorting engine, and the sorting engine controls the command processor to sequentially generate the column address information and the read command according to the access command.

8. A memory capable of receiving an access command from a memory controller, Features Includes: a first decoder, configured to decode a read command corresponding to the access command; and a column bit switch decoder; wherein the memory receives a pre-column address command corresponding to the access command before receiving the read command and after receiving an activate command, wherein the pre-column address command is generated by the memory controller and includes a column address information; The pre-column address command and the read command are generated based on the access command, and there is no delay chain circuit between the first decoder and the column switch decoder.

9. The memory as claimed in claim 8, Features Also includes: a second decoder, configured to decode an activation command corresponding to the access command; The memory receives the column address information at a falling edge of a clock or a rising edge of a clock after receiving the activation command.

10. The memory according to claim 8, Features Also includes: A third decoder is used to decode the pre-column address command corresponding to the access command.

11. The memory according to claim 10, Features :The memory receives the column address information and the pre-column address command in one clock cycle or simultaneously.

12. The memory according to claim 11, Features Also includes: A column address latch, wherein the third decoder decodes the pre-column address command and generates a latch signal to the column address latch to latch the column address information before the memory receives the read command.

13. The memory according to claim 9, Features Also includes: a fourth decoder, configured to decode a precharge command corresponding to the access command; The memory receives a row of address information after receiving the precharge command and before receiving the activate command.

14. The memory as claimed in claim 13, Features : The memory receives the row address information and a pre-row address command in one clock cycle or simultaneously.

15. The memory as claimed in claim 14, Features Also includes: a fifth decoder, for decoding the advance row address command corresponding to the access command; The advance row address command is received by the memory before the memory receives the activate command.

16. The memory as claimed in claim 15, Features Also includes: A row address latch, wherein the fifth decoder decodes the pre-row address command and generates a latch signal to the row address latch to latch the row address information before the memory receives the activate command.

17. A storage system, Features Includes: a storage controller including a command processor; and a memory coupled to the memory controller, wherein the memory comprises at least a decoder and a row switch decoder; wherein when the memory controller executes an access command, the command processor generates a pre-column address command to the memory before generating a read command to the memory and after generating an activate command, wherein the pre-column address command includes a column address information, there is no delay chain circuit between the decoder and the column switch decoder, and the decoder is used to decode the read command; The command processor generates the pre-column address command and the read command based on the access command.

18. The storage system according to claim 17, Features :The command processor is used to generate the pre-column address command to the memory to latch the column address information before the memory receives the read command.

19. The storage system according to claim 18, Features : The column address information and the pre-column address command are generated to the memory in one clock cycle or simultaneously.

20. The storage system according to claim 18, Features : After another read command corresponding to another access command is generated, the pre-column address command and the column address information corresponding to the access command are generated, wherein the storage controller executes the other access command before the access command.

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