Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: providing a substrate, the substrate including a central region and a crystal edge region surrounding the central region; forming a target pattern layer on the substrate, the target pattern layer located in the central region being a device target pattern layer, and the target pattern layer located in the crystal edge region being a pseudo-target pattern layer; doping ions in the pseudo-target pattern layer to form a doped pattern layer, the etched difficulty of the doped pattern layer being less than that of the device target pattern layer; and removing the doped pattern layer. In the embodiment of the present invention, ions are doped in the pseudo-target pattern layer in the crystal edge region to form a doped pattern layer, and the etched difficulty of the doped pattern layer is less than that of the device target pattern layer; thus, during the process of removing the doped pattern layer, the damage to the device target pattern layer is small, which is beneficial to improving the uniformity of the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In current large-scale integrated circuit manufacturing, plasma dry etching is a basic process for pattern transfer. It is commonly used to form required patterns in semiconductor device layers, such as the etching of top metal layers. In etching, it is usually necessary to first use a photolithography method to form a mask pattern on the metal layer to be etched to protect the metal patterns to be retained. Photolithography is a process of removing specific parts of the thin film on the wafer surface through a series of production steps. After that, a thin film with a micro-pattern structure will be left on the wafer surface. Through the photolithography process, the final feature pattern part is retained on the wafer.

[0003] The standard process method for forming a mask pattern by photolithography is as follows: First, a photoresist layer is formed on the metal layer; then soft baking is performed to remove the solvent, enhance adhesion, release the stress in the photoresist film, and prevent the photoresist from contaminating the equipment; then the removal of the edge photoresist. After the photoresist is coated, there will be a buildup of photoresist on both the front and back sides of the wafer edge. The edge photoresist is generally unevenly spin-coated, and a good pattern cannot be obtained, and it is prone to peeling, which affects the patterns of other parts. Therefore, it needs to be removed. The chemical method (Edge Bead Removal, EBR) uses PGMEA or EGMEA edge removal solvent, sprays a small amount on the front and back edges to remove the edge photoresist; alternatively, wafer edge exposure (WEE) is used. After the pattern is exposed, the wafer edge is exposed with a laser to remove the edge photoresist. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, and to improve the performance uniformity of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a central region and a crystal edge region surrounding the central region; forming a target pattern layer on the substrate, the target pattern layer located in the central region being a device target pattern layer, and the target pattern layer located in the crystal edge region being a pseudo-target pattern layer; doping ions in the pseudo-target pattern layer to form a doped pattern layer, the etching difficulty of the doped pattern layer being less than the etching difficulty of the device target pattern layer; removing the doped pattern layer.

[0006] Optionally, an ion implantation process such as an edge plasma process or a ribbon ion beam implantation process is used to dope ions in the pseudo-target pattern layer to form the doped pattern layer.

[0007] Optionally, an edge plasma process is used to dope ions in the pseudo-target pattern layer. The process parameters of the edge plasma process include: the reaction gas includes one or more of Ar, H2, N2, and He, the chamber pressure is 500 mtorr to 2000 mtorr, the source power is 100 W to 1000 W, the bias power is 15 W to 200 W, and the process time is 10 seconds to 300 seconds.

[0008] Optionally, a ribbon ion beam implantation process is used to dope ions in the pseudo-target pattern layer. The process parameters of the ribbon ion beam implantation process include: the doped ions include one or more of Ar, H, B, P, and As, the doping dose is 1E13 atoms per square centimeter to 1E15 atoms per square centimeter, and the implantation energy is 10 keV to 200 keV.

[0009] Optionally, the method for forming the semiconductor structure further includes: after forming the target pattern layer on the substrate and before doping ions in the pseudo-target pattern layer, forming a mask layer that covers the central region and exposes the edge region; the method for forming the semiconductor structure further includes: after removing the doped pattern layer, removing the mask layer.

[0010] Optionally, in the step of providing the substrate, taking the direction from the center of the central region to the edge region as the radial direction, the size of the edge region in the radial direction is less than 2 mm.

[0011] Optionally, during the process of removing the doped pattern layer, the etching selectivity between the doped pattern layer and the device target pattern layer is greater than 3, and the etching selectivity between the doped pattern layer and the substrate is greater than 3.

[0012] Optionally, the step of forming the target pattern layer on the substrate includes: forming a target material layer on the substrate; forming a photoresist material layer on the target material layer; patterning the photoresist material layer to form a photoresist layer; etching the target material layer using the photoresist layer as a mask, and the remaining target material layer serves as the target pattern layer.

[0013] Optionally, the step of forming the photoresist layer further includes: performing a photoresist edge repair process on the photoresist material layer.

[0014] Optionally, a wet etching process is used to remove the doped pattern layer.

[0015] Optionally, the etching solution used in the wet etching process includes: a mixed solution formed by hydrofluoric acid, nitric acid, and acetic acid, or a diluted hydrofluoric acid solution.

[0016] Optionally, a remote plasma etching process is used to remove the doped pattern layer.

[0017] Optionally, the material of the target pattern layer includes one or both of silicon oxide and silicon nitride.

[0018] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate, the substrate includes a central region and a crystal edge region surrounding the central region; a device target pattern layer located in the central region of the substrate; a doped pattern layer located in the crystal edge region of the substrate, the doped pattern layer has doped ions, and the etching difficulty of the doped pattern layer is less than that of the device target pattern layer.

[0019] Optionally, the doped ions include one or more of Ar, H, B, P, and As; or, the doped ions include one or more of Ar, H, N, and He.

[0020] Optionally, the doping concentration of the doped ions in the doped pattern layer is from 1E18 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.

[0021] Optionally, taking the direction from the center of the central region to the crystal edge region as the radial direction, the size of the crystal edge region in the radial direction is less than 2 mm.

[0022] Optionally, the etching selectivity between the doped pattern layer and the device target pattern layer is greater than 3, and the etching selectivity between the doped pattern layer and the substrate is greater than 3.

[0023] Optionally, the material of the device target pattern layer includes one or both of silicon oxide and silicon nitride.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0025] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the substrate includes a central region and a crystal edge region surrounding the central region. The target pattern layer located in the central region is a device target pattern layer, and the target pattern layer located in the crystal edge region is a pseudo-target pattern layer. The step of forming a target pattern layer on the substrate generally includes forming a target material layer on the substrate, forming a photoresist layer on the target material layer, and etching the target material layer using the photoresist layer as a mask to form a target pattern layer. The photoresist layer is generally formed by a spin coating process, and the formation quality of the photoresist layer in the crystal edge region is generally poor, resulting in a poor formation quality of the pseudo-target pattern layer accordingly. In the embodiment of the present invention, ions are doped into the pseudo-target pattern layer in the crystal edge region to form a doped pattern layer, and the etching difficulty of the doped pattern layer is less than that of the device target pattern layer; thus, during the process of removing the doped pattern layer, the damage to the device target pattern layer is small, which is beneficial to improving the uniformity of the electrical performance of the semiconductor structure. Description of the Drawings

[0026] Figures 1 to 6 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;

[0027] Figures 7 to 13 are schematic structural diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed Embodiments

[0028] Currently, the formed semiconductor structure still has problems with poor performance. The reasons for poor performance are analyzed in combination with a method for forming a semiconductor structure.

[0029] Figures 1 to 6 , are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure.

[0030] As Figure 1 and Figure 2 shown, Figure 2 is Figure 1 a cross-sectional view at aa, providing a substrate, the substrate includes a central region I and a crystal edge region II surrounding the central region I ( Figure 1 only the crystal edge region II on one side of the central region I is schematically shown), the substrate includes an initial substrate 1 and a core material layer 2 located on the initial substrate 1; a mask layer 3 is formed on the core material layer 2, and the mask layer 3 includes an organic material layer 31, an anti-reflection coating 32 located on the organic material layer 31, and a photoresist layer 33 located on the anti-reflection coating 32.

[0031] As Figure 3 and Figure 4 shown, Figure 4 is Figure 3In the cross-sectional view at bb, the photoresist layer 33 in the crystal edge region II is removed by Edge Bead Removal (EBR).

[0032] As Figure 5 shown, the core material layer 2 is etched using the mask layer 3 as a mask to form the core layer 4.

[0033] As Figure 6 shown, a sidewall material layer (not shown in the figure) is formed on the core layer 4 and on the substrate exposed by the core layer 4; the sidewall material layer on the top surface of the core layer 4 and the surface of the substrate 1 is removed, and the remaining sidewall material layer on the sidewalls of the core layer 4 serves as the sidewall layer 5; after the sidewall layer 5 is formed, the core layer 4 is removed.

[0034] The formation process of the photoresist layer 33 generally includes: forming a photoresist material layer (not shown in the figure) on the anti-reflection coating 32 by spin coating, and performing exposure and development on the photoresist material layer to form the photoresist layer 33. During the process of forming the photoresist material layer by spin coating, the excess glue will be pushed by centrifugal force to the crystal edge region II, most of which is spun off the substrate, and a part remains in the crystal edge region II. Due to the relatively high relative air flow velocity in the crystal edge region II, the glue in the crystal edge region II quickly solidifies to form a bulge (as Figure 1 shown at A). During the process of removing the bulge by photoresist edge repair treatment, backspatter will occur, and backspatter bodies are formed in some regions of the photoresist layer 33 (as Figure 3 shown at B). During the process of etching the core material layer 2 using the mask layer 3 as a mask to form the core layer 4, the volume of the core layer 4 formed within the dashed box using the backspatter body as a mask is too large. Correspondingly, it results in a deviation between the position of the sidewall layer 5 within the Figure 5 dashed box and the preset position, leading to poor formation of the finally formed semiconductor structure.

[0035] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a central region and a crystal edge region surrounding the central region; forming a target pattern layer on the substrate, the target pattern layer in the central region being a device target pattern layer, and the target pattern layer in the crystal edge region being a pseudo-target pattern layer; doping ions in the pseudo-target pattern layer to form a doped pattern layer, the etching difficulty of the doped pattern layer being less than that of the device target pattern layer; removing the doped pattern layer.

[0036] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the substrate includes a central region and an edge region surrounding the central region. The target pattern layer located in the central region is a device target pattern layer, and the target pattern layer located in the edge region is a pseudo-target pattern layer. The step of forming a target pattern layer on the substrate generally includes forming a target material layer on the substrate, forming a photoresist layer on the target material layer, and etching the target material layer using the photoresist layer as a mask to form a target pattern layer. The photoresist layer is generally formed by a spin coating process, and the formation quality of the photoresist layer in the edge region is generally poor, resulting in a poor formation quality of the pseudo-target pattern layer accordingly. In the embodiment of the present invention, ions are doped into the pseudo-target pattern layer in the edge region to form a doped pattern layer, and the etching difficulty of the doped pattern layer is less than that of the device target pattern layer; thus, during the process of removing the doped pattern layer, the damage to the device target pattern layer is small, which is beneficial to improving the uniformity of the electrical performance of the semiconductor structure.

[0037] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0038] Figures 7 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0039] As Figure 7 shown, Figure 7 including Figure 7 (a) and Figure 7 (b), Figure 7 (b) is Figure 7 a cross-sectional view in the EE direction of (a), providing a substrate 100, and the substrate 100 includes a central region I and an edge region II surrounding the central region I.

[0040] The substrate 100 prepares for the subsequent formation of the bottom pattern.

[0041] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0042] In this embodiment, the central region I prepares for the subsequent formation of the device target pattern layer, and the edge region II prepares for the formation of the pseudo-target pattern layer.

[0043] It should be noted that in the step of providing the substrate 100, taking the direction from the center of the central region I to the crystal edge region II as the radial direction, the size of the crystal edge region II in the radial direction should not be too large. If the size of the crystal edge region II in the radial direction is too large, the corresponding ratio of the crystal edge region II to the central region I is too large, and the effective region of the substrate for forming semiconductor devices is too small, which is not conducive to improving the yield of the semiconductor structure. In this embodiment, the size of the crystal edge region II in the radial direction is less than 2 mm.

[0044] Reference Figures 8 to 10 , a target pattern layer 101 is formed on the substrate 100 (as Figure 10 shown), the target pattern layer 101 located in the central region I is the device target pattern layer 1011, and the target pattern layer 101 located in the crystal edge region II is the dummy target pattern layer 1012.

[0045] The device target pattern layer 1011 prepares for the subsequent etching of the substrate 100; the dummy target pattern layer 1012 is removed in the subsequent process.

[0046] The material of the target pattern layer 101 is different from that of the substrate 100. Correspondingly, in the step of etching the substrate 100 using the device target pattern layer 1011 as a mask subsequently, the substrate 100 and the device target pattern layer 1011 have a large etching selectivity ratio.

[0047] Specifically, the material of the target pattern layer 101 includes one or both of silicon oxide and silicon nitride. In this embodiment, the material of the target pattern layer 101 includes silicon nitride. Silicon nitride is a commonly used dielectric material in the process with low cost and has high process compatibility, which is beneficial to reducing the process difficulty and process cost of forming the target pattern layer 101.

[0048] The step of forming the target pattern layer 101 on the substrate 100 includes: as Figure 8 shown, a target material layer 102 is formed on the substrate 100; a photoresist material layer 104 (not shown in the figure) is formed on the target material layer 102; as Figure 9 shown, the photoresist material layer 104 is patterned to form a photoresist layer 103; as Figure 10 shown, the target material layer 102 is etched using the photoresist layer 103 as a mask, and the remaining target material layer 102 serves as the target pattern layer 101.

[0049] In this embodiment, using the photoresist layer 103 as a mask, the target material layer 102 is etched by a dry etching process, and the remaining target material layer 102 serves as the target pattern layer 101. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is beneficial to making the morphology of the target pattern layer 101 meet the process requirements. Moreover, during the etching process, the top of the substrate 100 can be used as the etching stop position, which is beneficial to reducing the damage to other film layer structures. Furthermore, by changing the etching gas, the dry etching process can etch each film layer in the same etching equipment, simplifying the process steps.

[0050] It should be noted that the photoresist material layer 104 is usually formed by a spin coating process. During the formation of the photoresist material layer 104, the excess photoresist material layer 104 will be pushed to the edge of the crystal edge region II by centrifugal force, and most of it will be spun off the substrate. A part remains in the crystal edge region II. Since the relative air flow velocity in the crystal edge region II is relatively large, the photoresist material layer 104 in the crystal edge region II quickly solidifies, forming a raised edge (as shown in E in Figure 8 ). Under the action of surface tension, a small amount of the photoresist material layer 104 even flows along the edge to the back side of the wafer, causing contamination to the back side of the wafer. This part of the photoresist material layer 104 is prone to peeling, affecting the patterns of other parts, or causing contamination.

[0051] It should be noted that an organic material layer 106 and a bottom anti-reflection coating 105 located on the organic material layer 106 are also formed between the target material layer 102 and the photoresist material layer 104. During the process of etching the target material layer 102 using the photoresist layer 103 as a mask, the organic material layer 106 and the bottom anti-reflection coating 105 are also etched.

[0052] It should be noted that in other embodiments, the step of forming a target pattern layer on the substrate further includes: performing a photoresist edge repair treatment (Edge Bead Removal, EBR) on the photoresist material layer.

[0053] The photoresist edge repair treatment uses propylene glycol methyl ether acetate (PGMEA) or ethylene glycol methyl ether acetate (EGMEA) as a deburring solvent, and sprays a small amount in the crystal edge region II, which can remove the photoresist material layer in the crystal edge region II.

[0054] Refer to Figure 11 , ions are doped in the pseudo-target pattern layer 1012 to form a doped pattern layer 107, and the etching difficulty of the doped pattern layer 107 is less than that of the device target pattern layer 1011.

[0055] The steps of forming the target pattern layer 101 on the substrate 100 generally include forming a target material layer 102 on the substrate 100, forming a photoresist layer 103 on the target material layer 102, etching the target material layer 102 using the photoresist layer 103 as a mask to form the target pattern layer 101. Among them, the photoresist layer 103 is usually formed by a spin coating process, and the formation quality of the photoresist layer 103 in the bevel region II is generally poor, which correspondingly results in poor formation quality of the pseudo-target pattern layer 1012. In the embodiment of the present invention, ions are doped into the pseudo-target pattern layer 1012 in the bevel region II to form a doped pattern layer 101. The etching difficulty of the doped pattern layer 101 is less than that of the device target pattern layer 1011. Therefore, during the process of removing the doped pattern layer 101, the damage to the device target pattern layer 1011 is small, which is beneficial to improving the uniformity of the electrical performance of the semiconductor structure.

[0056] In this embodiment, a bevel plasma process is used to dope ions into the pseudo-target pattern layer 1012 to form the doped pattern layer 107. The bevel plasma process can dope ions into the pseudo-target pattern layer 1012 while preventing ions from doping into the device target pattern layer 1011 in the central region I. The ions doped into the pseudo-target pattern layer 1012 can reduce the bond energy between atoms in the pseudo-target pattern layer 1012, so that the bond energy between atoms in the formed doped pattern layer 107 is less than the bond energy between atoms in the device target pattern layer 1011. During the subsequent process of removing the doped pattern layer 107, the doped pattern layer 107 and the device target pattern layer 1011 have a large etching selectivity ratio.

[0057] The process parameters of the bevel plasma process include: the reaction gas includes one or more of Ar, H2, N2, and He. The reaction gas is plasmaized under the action of the source power.

[0058] In this embodiment, the material of the target pattern layer 101 is silicon nitride. Correspondingly, the reaction gas includes H2. Doping with hydrogen ions in the doped pattern layer 107 can reduce the bond energy between atoms in the doped pattern layer 107.

[0059] It should be noted that during the crystal edge plasma process, the chamber pressure should not be too high or too low. If the chamber pressure is too high, the velocity of the ionized ions is likely to be small, and the ionized ions are not easily doped into the bottom of the pseudo-target pattern layer 1012, resulting in poor formation quality of the doped pattern layer 107. During the subsequent process of removing the doped pattern layer 107, the bottom of the doped pattern layer 107 is difficult to be removed. Correspondingly, during the subsequent process of etching the substrate 100 with the device target pattern layer 1011 as a mask, the remaining doped pattern layer 107 in the crystal edge region II will etch the substrate 100 as a mask, forming a chaotic crystal edge pattern, which is not conducive to improving the uniformity of the semiconductor structure performance. If the chamber pressure is too low, the velocity of the ionized ions is too large. During the process of doping the ionized ions into the pseudo-target pattern layer 1012, the top of the pseudo-target pattern layer 1012 is easily damaged, resulting in a decrease in the thickness of the pseudo-target pattern layer 1012. In addition, if the chamber pressure is too low, the process controllability and reaction rate uniformity of the doping process of the pseudo-target pattern layer 1012 are small, resulting in poor formation quality of the doped pattern layer 107, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, during the crystal edge plasma process, the chamber pressure is 500 mtorr to 2000 mtorr.

[0060] It should be noted that during the crystal edge plasma process, the source power should not be too small or too large. If the source power is too small during the crystal edge plasma process, it is easy to reduce the plasma density, and then the doping ion rate of the pseudo-target pattern layer 1012 is too slow, which is not conducive to improving the formation rate of the doped pattern layer 107. If the source power of the plasma treatment is too large during the crystal edge plasma process, it is easy to cause the plasma density to be too large, and then the doping uniformity of the pseudo-target pattern layer 1012 is poor, resulting in poor formation quality of the doped pattern layer 107. Therefore, in this embodiment, during the crystal edge plasma process, the source power is 100 W to 1000 W.

[0061] It should be noted that during the edge plasma process, the bias power should neither be too large nor too small. If the bias power is too large during the edge plasma process, the speed of the ionized ions is likely to be too fast. During the process of the ionized ions doping into the pseudo-target pattern layer 1012, the top of the pseudo-target pattern layer 1012 is likely to be damaged, resulting in a decrease in the thickness of the pseudo-target pattern layer 1012. In addition, if the bias power is too large, the process controllability and reaction rate uniformity of the doping process of the pseudo-target pattern layer 1012 are small, resulting in poor formation quality of the doped pattern layer 107, which is not conducive to improving the electrical performance of the semiconductor structure. If the bias power is too small during the edge plasma process, the speed of the ionized ions is likely to be small, and the ionized ions are not easily doped into the bottom of the pseudo-target pattern layer 1012. As a result, the formation quality of the doped pattern layer 107 is poor. During the subsequent process of removing the doped pattern layer 107, the bottom of the doped pattern layer 107 is difficult to be removed. Correspondingly, during the subsequent process of etching the substrate 100 using the device target pattern layer 1011 as a mask, the remaining doped pattern layer 107 in the edge region II will be used as a mask to etch the substrate 100, forming a chaotic edge pattern, which is not conducive to improving the uniformity of the semiconductor structure performance. Therefore, in this embodiment, the bias power is 15 W to 200 W.

[0062] It should be noted that the process time of the edge plasma process should neither be too long nor too short. If the process time of the edge plasma process is too long, the efficiency of the semiconductor structure will be low. If the process time of the edge plasma process is too short, the ion content in the doped pattern layer 107 is small. During the subsequent process of removing the doped pattern layer 107, the etching selectivity between the doped pattern layer 107 and the device target pattern layer 1011 is small. During the process of removing the doped pattern layer, the doped pattern layer 107 is likely to have residues. During the subsequent process of etching the substrate 100 using the device target pattern layer 1011 as a mask, the remaining doped pattern layer 107 will be used as a mask to etch the substrate 100, forming a chaotic pattern in the edge region II, which is not conducive to improving the uniformity of the semiconductor structure performance. In this embodiment, the process time of the edge plasma process is 10 seconds to 300 seconds.

[0063] In other embodiments, a ribbon beam implantation process can also be used to dope ions in the pseudo-target pattern layer to form the doped pattern layer. The ribbon beam implantation process has a good process window and can specifically inject ions into the pseudo-target pattern layer in the edge region II.

[0064] The process parameters of the ribbon beam implantation process include: the doped ions include one or more of Ar, H, B, P, and As.

[0065] It should be noted that during the process of the strip ion beam implantation process, the doping dose of the doping ions in the doping pattern layer should not be too high or too low. If the doping dose of the doping ions in the doping pattern layer is too high, the process time required for the corresponding strip ion beam implantation process is too long, resulting in a low efficiency of the semiconductor structure. If the doping dose of the doping ions in the doping pattern layer is too low, the ion content in the doping pattern layer is small. During the subsequent process of removing the doping pattern layer, the etching selectivity between the doping pattern layer and the device target pattern layer is small, and the doping pattern layer is prone to residue. During the subsequent process of etching the substrate with the device target pattern layer as a mask, the remaining doping pattern layer will be used as a mask to etch the substrate, forming a disordered pattern in the crystal edge region II, which is not conducive to improving the uniformity of the semiconductor structure performance. In other embodiments, the doping dose of the doping ions in the strip ion beam implantation process is from 1E13 atoms per square centimeter to 1E15 atoms per square centimeter.

[0066] It should be noted that during the process of the strip ion beam implantation process, the implantation energy should not be too large or too small. If the implantation energy is too large during the strip ion beam implantation process, the doping ions are easily penetrated through the pseudo target pattern layer into the substrate. Correspondingly, the doping dose of the doping ions in the formed doping pattern layer is small. During the subsequent process of removing the doping pattern layer, the etching selectivity between the doping pattern layer and the device target pattern layer is small, and the doping pattern layer is prone to residue. During the subsequent process of etching the substrate with the device target pattern layer as a mask, the remaining doping pattern layer will be used as a mask to etch the substrate, forming a disordered pattern in the crystal edge region II, which is not conducive to improving the uniformity of the semiconductor structure performance. If the implantation energy is too small during the strip ion beam implantation process, the doping ions are only formed on the surface of the doping pattern layer. During the subsequent process of removing the doping pattern layer, the etching selectivity between the doping pattern layer and the device target pattern layer is small, and the doping pattern layer is prone to residue. During the subsequent process of etching the substrate with the device target pattern layer as a mask, the remaining doping pattern layer will be used as a mask to etch the substrate, forming a disordered pattern in the crystal edge region II, which is not conducive to improving the uniformity of the semiconductor structure performance. In this embodiment, during the process of the strip ion beam implantation process, the implantation energy is from 10 kev to 200 kev.

[0067] It should be noted that in other embodiments, the method for forming the semiconductor structure further includes: after forming the target pattern layer on the substrate and before doping ions in the pseudo target pattern layer, forming a shielding layer (not shown in the figure) that covers the central region I and exposes the crystal edge region II, where the shielding layer covers the device target pattern layer in the central region I and exposes the pseudo target pattern layer in the crystal edge region II.

[0068] During the process of doping ions in the pseudo-target pattern layer located in the crystal edge region II, the shielding layer can protect the device target pattern layer from being doped with ions.

[0069] In this embodiment, the material of the shielding layer includes organic materials, such as: BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer) material, photoresist, DARC (dielectric anti-reflective coating) material, DUO (Deep UV Light Absorbing Oxide) material, or APF (Advanced Patterning Film) material.

[0070] The method for forming the semiconductor structure further includes: removing the doping pattern layer and then removing the shielding layer.

[0071] In this embodiment, the material of the shielding layer is an organic material, and accordingly, an ashing process is used to remove the shielding layer.

[0072] Reference Figure 12 , remove the doping pattern layer 107.

[0073] The etching difficulty of the doping pattern layer 107 is less than that of the device target pattern layer 1011; thus, during the process of removing the doping pattern layer 107, the damage to the device target pattern layer 1011 is relatively small. During the subsequent process of etching the substrate 100 using the device target pattern layer 1011 as a mask, it is possible to prevent the formation of patterns in the crystal edge region II, thereby achieving the effect of forming a semiconductor structure only in the central region I, which is beneficial to obtaining a semiconductor structure with high performance uniformity.

[0074] In this embodiment, a wet etching process is used to remove the doping pattern layer 107. The wet etching process is isotropic etching, which has a high etching rate, simple operation, and low process cost.

[0075] Specifically, the wet etching process includes: bevel wet etching process (bevel WET) and whole wafer wet etching process (whole wafer WET).

[0076] In this embodiment, the material of the doped pattern layer 107 is silicon nitride doped with H ions. The etching solution used in the wet etching process includes: diluted hydrofluoric acid solution (DHF). In other embodiments, the etching solution used in the wet etching process may also include a mixed solution (HNA) formed by hydrofluoric acid, nitric acid, and acetic acid.

[0077] It should be noted that during the process of removing the doped pattern layer 107, the etching selectivity between the doped pattern layer 107 and the device target pattern layer 1011 is greater than 3, and the etching selectivity between the doped pattern layer 107 and the substrate 100 is greater than 3. Thus, during the process of removing the doped pattern layer 107, the damage to the device target pattern layer 1011 and the substrate 100 is relatively small.

[0078] In other embodiments, a remote plasma etching process (Remote Plasma) may also be used to remove the doped pattern layer. The remote plasma etching process is a process that uses a plasma source to form plasma outside the crystal edge region II, and then introduces the plasma into the crystal edge region II through air flow, electric field, magnetic field, etc. to etch the doped pattern layer. In the remote plasma etching process, the distance between the plasma ionization region and the etching reaction region is relatively far, which is beneficial to obtaining better spatial uniformity, or obtaining a more appropriate ratio of ions, neutral components, and different radical ratios, thereby being beneficial to improving the etching effect of the plasma etching process.

[0079] Reference Figure 13 , after removing the doped pattern layer 107, the substrate 100 is etched using the device target pattern layer 1011 as a mask to form a substrate 109 and a bottom pattern 110 located on the substrate 109.

[0080] In this embodiment, the substrate 100 is etched using a dry etching process with the device target pattern layer 1011 as a mask. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is beneficial to making the morphology of the bottom pattern 110 meet the process requirements, and using the dry etching process is beneficial to precisely controlling the removal thickness of the substrate 100.

[0081] Correspondingly, reference Figure 11 , the embodiment of the present invention also provides a semiconductor structure.

[0082] The semiconductor structure includes: a substrate 100, and the substrate 100 includes a central region I and a crystal edge region II surrounding the central region I ( Figure 11Only the crystal edge region II on one side of the central region I is schematically shown); the device target pattern layer 1011 is located in the central region I of the substrate 100; the doping pattern layer 107 is located in the crystal edge region II of the substrate 100, the doping pattern layer 107 has doping ions, and the etching difficulty of the doping pattern layer 107 is less than that of the device target pattern layer 1011.

[0083] In the semiconductor structure provided by the embodiment of the present invention, doping ions are doped in the doping pattern layer 107 in the crystal edge region II, and the etching difficulty of the doping pattern layer 107 is less than that of the device target pattern layer 1011; in the subsequent process of removing the doping pattern layer 107, the damage to the device target pattern layer 1011 is small. In the subsequent process of etching the substrate 100 with the device target pattern layer 1011 as a mask, it is possible to prevent the formation of a pattern in the crystal edge region II, so as to achieve the effect of forming a semiconductor structure only in the central region I, which is beneficial to making the performance uniformity of the finally formed semiconductor structure relatively high.

[0084] The substrate 100 prepares for the subsequent formation of the bottom pattern.

[0085] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0086] It should be noted that taking the direction from the center of the central region I to the crystal edge region II as the radial direction, the size of the crystal edge region II in the radial direction should not be too large. If the size of the crystal edge region II in the radial direction is too large, the corresponding ratio of the crystal edge region II to the central region I is too large, and the effective area of the substrate for forming semiconductor devices is too small, which is not conducive to improving the yield of the semiconductor structure. In this embodiment, the size of the crystal edge region II in the radial direction is less than 2 mm.

[0087] The device target pattern layer 1011 prepares for the subsequent etching of the substrate to form the bottom pattern.

[0088] The material of the device target pattern layer 1011 is different from that of the substrate 100. In the subsequent step of etching the substrate 100 with the device target pattern layer 1011 as a mask, the substrate 100 and the device target pattern layer 1011 have a large etching selectivity ratio.

[0089] Specifically, the material of the device target pattern layer 1011 includes one or both of silicon oxide and silicon nitride. In this embodiment, the material of the device target pattern layer 1011 includes silicon nitride. Silicon nitride is a commonly used dielectric material in the process with low cost and has high process compatibility, which is beneficial to reducing the process difficulty and process cost of forming the device target pattern layer 1011.

[0090] The doped pattern layer 107 is removed in the subsequent process. During the process of etching the substrate 100 with the device target pattern layer 1011 subsequently, no pattern is formed in the substrate 100 in the crystal edge region II.

[0091] In this embodiment, the etching selectivity between the doped pattern layer 107 and the device target pattern layer 1011 is greater than 3, and the etching selectivity between the doped pattern layer 107 and the substrate 100 is greater than 3. During the process of removing the doped pattern layer 107, the damage to the device target pattern layer 1011 and the substrate 100 is relatively small.

[0092] In this embodiment, the doped ions include one or more of Ar, H, N, and He.

[0093] The ions in the doped pattern layer 107 can reduce the bond energy between atoms in the doped pattern layer 107, so that the bond energy between atoms in the formed doped pattern layer 107 is less than the bond energy between atoms in the device target pattern layer 1011. During the subsequent process of removing the doped pattern layer 107, the doped pattern layer 107 and the device target pattern layer 1011 have a large etching selectivity.

[0094] In other embodiments, the doped ions may also include one or more of Ar, H, B, P, and As.

[0095] It should be noted that the doping concentration of the doped ions in the doped pattern layer 107 should not be too high or too low. If the doping concentration of the doped ions in the doped pattern layer 107 is too high, the corresponding process time required to form the doped pattern layer 107 is too long, resulting in low efficiency of the semiconductor structure. If the doping concentration of the doped ions in the doped pattern layer 107 is too low, the ion content in the doped pattern layer 107 is small. During the subsequent process of removing the doped pattern layer 107, the etching selectivity between the doped pattern layer 107 and the device target pattern layer 1011 is small, and the doped pattern layer 107 is likely to have residues. During the subsequent process of etching the substrate 100 with the device target pattern layer 1011 as the mask, the remaining doped pattern layer 107 will be used as the mask to etch the substrate 100, and a disordered pattern will be formed in the crystal edge region II, which is not conducive to improving the uniformity of the semiconductor structure performance. In this embodiment, the doping concentration of the doped ions is 1E18 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.

[0096] The semiconductor structure described in this embodiment can be formed by the formation method described in the foregoing embodiment, or can be formed by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, and details thereof are not repeated herein.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a central region and a crystal edge region surrounding the central region; Forming a patterned target pattern layer on the substrate, the target pattern layer located in the central region being a device target pattern layer, and the target pattern layer located in the crystal edge region being a pseudo-target pattern layer. The step of forming the target pattern layer on the substrate includes: forming a target material layer on the substrate; forming a photoresist material layer on the target material layer; patterning the photoresist material layer in the central region and the photoresist material layer remaining in the crystal edge region to form a photoresist layer; etching the target material layer using the photoresist layer as a mask, and the remaining target material layer serving as the target pattern layer; After forming the patterned target pattern layer, doping ions in the pseudo-target pattern layer to form a doped pattern layer, the etched difficulty of the doped pattern layer being less than that of the device target pattern layer; Removing the doped pattern layer; Etching the substrate using the device target pattern layer as a mask to form a substrate and a bottom pattern located on the substrate.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, Using a crystal edge plasma process or a ribbon ion beam implantation process to dope ions in the pseudo-target pattern layer to form the doped pattern layer.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, Using a crystal edge plasma process to dope ions in the pseudo-target pattern layer; The process parameters of the crystal edge plasma process include: the reaction gas includes one or more of Ar, H2, N2, and He, the chamber pressure is 500 mtorr to 2000 mtorr, the source power is 100 W to 1000 W, the bias power is 15 W to 200 W, and the process time is 10 seconds to 300 seconds.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, Using a ribbon ion beam implantation process to dope ions in the pseudo-target pattern layer; The process parameters of the ribbon ion beam implantation process include: the doped ions include one or more of Ar, H, B, P, and As, the doping dose is 1E13 atoms per square centimeter to 1E15 atoms per square centimeter, and the implantation energy is 10 kev to 200 kev.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the semiconductor structure further includes: after forming the target pattern layer on the substrate and before doping ions in the pseudo-target pattern layer, forming a shielding layer covering the central region and exposing the crystal edge region; The method for forming the semiconductor structure further includes: after removing the doped pattern layer, removing the shielding layer.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of providing the substrate, taking the direction from the center of the central region to the crystal edge region as the radial direction, the size of the crystal edge region in the radial direction is less than 2 mm.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, During the process of removing the doped pattern layer, the etching selectivity between the doped pattern layer and the device target pattern layer is greater than 3, and the etching selectivity between the doped pattern layer and the substrate is greater than 3.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The step of forming the photoresist layer further includes: performing photoresist edge repair treatment on the photoresist material layer.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, Using a wet etching process to remove the doped pattern layer.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The etching solution used in the wet etching process includes: a mixed solution formed by hydrofluoric acid, nitric acid, and acetic acid, or a diluted hydrofluoric acid solution.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The doped pattern layer is removed by a remote plasma etching process.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the device target pattern layer includes one or both of silicon oxide and silicon nitride.

13. A semiconductor structure, characterized in that, Comprising a substrate, the substrate including a central region and a crystal edge region surrounding the central region; a device target pattern layer, located in the central region of the substrate, the device target pattern layer being used as a mask to etch the substrate to form a substrate and a bottom pattern located on the substrate; a doped pattern layer, located in the crystal edge region of the substrate, the doped pattern layer being a pseudo target pattern layer having doped ions, the etching difficulty of the doped pattern layer being less than the etching difficulty of the device target pattern layer; wherein, the device target pattern layer and the pseudo target pattern layer are obtained by etching a target material layer using a photoresist layer as a mask, and the photoresist layer for forming the pseudo target pattern layer is obtained by patterning the photoresist material layer remaining in the crystal edge region.

14. The semiconductor structure according to claim 13, wherein, The doped ions include one or more of Ar, H, B, P, and As; Or, The doped ions include one or more of Ar, H, N, and He.

15. The semiconductor structure according to claim 13, wherein, The doping concentration of the doped ions in the doped pattern layer is from 1E18 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.

16. The semiconductor structure according to claim 13, wherein, Taking the direction from the center of the central region to the crystal edge region as the radial direction, the size of the crystal edge region in the radial direction is less than 2 mm.

17. The semiconductor structure according to claim 13, wherein, The etching selectivity between the doped pattern layer and the device target pattern layer is greater than 3, and the etching selectivity between the doped pattern layer and the substrate is greater than 3.

18. The semiconductor structure according to claim 13, wherein, The material of the device target pattern layer includes one or both of silicon oxide and silicon nitride.

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