Semiconductor device and method of manufacturing the same

Abstract

Semiconductor devices and methods of manufacturing the same are provided. The method includes forming a first dielectric layer on a substrate; forming a via in the first dielectric layer; sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an anti-reflection pattern on the first dielectric layer; and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. Forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0037771, filed on March 27, 2020, and Korean Patent Application No. 10-2020-0095459, filed on July 30, 2020, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Some example embodiments relate to a semiconductor device and / or a method of manufacturing the semiconductor device. Background Technology

[0004] Semiconductor devices are advantageous in the electronics industry due to their small size, versatility, and / or low manufacturing cost. Semiconductor devices can include semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and / or hybrid semiconductor devices having both memory and logic elements. As the electronics industry advances, semiconductor devices increasingly require high levels of integration. For example, there is a growing demand for semiconductor devices with high reliability, high speed, and / or versatility. Semiconductor devices are becoming increasingly complex and integrated to meet these requirements. Summary of the Invention

[0005] Some exemplary embodiments of the inventive concept provide a semiconductor device with improved electrical characteristics.

[0006] Some exemplary embodiments of the inventive concept provide a method for manufacturing a semiconductor device with improved electrical characteristics.

[0007] According to some example embodiments, a method of manufacturing a semiconductor device may include: forming a first dielectric layer on a substrate; forming a via in the first dielectric layer; sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an anti-reflective pattern on the first dielectric layer; and performing an annealing process to cause the first metal oxide pattern and the second metal pattern to react with each other to form a second metal oxide pattern. Forming the second metal oxide pattern includes forming the second metal oxide pattern through a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

[0008] According to some example embodiments, a semiconductor device may include: a substrate; a first metal pattern on the substrate; a second metal pattern on the first metal pattern; a pathway between the first metal pattern and the second metal pattern; a metal oxide pattern on the second metal pattern; and an anti-reflective pattern on the metal oxide pattern. The second metal pattern comprises aluminum (Al), the metal oxide pattern comprises titanium oxide, the anti-reflective pattern comprises titanium nitride, the pathway comprises a metal material different from the metal material of the second metal pattern, and the first metal pattern comprises a metal material different from the metal material of the second metal pattern and the metal material of the pathway.

[0009] According to some example embodiments, a semiconductor device may include: a substrate; a first dielectric layer on the substrate; a metal pattern on the first dielectric layer; a metal oxide pattern on the metal pattern; an anti-reflective pattern on the metal oxide pattern; a second dielectric layer on the first dielectric layer, the second dielectric layer covering the metal pattern, the metal oxide pattern, and the anti-reflective pattern; a first via penetrating the first dielectric layer and connected to the metal pattern; and a second via penetrating a portion of the second dielectric layer and connected to the metal pattern. The metal pattern includes aluminum (Al), the metal oxide pattern includes titanium oxide, the anti-reflective pattern includes titanium nitride, and the first and second vias include materials different from the material of the metal pattern. Attached Figure Description

[0010] Figure 1 A simplified cross-sectional view of a semiconductor device illustrating some example embodiments of the inventive concept is shown.

[0011] Figure 2 A simplified cross-sectional view of a semiconductor device illustrating some example embodiments of the inventive concept is shown.

[0012] Figures 3 to 12 A cross-sectional view is shown illustrating a method for manufacturing a semiconductor device according to some example embodiments of the inventive concept. Detailed Implementation

[0013] Some exemplary embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings to help to clearly explain the inventive concept.

[0014] Figure 1 A simplified cross-sectional view of a semiconductor device illustrating some example embodiments of the inventive concept is shown.

[0015] Reference Figure 1A semiconductor device according to some exemplary embodiments of the present invention may include a substrate 100, a lower dielectric layer 201, a first dielectric layer 301, a first metal pattern 310, a second dielectric layer 501, a first channel 520, a third dielectric layer 502, a second metal pattern 551, a metal oxide pattern 590, an anti-reflective pattern 571, a second channel 620, a first passivation layer 503, an upper dielectric layer 601, and a second passivation layer 603.

[0016] Substrate 100 may be or include a semiconductor substrate, such as a silicon substrate, germanium substrate, silicon-germanium substrate, and / or silicon-on-insulator (SOI) substrate. Transistor 200 may be formed on substrate 100, or on and within substrate 100. Transistor 200 may include a gate dielectric pattern 210, a gate electrode 220, and a gate cover pattern 230 stacked in sequence. Transistor 200 may also include gate spacers 240 located on opposite sidewalls of each of the gate dielectric pattern 210, gate electrode 220, and gate cover pattern 230. Transistor 200 may have impurity regions 100a and 100b on opposite sides thereof serving as source / drain regions. Multiple transistors 200 may be formed on substrate 100. Transistor 200 may be an N-type transistor or a P-type transistor.

[0017] The gate dielectric pattern 210 may include at least one of oxides, nitrides, oxide oxynitrides, or metal silicates. The gate electrode 220 may include a conductive material such as tungsten (W), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), and / or tantalum nitride (TaN). The gate overlay pattern 230 may include silicon oxide and / or silicon nitride. The gate spacer 240 may include silicon oxide and / or silicon nitride.

[0018] A lower dielectric layer 201 covering the transistor 200 may be disposed on the substrate 100. A lower contact 250 penetrating the lower dielectric layer 201 and connected to the substrate 100 may be disposed on the substrate 100. The lower dielectric layer 201 may include silicon oxide, for example, at least one of tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), and undoped silicate glass (USG). The lower contact 250 may include a conductive material such as copper (Cu).

[0019] Multiple first metal patterns 310 may be disposed on the lower dielectric layer 201. The lowermost first metal pattern of the first metal patterns 310 may be connected to the lower contact 250. The first metal patterns 310 may be spaced apart from each other in a direction perpendicular to the top surface of the substrate 100. Multiple upper contacts 320 may be disposed alternately with the first metal patterns 310. The first metal patterns 310 may be electrically connected to each other through the upper contacts 320. The first metal patterns 310 and the upper contacts 320 may comprise a conductive material such as copper (Cu). The number of layers of the first metal patterns 310 may be an integer, such as one, two, three, four, five, six, seven, eight, nine, ten, or more than ten. Similarly, the number of layers of the upper contacts 320 may be an integer, such as one, two, three, four, five, six, seven, eight, nine, ten, or more than ten. The number of layers of the upper contacts 320 may be one less than the number of layers of the first metal patterns 310; however, the exemplary embodiments are not limited thereto. The first metal pattern 310 and the upper contact 320 can be formed by a first-pass process or a second-pass process; however, the example embodiments are not limited thereto.

[0020] A first dielectric layer 301 covering the first metal pattern 310 and the upper contact 320 may be disposed on the lower dielectric layer 201. The first dielectric layer 301 may include silicon oxide as an intermetallic dielectric (IMD), such as at least one of tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), and undoped silicate glass (USG).

[0021] The second dielectric layer 501 may be disposed on the uppermost first metal pattern and the first dielectric layer 301 in the first metal pattern 310, and may cover the uppermost first metal pattern and the first dielectric layer 301 in the first metal pattern 310. The second dielectric layer 501 may include silicon oxide as an intermetallic dielectric (IMD), for example, at least one of tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), and undoped silicate glass (USG).

[0022] A plurality of first channels 520, penetrating the second dielectric layer 501 and electrically connected to the uppermost first metal pattern 310, may be formed on the uppermost first metal pattern 310. A first barrier layer 510 may be disposed between the side surfaces of the second dielectric layer 501 and the first channels 520, and extend between the uppermost first metal pattern 310 and the bottom surface of the first channels 520. The first barrier layer 510 may be formed to have a uniform thickness. The first channels 520 may include a material different from the material of the first metal pattern 310. For example, all or at least one material included in the first channels 520 may be different from any material included in the first metal pattern 310. The first channels 520 may include a conductive material such as tungsten (W). The first barrier layer 510 may include a conductive material or a conductive metal nitride. For example, the first barrier layer 510 may include tungsten nitride (WN) or tungsten carbonitride (WCN).

[0023] Multiple second metal patterns 551 may be disposed on the second dielectric layer 501. The second metal patterns 551 may be electrically connected to the first passage 520. The second metal patterns 551 may include materials different from the material of the first metal pattern 551. For example, all or at least one material included in the second metal pattern 551 may be different from any material included in the first metal pattern 310. The second metal pattern 551 may include materials different from the material of the first passage 520. The second metal pattern 551 may include a conductive material such as aluminum (Al). A metal oxide pattern 590 and an anti-reflective pattern 571 may be sequentially formed on the second metal pattern 551. The metal oxide pattern 590 may include a conductive metal oxide such as titanium dioxide (TiO2). The anti-reflective pattern 571 may include the same metal element as the metal element of the metal oxide pattern 590. The anti-reflective pattern 571 may include materials different from the material of the first barrier layer 510. For example, all or at least one material included in the anti-reflective pattern 571 may be different from any material included in the first barrier layer 510. The anti-reflective pattern 571 may include a conductive metal nitride such as titanium nitride (TiN). The metal oxide pattern 590 may be in contact / direct contact with the top surface of the second metal pattern 551, and the anti-reflective pattern 571 may be in contact / direct contact with the top surface of the metal oxide pattern 590. Since the metal oxide pattern 590 is formed on the second metal pattern 551, the possibility of nitrogen (N) diffusion into the second metal pattern 551 can be prevented or reduced; therefore, the second metal pattern 551 may have no nitrogen (N) concentration, or a minimal or reduced concentration of nitrogen (N). The presence of the metal oxide pattern 590 can reduce the resistance of the semiconductor device and can reduce (e.g., minimize) the thermal stress generated by the annealing process. Alternatively or additionally, the metal oxide pattern 590 can promote hydrogen diffusion into the semiconductor substrate, and thus the transistor can reduce its leakage current, and in particular, volatile and / or non-volatile semiconductor devices can have improved refresh characteristics; as a result, the semiconductor device can be provided with improved electrical characteristics.

[0024] A third dielectric layer 502 may be disposed on the second dielectric layer 501. The third dielectric layer 502 may cover the side surfaces of the second metal pattern 551, the side surfaces of the metal oxide pattern 590, and the side and top surfaces of the anti-reflective pattern 571. The third dielectric layer 502 may include silicon oxide as an intermetallic dielectric (IMD), such as at least one of tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), and undoped silicate glass (USG).

[0025] A first passivation layer 503 may be disposed on a third dielectric layer 502. The first passivation layer 503 may cover the third dielectric layer 502. The first passivation layer 503 may be formed to have a uniform thickness on the third dielectric layer 502. The first passivation layer 503 may include a material different from the material of the second dielectric layer 501 and the third dielectric layer 502. For example, there may be no common material between any of the first passivation layer 503, the second dielectric layer 501, or the third dielectric layer 502. The first passivation layer 503 may include one or more of silicon nitride, silicon carbonitride, silicon oxynitride, and silicon carbonitride. The first passivation layer 503 may include one or more of, for example, SiN, SiCN, SiON, and SiOCN.

[0026] The upper pad 650 may be disposed on the first passivation layer 503. A protective layer 655 may be disposed on the upper pad 650. The upper pad 650 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), or nickel (Ni). The protective layer 655 may include a conductive material, a conductive nitride, a conductive carbide, and / or a conductive carbonitride. For example, the protective layer 655 may include one or more of Ti, Ta, TaN, TiN, TiSiN, W, WN, WC, and WCN.

[0027] An upper dielectric layer 601 may be disposed on the first passivation layer 503. The upper dielectric layer 601 may cover the upper pad 650 and the protective layer 655. A second passivation layer 603 may be disposed on the upper dielectric layer 601. The second passivation layer 603 may cover the upper dielectric layer 601. The second passivation layer 603 may be formed to have a uniform thickness on the upper dielectric layer 601. The upper dielectric layer 601 may include silicon oxide as an intermetallic dielectric (IMD), such as at least one of tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), and undoped silicate glass (USG). The second passivation layer 603 may include one or more of silicon nitride, silicon carbonitride, silicon oxynitride, and silicon carbonitride. For example, the second passivation layer 603 may include one or more of SiN, SiCN, SiON, and SiOCN.

[0028] Multiple second channels 620 may be provided on some of the multiple anti-reflective patterns 571, penetrating a portion of the third dielectric layer 502, the first passivation layer 503, and a portion of the upper dielectric layer 601. The second channels 620 can electrically connect the upper pad 650 to the second metal pattern 551. A second barrier layer 610 may be configured between the side surface of the second channel 620 and a portion of the third dielectric layer 502, the first passivation layer 503, and the upper dielectric layer 601, while extending between the anti-reflective pattern 571 and the bottom surface of the second channel 620. The second channel 620 may include a material different from that of the second metal pattern 551. There may be no common material between the second channel 620 and the second metal pattern 551. The second channel 620 may include a conductive material such as tungsten (W).

[0029] The second barrier layer 610 may include a material different from that of the first barrier layer 510. For example, the second barrier layer 610 may not include any materials included in the material of the first barrier layer 510. The second barrier layer 610 may include the same material as the anti-reflective pattern 571. For example, the second barrier layer 610 may be the same material as the anti-reflective pattern 571. The second barrier layer 610 may include a conductive material or a conductive metal nitride. For example, the second barrier layer 610 may include titanium nitride (TiN).

[0030] The upper pad 650, the protective layer 655, the upper dielectric layer 601, and the second passivation layer 603 may be partially removed to form a first recess 605, with a portion of the upper pad 650 exposed to the first recess 605.

[0031] According to some exemplary embodiments of the inventive concept, and Figure 1 The difference shown may not include the upper pad 650. For example, a redistribution line may be provided instead.

[0032] Figure 2 A simplified cross-sectional view of a semiconductor device illustrating some example embodiments according to the inventive concept is shown. For the sake of brevity, the following will primarily explain and refer to... Figure 1 The differences between the semiconductor devices discussed.

[0033] Reference Figure 2An intermediate dielectric layer 401 may be located between a first dielectric layer 301 and a second dielectric layer 501. A plurality of intermediate pathways 420 penetrating the intermediate dielectric layer 401 may be provided on the uppermost first metal pattern 310. The intermediate pathways 420 may be electrically connected to the first metal pattern 310. An intermediate barrier layer 410 may be located between the side surfaces of the intermediate dielectric layer 401 and the intermediate pathways 420, and extend between the uppermost first metal pattern 310 and the bottom surface of the intermediate pathways 420. The intermediate barrier layer 410 may be formed to have a uniform thickness within the intermediate dielectric layer 401. The intermediate pathways 420 may include a conductive material such as tungsten (W). The intermediate barrier layer 410 may include a conductive material and / or a conductive metal nitride. For example, the intermediate barrier layer 410 may include tungsten nitride (WN) and / or tungsten carbonitride (WCN).

[0034] A lower metal pattern 451 may be disposed on an intermediate dielectric layer 401. The lower metal pattern 451 may be disposed between an intermediate passage 420 and a first passage 520. The lower metal pattern 451 may be electrically connected to the intermediate passage 420 and the first passage 520. The lower metal pattern 451 may include a conductive material such as aluminum (Al). A lower metal oxide pattern 490 and a lower anti-reflective pattern 471 may be sequentially formed on the lower metal pattern 451. The lower metal oxide pattern 490 may include a conductive metal oxide such as titanium oxide (TiO2). The lower anti-reflective pattern 471 may include at least one of the same metal elements as the lower metal oxide pattern 490. The lower anti-reflective pattern 471 may include a conductive metal nitride such as titanium nitride (TiN). The lower metal oxide pattern 490 may be in contact / direct contact with the top surface of the lower metal pattern 451, and the lower anti-reflective pattern 471 may be in contact / direct contact with the top surface of the lower metal oxide pattern 490.

[0035] Since the lower metal oxide pattern 490 is formed on the lower metal pattern 451, the possibility of nitrogen (N) diffusion into the lower metal pattern 451 can be prevented or reduced. Therefore, the lower metal pattern 451 may have no nitrogen (N) concentration, or a minimum or reduced nitrogen (N) concentration. The presence of the lower metal oxide pattern 490 can reduce the resistance of the semiconductor device and can reduce or minimize the thermal stress generated by the annealing process. Alternatively or additionally, the lower metal oxide pattern 490 can promote hydrogen diffusion into the semiconductor substrate, and thus the transistor can reduce its leakage current. In particular, volatile and / or non-volatile semiconductor devices can have improved refresh characteristics, resulting in improved electrical characteristics for the semiconductor device.

[0036] The second dielectric layer 501 may cover a portion of the side surface of the lower metal pattern 451, the side surface of the lower metal oxide pattern 490, the side surface of the lower anti-reflective pattern 471, and the top surface below the lower anti-reflective pattern 471.

[0037] The semiconductor device according to some example embodiments can be compared with reference to... Figure 1 The semiconductor devices discussed are essentially the same, except that they may further include other elements besides or alternatives to the intermediate dielectric layer 401, intermediate via 420, intermediate barrier layer 410, lower metal pattern 451, lower metal oxide pattern 490, and lower anti-reflective pattern 471.

[0038] Figures 3 to 12 A cross-sectional view is shown illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept. For the sake of brevity, only a portion will be shown. Figure 1 Semiconductor devices.

[0039] Reference Figure 1 A transistor 200 can be formed on the substrate 100. A lower dielectric layer 201 can be formed on the substrate 100 to cover the transistor 200. A lower contact 250 can be formed on the substrate 100 to penetrate the lower dielectric layer 201 and connect to the substrate 100. A plurality of first metal patterns 310 can be formed on the lower dielectric layer 201 to connect to the lower contact 250. A plurality of upper contacts 320 can be formed between and connected to the first metal patterns 310. A first dielectric layer 301 can be formed on the lower dielectric layer 201 to cover the first metal patterns 310 and the upper contacts 320.

[0040] Reference Figure 1 and Figure 3A second dielectric layer 501 can be formed on a first dielectric layer 301, and a first barrier layer 510 and a first via 520 can be formed in the second dielectric layer 501. The formation of the first barrier layer 510 and the first via 520 may include partially removing the second dielectric layer 501 to form a via penetrating the second dielectric layer 501, and then locally forming the first barrier layer 510 and the first via 520 in the via. The via penetrating the second dielectric layer 501 can be formed by at least one of dry etching, wet etching, laser drilling, or mechanical drilling. The first barrier layer 510 can be formed to fill a portion of the via and has a uniform thickness within the via. The first barrier layer 510 can be formed by at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes. The first via 520 can be formed to fill the remaining portion of the via. The first via 520 can be formed by at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes.

[0041] A second metal layer 550 may be formed on the second dielectric layer 501. The second metal layer 550 may include a conductive material such as aluminum (Al). The second metal layer 550 may be formed by at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes.

[0042] Reference Figure 4 A second metal oxide layer 555 can be formed on the second metal layer 550. The second metal oxide layer 555 can be formed to have a uniform thickness. The second metal oxide layer 555 may include, for example, aluminum oxide (Al₂O₃). x The conductive metal oxide layer 555 is formed by at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes.

[0043] Reference Figure 5 A third metal layer 560 can be formed on the second metal oxide layer 555. The third metal layer 560 can be formed to have a uniform thickness. The third metal layer 560 may include a conductive material such as titanium (Ti). The third metal layer 560 can be formed by at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0044] Reference Figure 6An antireflective layer 570 can be formed on the third metal layer 560. The antireflective layer 570 can be formed to have a uniform thickness. The antireflective layer 570 may include the same metal element as the third metal layer 560. The antireflective layer 570 may include a conductive metal nitride such as titanium nitride (TiN). The antireflective layer 570 can be formed by at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes.

[0045] Reference Figure 7 and Figure 8 A photoresist layer 580 can be formed on the anti-reflective layer 570. Exposure and development processes can be performed by irradiating the photoresist layer 580 with light 582, such as ultraviolet light, using a mask 581. The photoresist layer 580 can then be formed into a photoresist pattern 583 to define the area where the pattern will be formed. The photoresist pattern 583 can be used as an etching mask to pattern the second metal layer 550, the second metal oxide layer 555, the third metal layer 560, and the anti-reflective layer 570. When irradiated with light 582, the anti-reflective layer 570 can protect the second metal layer 550 and / or help avoid standing waves within the photoresist layer 580.

[0046] Reference Figure 9 An etching process, such as a dry etching process and / or a wet etching process, can be performed, in which a second metal layer 550, a second metal oxide layer 555, a third metal layer 560, and an anti-reflective layer 570 are etched to form a second metal pattern 551, a second metal oxide pattern 556, a third metal pattern 561, and an anti-reflective pattern 571. After the etching process, the photoresist pattern 583 can be removed by an ashing and / or stripping process. The anti-reflective pattern 571 may include the same metal elements as the third metal pattern 561. The second metal pattern 551 may include a material different from the material of the third metal pattern 561 (e.g., a metal different from the metal of the third metal pattern 561). The first passage 520 may include a material different from the materials of the second metal pattern 551 and the third metal pattern 561.

[0047] Reference Figure 10A third dielectric layer 502 can be formed on the second dielectric layer 501. The third dielectric layer 502 can cover the side surfaces of the second metal pattern 551, the second metal oxide pattern 556, the side surfaces of the second metal pattern 551, and the side and top surfaces of the anti-reflective pattern 571. A first passivation layer 503 can be formed on the third dielectric layer 502. The first passivation layer 503 can be formed to have a uniform thickness. The third dielectric layer 502 and the first passivation layer 503 can be formed by at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes.

[0048] Reference Figure 11 An annealing process can be performed in which the second metal oxide pattern 556 and the third metal pattern 561 react with each other to form a metal oxide pattern 590. For example, the metal element (e.g., Ti) of the third metal pattern 561 and the oxygen element of the second metal oxide pattern 556 can react with each other to form the metal oxide pattern 590. The metal oxide pattern 590 may include a conductive metal oxide such as titanium oxide (TiO2). The annealing process can be performed at approximately 300°C to approximately 500°C and can be performed by a rapid thermal annealing (RTA) process and / or by a furnace process; however, the example embodiments are not limited thereto.

[0049] Since the metal oxide pattern 590 is formed through the annealing process, the possibility of nitrogen (N) diffusion into the second metal pattern 551 can be prevented or reduced. Therefore, the second metal pattern 551 may have no nitrogen (N) concentration, a minimal nitrogen (N) concentration, or a reduced nitrogen (N) concentration. Thus, the resistance of the semiconductor device can be reduced, and the thermal stress generated by the annealing process can be reduced or minimized. Alternatively or additionally, the metal oxide pattern 590 can promote hydrogen diffusion into the semiconductor substrate, and therefore the transistor can have reduced leakage current. In particular, volatile and non-volatile semiconductor devices can have improved refresh characteristics, resulting in improved electrical characteristics for the semiconductor device.

[0050] Reference Figure 12 The first passivation layer 503, the third dielectric layer 502, and the anti-reflective pattern 571 can be partially removed to form a second recess 505 that exposes a portion of the anti-reflective pattern 571.

[0051] Methods for manufacturing semiconductor devices according to some exemplary embodiments of the present invention can be compared with those described in reference. Figure 1 The methods used in the discussion are basically the same.

[0052] Semiconductor devices according to some exemplary embodiments of the inventive concept may include a metal oxide layer formed by annealing a metal layer and a metal nitride layer sequentially stacked on aluminum wires. Therefore, the resistance of the semiconductor device can be reduced, and the thermal stress generated by the annealing process can be reduced or minimized. Alternatively or additionally, the metal oxide layer can promote hydrogen diffusion into the semiconductor substrate, and thus the transistor can reduce its leakage current, and in particular, volatile and non-volatile semiconductor devices can have improved refresh characteristics; as a result, the semiconductor device can be provided with improved electrical characteristics.

[0053] Although the inventive concept has been described in conjunction with some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and essential characteristics of the inventive concept. Therefore, the exemplary embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: forming a first dielectric layer on a substrate; forming a via in the first dielectric layer; sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an anti-reflection pattern on the first dielectric layer; and performing an annealing process to cause the first metal oxide pattern and the second metal pattern to react with each other to form a second metal oxide pattern, wherein forming the second metal oxide pattern comprises forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

2. The method of claim 1, wherein, sequentially forming the first metal pattern, the first metal oxide pattern, the second metal pattern, and the anti-reflection pattern on the first dielectric layer comprises: forming a first metal layer on the first dielectric layer; forming a first metal oxide layer on the first metal layer; sequentially forming a second metal layer and an anti-reflection layer on the first metal oxide layer; and etching the first metal layer, the first metal oxide layer, the second metal layer, and the anti-reflection layer.

3. The method of claim 1, wherein, the via comprises a material different from a material of the first metal pattern, a material of the second metal pattern, or a material of the first metal pattern and a material of the second metal pattern.

4. The method of claim 1, wherein, the first metal pattern and the second metal pattern comprise materials different from each other.

5. The method of claim 1, wherein, the first metal pattern comprises aluminum, and the second metal pattern comprises titanium.

6. The method of claim 1, wherein, the anti-reflection pattern comprises a conductive metal nitride, and the anti-reflection pattern comprises a same metal element as a metal element of the second metal pattern.

7. The method of claim 1, the method further comprising: before performing the annealing process, forming a second dielectric layer on the anti-reflection pattern, the second dielectric layer covering a side surface of the first metal pattern, a side surface of the first metal oxide pattern, a side surface of the second metal pattern, and a side surface of the anti-reflection pattern; and forming a passivation layer on the second dielectric layer, the passivation layer covering the second dielectric layer, wherein the passivation layer comprises a material different from a material of the first dielectric layer and a material of the second dielectric layer. forming the via in the first dielectric layer comprises:

8. The method of claim 1, wherein, removing a portion of the first dielectric layer to form a through-hole; forming a barrier layer filling a portion of the through-hole; and forming the via filling a remaining portion of the through-hole. the barrier layer comprises a material different from a material of the anti-reflection pattern.

9. The method of claim 8, wherein, the annealing process is performed at 300°C to 500°C.

10. The method of claim 1, wherein, 11. A semiconductor device, the semiconductor device comprising: a substrate; a first metal pattern on the substrate; a second metal pattern on the first metal pattern; a via between the first metal pattern and the second metal pattern; a metal oxide pattern on the second metal pattern; and a passivation layer on the second dielectric layer. ​ an anti-reflective pattern on the metal oxide pattern, wherein the second metal pattern includes aluminum, the metal oxide pattern includes titanium oxide, the anti-reflective pattern includes titanium nitride, the via includes a metal material different from a metal material of the second metal pattern, and the first metal pattern includes a metal material different from a metal material of the second metal pattern and a metal material of the via.

12. The semiconductor device of claim 11, wherein the via includes tungsten, and the first metal pattern includes copper.

13. The semiconductor device of claim 11, further comprising: a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a third dielectric layer on the second dielectric layer, the third dielectric layer covering the second metal pattern, the metal oxide pattern, and the anti-reflective pattern; and a passivation layer on the third dielectric layer, wherein the first dielectric layer covers the first metal pattern, and the via penetrates the second dielectric layer.

14. The semiconductor device of claim 13, further comprising: a barrier layer between the second dielectric layer and a side surface of the via, the barrier layer extending between the first metal pattern and a bottom surface of the via, wherein the barrier layer includes a metal nitride, and the barrier layer includes a material different from a material of the anti-reflective pattern.

15. The semiconductor device of claim 14, further comprising: a lower dielectric layer between the first dielectric layer and the second dielectric layer; a lower metal pattern on the lower dielectric layer; and a lower via penetrating the lower dielectric layer and connected to the first metal pattern and the lower metal pattern.

16. The semiconductor device of claim 15, further comprising: a lower metal oxide pattern on the lower metal pattern; and a lower anti-reflective pattern on the lower metal oxide pattern. the lower metal oxide pattern includes a same metal element as a metal element of the lower anti-reflective pattern.

18. A semiconductor device, comprising: a substrate; 17. The semiconductor device according to claim 16, wherein a first dielectric layer on the substrate; a metal pattern on the first dielectric layer; a metal oxide pattern on the metal pattern; an anti-reflective pattern on the metal oxide pattern; a second dielectric layer on the first dielectric layer, the second dielectric layer covering the metal pattern, the metal oxide pattern, and the anti-reflective pattern; a first via penetrating the first dielectric layer and connected to the metal pattern; and a second via penetrating a portion of the second dielectric layer and connected to the metal pattern, wherein the metal pattern includes aluminum, the metal oxide pattern includes titanium oxide, the anti-reflective pattern includes titanium nitride, and the first via and the second via include a material different from a material of the metal pattern. ​ ​ ​ ​ 19. The semiconductor device of claim 18, further comprising: a first barrier layer between the first dielectric layer and a side surface of the first via, the first barrier layer extending between a bottom surface of the first via and a bottom surface of the first dielectric layer; and a second barrier layer between the second dielectric layer and a side surface of the second via, the second barrier layer extending between the antireflection pattern and a bottom surface of the second via, wherein the first barrier layer and the second barrier layer comprise a conductive metal nitride, and the first barrier layer and the second barrier layer comprise different materials from each other. the antireflection pattern and the second barrier layer comprise the same material from each other.

20. The semiconductor device according to claim 19, wherein ​

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