Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. Embodiments include a method that includes: forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device; conformally depositing a first dielectric layer in the opening; conformally depositing a silicon layer over the first dielectric layer; performing an oxidation process on the silicon layer to form a first silicon oxide layer; filling the opening with a second silicon oxide layer; performing chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device; and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

Description

Field of the Technology

[0001] The present disclosure relates to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in various electronic applications such as personal computers, cellular telephones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials over a semiconductor substrate and using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry has continuously improved the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise that should be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, including: forming an opening in a cut metal gate region of a metal gate structure of the semiconductor device; conformally depositing a first dielectric layer in the opening; conformally depositing a silicon layer over the first dielectric layer; performing an oxidation process on the silicon layer to form a first silicon oxide layer; filling the opening with a second silicon oxide layer; and performing chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, including: forming a first semiconductor fin and a second semiconductor fin over a substrate, the second semiconductor fin being adjacent to the first semiconductor fin; forming an isolation region surrounding a lower portion of the first semiconductor fin and the second semiconductor fin; forming a dummy gate structure over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin and along a top surface of the isolation region; replacing the dummy gate structure with an active gate structure; etching a first opening through the active gate structure, the first opening being between the first semiconductor fin and the second semiconductor fin, etching the first opening through the active gate structure including: forming a first mask layer over the active gate structure; patterning the first mask layer to form a second opening that passes through the first mask layer over the active gate structure; conformally forming a second mask layer over the patterned first mask layer, the second mask layer being on sidewalls and a bottom of the second opening that passes through the first mask layer; removing the second mask layer from a bottom of the second opening; using the first mask layer and the second mask layer as a mask to etch a first portion of the first opening, the first portion of the first opening having a first depth; using the first mask layer as a mask to etch a second portion of the first opening, the second portion of the first opening having a second depth, the second depth being less than the first depth; forming a barrier layer in the first opening and over the active gate structure; forming an oxygen barrier layer over the barrier layer in the first opening and over the active gate structure; performing an oxidation process on the oxygen barrier layer, the oxidation process forming a first oxide layer; and forming a dielectric layer over the first oxide layer to fill the first opening.

[0006] According to yet another embodiment of the present disclosure, a semiconductor device is provided, including: a semiconductor fin extending from a substrate; an isolation region surrounding a lower portion of the semiconductor fin; a metal gate structure over the semiconductor fin and the isolation region, the metal gate structure being disposed in an interlayer dielectric layer; and an isolation structure disposed in the metal gate structure, the isolation structure dividing the metal gate structure into two different portions, the isolation structure including: a conformal silicon nitride layer extending along sidewalls of the two different portions of the metal gate structure; a conformal silicon layer over the conformal silicon nitride layer; and a silicon oxide layer over the conformal silicon layer. Description of the Drawings

[0007] Aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figures 1A to 5C Shows an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0009] Figures 6A to 16C Shows an intermediate stage in the fabrication of a FinFET with a cut metal gate according to some embodiments.

[0010] Figures 17A to 19C Shows an intermediate stage in the fabrication of a FinFET with a cut metal gate according to some other embodiments.

[0011] Figure 20 Shows a semiconductor device after an additional stage in the fabrication of a FinFET with a cut metal gate according to some embodiments.

[0012] Figures 21A to 22C Shows an intermediate stage in the fabrication of a FinFET with a cut metal gate according to some other embodiments. Detailed Description

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on top of a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] In addition, spatially relative terms (such as, "below", "beneath", "lower", "above", "upper", etc.) may be used herein to facilitate describing one element or feature's relationship to another (one or more) element or (one or more) feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] This disclosure relates to semiconductor devices and methods of manufacturing the same. Certain embodiments relate to a semiconductor device including a fin field-effect transistor (FinFET) having a cut metal gate (CMG) and a method of manufacturing the semiconductor device. Embodiments disclosed herein relate to forming a plurality of FinFETs within a wafer.

[0016] The embodiments discussed herein may be discussed in a particular context, namely, a CMG isolation structure formed in a cut metal gate (CMG) trench, which improves the resistance-capacitance delay of the device and does not reduce the threshold voltage of the device. In some embodiments, the CMG isolation structure includes a plurality of layers having a silicon nitride layer, a silicon layer, and a silicon oxide layer. In some embodiments, the silicon nitride layer serves as a barrier layer to prevent the diffusion of materials of the gate stack into the CMG trench during subsequent processing. In some embodiments, the silicon layer serves as a barrier against oxidation of the underlying barrier layer and the gate stack. Since the silicon layer protects the underlying layers from oxidation, a silicon oxide layer may be formed on the silicon layer, which reduces the dielectric constant of the CMG isolation structure. In addition, by protecting the underlying layers (e.g., the gate stack) from oxidation, the threshold voltage of the device can be maintained while using the CMG method.

[0017] Figures 1A to 5C An intermediate stage in the manufacture of a FinFET according to some embodiments is shown. Figure 1A 、 Figure 2A 、 Figure 3A 、 Figure 4A and Figure 5A are three-dimensional views. Figure 1B 、 Figure 2B 、 Figure 3B 、 Figure 4B and Figure 5B are cross-sectional views taken along the longitudinal axis of the FinFET, e.g., perpendicular to the direction of current flow between the source / drain regions of the FinFET, and are shown for a single FinFET. Figure 1C 、 Figure 2C 、 Figure 3C 、 Figure 4C and Figure 5C are cross-sectional views taken along the transverse axis of the FinFET, e.g., parallel to the direction of current flow between the source / drain regions of the FinFET, and are shown for a single FinFET. Figure 2D is a cross-sectional view taken along the longitudinal axis of the FinFET, the cross-section passing through the source / drain regions of the FinFET.

[0018] Some embodiments discussed herein are discussed in the context of FinFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Additionally, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs).

[0019] In Figures 1A to 1C , a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a strained SOI substrate, a silicon-germanium-on-insulator substrate, etc., which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Other substrates may also be used, such as multi-layer or gradient substrates. An area of the substrate 50 is shown, which may be used to form an n-type device (e.g., an NMOS transistor, such as an n-type FinFET) or to form a p-type device (e.g., a PMOS transistor, such as a p-type FinFET). The substrate 50 may include multiple physically separated areas in which any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be formed.

[0020] Additionally, fins 52 are formed extending from the substrate 50. The fins 52 are semiconductor strips. In the illustrated embodiment, the fins 52 are epitaxially grown semiconductor material that is different from the material of the substrate 50. The fins 52 may be formed of silicon, silicon-germanium (Si x Ge 1-x , where x may range from 0 to 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, etc. For example, available materials for forming group III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc. In the illustrated embodiment, the fins 52 are formed by epitaxially growing a layer of semiconductor material on the substrate 50 and then etching trenches 54 in the semiconductor material, where the fins 52 are formed of the portions of the semiconductor material that remain unremoved. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination of the foregoing. The etching may be anisotropic. In other embodiments, the fins 52 are the same material as the substrate 50 and are formed by etching trenches in the substrate 50. As described below, the fins 52 are used to form the channel regions of the FinFETs. Although only two fins 52 are shown, it should be understood that any number of fins 52 may be formed.

[0021] The fin 52 can be patterned by any suitable method. For example, one or more lithography processes including double patterning or multi-patterning processes can be used to pattern the fin 52. Generally, double patterning or multi-patterning processes combine lithography processes and self-alignment processes, thus allowing the creation of patterns with pitches, for example, smaller than those obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then the remaining spacer can be used to pattern the fin.

[0022] As will be recognized by those of ordinary skill in the art, the above processes and materials for forming the fin 52 are merely example processes and are not meant to be the only embodiments. Instead, any suitable process capable of forming the fin 52 can be utilized, and any suitable process including any number of masking and removal steps can be used. Once formed, these fins 52 can be used to form the channel regions and source / drain (S / D) regions of multiple FinFET transistors as described below.

[0023] Fins 52 having a width of W1 are formed at the surface of the substrate 50. In some embodiments, the width W1 ranges between about 6 nm and about 600 nm. Additionally, the fins 52 are spaced apart from each other by a distance D1. By spacing the fins 52 in this manner, the fins 52 can each form separate channel regions while still being close enough to share a common gate. As discussed further below, the distance D1 is selected in a manner that helps to reduce the contact resistance (R c ) of the contacts to the gate of the subsequently formed FinFET. In some embodiments, the distance D1 is larger, for example, in the range of about 22 nm to about 800 nm. In some embodiments, the distance D1 is smaller, for example, in the range of about 22 nm to about 200 nm.

[0024] Furthermore, shallow trench isolation (STI) regions 56 are formed between the fins 52. The STI regions 56 can be formed by filling the trenches 54 with a dielectric material and recessing the dielectric material in the trenches 54 to form the STI regions 56. The dielectric material can be an oxide material, a high density plasma (HDP) oxide, etc. After optional cleaning and liner deposition of the trenches 54, the dielectric material can be formed using chemical vapor deposition (CVD) methods, high density plasma CVD methods, or other suitable formation methods known in the art.

[0025] The trench 54 can be filled in the following manner: overfill the trench 54 and the substrate 50 with a dielectric material, and then remove the excess material outside the trench 54 and the fin 52 by a suitable process (e.g., chemical mechanical polishing (CMP), etching, a combination of the foregoing, etc.). In an embodiment, the removal process removes the dielectric material covering the fin 52 such that the top surface of the fin 52 is exposed.

[0026] Once the trench 54 has been filled with the dielectric material, the dielectric material can then be recessed from the top surface of the fin 52. The recessing can be performed to expose at least a portion of the sidewall of the fin 52 adjacent to the top surface of the fin 52. The dielectric material can be recessed by wet etching by immersing the top surface of the fin 52 in an etchant (e.g., HF), although other etchants (e.g., H2) and other methods (e.g., reactive ion etching, dry etching using an etchant such as NH3 / NF3, chemical oxide removal, or dry chemical cleaning) can be used. The dielectric material is recessed such that the exposed portion of the fin 52 has a first height H1. In some embodiments, the first height H1 is in the range of about to about . Additionally, the recessing can also remove any remaining dielectric material located on top of the fin 52, exposing the fin 52 for further processing.

[0027] The above steps can be only a part of the entire process flow for filling and recessing the dielectric material. For example, a liner step, a cleaning step, an annealing step, a gap filling step, a combination of the foregoing, etc. can also be used to form the trench and fill the trench with the dielectric material. All possible process steps are fully intended to be included within the scope of the embodiments of the present disclosure.

[0028] In Figures 2A to 2C , a dummy gate dielectric 58 and a dummy gate electrode 60 are formed over each fin 52. In some embodiments, the dummy gate dielectric layer is formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art and used for forming a dielectric layer. Depending on the technology for forming the gate dielectric, the thickness of the dummy gate dielectric layer on top of the fin 52 can be different from the thickness of the dummy gate dielectric layer on the sidewall of the fin 52.

[0029] The dummy gate dielectric layer can include a thickness in the range of about to about (e.g., about ) materials such as silicon dioxide or silicon oxynitride. The dummy gate dielectric layer can be formed of a high dielectric constant (high-k) material (e.g., relative dielectric constant greater than about 5), such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), or zirconium oxide (ZrO2), or a combination of the foregoing, where the equivalent oxide thickness is between about and about , for example about or less. In addition, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials can also be used for the dummy gate dielectric layer.

[0030] Then, the dummy gate electrode layer is formed on the dummy gate dielectric layer. The dummy gate electrode layer can be formed of a conductive material such as polysilicon (e.g., dummy polysilicon (DPO), poly-silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, metal, etc.), including, for example, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of the foregoing, etc. The dummy gate electrode layer can be formed by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, etc.). The thickness of the dummy gate electrode layer can be between about and about . The top surface of the dummy gate electrode layer can have a non-planar top surface and can be planarized before patterning the dummy gate electrode layer or performing a gate etching process. At this time, ions can be introduced into the dummy gate electrode layer or not. For example, ions can be introduced by ion implantation technology.

[0031] Then, for example, by acceptable lithography and etching processes, the dummy gate electrode layer and the dummy gate dielectric layer are patterned with the remaining portions of the dummy gate dielectric layer and the dummy gate electrode layer, respectively, to form a dummy gate dielectric 58 and a dummy gate electrode 60 (collectively referred to as the "dummy gate"). The dummy gate defines a plurality of channel regions on each side of the fin 52 located under the dummy gate dielectric layer. The dummy gate can be formed by depositing and patterning a gate mask on the dummy gate electrode layer using, for example, any suitable deposition and lithography techniques. The gate mask can include any suitable mask and sacrificial material, such as (but not limited to) silicon dioxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, and can be deposited to a thickness between about and about . A dry etching process can be used to etch the dummy gate electrode layer and the dummy gate dielectric layer to form the patterned dummy gate.

[0032] In addition, gate spacers 62 are formed on opposite sides of dummy gate electrodes 60 and over each of the fins 52. In some embodiments, the gate spacers 62 are formed, for example, by blanket depositing a spacer layer on a previously formed structure. The spacer layer may include SiCON, SiN, nitrogen oxides, SiC, SiON, SiOC, oxides, etc., and may be formed by any suitable method (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, and any other suitable method) to form such a layer. The spacer layer may include different materials or the same material having different etching characteristics from the dielectric material within the STI region 56. The spacer layer is then patterned, for example, by one or more etches to remove the horizontal portions of the spacer layer, while the remaining vertical portions of the spacer layer form the gate spacers 62.

[0033] In some embodiments, once the gate spacers 62 have been formed, portions of the fins 52 that are not protected by the dummy gates and gate spacers 62 may be removed using reactive ion etching (RIE) or by using any other suitable removal process, where the RIE uses the dummy gates and gate spacers 62 as a hard mask. The removal process may continue until the fins 52 are coplanar with the surface of the STI region 56 or below the surface of the STI region 56.

[0034] Epitaxial source / drain regions 64 are formed in the fins 52 such that each dummy gate electrode 60 is laterally disposed between a corresponding adjacent pair of epitaxial source / drain regions 64. The epitaxial source / drain regions 64 apply stress in the region that will become the channel region of the resulting FinFET, thereby improving performance. The gate spacers 62 separate the epitaxial source / drain regions 64 from the dummy gate electrodes 60 by an appropriate lateral distance such that the epitaxial source / drain regions 64 do not short circuit the subsequently formed gates of the resulting FinFET. The epitaxial source / drain regions 64 are formed by etching recesses in the fins 52. The epitaxial source / drain regions 64 in the recesses are then epitaxially grown. The epitaxial source / drain regions 64 may include any acceptable material, such as materials suitable for n-type or p-type FinFETs. For example, when forming an n-type FinFET, the epitaxial source / drain regions 64 may include materials that apply tensile stress in the channel region of the fins 52, such as silicon, SiC, SiCP, SiP, etc. Similarly, when forming a p-type FinFET, the epitaxial source / drain regions 64 may include materials that apply compressive stress in the channel region of the fins 52, such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain regions 64 may have a surface that protrudes from the corresponding surface of the fins 52 and may have facets.

[0035] In an embodiment where fin 52 comprises silicon and the FinFET is a p-type device, a material having a lattice constant different from that of the channel region (e.g., silicon, silicon germanium, silicon phosphorus) can be used to regrow source / drain regions 64. The epitaxial growth process can use precursors such as silane, dichlorosilane, germane, etc., and can last for about 5 minutes to about 120 minutes, such as about 30 minutes. In other embodiments, source / drain regions 64 can include materials such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, combinations of the foregoing, etc.

[0036] In some embodiments, once source / drain regions 64 are formed, dopants can be implanted into source / drain regions 64 by implanting suitable dopants to supplement the dopants in fin 52. For example, p-type dopants such as boron, gallium, indium, etc. can be implanted to form a PMOS device. Alternatively, n-type dopants such as phosphorus, arsenic, antimony, etc. can be implanted to form an NMOS device. The dummy gate and gate spacer 62 can be used as a mask to implant these dopants. However, any other suitable process, step, etc. can be used to implant dopants. For example, various combinations of spacers and liners can be used to perform multiple implantation processes to form source / drain regions having a specific shape or characteristics suitable for a particular purpose. Any of these processes can be used to implant dopants, and the above description is not meant to limit the embodiments of the present disclosure to the steps presented above.

[0037] Due to the epitaxial process used to form epitaxial source / drain regions 64, the upper surface of epitaxial source / drain regions 64 has facets that laterally extend outward beyond the sidewalls of fin 52. In Figures 2A to 2C the illustrated embodiment, after the epitaxial process is completed, adjacent epitaxial source / drain regions 64 remain separated. In other embodiments, for example Figure 2D as shown, these facets cause adjacent epitaxial source / drain regions 64 of the same FinFET to merge.

[0038] In Figures 3A to 3C , an interlayer dielectric (ILD) 66 (e.g., ILD0 layer) is deposited over substrate 50. ILD 66 can be formed of a dielectric material and can be deposited by any suitable method (e.g., CVD, PECVD, or flowable CVD (FCVD)). The dielectric material can include silicon oxide (SiO2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicon glass (USG), etc. Other insulating materials formed by any acceptable process can be used.

[0039] In some embodiments, a contact etch stop layer is disposed between the ILD 66 and the epitaxial source / drain regions 64, the gate spacers 62, and the dummy gate electrode 60. The contact etch stop layer may include a dielectric material having an etch rate different from that of the material of the ILD 66, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and may be deposited in a deposition chamber using, for example, one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD) processes, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc. However, any suitable material and any suitable process may be utilized to deposit the contact etch stop layer.

[0040] In some embodiments, once the ILD 66 is formed, the ILD 66 may be annealed using, for example, a first annealing process. In one embodiment, the first annealing process may be a thermal annealing, where the substrate 50 and the ILD 66 are heated in an inert atmosphere, such as in a furnace. The first annealing process may be performed at a temperature between about 200 °C and about 1000 °C (e.g., about 500 °C), and may last for a time between about 60 seconds and about 360 minutes, such as about 240 minutes.

[0041] In some embodiments, a planarization process such as CMP is performed to make the top surface of the ILD 66 flush with the top surfaces of the dummy gate electrode 60 and the gate spacers 62.

[0042] In Figures 4A to 4C , the dummy gate electrode 60 and the dummy gate dielectric 58 are removed in one or more etching steps (e.g., a wet etching process), thereby forming a groove 68. Each groove 68 exposes the channel region of a corresponding fin 52. Each channel region is laterally disposed between a pair of adjacent epitaxial source / drain regions 64. During the removal, the dummy gate dielectric 58 may be used as an etch stop layer when etching the dummy gate electrode 60. Then, after removing the dummy gate electrode 60, the dummy gate dielectric 58 may be optionally removed.

[0043] In Figures 5A to 5C , a gate dielectric 70 and a gate electrode 72 are formed for the replacement gate. The replacement gate may include, for example, a gate dielectric, one or more conduction barrier layers, one or more work function layers, and a conductive fill material. The gate dielectric 70 is conformally deposited in the groove 68, such as on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate spacers 62. The gate dielectric 70 may also be formed on the top surface of the ILD 66. According to some embodiments, the gate dielectric 70 includes silicon oxide, silicon nitride, or a multi-layer of the foregoing.

[0044] In some embodiments, the gate dielectric 70 includes a high-k dielectric material, and in these embodiments, the gate dielectric 70 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations of the foregoing. According to some embodiments, the high-k gate dielectric includes materials such as HfO2, ZrO2, HfZrOx, HfSiO x , HfSiON, ZrSiO x , HfZrSiO x , Al2O3, HfAlO x , HfAlN, ZrAlO x , La2O3, TiO2, Yb2O3, etc., and may be a single layer or a composite layer formed using a deposition process such as atomic layer deposition. However, any suitable material and any suitable process may be used to form the high-k gate dielectric.

[0045] The method of forming the gate dielectric 70 may include molecular beam deposition (MBD), atomic layer deposition, PECVD, etc. In embodiments where portions of the dummy gate dielectric 58 remain in the grooves 68, the gate dielectric 70 includes the material of the dummy gate dielectric 58 (e.g., SiO2).

[0046] The gate electrodes 72 are respectively deposited over the gate dielectric 70 and fill the remaining portions of the grooves 68. The gate electrodes 72 may include a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations of the foregoing, or multilayers of the foregoing. The gate electrodes 72 may be formed by a deposition process (e.g., atomic layer deposition (ALD)). The gate electrodes 72 may include any number of liner layers, work function adjustment layers, and fill materials.

[0047] According to some embodiments, one or more diffusion barrier layers and one or more work function adjustment layers may be formed as multiple stacked layers. For example, the barrier layer may be formed as a titanium nitride (TiN) layer, which may (or may not) be doped with silicon. In the case of a p-type FinFET, the work function adjustment layer may be formed with the corresponding gate electrode 72 as a stacked layer including Ti, Al, TiAl, TiAlN, Ta, TaN, TiAlC, TaAlCSi, TaAlC, TiSiN, etc. In the case where an n-type FinFET is formed with the corresponding gate electrode 72, the work function adjustment layer may be formed with the corresponding gate electrode 72 as a stacked layer including TiN, TaN, TiAl, W, Ta, Ni, Pt, etc. In these embodiments, after depositing the (one or more) work function adjustment layers, a barrier layer (e.g., another TiN layer) may be formed.

[0048] According to some embodiments, the conductive fill material may be formed of materials such as tungsten, cobalt, copper, ruthenium, aluminum, etc. The conductive fill material is deposited over the gate dielectric, one or more conductive barrier layers, and one or more work function adjustment layers such that the remaining space between the corresponding spacers 62 of the corresponding gate electrode 72 is filled or overfilled.

[0049] After filling (or overfilling) the gate electrode 72, a planarization process (e.g., CMP) may be performed to remove the excess portions of the materials of the gate dielectric 70 and the gate electrode 72 that are above the top surface of the ILD 66. The remaining portions of the materials of the gate electrode 72 and the gate dielectric 70 thus form the replacement gate of the resulting FinFET. The gate electrode 72 and the gate dielectric 70 may be collectively referred to as the gate stack 74. The gate stack 74 extends along the sidewalls of the channel region of the fin 52.

[0050] In some embodiments, once the ILD 66 has been planarized and the planar surfaces of the gate stack 74 and the gate spacers 62 are exposed, the ILD 66 may be annealed again using, for example, a second annealing process. In an embodiment, the second annealing process may be a thermal annealing where the substrate 50 and the ILD 66 are heated in an inert atmosphere, e.g., in a furnace. The second annealing process may be performed at a temperature between about 200°C and about 1000°C (e.g., about 500°C) and may last for a time between about 60 seconds and about 360 minutes, e.g., about 240 minutes.

[0051] After formation, the gate stack 74 has a width W2. In some embodiments, the width W2 is in the range of about 6 nm to about 300 nm. As discussed further below, the distance D1 between the fins 52 is selected based on the width W2 of the formed gate stack 74 (see Figure 1A ).

[0052] Figure 5A Further shown are reference cross-sections used in the subsequent figures. Cross-section A-A' is located between the fins 52 and is parallel to the longitudinal axis of the fins 52. Cross-section B-B' is perpendicular to cross-section A-A' and along the longitudinal axis of the gate stack 74 and, for example, in a direction perpendicular to the current flow between the epitaxial source / drain regions 64 of the FinFET. Cross-section C-C' is parallel to cross-section B-B' and extends through the epitaxial source / drain regions 64 of the FinFET. For clarity, the subsequent figures refer to these reference cross-sections.

[0053] Figures 6A - 19C and Figures 21A - 22C represent cross-sectional views taken through intermediate structures formed using intermediate steps associated with the corresponding figures. Figure 6A 、 Figure 7A, Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 21A and Figure 22A (“Cross - section ‘A’”) is taken along the Figure 5A line A - A’ except having different numbers of gate stacks 74. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 21B and Figure 22B (“Cross - section ‘B’”) is a view taken along the Figure 5A line B - B’ except having different numbers of fins 52. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 21C and Figure 22C (“Cross - section ‘C’”) is a view taken along the Figure 5A line C - C’ except having different numbers of fins 52. Note that Figure 5A the cross - sections A - A’, B - B’ and C - C’ shown in Figures 6A - 19C and Figures 21A - 22C are shown on an exemplary FinFET structure and Figures 6A - 19C and Figures 21A - 22C the relative arrangements of these cross - sections are shown in

[0054] In addition, the cross-sectional view of "A" is taken along the line A-A' shown in association with the cross-sectional views of "B" and "C" to show a series of gate structures in a direction parallel to the fins of the formed FinFET. The cross-sectional view of "B" is taken along the line B-B' shown in association with the cross-sectional views of "A" and "C" to show the gate structures in a series of gate structures in the region of the cut metal gate (CMG) of the corresponding intermediate structure in a direction perpendicular to the fins of the formed FinFET. The cross-sectional view of "C" is taken along the line C-C' shown in the associated cross-sectional views of "A" and "B" to show the region of the ILD0 / EPI interface associated with the cut metal gate (CMG) of the corresponding intermediate structure in a direction perpendicular to the fins of the formed FinFET.

[0055] Figures 6A - 16C An intermediate stage in the fabrication of a FinFET having a cut metal gate is shown in accordance with some embodiments. Figures 6A - 6C An intermediate structure similar to Figures 5A - 5C is shown, and is the same step in the fabrication process of the FinFET. In Figure 6A , four gate stacks 74 are shown on a substrate 50, and in Figure 6B and Figure 6C , two pairs of fins 52 are shown in the respective views. Although four gate stacks 74 are shown in the same region of the substrate 50, those of ordinary skill in the art will understand that these gate stacks 74 may be physically separated from each other and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be provided between the gate stacks 74. For example, Figures 6A to 16C the rightmost gate 74 in Figures 6A to 16C may be in the input / output region of the substrate 50, while the three leftmost gate stacks 74 in Figures 6A to 16C may be in the memory region of the substrate, such as a static random access memory (SRAM) region. In some embodiments, the gate stacks 74 may have different channel lengths. For example, as shown in Figures 6A to 16C , the rightmost gate stack 74 is wider than the other shown gate stacks 74, and thus, the rightmost gate stack 74 may have a longer channel length than the other shown gate stacks 74.

[0056] Figures 7A - 7C Shows some initial steps in forming a "cut metal gate" (CMG) in one or more of the gate stacks 74 of the intermediate structure shown in Figures 6A - 6C . Once the gate stacks 74 have been planarized, a series of hard mask layers may be formed over the planar surfaces of the gate stacks 74 and the ILD 66.

[0057] In some embodiments, the first layer in a series of mask layers may be an etch stop layer 80. The etch stop layer 80 may be formed by depositing a material (e.g., Si, TiN, SiN, SiO2, combinations thereof, etc.) using a deposition method (e.g., atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), etc.) over the planar surfaces of the gate stack 74 and the ILD 66. However, any suitable material and any suitable method may be used to form the etch stop layer 80.

[0058] The hard mask layer 82 may be deposited over the etch stop layer 80 as the second layer in the series of mask layers. The hard mask layer 82 is formed over the etch stop layer 80 and is formed of a second hard mask material (e.g., SiN, SiO2, combinations thereof, etc.). The second hard mask material used to form the hard mask layer 82 is different from the first hard mask material used to form the etch stop layer 80. Thus, the etch stop layer 80 may be used as an etch stop for subsequent patterning of the hard mask layer 82. According to some embodiments, the hard mask layer 82 may be placed over the etch stop layer 80 using a deposition method (e.g., atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), etc.). However, any suitable material and formation process may be used for the hard mask layer 82 in the first series of hard mask layers.

[0059] Figures 8A - 8C A deposition and patterning process is shown to form an opening 84 through a photoresist layer 86 deposited over the hard mask layer 82. According to an embodiment, the photoresist layer 86 may be deposited over the hard mask layer 82 as the third layer in the series of mask layers. The photoresist layer 86 may be deposited using any suitable deposition process, may be formed to any suitable thickness, and may be patterned using any suitable lithography method to form an opening 84 through the photoresist layer 86 and expose the surface of the hard mask layer 82 of the first series of mask layers in an area covering one or more of the gate stacks 74.

[0060] Figures 9A - 9C A first etchant is shown being used to Figures 8A - 8CThe pattern of the photoresist layer 86 is transferred into the hard mask layer 82 to form an opening 88 through the hard mask layer 82. In some embodiments, the first etchant may use a reactant gas that has a greater etch selectivity for the hard mask material used to form the hard mask layer 82 than for the hard mask material used to form the etch stop layer 80. Thus, the etch stop layer 80 serves as an etch stop layer, and the region of the etch stop layer 80 covering one or more of the gate stacks 74 is exposed through the opening 88. In some embodiments, the etching process may be performed using, for example, a carbon- and fluorine-containing gas (e.g., CF4, CH2F2, CHF3, etc.). However, any suitable gas may be used for the first etchant.

[0061] According to some embodiments, Figure 9A the opening 88 in may be formed to have one or more widths W88 X , which is between about 5 nm and about 500 nm, such as about 100 nm, and in Figure 9B and Figure 9C the opening 88 in may be formed to have one or more widths W88 Y , which is between about 5 nm and about 50 nm, such as about 30 nm. However, any suitable width may be used for the opening 88. Once the opening 88 is formed, the remaining photoresist layer 86 is removed. Any suitable process known in the art for removing a photoresist layer may be used to remove the remaining photoresist layer 86.

[0062] Figures 10A - 10C illustrates narrowing the opening 88 to form a narrow opening 90 by redepositing a second hard mask material as a blanket mask layer 92. The blanket mask layer 92 may be formed by, for example, a conformal deposition process (e.g., chemical vapor deposition (CVD) or atomic layer deposition (ALD)) such that the blanket mask layer 92 lines the exposed surface of the etch stop layer 80, lines the exposed surface of the hard mask layer 82, and lines the sidewalls of the opening 88 through the hard mask layer 82. According to some embodiments, the blanket mask layer 92 may be formed of the same hard mask material as the hard mask material used to form the hard mask layer 82 (e.g., silicon nitride). In an embodiment, the blanket mask layer 92 is formed to have a thickness that is highly uniform between about and about , such as about Thus, Figure 10A the narrow opening 90 in may be formed to have one or more widths W90 X , which is between about 5 nm and about 500 nm, such as about 100 nm, and in Figure 10B and Figure 10C the narrow opening 90 in may be formed to have one or more widths W90 Y, which is between about 5 nm and about 50 nm, such as about 30 nm. However, any suitable width can be used for the narrow opening 90.

[0063] Figures 11A - 11C An anisotropic etching process is shown, and the anisotropic etching process is performed to remove the portion of the blanket mask layer 92 that lines the bottom of the narrow opening 90. The etch stop layer 80 serves as an etch stop layer during the anisotropic etching process. Thus, at least a portion of the region of the etch stop layer 80 covering one or more of the gate stacks 74 is re-exposed through the narrow opening 90. In the anisotropic etching, the horizontal portion of the blanket mask layer 92 that lines the bottom of the narrow opening 90 is removed, while the remaining vertical portions on the sidewalls of the narrow opening 90 remain intact. In this way, the vertical portions on the sidewalls of the narrow opening 90 form a complete ring having dimensions corresponding to Figures 10A - 10C the width W90 shown X and W90 Y corresponding thereto and corresponding to Figures 6A - 6C the cut lines A-A', B-B', C-C' shown. In some embodiments, the anisotropic etching process can be performed to remove the blanket mask layer 92 that lines the bottom of the narrow opening 90 using, for example, a gas containing carbon and fluorine (e.g., CF4, CH2F2, CHF3, etc.). However, any suitable gas can be used for the anisotropic etching process.

[0064] Figures 12A - 12C A cut metal gate (CMG) etching process is shown, and the CMG etching process is performed to remove the exposed portion of the region of the etch stop layer 80 and remove one or more target portions of the gate stack 74 (which can be referred to as the cut metal gate region of the gate stack 74), the associated gate spacers 62, and portions of the ILD 66 in order to form the CMG trench 94. The CMG etching process divides one or more target portions of the gate stack 74 into a first metal gate portion 74a and a second metal gate portion 74b, effectively "cutting" the first portion from the second portion, as Figure 12B shown. The CMG etching process also divides one or more target portions of the ILD 66 of the source / drain regions into a first ILD portion 66a and a second ILD portion 66b, effectively "cutting" the first portion from the second portion, as Figure 12C shown. According to some embodiments, the CMG etching process includes dry etching using a chlorine-containing or fluorine-containing gas (e.g., Cl2, NF3, SiCl4, BCl3, O2, N2, H2, Ar, combinations of the foregoing, etc.). However, any suitable dry etching gas can be used for the CMG etching process.

[0065] In some embodiments, the CMG trench 94 is formed to a first depth P1 in a first portion of the CMG trench 94 and to a second depth P2 in a second portion of the CMG trench 94. The first portion of the CMG trench 94 is formed by removing material of a target portion of the gate stack 74, removing material of a target portion of the gate spacer 62, and removing material of a portion of the ILD 66 that is below the target portion of the gate stack 74 and the target portion of the gate spacer 62. Thus, the first portion of the CMG trench 94 is formed to a first width W94 X1 , which first width W94 X1 corresponds to the width of the target gate of the gate stack 74 and corresponds to the thickness of the gate spacer 62 in the ILD 66.

[0066] The second portion of the CMG trench 94 is formed by removing material of the blanket mask layer 92 that is formed along the vertical sidewalls of the opening 88 through the hard mask layer 82, and by removing material of a portion of the ILD 66 that is below the blanket mask layer 92 formed along the vertical sidewalls of the opening 88 through the hard mask layer 82. Thus, the second portion of the CMG trench 94 is formed to a second width W94 that corresponds to the width of the opening W88 X in the hard mask layer 82. X2 .

[0067] Figure 12B A cross-section taken along the cut line B-B' near or at the center of the CMG trench 94 shows that the CMG trench 94 is formed to the first depth P1 at which the target gate stack 74 is completely separated (i.e., "cut") into a first portion 74a and a second portion 74B of the target gate stack 74. Figure 12C A cross-section taken along the cut line C-C' near or at the source / drain region 64 of the CMG trench 94 shows that the CMG trench 94 is formed to the second depth P2 at which a portion of the ILD 66 remains over the isolation region 56 that isolates portions of the fins 52 of adjacent devices.

[0068] As Figures 12A - 12C further shown, during the CMG etching process, residual byproduct material 96 (e.g., polymer) can be formed as a byproduct of the reaction between the material of the hard mask layer 82, the etch stop layer 80, the material of the target gate stack 74, the material of the gate spacer 62, the material of the ILD 66, and the reactant gas during the CMG etching process. For example, as Figures 12A - 12C shown, the residual byproduct material 96 can be formed over the hard mask layer 82 and along the sidewalls of the CMG trench 94.

[0069] Figures 13A - 13C The removal of the residual byproduct material 96 is shown. Once the CMG trench 94 has been formed, a polymer removal process is performed to remove any residual polymer byproducts 96. For example, a non-plasma formulation with HF / NH3 gas can be used to remove the polymer material. The non-plasma formulation with HF / NH3 gas has low selectivity for metals and can be adjusted to have different selectivity for SiN by adjusting the pressure and temperature during the removal of the polymer byproduct 96.

[0070] Once the CMG polymer byproduct 96 has been removed, a wet clean can be performed to ensure the surface of the CMG trench 94 is clean for further processing. According to some embodiments, a solution such as an SC-1 or SC-2 cleaning solution can be used for the wet clean process. Although other solutions can also be used, such as a mixture of H2SO4 and H2O2 (referred to as SPM), or a solution of hydrogen fluoride (HF). However, any suitable solution or any suitable process can be used for the wet clean process and is fully intended to be included within the scope of the embodiments.

[0071] According to some embodiments, after the removal of the CMG polymer byproduct 96, the CMG trench 94 can be formed to a first depth P1 between about 50 nm and about 300 nm, and to a first width W94 between about 5 nm and about 500 nm (e.g., about 100 nm). X1 The CMG trench 94 can also be formed to a second depth P2 between about 48 nm and about 298 nm (e.g., about 198 nm), and to a second width W94 between about 1 nm and about 10 nm (e.g., about 4 nm). X2 However, any suitable depth and any suitable width can be used for the first depth P1 and the second depth P2 of the CMG trench 94, and any suitable width can be used for the first width W94 of the CMG trench 94. X1 and the second width W94 X2 .

[0072] In addition, when viewed in the cross-section in Figure 13B and Figure 13C and in subsequent figures in these same cross-sections, the CMG trench 94 can have, for example, a U, V, or square shape. In the Figures 13A - 13C embodiment, the CMG trench 94 has a square shape, however other shapes are possible and are fully intended to be included within the scope of the embodiments (e.g., see Figures 21A - 22C ).

[0073] Figures 14A - 14C Shows in Figures 13A - 13CA barrier layer 100 is deposited on top of the structure. The barrier layer 100 can help prevent the material of the CMG trench 94 from diffusing into the gate stack 74 during subsequent processing. In some embodiments, the barrier layer 100 can include silicon nitride or the like. The barrier layer 100 can have, for example, a dielectric constant in the range of about 6.5 to about 8. The barrier layer 100 can be conformally deposited using a deposition process such as ALD. The barrier layer 100 can be deposited on each side of the CMG trench 94 to a thickness between about 1 nm and about 15 nm (e.g., about 5 nm).

[0074] In an embodiment, the barrier layer 100 is a silicon nitride layer deposited by a plasma enhanced atomic layer deposition (PEALD) process. In this embodiment, the PEALD process can be performed in a temperature range from 300 °C to about 600 °C. Additionally, in this embodiment, the PEALD process for forming the silicon nitride layer can include precursors of disilane (SiH2I2) and NH3.

[0075] Figures 14A - 14C Further shown is an oxygen blocking layer 102 conformally deposited on top of the barrier layer 100. In an embodiment, the oxygen blocking layer 102 can be formed as a layer of amorphous silicon material or the like. In an example where the oxygen blocking layer 102 is a silicon layer 102, the silicon layer 102 can be deposited on each side of the CMG trench 94 to a thickness in the range of about to about , for example, about In Figures 14A - 14C the embodiment, the silicon layer 102 is deposited to a thickness less than about . The silicon layer 102 can be conformally deposited using a deposition process such as CVD. The silicon layer 102 serves as a barrier against oxidation of the underlying barrier layer 100 and the gate stack 74. In some embodiments, the oxygen blocking layer 102 can be formed of other suitable materials with a low k value and will serve as a barrier against oxidation of the underlying barrier layer 100 and the gate stack 74.

[0076] In an embodiment, the silicon layer 102 is deposited by CVD in a furnace at a temperature in the range from about 350 to about 450 °C, at a pressure of about 1 to about 3 Torr, with a disilane flow rate of about 0.3 to about 0.5 standard liters per minute (slm) and an N2 carrier gas flow rate of about 0 to 1 slm.

[0077] In another embodiment, a silicon layer 102 is deposited by PEALD in a single-wafer chamber at a temperature in the range of about 300 °C to about 600 °C, at a pressure of about 10 to about 20 Torr, with a precursor diiodosilane (SiH2I2) and N2 flow rate of about 200 to about 2000 slm (e.g., 800 slm), at a radio frequency of about 600 to about 800 watts, for a duration of about 0.2 to about 10 minutes (e.g., one minute).

[0078] In another embodiment, at a temperature in the range of about 200 °C to about 500 °C, at a pressure in the range of about 2 to about 5 Torr, with a precursor N-(diethylaminosilyl)-N-ethylethylamine (C8H 22 N2Si) and Ar flow rate in the range of about 0.5 to about 10 slm (e.g., 2 slm), at a radio frequency of about 15 to 100 watts, and for a time duration in the range of about 0.2 to about 10 minutes (e.g., one minute), a silicon layer 102 is deposited by PEALD in a furnace.

[0079] After depositing the silicon layer 102, an oxidation process is performed to convert at least a portion of the silicon layer 102 into a silicon oxide layer. In an embodiment, the oxidation process includes an in-situ O2 purge oxidation method. In an embodiment, the oxidation process includes an in-situ O2 soak in a furnace at a temperature in the range of about 350 °C to 450 °C, at a pressure in the range of about 1 to about 3 Torr, with an O2 flow rate in the range of about 0.2 to about 10 slm, and for a time duration in the range of about 2 minutes to about 30 minutes. In an embodiment where the silicon layer 102 is formed to have a thickness less than about the oxidation process completely converts the silicon layer 102 into a silicon oxide layer.

[0080] In another embodiment, the oxidation process is performed by breaking the vacuum to expose the silicon layer 102 to ambient atmosphere while the device is in queue for the next processing stage described below with reference to Figures 15A - 15C the next processing stage.

[0081] In some embodiments, after the oxidation process, on each side of the CMG trench 94, the combined thickness of any remaining silicon layer 102 and the newly formed silicon oxide layer can have a thickness of about 0.4 nm to about 1.5 nm.

[0082] In Figures 15A - 15C a filling material 104 is deposited on top of the Figures 14A - 14C oxidized structure. The CMG trench 94 can be filled with the filling material 104. In Figures 15A - 15CIn the present and subsequent figures, the silicon oxide layer is shown as part of the fill material 104 because the material composition can be the same. The fill material 104 can be a dielectric material such as silicon oxide, silicon nitride, silicon oxycarbide, and / or silicon oxynitride, where carbon is present in the compound in a weight percentage of about 1% to 10%, and / or nitrogen is present in the compound in a weight percentage of less than about 50%, and can be represented by the formula (Si) (1-y) N y , (SiO) (1-x) C x and / or (SiO) (1-x-y) C x N y , where x = 0.01 - 0.1 and y < 0.5. The fill material 104 can be deposited using a deposition process (e.g., PEALD, PECVD, ALD, CVD, etc.). In an embodiment, the fill material 104 is silicon oxide having a dielectric constant of about 3.5 to about 5. In an embodiment, the fill material 104 can be deposited to overfill the CMG trench 94 to a level above the top surface of the hard mask layer 82.

[0083] In an embodiment, the fill material is deposited by PEALD using the precursors N-(diethylaminosilyl)-N-ethylethylamine (C8H 22 N2Si) and O2.

[0084] In an embodiment, each of the deposition of the barrier layer 100, the deposition of the silicon layer 102, and the oxidation of the silicon layer 102 can be performed in a single chamber. In other embodiments, the barrier layer 100 is deposited in a separate chamber.

[0085] In an embodiment, each of the deposition of the silicon layer 102, the oxidation of the silicon layer 102, and the deposition of the fill material 104 can be performed in a single chamber. In this embodiment, the deposition of the barrier layer 100 is performed in a separate chamber.

[0086] In an embodiment, after depositing a silicon layer 102 having a thickness of less than about , oxidizing the silicon layer 102, and depositing the silicon oxide fill material 104, all or substantially all of the silicon layer 102 is oxidized. Thus, in this particular embodiment, both the silicon oxide layer 102 and the fill material 104 are silicon oxide and are above the barrier layer 100 in the CMG trench 94.

[0087] Figures 16A - 16CIllustrated is the planarization of the fill material 104, which can be performed using, for example, a chemical mechanical (CMP) planarization process to remove excess material of the fill material 104. The CMP planarization process can continue until the etch stop layer 80 has been completely removed, and can continue until the top surfaces of the fill material 104, the gate stack 74, and the corresponding gate spacers 62 are exposed within the planar surface of the ILD 66. Thus, the CMG plug 106 is formed of the barrier layer 100, the silicon layer 102 (if present), and the remaining material of the fill material 104 disposed within the ILD 66. In some embodiments, once reduced, the height of the gate stack 74 and the height of the CMG plug 106 can be reduced to a first total height H1 between about 50 nm and about 120 nm (e.g., about 100 nm). However, any suitable height can be used for the gate stack 74 and the CMG plug 106.

[0088] Figures 17A - 19C Illustrated is an intermediate stage in the fabrication of a FinFET having a cut metal gate according to some other embodiments. Figures 17A - 19C The embodiments in Figure 16C are similar to the embodiments shown in FIGS. 1-

[0089] Figures 17A - 17C except that in this embodiment, some of the oxygen barrier layer 202 remains unoxidized in the final structure. In this embodiment, the oxygen barrier layer 202 can be formed thicker than the oxygen barrier layer 102 of the previous embodiment such that the oxidation process does not oxidize all of the oxygen barrier layer 202. Similar to the previous embodiment, by way of example, the oxygen barrier layer 202 can be a silicon layer 202. Details regarding this embodiment similar to the details of the foregoing embodiments will not be repeated here. Figures 14A - 14C Illustrated is an intermediate stage of a process similar to the process described above in Figures 17A - 17C and the description of forming the intermediate stage of this process will not be repeated here. As shown in Figures 13A - 13C after removing the residual byproduct material 96 in Figures 13A - 13C a barrier layer 200 is deposited over the structure of

[0090] Figures 17A - 17C Further illustrated is a silicon layer 202 conformally deposited over the barrier layer 200. The silicon layer 202 can be deposited on each side of the CMG trench 94 to a thickness in the range of about to about In the embodiment of Figures 17A - 17C the silicon layer 202 is deposited to a thickness greater than or equal to about The thickness. The materials and processes used to form the silicon layer 202 can be similar to those of the silicon layer 102 described above and will not be repeated here.

[0091] After depositing the silicon layer 202, an oxidation process is performed to convert a portion of the silicon layer 202 into a silicon oxide layer while leaving some of the silicon layer 202 intact. This oxidation process can be similar to the oxidation process described above with reference to Figures 14A - 14C and will not be repeated here. Since the silicon layer 202 is formed relatively thick in this embodiment, the oxidation process does not convert all of the silicon layer 202 into a silicon oxide layer but leaves some of the silicon layer 202 intact.

[0092] In Figures 18A - 18C the fill material 204 is deposited over the Figures 17A - 17C oxidation structure. The materials and processes used to form the fill material 204 can be similar to those of the fill material 104 described above and will not be repeated here.

[0093] In Figures 19A - 19C excess material of the fill material 204 is removed using, for example, a CMP planarization process to planarize the fill material 204. The CMP planarization process can continue until the etch stop layer 80 has been completely removed and can continue until the top surfaces of the fill material 204, the gate stack 74, and the corresponding gate spacers 62 are exposed within the planar surface of the ILD 66. Thus, the CMG plug 206 is formed from the remaining material of the barrier layer 200, the silicon layer 202, and the fill material 204 disposed within the ILD 66. In some embodiments, once reduced, the height of the gate stack 74 and the height of the CMG plug 206 can be reduced to a total height H2 between about 50 nm and about 120 nm (e.g., about 100 nm). However, any suitable height can be used for the gate stack 74 and the CMG plug 206.

[0094] Figure 20 shows a semiconductor device after additional stages in the fabrication of a FinFET with a cut metal gate.

[0095] After forming the cut metal gate, for example, in a stage after Figures 16A - 16C or Figures 19A - 19C as shown in Figure 20 an ILD 76 is deposited over the ILD 66. In some embodiments, the ILD 76 is a flowable film formed by a flowable CVD method. In some embodiments, the ILD 76 is formed of a dielectric material (e.g., PSG, BSG, BPSG, USG, etc.) and can be deposited by any suitable method (e.g., CVD and PECVD).

[0096] In addition, the gate contact 78 and source / drain contacts (not shown) are formed through the ILD 76 and the ILD 66. Openings for the source / drain contacts are formed through the ILD 66 and the ILD 76, and an opening for the gate contact 78 is formed through the ILD 76 (and optionally, through the gate mask if a gate mask is formed). The gate contact 78 (or the source / drain contacts) may include a liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material. Acceptable lithography and etching techniques may be used to form the openings. The liner and the conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. The conductive material may be formed by a deposition process (e.g., CVD).

[0097] A planarization process (e.g., CMP) may be performed to remove excess material from the surface of the ILD 76. The remaining liner and conductive material form the source / drain contacts and the gate contact 78 in the openings. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain region 64 and the source / drain contacts. The source / drain contacts are physically and electrically coupled to the epitaxial source / drain region 64, and the gate contact 78 is physically and electrically coupled to the gate electrode 72. The source / drain contacts and the gate contact 78 may be formed in different processes or may be formed in the same process.

[0098] Figures 21A - 22C An intermediate stage in the fabrication of a FinFET with a cut metal gate according to some other embodiments is shown. Figures 21A - 22C The embodiments in Figures 1A - 16C and Figures 17A - 19C are similar to the embodiments shown in

[0099] Figures 21A - 21C except that in this embodiment, the CMG trench is formed to be U-shaped. In addition, in this embodiment, the trench may be formed deeper to extend through the isolation region 56 and partially into the substrate 50. Details of this embodiment similar to the details of the foregoing embodiments will not be repeated here.

[0099] Figures 21A - 21C An intermediate stage of a process similar to the process described above in Figures 13A - 13C is shown, and the description of forming the intermediate stage of this process will not be repeated here. In Figures 21A - 21CTherein, a cut metal gate (CMG) etching process is performed to remove the exposed portions of the regions of the etch stop layer 80, and one or more target portions of the gate stack 74, the associated gate spacers 62, and portions of the ILD 66 are removed to form the CMG trench 300. The materials and processes for forming the CMG trench 300 may be similar to the above-described CMG trench 94 and will not be described again here. In this embodiment, the etching time for forming the CMG trench 300 may be increased from the previous embodiment so that the CMG trench 300 is formed to a greater depth.

[0100] As Figures 21A - 22C shown, after removing the residual byproduct material 96 in Figures 13A - 13C , the CMG trench 300 is formed to a depth P3 in the first portion of the CMG trench 300 and to a depth P4 in the second portion of the CMG trench 300. The first portion of the CMG trench 300 is formed by removing the material of the target portion of the gate stack 74, removing the material of the target portion of the gate spacers 62, and removing the material of the portion of the ILD 66 located below the target portion of the gate stack 74 and the target portion of the gate spacers 62. Accordingly, the first portion of the CMG trench 300 is formed to a first width W300 X1 , which corresponds to the width of the target gate of the gate stack 74 and corresponds to the thickness of the gate spacers 62 in the ILD 66.

[0101] The second portion of the CMG trench 300 is formed by removing the material of the blanket mask layer 92 formed along the vertical sidewalls of the opening 88 through the hard mask layer 82, and by removing the material of the portion of the ILD 66 located below the blanket mask layer 92 formed along the vertical sidewalls of the opening 88 through the hard mask layer 82. Accordingly, the second portion of the CMG trench 300 is formed to a second width W300 X2 , which corresponds to the width of the opening W88 in the hard mask layer 82 X (e.g., see Figures 9A - 9C ).

[0102] According to some embodiments, after removing the CMG polymer byproduct 96, the CMG trench 300 may be formed to a first depth P3 between about 150 nm and about 350 nm and to a first width W300 between about 5 nm and about 25 nm (e.g., about 10 nm) X1 . The CMG trench 300 may also be formed to a second depth P4 between about 130 nm and about 330 nm (e.g., about 250 nm) and to a second width W300 between about 2 nm and about 20 nm (e.g., about 7 nm) X2However, any suitable depth and any suitable width can be used for the first depth P3 and the second depth P4 of the CMG trench 300, and any suitable width can be used for the first width W300 of the CMG trench 94 X1 and the second width W300 X2 .

[0103] In addition, when viewed in the cross-section in Figure 21B and Figure 21C and in subsequent figures in these same cross-sections, the CMG trench 300 can have, for example, a U, V, or square shape. In the Figures 21A - 21C embodiment, the CMG trench 300 has a U-shape, however other shapes are possible and are fully intended to be included within the scope of the embodiment.

[0104] Figures 22A - 22C Illustrates subsequent processing performed on the structure in Figures 21A - 21C . Figures 21A - 21C and 22A- Figure 22C The subsequent processing between is similar to the processing shown and described above in Figures 14A - 14C and Figures 16A - 16C or Figures 17A - 17C and Figures 19A - 19C and will not be described again here.

[0105] Figures 22A - 22C Illustrates a barrier layer 302 formed in the CMG trench 300 and a filling material 304 formed on the barrier layer 302. Although it is not described in this embodiment that an oxygen barrier layer (e.g., the silicon layer 102 or 202) will be retained, an oxygen barrier layer between the barrier layer 302 and the filling material 304 is possible and is fully intended to be included within the scope of this embodiment. In this embodiment, since the CMG trench 300 exposes the substrate 50, the barrier layer 302 physically contacts the substrate 50 in the trench 300. The barrier layer 302 can be similar to the barrier layer 100, and the filling material 304 can be similar to the filling material 104. The materials and processes for forming the barrier layer 102 and the filling material 104 are as described above and will not be described again here.

[0106] In addition, Figures 22A - 22C further illustrates the CMG plug 306. The materials and processes for forming the CMG plug 306 can be similar to those of the CMG plug 106 described above and will not be described again here. In this embodiment, once reduced, the height of the gate stack 74 and the height of the CMG plug 306 can be reduced to a first total height H3 between about 50 nm and about 150 nm. However, any suitable height can be used for the gate stack 74 and the CMG plug 306.

[0107] Embodiments can achieve advantages. The embodiments include a CMG isolation structure formed in a cut metal gate (CMG) trench, which improves the resistance-capacitance delay of the device and does not reduce the threshold voltage of the device. In some embodiments, the CMG isolation structure includes multiple layers having a silicon nitride layer, a silicon layer, and a silicon oxide layer. In some embodiments, the silicon nitride layer serves as a barrier layer to prevent the materials of the gate stack from diffusing into the CMG trench during subsequent processing. In some embodiments, the silicon layer serves as a barrier against oxidation of the underlying barrier layer and the gate stack. Since the silicon layer protects the underlying layers from oxidation, a silicon oxide layer can be formed on the silicon layer, which reduces the dielectric constant of the CMG isolation structure. In addition, by protecting the underlying layers (e.g., the gate stack) from oxidation, the threshold voltage of the device can be maintained while using the CMG method.

[0108] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0109] Example 1 is a method for forming a semiconductor device, including: forming an opening in a cut metal gate region of a metal gate structure of the semiconductor device; conformally depositing a first dielectric layer in the opening; conformally depositing a silicon layer on the first dielectric layer; performing an oxidation process on the silicon layer to form a first silicon oxide layer; filling the opening with a second silicon oxide layer; and performing chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device.

[0110] Example 2 is the method according to Example 1, wherein the first dielectric layer includes silicon nitride.

[0111] Example 3 is the method according to Example 1, wherein performing the oxidation process on the silicon layer converts all of the silicon layer into the first silicon oxide layer.

[0112] Example 4 is the method according to Example 3, wherein the second silicon oxide layer is directly formed on the first silicon oxide layer.

[0113] Example 5 is the method according to Example 1, wherein performing the oxidation process on the silicon layer converts only a part of the silicon layer into the first silicon oxide layer, and wherein a part of the silicon layer remains unconverted.

[0114] Example 6 is the method described in Example 5, wherein the remaining silicon layer separates the first dielectric layer from the first silicon oxide layer.

[0115] Example 7 is the method described in Example 1, further comprising: forming a first semiconductor fin on a substrate; forming an isolation region around a lower portion of the first semiconductor fin; forming a dummy gate structure on a top surface and sidewalls of the first semiconductor fin and along a top surface of the isolation region; forming source / drain regions on the first semiconductor fin; forming an interlayer dielectric layer on the dummy gate structure, the source / drain regions, and the isolation region; and replacing the dummy gate structure with the metal gate structure, an opening in the cut metal gate region of the metal gate structure extending through the interlayer dielectric layer.

[0116] Example 8 is the method described in Example 7, wherein the opening in the cut metal gate region of the metal gate structure extends through the isolation region and into the substrate.

[0117] Example 9 is the method described in Example 1, wherein performing an oxidation process on the silicon layer includes a plasma-enhanced atomic layer deposition process.

[0118] Example 10 is a method for forming a semiconductor device, including: forming a first semiconductor fin and a second semiconductor fin over a substrate, the second semiconductor fin being adjacent to the first semiconductor fin; forming an isolation region surrounding a lower portion of the first semiconductor fin and the second semiconductor fin; forming a dummy gate structure over a top surface and sidewalls of the first semiconductor fin and the second semiconductor fin and along a top surface of the isolation region; replacing the dummy gate structure with an active gate structure; etching a first opening through the active gate structure, the first opening being between the first semiconductor fin and the second semiconductor fin, and etching the first opening through the active gate structure includes: forming a first mask layer over the active gate structure; patterning the first mask layer to form a second opening, the second opening passing through the first mask layer over the active gate structure; conformally forming a second mask layer over the patterned first mask layer, the second mask layer being on sidewalls and a bottom of the second opening passing through the first mask layer; removing the second mask layer from a bottom of the second opening; using the first mask layer and the second mask layer as masks to etch a first portion of the first opening, the first portion of the first opening having a first depth; using the first mask layer as a mask to etch a second portion of the first opening, the second portion of the first opening having a second depth, the second depth being less than the first depth; forming a barrier layer in the first opening and over the active gate structure; forming an oxygen barrier layer over the barrier layer in the first opening and over the active gate structure; performing an oxidation process on the oxygen barrier layer, the oxidation process forming a first oxide layer; and forming a dielectric layer over the first oxide layer to fill the first opening.

[0119] Example 11 is the method according to Example 10, wherein the dielectric layer is a silicon oxide layer.

[0120] Example 12 is the method according to Example 10, further including: growing epitaxial source / drain regions on the first semiconductor fin and the second semiconductor fin, the epitaxial source / drain regions being on opposite sides of the dummy gate structure; and forming an interlayer dielectric layer over the dummy gate structure, the epitaxial source / drain regions, and the isolation region, the first opening in the active gate structure extending through the interlayer dielectric layer.

[0121] Example 13 is the method according to Example 12, wherein the first opening in the active gate structure extends through the isolation region and into the substrate.

[0122] Example 14 is the method according to Example 10, wherein performing the oxidation process on the oxygen barrier layer further includes: performing an O2 soak process.

[0123] Example 15 is the method described in Example 10, wherein the oxygen barrier layer is a silicon layer, and wherein forming the oxygen barrier layer over the barrier layer further comprises: performing a plasma enhanced atomic layer deposition process including disilane (SiH2I2).

[0124] Example 16 is the method described in Example 10, wherein the oxygen barrier layer is a silicon layer, and wherein forming the oxygen barrier layer over the barrier layer further comprises: performing a plasma enhanced atomic layer deposition process including N-(diethylaminosilyl)-N-ethylethylamine (C8H 22 N2Si).

[0125] Example 17 is the method described in Example 10, wherein performing an oxidation process on the oxygen barrier layer converts all of the oxygen barrier layer to the first oxide layer.

[0126] Example 18 is a semiconductor device, comprising: a semiconductor fin extending from a substrate; an isolation region surrounding a lower portion of the semiconductor fin; a metal gate structure over the semiconductor fin and the isolation region, the metal gate structure being disposed in an interlayer dielectric layer; and an isolation structure disposed in the metal gate structure, the isolation structure dividing the metal gate structure into two different portions, the isolation structure comprising: a conformal silicon nitride layer extending along sidewalls of two different portions of the metal gate structure; a conformal silicon layer over the conformal silicon nitride layer; and a silicon oxide layer over the conformal silicon layer.

[0127] Example 19 is the semiconductor device described in Example 18, wherein the isolation structure extends through the isolation region and partially into the substrate, and wherein the conformal silicon nitride layer of the isolation structure contacts the substrate.

[0128] Example 20 is the semiconductor device described in Example 18, wherein the conformal silicon nitride layer extends along a top surface of the isolation region from a sidewall of one of two different portions of the metal gate structure to a sidewall of the other of the two different portions of the metal gate structure.

Claims

1. A method for forming a semiconductor device, comprising: An opening is formed in a cut metal gate region of a metal gate structure of a semiconductor device; A first dielectric layer is conformally deposited in the opening; A silicon layer is conformally deposited over the first dielectric layer; An oxidation process is performed on the silicon layer to form a first silicon oxide layer; The opening is filled with a second silicon oxide layer; And A chemical mechanical polishing is performed on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, Wherein, performing the oxidation process on the silicon layer converts all of the silicon layer into the first silicon oxide layer, and wherein, the second silicon oxide layer is directly formed on the first silicon oxide layer.

2. The method according to claim 1, wherein, The first dielectric layer includes silicon nitride.

3. The method according to claim 1, further comprising: A first semiconductor fin is formed over a substrate; An isolation region is formed surrounding a lower portion of the first semiconductor fin; A dummy gate structure is formed over a top surface and sidewalls of the first semiconductor fin and along a top surface of the isolation region; Source / drain regions are formed on the first semiconductor fin; An interlayer dielectric layer is formed over the dummy gate structure, the source / drain regions, and the isolation region; And The dummy gate structure is replaced with the metal gate structure, an opening in the cut metal gate region of the metal gate structure extending through the interlayer dielectric layer.

4. The method according to claim 3, wherein, The opening in the cut metal gate region of the metal gate structure extends through the isolation region and into the substrate.

5. The method according to claim 1, wherein, Performing the oxidation process on the silicon layer includes a plasma enhanced atomic layer deposition process.

6. A method for forming a semiconductor device, comprising: A first semiconductor fin and a second semiconductor fin are formed over a substrate, the second semiconductor fin being adjacent to the first semiconductor fin; An isolation region is formed surrounding lower portions of the first semiconductor fin and the second semiconductor fin; A dummy gate structure is formed over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin and along a top surface of the isolation region; The dummy gate structure is replaced with an active gate structure; A first opening is etched through the active gate structure, the first opening being between the first semiconductor fin and the second semiconductor fin, etching through the first opening in the active gate structure including: A first mask layer is formed over the active gate structure; The first mask layer is patterned to form a second opening, the second opening extending through the first mask layer over the active gate structure; A second mask layer is conformally formed over the patterned first mask layer, the second mask layer being on sidewalls and a bottom of the second opening extending through the first mask layer; The second mask layer is removed from a bottom of the second opening; A first portion of the first opening having a first depth is etched using the first mask layer and the second mask layer as a mask; A second portion of the first opening having a second depth less than the first depth is etched using the first mask layer as a mask; a barrier layer is formed in the first opening and over the active gate structure; Form an oxygen barrier layer over the barrier layer in the first opening and over the active gate structure; Perform an oxidation process on the oxygen barrier layer, the oxidation process forming a first oxide layer; and Form a dielectric layer over the first oxide layer to fill the first opening.

7. The method according to claim 6, wherein, The dielectric layer is a silicon oxide layer.

8. The method according to claim 6 further comprises: Grow epitaxial source / drain regions on the first semiconductor fin and the second semiconductor fin, the epitaxial source / drain regions being on opposite sides of the dummy gate structure; And Form an interlayer dielectric layer over the dummy gate structure, the epitaxial source / drain regions, and the isolation region, the first opening in the active gate structure extending through the interlayer dielectric layer.

9. The method according to claim 8, wherein The first opening in the active gate structure extends through the isolation region and into the substrate.

10. The method according to claim 6, wherein Performing the oxidation process on the oxygen barrier layer further includes: Performing an O2 soak process.

11. The method according to claim 6, wherein The oxygen barrier layer is a silicon layer, and wherein forming the oxygen barrier layer over the barrier layer further includes: Performing a plasma-enhanced atomic layer deposition process including disilane (SiH2I2).

12. The method according to claim 6, wherein The oxygen barrier layer is a silicon layer, and wherein forming the oxygen barrier layer over the barrier layer further includes: Perform a plasma-enhanced atomic layer deposition process including N-(diethylaminosilyl)-N-ethylethylamine (C8H 22 N2Si).

13. The method according to claim 6, wherein Performing an oxidation process on the oxygen barrier layer converts all of the oxygen barrier layer to the first oxide layer.

14. A semiconductor device, comprising: A semiconductor fin extending from a substrate; An isolation region surrounding a lower portion of the semiconductor fin; A metal gate structure on the semiconductor fin and the isolation region, the metal gate structure being disposed in an interlayer dielectric layer; And An isolation structure disposed in the metal gate structure, the isolation structure dividing the metal gate structure into two different portions, the isolation structure including: A conformal silicon nitride layer extending along sidewalls of two different portions of the metal gate structure; A first silicon oxide layer, wherein the first silicon oxide layer is formed by performing an oxidation process on a conformal silicon layer formed on the conformal silicon nitride layer, and wherein performing the oxidation process on the conformal silicon layer converts all of the conformal silicon layer to the first silicon oxide layer; and A second silicon oxide layer, wherein the second silicon oxide layer is formed directly on the first silicon oxide layer.

15. The semiconductor device according to claim 14, wherein The isolation structure extends through the isolation region and partially into the substrate, wherein the conformal silicon nitride layer of the isolation structure contacts the substrate.

16. The semiconductor device according to claim 14, wherein The conformal silicon nitride layer extends along a top surface of the isolation region from a sidewall of one portion of the two different portions of the metal gate structure to a sidewall of the other portion of the two different portions of the metal gate structure.

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