Semiconductor device and method of forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. The method for forming the semiconductor device includes forming fins in a device region and forming other fins in a multi-channel device region in a multi-layer stack of semiconductor materials. A sacrificial layer is removed from the top of the multi-layer stack to expose the topmost nanostructure in the multi-channel device region. Once the sacrificial layer is removed, a stack of nanostructures can be formed from the multi-layer stack. A native oxide of a first thickness is formed on the topmost nanostructure, and a native oxide layer of a second thickness is formed on the remaining nanostructures of the stack, and the first thickness is greater than the second thickness. A gate dielectric layer is formed on the fins in the device region. A gate is formed on the gate dielectric layer in the device region and surrounds the native oxide in the multi-channel device region.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Methods of fabricating semiconductor devices typically involve sequentially depositing materials for insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form electronic components and cells on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce the minimum feature size to continuously improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like), allowing more components to be integrated into a given area. However, as the minimum feature size shrinks, additional problems arise that need to be solved. Summary of the Invention

[0004] Embodiments of the present invention aim to provide a semiconductor device and a method of forming the same to solve at least one of the above problems.

[0005] In some embodiments, a method of forming a semiconductor device includes forming semiconductor fins on a substrate; forming multi-channel fins on the substrate, and the multi-channel fins include sacrificial material; removing the sacrificial material from the multi-channel fins without removing material from the semiconductor fins; after removing the sacrificial material, forming a stack of multiple nanostructures from the multi-channel fins; and forming a gate on the stack of nanostructures and the semiconductor fins.

[0006] In another embodiment, a method of forming a semiconductor device includes: forming a first fin on a substrate; forming a second fin on the substrate, and the second fin includes a stack of semiconductor materials and a sacrificial layer on the multi-layer stack; removing the sacrificial layer; after removing the sacrificial layer, forming nanostructures from the multi-layer stack; and forming a gate on the first fin and the nanostructures, and an upper surface of the gate is separated from the first fin by a first distance and from the topmost nanostructure of the nanostructures by a second distance, and the second distance is greater than the first distance.

[0007] In yet another embodiment, a semiconductor device includes a semiconductor fin located on a substrate; a multi-channel device located on the substrate; a first gate dielectric layer including a first interface surrounding the topmost nanostructure of the multi-channel device and a second interface surrounding another nanostructure of the multi-channel device, and a first thickness of the first gate dielectric layer at the first interface is greater than a second thickness of the first gate dielectric layer at the second interface; and a gate located on the first gate dielectric layer at the first interface and the second interface and surrounding the first gate dielectric layer at the first interface and the second interface, and a first height of the gate on the semiconductor fin is less than a second height of the gate on the topmost nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. is a perspective view of a multi-layer structure in an intermediate step of forming an integrated circuit device in some embodiments.

[0009] Figure 2 FIG. is a cross-sectional view of forming a dielectric material to prepare for forming an isolation region in some embodiments.

[0010] Figure 3 FIG. is a cross-sectional view of forming a recess in a multi-layer stack in some embodiments.

[0011] Figure 4 FIG. is a cross-sectional view of forming an isolation region in some embodiments.

[0012] Figure 5 FIG. is a cross-sectional view of an intermediate structure after forming a dummy gate dielectric layer and a dummy gate in some embodiments.

[0013] Figure 6 FIG. is a cross-sectional view of an intermediate structure after removing the dummy gate, the dummy gate dielectric layer, and the second layer of the multi-layer stack in a circuit release process in some embodiments.

[0014] Figure 7A And 7B FIG. is a cross-sectional view of performing a first interface treatment on the intermediate structure in some embodiments Figure 6 FIG. is a cross-sectional view of performing a second interface treatment on the intermediate structure in some embodiments.

[0015] Figure 8 FIG. is a cross-sectional view of an integrated circuit device in some embodiments.

[0016] Figure 9 FIG. is a partial perspective view of the integrated circuit device shown in some embodiments Figure 8 FIG. is a partial perspective view of the integrated circuit device shown in some embodiments.

[0017] Figure 10 FIG. is a cross-sectional view of performing a second interface treatment on the intermediate structure in some embodiments Figure 6 FIG. is a cross-sectional view of performing a second interface treatment on the intermediate structure in some embodiments.

[0018] Figure 11AA cross-sectional view of an integrated circuit containing a cut metal gate structure, in some embodiments.

[0019] Figure 11B In some embodiments, Figure 11A A partial perspective view of the integrated circuit shown.

[0020] Figure 12 In other embodiments, a schematic diagram of an integrated circuit.

[0021] The reference numerals are as follows:

[0022] CD1: First critical dimension

[0023] CD2: Second critical dimension

[0024] CD3: Third critical dimension

[0025] D1: First depth

[0026] D2: Second distance

[0027] H1: First height

[0028] S1: First space

[0029] Th1: First thickness

[0030] Th2: Second thickness

[0031] Th3: Third thickness

[0032] Th4: Fourth thickness

[0033] Th5: Fifth thickness

[0034] W1: First width

[0035] W2: Second width

[0036] W3: Third width

[0037] W4: Fourth width

[0038] 100: Structure

[0039] 101: Substrate

[0040] 103: First trench

[0041] 105: Fin

[0042] 107, 1111: Dielectric material

[0043] 117: Multi-channel device region

[0044] 119: Multilayer stack

[0045] 120: Device Area

[0046] 121: First Layer

[0047] 123: Second Layer

[0048] 125: Topmost Layer

[0049] 130: First Multi-Channel Device Area

[0050] 140: Second Multi-Channel Device Area

[0051] 301: Depression

[0052] 401: Isolation Region

[0053] 501: dummy gate dielectric layer

[0054] 503: dummy gate

[0055] 505: dummy gate stack

[0056] 507: First Hard Mask

[0057] 509: Second Hard Mask

[0058] 601: Nanostructure

[0059] 603: Nanostructure Stack

[0060] 700: First Interface Treatment

[0061] 701: Protection Material

[0062] 703: Topmost Channel

[0063] 705: Reserved Channel

[0064] 707: First Gate Dielectric Layer

[0065] 800: Integrated Circuit Device

[0066] 803: Second Gate Dielectric Layer

[0067] 805: Gate

[0068] 807: Portion

[0069] 809: Common Gate Stack

[0070] 901: Source / Drain Region

[0071] 903: Contact Etch Stop Layer

[0072] 905: Gate Spacer

[0073] 907: Interlayer Dielectric Layer

[0074] 1000: Gate dielectric deposition process

[0075] 1001: Outer gate dielectric layer

[0076] 1003: Gate dielectric layer

[0077] 1101: Cut metal gate structure

[0078] 1103: First isolated gate stack

[0079] 1105: Second isolated gate stack

[0080] 1107: Third isolated gate stack

[0081] 1109: Second part Detailed implementation mode

[0082] The following detailed description can be combined with the accompanying drawings for understanding various aspects of the present invention. It should be noted that various structures are only for illustrative purposes and are not drawn to scale, as is normal in the industry. In fact, for clear illustration, the sizes of various structures can be increased or decreased arbitrarily.

[0083] The different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are used to simplify the present disclosure rather than limit the present invention. For example, the description of forming a first component on a second component includes both direct contact between the two, or there are other additional components between the two rather than direct contact. In addition, the same reference numerals can be reused in multiple instances of the present invention for simplicity, but the elements with the same reference numerals in multiple embodiments and / or settings do not necessarily have the same corresponding relationship.

[0084] In addition, spatial relative terms such as "below", "beneath", "lower side", "above", "upper side" or similar terms can be used to simplify the relative relationship between one element and another element in the drawings. The spatial relative terms can be extended to elements used in other directions, rather than being limited to the directions in the drawings. The elements can also be rotated 90° or other angles, so the directional terms are only used to illustrate the directions in the drawings. The units with the same reference numerals in the drawings can have the same material composition, unless otherwise specified.

[0085] The following content will be described in conjunction with specific embodiments containing multiple active components and multiple nanostructure devices of fin field-effect transistors. However, the embodiments described here are only for illustration and do not limit the embodiments of the present invention to the content clearly described here. On the contrary, the concepts described here can be combined into a wide variety of embodiments.

[0086] As Figure 1As shown, the structure 100 includes a substrate 101, in which a first trench 103 is formed, and the first trench 103 is located between the device region 120, the first multi-channel device region 130, and the second multi-channel device region 140. The substrate 101 can be a silicon substrate, but other substrates such as a semiconductor-on-insulator substrate, a strained semiconductor-on-insulator substrate, or a silicon-germanium-on-insulator substrate can also be used. The substrate 101 can be a p-type semiconductor, but in other embodiments, the substrate 101 can be an n-type semiconductor.

[0087] In some embodiments, the substrate 101 includes a multi-channel device region 117 for forming active devices (such as multi-channel devices). In these embodiments, voids are initially formed in the substrate 101 to form a multi-layer stack of semiconductor materials in the multi-channel device region 117. A mask layer (not shown in Figure 1 ) and a suitable etching process can be used to form voids in the substrate 101. For example, the mask layer can be a hard mask containing silicon nitride, and its formation process can be chemical vapor deposition. However, other materials can also be used as the mask layer, such as oxides, oxynitrides, silicon carbide, combinations thereof, or the like. Other processes such as plasma-assisted chemical vapor deposition or low-pressure chemical vapor deposition can also be used. The formation method of the mask layer can also be a nitridation process after forming silicon oxide. Once the mask layer is formed, the mask layer can be patterned by a suitable photolithography process to expose the portion of the substrate 101 that will be removed to form voids.

[0088] Those skilled in the art of the present technology should understand that the above processes and materials for forming the mask layer are not the only methods to protect part of the substrate 101 and expose other parts of the substrate 101 for forming voids. Any suitable process such as a patterned and developed photoresist can be used to expose the portion of the substrate 101 that will be removed to form voids. All of these methods are fully included in the scope of the embodiments of the present invention.

[0089] Once the mask layer is formed and patterned, voids can be formed in the multi-channel device region 117 of the substrate 101. The method of removing the exposed substrate 101 to form voids can be a suitable process such as reactive ion etching, but any suitable process can also be used. Once voids are formed in the substrate 101, a series of deposition processes can be performed to form a multi-layer stack 119 of interleaved materials in the voids of the substrate 101. In some embodiments, the multi-layer stack 119 includes a first layer 121 of a first semiconductor material and a second layer 123 of a second semiconductor material.

[0090] In some embodiments, the composition of the first layer 121 may employ a first semiconductor material with a first lattice constant, such as silicon germanium, germanium, silicon, gallium arsenide, indium antimonide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimonide phosphide, gallium antimonide arsenide, combinations of the foregoing, or the like. In some embodiments, the first layer 121 of the first semiconductor material (such as silicon germanium) may be epitaxially grown on the substrate 101, and the deposition technique thereof may be epitaxial growth, vapor phase epitaxy, or molecular beam epitaxy, but other deposition processes such as chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, remote plasma chemical vapor deposition, combinations of the foregoing, or similar processes may also be employed. In some embodiments, the first thickness of the first layer 121 is between about and about . However, any suitable thickness may be employed, and this still falls within the scope of the embodiments.

[0091] Once the first layer 121 is formed in the cavity of the substrate 101, the second layer 123 may be formed on the first layer 121. In some embodiments, the composition of the second layer 123 may employ a second semiconductor material with a second lattice constant, such as silicon, silicon germanium, germanium, gallium arsenide, indium antimonide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimonide phosphide, gallium antimonide arsenide, combinations of the foregoing, or the like, and the second lattice constant is different from the first lattice constant of the first layer 121. In a specific embodiment, the first layer 121 is silicon germanium and the second layer is silicon. However, any suitable combination of materials may be employed for the first layer 121 and the second layer 123.

[0092] In some embodiments, the second layer 123 is epitaxially grown on the first layer 121, and the formation method thereof may be similar to the deposition technique for forming the first layer 121. However, the formation method of the second layer 123 may employ any deposition technique suitable for forming the first layer 121, such as the foregoing or any other suitable technique. In some embodiments, the thickness of the second layer 123 is similar to that of the first layer 121. However, the thickness of the second layer 123 is different from that of the first layer 121. In some embodiments, the second thickness of the second layer 123 may be between about and about . However, any suitable thickness may be employed.

[0093] Once the second layer 123 is formed on the first layer 121, the deposition process may be repeated to form a series of alternating first layers 121 and second layers 123 until the topmost layer required for the multi-layer stack 119 is formed. In this embodiment, the first layer 121 may have the same or similar first thickness, and the second layer 123 may have the same or similar second thickness. However, the thicknesses of the first layers 121 may be different from each other, and / or the thicknesses of the second layers 123 may be different from each other. The first layer 121 and the second layer 123 may have any combination of thicknesses.

[0094] In addition, the topmost layer 125 can be composed of a sacrificial material such as a silicon-based sacrificial material layer, such as silicon germanium, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbide, silicon oxycarbide, combinations of the above, or the like, and the forming method thereof can adopt deposition methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations of the above, or similar deposition methods. In some embodiments, the topmost layer 125 of the multi-layer stack 119, such as the first layer 121 (such as silicon germanium). In other embodiments, a silicon-based material is used to form the topmost layer 125, which is different from the first layer 121 and the second layer 123. In some embodiments, the thickness of the topmost layer 125 is between about and about . However, any suitable thickness can be adopted.

[0095] Although the embodiments disclosed herein include three to ten first layers 121 and three to ten second layers 123, the multi-layer stack 119 can have any suitable number of layers. For example, the multi-layer stack 119 can include 2 to 20 layers. In some embodiments, the multi-layer stack 119 can have the same number of first layers 121 and second layers 123. However, in other embodiments, the numbers of the first layer 121 and the second layer 123 are different. In addition, the multi-layer stack 119 can be formed to fill and / or overfill the voids in the substrate. Once the multi-layer stack 119 is formed, suitable planarization techniques such as chemical mechanical polishing can be used to planarize the top of the substrate 101 and the multi-layer stack 119.

[0096] Those skilled in the art of the present technology should understand that the above process for forming the multi-channel device region 117 is only a possible process rather than the only embodiment. On the contrary, any suitable process can be adopted to form the multi-channel device region 117, including using any suitable number of masks and removal steps.

[0097] Once the multi-channel device region 117 is formed, the first trench 103 can be formed as an initial step for finally forming the isolation region 401. The forming method of the first trench 103 can be to use a mask layer (not shown in Figure 1 ) and a suitable etching process, such as the above process for forming voids. Once the mask layer is formed, a suitable lithography process can be used to pass through the mask layer to expose the substrate 101 and the part of the multi-layer stack that is about to be removed to form the first trench 103.

[0098] However, those skilled in the art of the present technology should understand that the above process and materials for forming the mask layer are not the parts for protecting the substrate 101 and the multi-layer stack 119, and are not the only method for exposing the substrate 101 and the multi-layer stack 119 to form the first trench 103. Any suitable process (such as a photomask for patterning and developing) can be used to expose these parts that are about to be removed and form the first trench 103. All these methods are fully included in the scope of the embodiments of the present invention.

[0099] Once the patterned mask layer is formed, the first trench 103 can be formed in the substrate 101 and the multi-layer stack 119. The method of removing the exposed material to form the first trench 103 in the substrate 101 can be a suitable process such as one or more reactive ion etchings through the multi-layer stack 119, but any suitable process can also be adopted.

[0100] However, those skilled in the art should understand that the above process for forming the first trench 103 is only one of the possible processes and not the only embodiment. On the contrary, any suitable process can be adopted to form the first trench 103, including any number of masking and removal steps.

[0101] In addition to forming the first trench 103, the masking and etching process can additionally form a plurality of fins 105 from these portions of the substrate 101, and the multi-layer stack 119 remains unremoved. For the convenience of illustrating the fins 105, a dashed line is used to separate them from the substrate 101, but there may or may not be a physical separation. As described below, these fins 105 can be used to form active components, such as fin field-effect transistors and / or multi-channel transistors (such as nanosheet field-effect transistors, all-around gate transistors, or the like). Although Figure 1 two fins 105 in the display device area 120, one fin 105 in the first multi-channel device area 130, and two fins 105 in the second multi-channel device area 140 are shown, any of these device areas can adopt any number of fins 105.

[0102] The first width W1 of the fins 105 in the device area 120 on the surface of the substrate 101 can be between about 5 nm and about 80 nm. The second width W2 of the fins 105 in the first multi-channel device area 130 on the surface of the substrate 101 can be between about 3 nm and about 500 nm. In addition, the third width W3 of the fins 105 in the second multi-channel device area 140 on the surface of the substrate 101 can be between about 3 nm and about 300 nm. However, any suitable width and distance can be adopted. In some embodiments, the distance between the fins 105 in the separation area is close enough to share a common gate with one or more other fins 105 in other device areas.

[0103] In addition, although the above-described specific embodiments form the fins 105 of the active components in the device region 120, the first multi-channel device region 130, and the second multi-channel device region 140, these are for illustrative purposes only and do not limit the embodiments of the present invention. On the contrary, the fins 105 can be patterned by any suitable method. In another example, one or more photolithography processes can be used to pattern the fins 105, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography with self-alignment processes, and the resulting pattern pitch can be smaller than that obtained by using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the side portions of the patterned sacrificial layer using a self-alignment process. Then, the sacrificial layer is removed, and the remaining spacers can be used to pattern the fins 105 later. Any suitable process can be used.

[0104] Figure 2 is Figure 1 a cross-sectional view of the structure in, which further shows the deposition of the dielectric material 107 to prepare for forming the isolation region 401. Once the first trench 103 is formed, the dielectric material 107 such as an oxide material (such as flowable oxide), high-density plasma oxide, or the like can be filled into the first trench 103. After optionally contacting and lining the first trench 103, chemical vapor deposition (such as a high aspect ratio process), high-density plasma chemical vapor deposition, or other suitable methods can be used to form the dielectric material 107.

[0105] In some embodiments, the dielectric material 107 can be filled or overfilled into the first trench 103, and the dielectric material 107 is deposited on the substrate 101 and the fins 105. Once the dielectric material 107 is deposited, the extra material outside the first trench 103 and the fins 105 can be removed to planarize the dielectric material 107, the fins 105, and the topmost layer 125 of the multi-layer stack 119, and the planarization method can be a suitable process such as chemical mechanical polishing, etching, a combination of the above, or a similar process. In one embodiment, the removal process can remove any other dielectric material (such as a hard mask, a mask layer, or the like) on the fins 105, and the step of removing the dielectric material 107 will expose the surface of the fins 105 and the topmost layer 125 of the multi-layer stack 119 for subsequent process steps.

[0106] such as Figure 3As shown, a recess 301 is formed in the multi-layer stack 119. The method of forming the recess 301 can be to remove the sacrificial material of the topmost layer 125 of the multi-layer stack 119. In some embodiments, the method of forming the recess 301 can be to further remove some of the second layers 123 below and adjacent to the topmost layer 125. In some embodiments, the method of forming the recess 301 can employ dry etching and / or wet etching, and the etchant has a greater selectivity for the material of the topmost layer 125 (such as silicon germanium) than for the material of the second layer 123 (such as silicon).

[0107] For example, in an embodiment where the topmost layer 125 is silicon germanium and the second layer 123 is silicon, dry etching such as plasma etching, remote plasma etching, chemical etching or similar methods can be used to remove the topmost layer 125. In some embodiments, the method of removing the topmost layer 125 can introduce a first precursor (such as a main etching gas), a second precursor (such as a passivation gas) and / or a third precursor (such as a dilution gas) to the material of the topmost layer 125 to perform one or more of plasma etching, remote etching and / or chemical etching. The first precursor, the second precursor, and the third precursor can be regarded as an etching environment together. The first precursor can include but is not limited to gases such as chlorine, hydrogen bromide, carbon tetrafluoride, fluoroform, difluoromethane, fluoromethane, hexafluorobutadiene, boron trichloride, sulfur hexafluoride, hydrogen, nitrogen trifluoride, combinations of the above or the like. A second precursor can be added to adjust the selectivity of the etching process, which can include but is not limited to gases such as nitrogen, oxygen, carbon dioxide, sulfur dioxide, carbon monoxide, silicon tetrachloride, combinations of the above or the like. The third precursor can include but is not limited to inert gases such as argon, helium, neon, combinations of the above or the like. In some embodiments, the plasma source power of the dry etching process can be between about 10 watts and about 3000 watts, and the plasma bias power can be between about 0 watts and about 3000 watts. In some embodiments, the process pressure of the dry etching process can be between about 1 mTorr and about 10 mTorr. In some embodiments, the process flow rate of the precursor can be between about 10 sccm and about 5000 sccm. However, any suitable process conditions can be employed.

[0108] In other embodiments, a wet etching process may be performed instead of the dry etching process described above to prepare the structures for subsequent processes. In this embodiment, the wet etching process may use a cleaning solution, and the main etching chemical agent contained therein may be hydrofluoric acid, fluorine gas, or the like. In some embodiments, the cleaning solution may further contain an etching auxiliary chemical agent for selectively adjusting the cleaning solution. The etching auxiliary agent includes but is not limited to chemical agents such as sulfuric acid, hydrogen chloride, hydrogen bromide, ammonia, or the like. In addition, the cleaning solution contains a solvent such as deionized water, alcohols, acetone, or the like to transport the etching chemical agent in the cleaning solution. In some embodiments, the wet etching process may be an immersion process, a spraying process, a spin coating process, or the like. However, any suitable cleaning solution or any suitable process may be used, which is fully included in the scope of the embodiments.

[0109] In some embodiments, an etching process may be used to remove a portion of the sacrificial material and form a recess 301. For example, in some embodiments, the first depth D1 of the recess formed in the multi-layer stack 119 may be between about 0.5 nm and about 30 nm. However, any suitable depth may be used.

[0110] In addition, in some embodiments, an etching process may also be performed to remove a portion of the second layer 123 adjacent to and below the topmost layer 125, so that the size of the recess further extends into the multi-layer stack 119. In some embodiments, the depth to which the recess 301 extends into the second layer 123 may be between about 0.5 nm and about 20 nm. However, any suitable depth may be used.

[0111] Although the above describes the dry etching process and the wet cleaning etching process, these processes are not the only processes for recessing the topmost layer 125. For example, another embodiment for recessing the topmost layer 125 may use a wet etching process, an isotropic dry etching process, or a combination of a wet etching process and an isotropic etching process. Any suitable process may be used to recess the topmost layer 125, and all of these processes are fully included in the scope of the embodiments.

[0112] As Figure 4 shown in some embodiments, an isolation region 401 is formed. Once the dielectric material 107 is filled into the first trench 103 and the sacrificial material is removed, the dielectric material 107 can then be recessed from the surface of the fin 105. The recessing step may be performed to expose at least a portion of the sidewall of the fin 105 adjacent to the upper surface of the fin 105. The fin 105 may be immersed in an etchant such as hydrofluoric acid for wet etching to recess the dielectric material 107, but other etchants such as hydrogen gas may also be used, or other methods such as reactive ion etching, dry etching using etchants such as ammonia and nitrogen trifluoride, chemical oxide removal, or dry chemical cleaning. The dielectric material 107 may be recessed from the surface of the fin 105 by a second distance D2, which is between about to about In addition, the recessing step may also remove other remaining dielectric materials 107 on the fin 105, ensuring that the fin 105 is exposed for subsequent processes.

[0113] As Figure 5 shown in some embodiments, a dummy gate dielectric layer 501 is formed on the exposed portions of the fin 105 and the multi-layer stack 119. Once the isolation region 401 is formed, the dummy gate dielectric layer 501 can be formed, and the forming method can be thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art for forming a gate dielectric layer. In some embodiments, the dummy gate dielectric layer 501 can be formed by depositing a material such as oxygen, followed by oxidizing or nitriding a silicon layer to form a dielectric layer such as silicon oxide or silicon oxynitride. In these embodiments, the thickness of the dummy gate dielectric layer 501 can be between about and about . In other embodiments, the composition of the dummy gate dielectric layer 501 can also be a high-k material such as lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, or a combination of the above, and its equivalent oxide thickness is between about and about . In addition, any combination of silicon oxide, silicon oxynitride, and / or high-k materials can also be used for the dummy gate dielectric layer 501. Depending on the precise forming method, the dummy gate dielectric layer 501 can be selectively formed on the fin 105 (as shown), or deposited conformally on the entire structure.

[0114] As Figure 5 shown in some embodiments, a dummy gate 503 is formed on the dummy gate dielectric layer 501. In some embodiments, the dummy gate 503 can be formed by depositing a conductive material such as polysilicon, tungsten, aluminum, copper, aluminum copper, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, a combination of the above, or the like. The deposition method of the conductive material can be chemical vapor deposition, sputtering deposition, or other techniques known in the art for depositing conductive materials. The thickness of the conductive material can be about to about The conductive material can have an uneven upper surface, and processes such as chemical mechanical polishing can be used to planarize the upper surface of the conductive material before patterning the dummy gate 503 or gate etching. Ions may or may not be introduced into the dummy gate 503 at this time. For example, ions can be introduced by ion implantation techniques.

[0115] Once the conductive material is planarized, the dummy gate dielectric layer 501 and the dummy gate 503 can be patterned. In one embodiment, the patterning step may first form a first hard mask 507 on the dummy gate 503 and a second hard mask 509 on the first hard mask 507. In some embodiments, the first hard mask 507 includes a dielectric material such as silicon nitride, silicon oxide, titanium nitride, silicon oxynitride, a combination of the foregoing, or the like. The formation process of the first hard mask 507 may employ chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar processes.

[0116] However, any other suitable materials and formation methods may be employed. The thickness of the first hard mask 507 may be between about and about .

[0117] The second hard mask 509 comprises a dielectric material different from that of the first hard mask 507. The second hard mask 509 may comprise any material and may be formed using any process suitable for forming the first hard mask 507, and may have the same or a similar thickness as the first hard mask 507. In an embodiment where the first hard mask 507 contains silicon nitride, the second hard mask 509 may be an oxide. However, any suitable dielectric material, process, and thickness may be employed to form the second hard mask.

[0118] Once the first hard mask 507 and the second hard mask 509 are formed, the first hard mask 507 and the second hard mask 509 can be patterned. In one embodiment, the patterning method of the first hard mask 507 and the second hard mask 509 may first apply a photoresist (not shown) on the first hard mask 507 and the second hard mask 509 and expose the photoresist with a patterned energy source (such as light) to initiate a chemical reaction that adjusts the physical properties of the exposed portion of the photoresist. Then a developer is applied to develop the exposed photoresist, and the exposed area or the unexposed area can be selectively removed through the difference in physical properties between the exposed area and the unexposed area.

[0119] Once the photoresist is patterned, the photoresist can be used as a mask to pattern the underlying first hard mask 507 and second hard mask 509. In one embodiment, the method of patterning the first hard mask 507 and the second hard mask 509 may use the photoresist as a mask and perform one or more reactive ion etching processes. The patterning process can be continued until the dummy gate 503 under the first hard mask 507 is exposed.

[0120] Once the first hard mask 507 and the second hard mask 509 are patterned, the photoresist can be removed by methods such as ashing, for example, increasing the temperature of the photoresist until the photoresist thermally decomposes, which can be easily removed by one or more cleaning processes. However, any other suitable removal process may be employed.

[0121] Once the photoresist is removed, the dummy gate 503 and the dummy gate dielectric layer 501 can be patterned using the first hard mask 507 and the second hard mask 509 to form a dummy gate stack 505. In one embodiment, a non-isotropic etching process such as reactive ion etching can be used to pattern the dummy gate 503 and the dummy gate dielectric layer 501, but any suitable process can also be used.

[0122] Although Figure 5 not shown, a first spacer material can be deposited conformally on the exposed surfaces of the dummy gate stack 505 and the structure 100. In this way, the first spacer material can be deposited on the upper surface and sidewalls of the dummy gate stack 505, on the upper surface and sidewalls of the fin 105 and the multilayer stack 119, and on the upper surface of the isolation region 401. In some embodiments, the first spacer material includes a dielectric material, and it can be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, sputtering, thermal oxidation, or any other suitable method. In some embodiments, the materials included in the first spacer material can be silicon oxide, silicon oxynitride, silicon nitride, silicon carbon oxide, silicon carbon oxynitride, any suitable material such as a low-k material with a dielectric constant less than about 4.0, a combination of the above, or the like.

[0123] In some embodiments, the first spacer material can be deposited and patterned to form single or multiple layers of gate spacers 905 (not shown in Figure 5 but will be described below in conjunction with Figure 9 ). Any suitable number of spacer materials and any suitable combination of deposition and removal processes can be used to form the gate spacers 905, and all of these processes are fully within the scope of the embodiments.

[0124] Once the first spacer material is formed, the first spacer material can be patterned to form a plurality of gate spacers 905 (as Figure 9 shown) along the sidewalls of the dummy gate stack 505 and the fin 105, and expose the top of the second hard mask 509 and a portion of the fin 105 that is not covered by the dummy gate dielectric layer 501. In some embodiments, the method of patterning the first spacer material can use a non-isotropic etching process (dry etching process) such as a reactive ion etching process, an isotropic etching process (wet etching process), a combination of the above, or a similar method. In some embodiments, the first spacer material is formed on the fin 105, and the patterning process and / or subsequent etching process can recess the positions where the source / drain regions 901 (as Figure 9 shown) will be formed. In this way, a portion of the sidewall and the upper surface of the fin 105 at the positions where the source / drain regions 901 will be formed can be exposed again.

[0125] Once the fin 105 and the multi-layer stack 119 are re-exposed, the material of the multi-layer stack 119 between the fin 105 and the gate spacer 905 can be recessed to a desired depth to form an opening at the position where the source / drain region 901 is finally formed. In some embodiments, the depth to which the fin 105 and the multi-layer stack 119 are recessed is flush with the top of the isolation region 401. In some embodiments, the depth to which the fin 105 and the multi-layer stack 119 are recessed is lower than the top of the isolation region 401. In some embodiments, the opening at the position where the source / drain region 901 is finally formed extends to a depth in the substrate 101 that can be between about 3 nm and about 40 nm. However, these openings can have any suitable size. In some embodiments, one or more anisotropic etches such as reactive ion etching can be used to form the recesses in the fin 105 and the multi-layer stack 119, but any suitable process can also be used.

[0126] On the sidewalls of these openings used for the source / drain region 901, inner spacers (not shown) can be formed in the first layer 121 of the multi-layer stack 119 as appropriate. The inner spacers formed as appropriate can be formed by first patterning the material of the first layer 121 exposed on the sidewalls of the openings recessed to the source / drain region 901. In some embodiments, wet etching can be used and the etchant has a greater selectivity for the material of the first layer 121 (such as silicon germanium) than for the material of the second layer 123 or the substrate 101 (such as silicon) to form a recess in the first layer 121. For example, in one embodiment, the first layer 121 is silicon germanium and the second layer 123 is silicon, then the wet etching can use an etchant such as hydrogen chloride. However, any suitable materials and etchants can be used.

[0127] In one embodiment, the etching process can be an immersion process, a spraying process, a spin coating process, or a similar process, and any suitable process temperature (such as between about 400 °C and about 600 °C) and any suitable process time (such as between about 100 seconds and about 1000 seconds, for example about 300 seconds) can be used. However, any suitable process conditions and parameters can be used. The etching process can be continued so that recesses are formed in each first layer 121 and are recessed from the sidewalls of the openings to a desired distance. In some embodiments, the recesses formed in each first layer 121 have a surface limited by crystal planes.

[0128] However, the wet etching process is not the only process for recessing the first layer 121. For example, in another embodiment, the method for recessing the first layer 121 can be an isotropic dry etching process or a combination of a dry etching process and a wet etching process. Any suitable process can be used to recess the first layer 121, and these processes are fully within the scope of the embodiments.

[0129] Once a recess is formed in each first layer 121, a second spacer material can be formed on the structure 100. In some embodiments, the second spacer material can be different from the material of the gate spacer 905 and can be a silicon-containing dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, or silicon oxycarbide. However, any suitable material such as a low dielectric constant material with a dielectric constant lower than about 4.0, or even an air gap, or a combination of the above can also be used. The deposition method of the second spacer material can employ deposition processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the deposition thickness can be between about 2 nm and about 10 nm. However, any suitable thickness or deposition process can be used.

[0130] By depositing the second spacer material on the structure 100, the second spacer material will line the sidewalls of the openings in the positions where the source / drain regions 901 are to be padded and can also fill the recesses in the first layer 121. Once the second spacer material is filled into the recesses, a removal process can be performed to remove any excess second spacer material from the openings and retain the optionally formed inner spacers. In one embodiment, an etching process such as an anisotropic dry etching process such as a reactive ion etching process can be used to remove the excess second spacer material. However, any suitable etching process can be used to remove the excess second spacer material from the openings and retain the optionally formed inner spacers.

[0131] By filling the second spacer material into the recesses and removing the excess second spacer material from the openings, the optionally formed inner spacers conform to the shape of the recesses. Any suitable shape such as a convex shape or a concave shape can be used, and even the optionally formed inner spacers can be recessed. All of these shapes are fully within the scope of the embodiments. In some embodiments, the width of the optionally formed inner spacers can be between about 2 nm and about 10 nm, and the height can be between about 5 nm and about 20 nm. In addition, the distance between the optionally formed inner spacers can be between about 3 nm and about 10 nm. However, any suitable width, height, and separation distance can be used.

[0132] Once the openings and / or the optionally formed inner spacers are formed, the source / drain regions 901 can be formed in the openings. The source / drain regions 901 can be formed by a growth process such as selective epitaxy and a semiconductor material suitable for forming the desired device. For example, in embodiments where the source / drain regions 901 are used to form n-type metal oxide semiconductor devices, the source / drain regions 901 can be semiconductor materials such as silicon, silicon phosphide, silicon carbon phosphide, a combination of the above, or the like.

[0133] The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, or the like, and may last for about 5 minutes to about 120 minutes. In some embodiments, the height of the source / drain region 901 is between about 30 nm and about 90 nm. However, any suitable height and / or depth may be employed. Additionally, the epitaxial growth in some embodiments may extend beyond the initial dimensions of the fin 105 and / or the multi-layer stack 119. In this way, in some embodiments, the epitaxial growth associated with one or more fins 105 or with one of the multi-layer stacks 119, and the epitaxial growth associated with another fin 105 or with another multi-layer stack 119 may be carried out together. Furthermore, one or more epitaxial growths associated with the device region 120, the first multi-channel device region 130, and / or the second multi-channel device region 140 may be carried out together to form a single epitaxial growth region. However, these device regions may also be grown as separate epitaxial growth regions.

[0134] Once the source / drain region 901 is formed, a suitable doping may be implanted into the source / drain region 901 to complete the doping in the remaining part of the first device region. For example, an n-type doping such as phosphorus, carbon, arsenic, silicon, antimony, the like, or a combination of the above (such as silicon phosphide, silicon carbide, carbon silicon phosphide, silicon arsenide, silicon, antimony, or the like) may be implanted to form an n-type metal oxide semiconductor field effect transistor device. The method of implanting these dopings may use the dummy gate stack 505 and the gate spacer 905 as masks.

[0135] In another embodiment, the doping may be placed into the source / drain region 901 during the epitaxial growth of the source / drain region 901. For example, phosphorus may be in-situ implanted when the source / drain region 901 is formed. Any suitable process may be used to place the doping into the source / drain region 901, and all of these processes are fully within the scope of the embodiments. Additionally, annealing may be performed to activate the doping in the source / drain region 901. During the annealing process, the doping in the source / drain region 901 may laterally diffuse into the second layer 123 at the interface between the second layer 123 and the source / drain region 901. In this way, a lightly doped drain region may be formed in the second layer 123.

[0136] Once the source / drain region 901 is formed, a contact etch stop layer 903 (such as Figure 9 shown) may be formed on the source / drain region 901 and other exposed surfaces of the structure 100. The contact etch stop layer 903 may serve as an etch stop layer in subsequent etching processes and may include suitable materials such as silicon nitride, silicon oxynitride, silicon carbonitride, a combination of the above, or the like. The method of forming the contact etch stop layer 903 may be a suitable deposition process, such as chemical vapor deposition, physical vapor deposition, a combination of the above, or a similar process.

[0137] Once the contact etch stop layer 903 is formed, an interlayer dielectric layer 907 can be formed on the contact etch stop layer 903, as Figure 9 shown. In some embodiments, the interlayer dielectric layer 907 comprises materials such as silicon oxide, low dielectric constant dielectric materials (such as materials with a dielectric constant lower than that of silicon oxide) such as silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, organosilicate glass, silicon oxycarbide, spin-on glass, spin-on polymer, silicon carbide materials, compounds of the foregoing, composites of the foregoing, analogs, or combinations of the foregoing, but any suitable dielectric material can also be employed. The process for forming the interlayer dielectric layer 907 can use plasma-assisted chemical vapor deposition, but other processes such as low-pressure chemical vapor deposition can also be used.

[0138] Once the interlayer dielectric layer 907 is formed, a planarization process such as chemical mechanical polishing can be used to planarize the interlayer dielectric layer 907, the contact etch stop layer 903, the dummy gate 503, and the gate spacer 905. However, any suitable planarization process can be used. Additionally, the first hard mask 507 and the second hard mask 509 can be removed during the planarization process. In some embodiments, one or more etching processes and / or chemical mechanical polishing processes can be used to remove the first hard mask 507 and the second hard mask 509. In this way, the dummy gate 503 can be exposed after removing the first hard mask 507.

[0139] As Figure 6 shown, the dummy gate 503 and the dummy gate dielectric layer 501 are removed. Figure 6 It is also shown that in some embodiments, the second layer 123 is removed during the circuit release process. In one embodiment, once the dummy gate 503 is exposed, the dummy gate 503 can be removed to expose the underlying dummy gate dielectric layer 501. In one embodiment, the method for removing the dummy gate 503 can use one or more wet etching processes or dry etching processes that use an etchant selective to the material of the dummy gate 503. However, any suitable removal process can be used.

[0140] Once the dummy gate dielectric layer 501 is exposed, the dummy gate dielectric layer 501 can be removed. In one embodiment, the method for removing the dummy gate dielectric layer 501 can use a wet etching process. However, any suitable etching process can be used.

[0141] As Figure 6As shown, once the dummy gate dielectric layer 501 is removed and the side portions of the first layer 121 are exposed, the first layer 121 can be removed from between the second layers 123 by a line release process step. The line release process step can also be regarded as a sheet release process step, a sheet formation process step, a nanosheet formation process step, or a line formation process step. In one embodiment, a wet etching process can be used to remove the first layer 121, which can selectively remove the material (such as silicon germanium) of the first layer 121 without significantly removing the materials (such as silicon) of the fins 105 and the second layers 123. However, any suitable removal process can be used.

[0142] For example, an etchant used in one embodiment such as high-temperature hydrogen chloride can selectively remove the material (such as silicon germanium) of the first layer 121 without substantially removing the materials (such as silicon) of the fins 105 and / or the second layers 123. In addition, the temperature of the wet etching process can be between about 400°C and about 600°C, and the time can be between about 100 seconds and about 600 seconds. However, any suitable etchant, process parameters, and time can be used.

[0143] By removing the material of the first layer 121, the side portions of the second layers 123 can be exposed (re-labeled as Figure 6 the nanostructures 601 in). The nanostructures 601 can be arranged in a nanostructure stack 603 and are separated from each other by inner spacers (as described above) formed as appropriate in the recesses of the first layer 121. The inner spacers formed as appropriate can prevent the nanostructures from cracking during the line release process. In some embodiments, the nanostructures 601 are separated by a first space S1, which is between about 3 nm and about 20 nm. The nanostructures 601 include a channel region that extends between the source / drain regions 901 and is formed at the distal ends of the nanostructures 601. The channel length of the nanostructures 601 is between about 5 nm and about 180 nm. In one embodiment, the thickness of the nanostructures 601 is the same as the initial thickness of the second layers 123, such as between about 3 nm and about 15 nm. However, an etching process can also be used to reduce the thickness of the second layers 123.

[0144] As Figure 7A and Figure 7B shown in some embodiments, a first interface treatment 700 can form a first gate dielectric layer 707 on the exposed surfaces of the nanostructures 601 and the fins 105 and adjust their interfaces. In some embodiments, during the first interface treatment 700, the device region 120 can be protected by a protective material 701 (such as a photoresist). Once the device region 120 is protected, the first interface treatment 700 can be performed on the first multi-channel device region 130 and the second multi-channel device region 140. In some embodiments, the first interface treatment 700 includes a selective adjustment process, followed by a wet cleaning process and the deposition of a gate dielectric material.

[0145] The first interface treatment 700 can be used to control the formation and thickness of the first gate dielectric layer 707 of the topmost channel 703 and the retention channel 705 of the nanostructure stack 603. In some embodiments, the selective adjustment process employs a dry etching process such as plasma etching, remote plasma etching, chemical etching, a combination of the foregoing, or a similar process. The selective adjustment process is performed using a first precursor (such as a passivation gas) and a second precursor (such as a dilution gas) to selectively adjust the nanostructures 601 in the nanostructure stack 603. The first precursor may include, but is not limited to, gases such as nitrogen, oxygen, carbon dioxide, sulfur dioxide, carbon monoxide, silicon tetrachloride, hydrogen, a combination of the foregoing, or the like. The second precursor includes, but is not limited to, inert gases such as argon, helium, neon, a combination of the foregoing, or the like. The plasma source power used in the selective adjustment process ranges from about 10 watts to about 3000 watts, and the plasma bias power ranges from about 0 watts to about 3000 watts. In some embodiments, the process pressure of the selective adjustment process can range from about 1 mTorr to about 10 Torr. Additionally, the process flow rate of the selective adjustment process in some embodiments can range from about 1 sccm to about 5000 sccm.

[0146] In another embodiment, the first interface treatment 700 is a wet etching process such as a wet cleaning process, which can replace or be used in conjunction with the foregoing dry etching process. In some embodiments, the wet etching process can employ an etching aid and a solvent in a process (such as an immersion process, a spraying process, a spin coating process, or a similar process). The etching aid can be used to assist in selectively adjusting the thickness of the first gate dielectric layer 707. In some embodiments, the etching aid includes, but is not limited to, chemicals such as sulfuric acid, ozone, ammonia, a combination of the foregoing, or the like. During the wet cleaning process, the solvent is used to transport the etching aid. In some embodiments, the solvent includes, but is not limited to, deionized water, alcohols, acetone, a combination of the foregoing, or the like.

[0147] Once the wet cleaning process is performed in some embodiments, a gate dielectric deposition process can be carried out. The gate dielectric deposition process can use materials such as silicon nitride, silicon oxynitride, carbon oxynitride, silicon carbide, silicon oxycarbide, silicon dioxide, a combination of the foregoing, to form the first gate dielectric layer 707 on the surface of the nanostructures 601 and on the fins 105 of the nanostructure stack 603. In some embodiments, the method of the gate dielectric deposition process can employ a deposition process such as chemical vapor deposition, atomic layer deposition, a combination of the foregoing, or a similar process.

[0148] Figure 7BIn the first embodiment, an enlarged view of the first gate dielectric layer 707 formed on the nanostructure stack 603 in the first multi-channel device region 130 and the second multi-channel device region 140. In the first embodiment, the structure can be simply exposed to an oxygen-containing environment such as the atmosphere to form the first gate dielectric layer 707 such as a native oxide layer. In other embodiments, the first gate dielectric layer 707 can be formed by using one or more deposition processes, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, a combination of the above, or similar processes.

[0149] In addition, by controlling the number of deposition cycles and / or the time of each deposition cycle of the first interface treatment 700, a non-conforming treatment can be performed. In this way, the first gate dielectric layer 707 at the interface of the topmost channel 703 has a first thickness Th1, and the first gate dielectric layer 707 at the interface of the remaining channel 705 has a second thickness Th2, and the first thickness Th1 is greater than the second thickness Th2. The first interface treatment 700 can be performed in a single deposition cycle or multiple deposition cycles. In some embodiments, the number of deposition cycles used in the first interface treatment 700 can be between about 1 time and about 500 times. In some embodiments, the time of each deposition cycle can be between about 0.2 seconds and about 100 seconds. The number of deposition cycles and the time of each deposition cycle also depend on the chamber volume used. For example, compared with the time required to reach the deposition steady state in a larger-volume chamber (such as between about 10 seconds and about 100 seconds), the time to reach the deposition steady state in a smaller-volume chamber is faster (such as less than about 10 seconds). In some embodiments, the first thickness Th1 of the first gate dielectric layer 707 is between about and about In addition, the second thickness Th2 in some embodiments can be between about and about between.

[0150] Once the first interface treatment 700 is completed, the protective material 701 can be removed from the device region 120. In some embodiments, the protective material 701 can be removed by a suitable removal process. For example, in an embodiment where the protective material 701 is a photoresist, an ashing technique and a cleaning process can be used to remove the protective material 701. However, any suitable removal process can be used.

[0151] As Figure 8 shown, the second gate dielectric layer 803 and the gate 805 of the integrated circuit device 800 are formed. Figure 8Also shown is a portion 807 of the integrated circuit device 800. In some embodiments, a method of forming the second gate dielectric layer 803 on the fin 105 in the device region 120 may first provide a protective layer on the first multi-channel device region 130 and the second multi-channel device region 140. In some embodiments, any material and process suitable for forming the above-described protective material 701 may be employed to form the protective layer. However, any other suitable material and process may also be used to form the protective layer.

[0152] Once the first multi-channel device region 130 and the second multi-channel device region 140 are protected, the second gate dielectric layer 803 may be formed on the fin 105 in the device region 120. Any material and process (such as a deposition process) used to form the first gate dielectric layer 707 may be employed to form the second gate dielectric layer 803. In some embodiments, the second gate dielectric layer and the first gate dielectric layer 707 may have the same material composition. In other embodiments, the material of the second gate dielectric layer 803 is different from the material of the first gate dielectric layer 707.

[0153] In one embodiment, the second gate dielectric layer 803 is conformally deposited on the fin 105 in the device region 120, such as on the upper surface and sidewalls of the fin 105. The second gate dielectric layer 803 may also be formed on the upper surface of the interlayer dielectric layer 907, as Figure 9 shown. In some embodiments, the second gate dielectric layer 803 includes silicon oxide, silicon nitride, or a multi-layer of the above. In some embodiments, the second gate dielectric layer 803 includes a high-k (such as a dielectric constant greater than 7.0) dielectric material, which may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or a combination of the above. The method of forming the second gate dielectric layer 803 may include atomic layer deposition, plasma-assisted chemical vapor deposition, molecular beam deposition, or similar methods. However, any suitable material and forming method may be used to form the second gate dielectric layer 803. However, the second gate dielectric layer 803 may be formed using any suitable material and forming method. In some embodiments, the second gate dielectric layer 803 on the fin 105 in the device region 120 may have a third thickness Th3. In some embodiments, the first thickness Th1 is between about and about However, the second gate dielectric layer 803 may have any suitable thickness. Once the second gate dielectric layer 803 is formed, the protective layer may be removed from the first multi-channel device region 130 and the second multi-channel device region 140.

[0154] The gate 805 is formed on the second gate dielectric layer 803 of the device region 120, and is formed on and surrounds the first gate dielectric layer 707 of the first multi-channel device region 130 and the second multi-channel device region 140. The gate 805 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, tantalum, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although Figure 8 and Figure 9 The gate 805 is a single layer, but the gate 805 may include any number of liner layers, any number of work function adjustment layers and / or filling materials. After depositing the material of the gate 805, a planarization process such as chemical mechanical polishing may be performed to remove the second gate dielectric layer 803, the first gate dielectric layer 707, and the excess portion of the gate 805 on the upper surface of the interlayer dielectric layer 906. In some embodiments, the first height H1 of the gate 805 may be between about 20 nm and about 280 nm. However, the gate 805 may adopt any suitable height.

[0155] Therefore, in some embodiments, the gate 805, the first gate dielectric layer 707, and the second gate dielectric layer 803 can together form a single replacement gate (e.g., a common gate) of the final active component (e.g., a fin field effect transistor device or the like) and the final multi-channel device (e.g., a nanosheet field effect transistor device, a fully wrapped gate field effect transistor device or the like) of the integrated circuit device 800. The gate 805, the first gate dielectric layer 707, and the second gate dielectric layer 803 can be collectively considered as a common gate stack 809.

[0156] Figure 8 A common gate stack 809 having a first critical dimension CD1 is further shown, which is located on the fin 105 in the device region 120. In some embodiments, the distance of the first critical dimension CD1 may be between about to about between.

[0157] like Figure 8 As shown, the common gate stack 809 on the topmost channel 703 in the first multi-channel device region 130 has a second critical dimension CD2, and the common gate stack 809 on the topmost channel 703 in the second multi-channel device region 140 has a third critical dimension CD3. The second critical dimension CD2 and the second critical dimension CD3 may be greater than the first critical dimension CD1. In some embodiments, the second critical dimension CD2 and the third critical dimension CD3 may each be between about to about In some embodiments, the third critical dimension CD3 and the second critical dimension CD2 may be substantially the same, but may also be different.

[0158] Figure 9Perspective view of a portion 807 of an integrated circuit device 800 in some embodiments. In a specific embodiment, Figure 9 The fins 105 of the display device region 120 are separated from the fins 105 of the first multi-channel device region 130 by an isolation region 401. Figure 9 Further shown are a first gate dielectric layer 707, a second gate dielectric layer 803, and a gate 805 on the first gate dielectric layer 707 and the second gate dielectric layer 803. Figure 9 Also shown are a source / drain region 901, a gate spacer 905, a contact etch stop layer 903, and an interlayer dielectric layer 907 on the isolation region 401, and separating a first instance and a second instance of the gate 805 in the integrated circuit device 800.

[0159] Figure 10 Drawing of a gate dielectric deposition process 1000 in some embodiments. The gate dielectric deposition process 1000 can be combined with or separated from the first interface treatment 700 to form an outer gate dielectric layer 1001 on and surrounding the first gate dielectric layer 707 of the topmost channel 703. In this way, a composite gate dielectric layer 1003 can be formed to surround the nanostructure 601 of the topmost channel 703.

[0160] In some embodiments, the composition of the outer gate dielectric layer 1001 can be silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbide, silicon oxide, a combination of the above, or the like. However, any suitable material can be used. The outer gate dielectric layer 1001 can be formed on the first gate dielectric layer 707 to a fourth thickness Th4, which can be formed by deposition methods such as chemical vapor deposition, atomic layer deposition, a combination of the above, or similar methods. In some embodiments, the fourth thickness Th4 is between about and about In some embodiments, the sum of the first thickness Th1 of the first gate dielectric layer 707 and the fourth thickness Th4 of the outer gate dielectric layer 1001 can be between about and about However, the outer gate dielectric layer 1001 can be formed using any suitable deposition method and thickness.

[0161] Figure 11A In the cross-sectional view shown, some other embodiments of the integrated circuit device 800 include two cut metal gate structures 1101. The cut metal gate structures 1101 can divide a common gate stack 809 into multiple isolated gate stack structures, which include a first isolated gate stack 1103 of the device region 120, a second isolated gate stack 1105 of the first multi-channel device region 130, and a third isolated gate stack 1107 of the second multi-channel device region 140. Although Figure 11ATwo cut metal gate structures 1101 are shown, but any suitable number of cut metal gate structures 1101 can be formed to divide the common gate stack 809 into any suitable number or any suitable combination of isolated gate structures and / or common gate structures. For example, a cut metal gate structure 1101 can be formed at the interface between the device region 120 and the first multi-channel device region 130 to divide the common gate stack 809 into a first isolated gate stack 1103 of the device region 120 and a common gate stack structure on the first multi-channel device region 130 and the second multi-channel device region 140. In another example, a cut metal gate structure 1101 can be formed at the interface between the first multi-channel device region 130 and the second multi-channel device region 140 to divide the common gate stack 809 into a third isolated gate stack 1107 of the second multi-channel device region 140 and a common gate stack structure on the device region 120 and the first multi-channel device region 130. Figure 11A Also shown is a second portion 1109 of the integrated circuit device 800, which is emphasized by a dashed line and includes a cut metal gate structure 1101 at the interface between the device region 120 and the first multi-channel device region 130.

[0162] Figure 11B Shown Figure 11A is a perspective view of the second portion 1109 of the integrated circuit device 800. Specifically, Figure 11B shown in some embodiments is a cut metal gate structure 1101 at the interface between the device region 120 and the first multi-channel device region 130.

[0163] A method of forming the cut metal gate structure 1101 can be to first deposit a mask layer on the flat surfaces of the gate 805, the interlayer dielectric layer 907, the contact etch stop layer 903, and the gate spacer 905. Once the mask layer is deposited, the mask layer can be patterned to expose the underlying material at the desired locations where the cut metal gate structure 1101 is to be formed.

[0164] Once the patterned mask layer serves as an etch mask, the underlying material can be etched to form a second opening (such as a trench, recess, channel, or the like) at a desired location for cutting the metal gate structure 1101 (such as at the interface between the device region 120 and the first multi-channel device region 130). In the etching process, one or more anisotropic etching processes are used to etch the materials of the gate 805, the gate spacer 905, the contact etch stop layer 903, and / or the interlayer dielectric layer 907, which can stop at the upper surface of the first gate dielectric layer 707, the second gate dielectric layer 803, or the isolation region 401. In some embodiments, between the source / drain regions 901 of adjacent devices (such as the device region 120 and the first multi-channel device region 130), the etching process can continuously etch the second opening into the isolation region 401 but not through the isolation region 401. In other embodiments, between the source / drain regions 901 of adjacent devices, the continuous etching process can be used to etch the second opening through the isolation region 401 into the substrate 101. The second opening can cut through one or more gates 805. In some embodiments, the second opening can divide the gate spacer 905 and the interlayer dielectric layer 907 into two separate gate spacers 905 and two separate interlayer dielectric layers 907 for two adjacent devices (such as the device region 120 and the first multi-channel device region 130). Once the second opening is formed, the mask layer can be removed.

[0165] Once the second opening is formed, a dielectric material 1111 can be deposited first to fill and overfill the second opening to form the cut metal gate structure 1101. In some embodiments, the composition of the cut metal gate structure 1101 can use dielectric materials such as silicon nitride, oxide, silicon oxynitride, carbon oxynitride, carbon nitride, or the like. In some embodiments, the composition of the cut metal gate structure 1101 can use metal oxides such as oxides of zirconium, hafnium, aluminum, or the like. In addition, the method for forming the cut metal gate structure 1101 can use a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of the above, or a similar method. However, any suitable material and deposition process can be used. In some embodiments, the fourth width W4 of the cut metal gate structure 1101 is between about 5 nm and about 50 nm. However, any suitable width can be used.

[0166] The cut metal gate structure can divide the longer common gate stack 809 into shorter multiple gates and isolate the multiple gates from each other. In addition, processes such as chemical mechanical polishing can be used to planarize the excess dielectric material of the cut metal gate structure 1101, the gate 805, the gate spacer 905, the contact etch stop layer 903, and the interlayer dielectric layer 907 outside the second opening.

[0167] In some other embodiments, a cut dummy gate structure (not shown) may be formed as appropriate to replace or cooperate with the cut metal gate structure 1101. In some embodiments, dummy fins (not shown) located between one or more device regions 120, the first multi-channel device region 130, and the second multi-channel device region 140 may be employed to form a cut dummy gate structure as appropriate. In other embodiments, the method of forming a cut dummy gate structure as appropriate may not employ dummy fins.

[0168] As Figure 1 and Figure 2 shown in some embodiments, the method of forming a cut dummy gate structure formed as appropriate may be to first form sacrificial fins (not shown) between one or more device regions 120, the first multi-channel device region 130, and the second multi-channel device region 140. The method of forming the sacrificial fins may be similar to the method of forming the fins 105 in the device region 120, the multi-layer stack 119 and the fins 105 in the first multi-channel device region 130, the multi-layer stack 119 and the fins 105 in the second multi-channel device region 140, the above combinations, or the like.

[0169] As Figure 2 shown, once the sacrificial fins (not shown) are formed, a dielectric material 107 may be deposited on the sacrificial fins and the dielectric material 107, the sacrificial fins, the fins 105 in the device region 120, the multi-layer stack 119 and the fins 105 in the first multi-channel device region 130, and the multi-layer stack 119 and the fins 105 in the second multi-channel device region 140 may be planarized, such as in a similar process as above. Once the dielectric material 107 is formed, the sacrificial fins (not shown) may be removed and replaced with dummy fins (also not shown). In these embodiments, one or more acceptable etching processes are employed to remove at least a portion of the sacrificial fins. Thus, an opening may be formed in the dielectric material 107 between one or more device regions 120, the first multi-channel device region 130, and / or the second multi-channel device region 140. In some embodiments, the sacrificial fins may be completely removed. In other embodiments, a portion of the sacrificial fins may be retained at the bottom of the opening and exposed in the opening. Once the sacrificial fins are removed in a subsequent process, dummy fins may be formed in the opening.

[0170] In some embodiments, the dummy fins may comprise one or more layers of silicon-based materials (such as silicon nitride, silicon oxynitride, carbon oxynitride, silicon carbide, silicon oxide, or the like), metal-based materials (such as metal oxides, metal nitrides, or the like such as tantalum nitride, tantalum oxide, hafnium oxide, or the like), and / or the like. The dummy fins may be a single material or a multi-layer material (which may be stacked vertically and / or horizontally). In some embodiments, the width of the dummy fins may be about to about

[0171] The method of forming dummy fins can employ one or more deposition processes, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition, atomic layer deposition, physical vapor deposition, or similar processes. In embodiments where the dummy fins include multiple material layers, the method of forming the dummy fins may also include one or more etch-back and / or planarization steps before depositing additional material of the dummy fins. Additionally, the dummy fins can be deposited to first cover the isolation material, and planarization, etch-back, or similar processes can be used to remove the excess portion of the dummy fins and expose the dielectric material 107.

[0172] As Figure 2 shown, other methods may not require forming sacrificial fins first to form the dummy fins. In other embodiments, a conformal process can be used to deposit the dielectric material 107, only partially filling the space between the fins 105 in the device region 120, the fins 105 in the first multi-channel device region 130, and / or the fins 105 in the second multi-channel device region 140. The conformal deposition process can define openings in the partially filled space on the dielectric material 107. One or more materials and processes for forming the dummy fins can be used to subsequently fill the openings defined in the partially filled space and planarize the dummy fins and the dielectric material 107. In this way, the dummy fins can be located between the fins 105 in the device region 120, the fins 105 in the first multi-channel device region 130, and / or the fins 105 in the second multi-channel device region 140, and the dummy fins can be buried in the dielectric material 107. For example, the dielectric material 107 can contact the lower surface and sidewalls of the dummy fins.

[0173] As Figure 3 and Figure 4 shown, once the dummy fins (not shown) are formed using the above method, the dielectric material 107 can be etch-back to define the shallow trench isolation region 401. In this way, the dummy fins above the shallow trench isolation region 401, the fins 105 in the device region 120, the fins 105 in the first multi-channel device region 130, and / or the fins 105 in the second multi-channel device region 140 can be exposed. The method used for etch-back of the dielectric material 107 can be similar to the above processes and one or more precursors described in conjunction with Figure 4 and one or more precursors are more selective for the dielectric material 107 and less selective for the material of the dummy fins. In summary, other embodiments can complete the method of forming the dummy fins.

[0174] As Figure 5In the illustrated embodiment with dummy fins (not shown), in addition to forming a dummy gate dielectric layer 501 on the fins 105 in the device region 120, the first multi-channel device region 130, and / or the second multi-channel device region 140, the dummy gate dielectric layer 501 can also be formed on the exposed surface of the dummy fins. Once the dummy gate dielectric layer 501 is formed, a dummy gate 503, a first hard mask 507, and a second hard mask 509 can be formed on the dummy gate dielectric layer 501 and patterned into a dummy gate stack 505, as described above. In addition, once the dummy gate stack 505 is formed, a plurality of gate spacers 905 (as shown in Figure 9 ) can be patterned along the sidewalls of the dummy gate stack 505, as described above. Once the gate spacers 905 are patterned, source / drain regions 901, a contact etch stop layer 903, and an interlayer dielectric layer 907 can be formed, and the above structures and the dummy gate 503 can be planarized, as described above.

[0175] As Figure 5 shown, in an embodiment including dummy fins (not shown), an opening (also not shown) can be formed in the dummy gate 503. In some embodiments, the opening can be aligned with the dummy fins and directly located on the dummy fins. For example, a combination of lithography and etching can form an opening in the dummy gate 503. The opening can expose the sidewalls of the gate spacers 905. In addition, one or more parameters of the etching process used to form the opening (such as etching time or similar parameters) can be adjusted to control the depth to which the opening extends into the dummy gate 503.

[0176] In some embodiments, the method of etching an opening in the dummy gate 503 includes a plasma process such as plasma etching, remote plasma process, radical etching, or a similar process. The etching gas used in the plasma process can include chlorine, hydrogen bromide, carbon tetrafluoride, fluoroform, difluoromethane, fluoromethane, hexafluorobutadiene, boron trichloride, sulfur hexafluoride, hydrogen, a combination of the above, or the like. The plasma process also includes flowing a passivation gas over the structure 100 to adjust (such as increase) the etching selectivity between the dummy gate 503 and other structures of the structure 100. Examples of the passivation gas can include nitrogen, oxygen, carbon dioxide, sulfur dioxide, carbon monoxide, silicon tetrachloride, a combination of the above, or the like. One or more carrier gases, such as argon, helium, neon, a combination of the above, or the like, can be used in the plasma process. In addition, the plasma source power of the plasma process can be from about 10 watts to about 3000 watts, the bias power can be from about 0 watts to about 3000 watts, the pressure can be from about 1 mTorr to about 800 mTorr, and the gas mixture flow rate can be from about 10 sccm to about 5000 sccm.

[0177] In some embodiments, the step of etching the opening in the dummy gate 503 includes a wet etching process (sometimes regarded as wet cleaning). Examples of the etchant used in the wet etching process may include hydrofluoric acid, fluorine gas, combinations of the above, or the like. The wet etching process may further introduce an auxiliary etching chemical onto the structure 100 to adjust (e.g., increase) the etching selectivity between the dummy gate 503 and other structures of the structure 100. Examples of the auxiliary etching chemical may include chemicals such as sulfuric acid, hydrogen chloride, hydrogen bromide, ammonia, combinations of the above, or the like. Deionized water, alcohols, acetone, or the like may be used as solvents to mix the etchant and / or the auxiliary etching chemical during the wet etching process.

[0178] In some embodiments, a processing process is applied to the structure 100, such as the sidewalls and the lower surface of the opening in the dummy gate 503. The processing process may form a passivation region (not shown) on the sidewalls and the lower surface of the opening in the dummy gate 503. In some embodiments, a passivation region may also be formed in the gate spacer 905. Although not shown herein, the processing process may further form a passivation region in other exposed surfaces of the structure 100, such as the upper surface of the dummy gate 503 and the upper surface of the interlayer dielectric layer 907. These passivation regions may be removed in subsequent process steps to shape the profile of the opening in the dummy gate 503.

[0179] The processing process may be a conversion process that can convert the exposed portions of the dummy gate 503 into passivation regions and convert the exposed portions of the gate spacer 905 into passivation regions. The processing process for the etching process may be performed in-situ (in the same process chamber) or ex-situ (in different process chambers) to form an opening in the dummy gate 503. The individual thickness of each passivation region may be about to about

[0180] In some embodiments, the processing process includes a plasma process such as plasma implantation or a similar process. The passivation gas used in the plasma process may include nitrogen, oxygen, carbon dioxide, sulfur dioxide, carbon monoxide, combinations of the above, or the like. The plasma process may further introduce additional gases such as hydrocarbon-based gases (e.g., methane), silicon-based gases (e.g., silicon tetrachloride), combinations of the above, or the like to assist in forming the passivation region. In addition, the power of the plasma-generated electrical source may be about 10 watts to about 3000 watts, the bias power may be about 0 watts to about 3000 watts, the pressure may be about 1 mTorr to about 800 mTorr, and the gas mixture flow rate may be about 10 sccm to about 5000 sccm.

[0181] In some embodiments, the processing technology is non - plasma dry chemical processing, which uses processing gases such as hydrofluoric acid, nitrogen trifluoride, methane, combinations thereof, or the like. In some embodiments, the processing technology is a wet processing technology, and the solution used therein contains deionized water, ozone, carbon dioxide, hydrofluoric acid, hydrogen chloride, ammonia, combinations thereof, or the like. In some embodiments, the processing technology can be a deposition process that reacts with the existing materials of the dummy gate 503 and the gate spacer 905, and also deposits a dielectric material (such as silicon nitride, silicon oxynitride, carbon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, silicon carbide, combinations thereof, or the like) on the opening surfaces in the dummy gate 503 and the gate spacer 905. In these embodiments, the passivation region includes the reaction region of the dummy gate 503, the reaction region of the gate spacer 905, and the deposited dielectric material. Examples of the deposition process can include atomic layer deposition process, chemical vapor deposition process, combinations thereof, or the like.

[0182] Since the materials of the dummy gate 503 and the gate spacer 905 are different, the material compositions of the passivation regions of the dummy gate 503 and the gate spacer 905 can be different. For example, in an embodiment where the processing technology uses nitrogen and the gate spacer 905 contains oxygen, the passivation region in the dummy gate 503 can contain silicon and nitrogen, while the passivation region in the gate spacer 905 can contain silicon, oxygen, and nitrogen. In another example, if the processing technology uses oxygen and the gate spacer 905 contains nitrogen, the passivation region in the dummy gate 503 can contain silicon and oxygen, while the passivation region in the gate spacer 905 can contain silicon, oxygen, and nitrogen. In another example, if the processing technology uses nitrogen and the gate spacer 905 contains nitrogen, the nitrogen concentration in the passivation region of the dummy gate 503 can be lower than the nitrogen concentration in the passivation region of the gate spacer 905. In another example, if the processing technology uses oxygen and the gate spacer 905 contains oxygen, the oxygen concentration in the passivation region of the dummy gate 503 can be lower than the oxygen concentration in the passivation region of the gate spacer 905. In summary, the processing technology forms two different passivation regions, such as the passivation region in the dummy gate 503 and another passivation region in the gate spacer 905, and an etch selectivity can be achieved between the two different passivation regions. An etch selectivity can also be achieved between the passivation region in the gate spacer 905 and the rest of the gate spacer 905.

[0183] Once an opening is formed in the dummy gate 503 and / or a passivation region is formed in the dummy gate 503 and the gate spacer 905, an additional etching process can be performed on the dummy gate 503, which can further extend the opening towards the dummy fin (if any) and the semiconductor substrate 101. In some embodiments, the opening in the dummy gate 503 can be extended to expose the dummy fin (if any) or the substrate 101 of the semiconductor (if there is no dummy fin).

[0184] The etching process is selective between the passivation region material in the gate spacer 905 and the material of the gate spacer 905, enabling the etching process to remove the passivation region in the gate spacer 905 while substantially not removing the remaining material of the gate spacer 905. For example, the rate at which the etching process removes the passivation region material in the gate spacer 905 is greater than the rate at which it removes the remaining material of the gate spacer 905. In this way, the width of the upper side portion of the opening in the dummy gate 503 can be greater than the width of the lower side portion of the opening in the dummy gate 503.

[0185] In addition, the etching process can be a directional process that can remove the passivation region from the lower surface of the opening in the dummy gate 503 without significantly removing the passivation region along the sidewalls of the opening. In some embodiments, the etching process can be selective between the passivation region material in the dummy gate 503 and the passivation region material in the gate spacer 905. In this way, the passivation region material in the gate spacer 905 along the sidewalls of the opening can be removed without significantly removing the passivation region material in the dummy gate 503 along the sidewalls of the opening. In this way, the profile of the opening in the dummy gate 503 can be shaped to expand and maintain the effective gate width of the dummy gate 503 (and the corresponding replacement metal gate), thereby improving the device performance of the final device.

[0186] In some embodiments, the method of removing the passivation region in the gate spacer 905 and expanding the opening in the dummy gate 503 can include a plasma process such as plasma etching, remote plasma process, radical etching, or similar methods. The etching gas used in the plasma process can include chlorine gas, hydrogen bromide, carbon tetrafluoride, fluoroform, carbon difluoride, fluoromethane, hexafluorobutadiene, boron trichloride, sulfur hexafluoride, hydrogen gas, combinations of the above, or the like. The plasma process can also include flowing a passivation gas over the structure 100 to adjust (such as increase) the etching selectivity between the dummy gate 503 and other structures of the structure 100. Examples of the passivation gas can include nitrogen gas, oxygen gas, carbon dioxide, sulfur dioxide, carbon monoxide, silicon tetrachloride, combinations of the above, or the like. One or more carrier gases such as argon gas, helium gas, neon gas, combinations of the above, or the like can also be used in the plasma process. In addition, the plasma source power of the plasma process can be about 10 watts to 3000 watts, the bias power can be about 0 watts to about 3000 watts, the pressure can be about 1 mTorr to about 800 mTorr, and the flow rate of the gas mixture can be about 10 sccm to about 5000 sccm.

[0187] In some embodiments, a method of removing a passivation region in a gate spacer 905 and expanding an opening in a dummy gate 503 may include a wet etching process (sometimes regarded as wet cleaning). Examples of etchants used in the wet etching process may include hydrofluoric acid, fluorine gas, combinations of the above, or the like. The wet etching process may further direct an auxiliary etch chemistry onto the structure 100 to adjust (such as increase) the etch selectivity between the dummy gate 503 and other structures of the structure 100. Examples of the auxiliary etch chemistry may include sulfuric acid, hydrogen chloride, hydrogen bromide, ammonia, combinations of the above, or the like. Deionized water, alcohols, acetone, or the like may be used as solvents to be mixed with the etchant and / or the auxiliary etch chemistry during the wet etching process.

[0188] Although the above description applies one cycle of treatment and etching to the opening in the dummy gate 503 to expose the dummy fins (if any) or the substrate 101 (if no dummy fins), multiple cycles of treatment and etching may be performed. For example, the above steps may be repeated any number of times until the dummy fins or the substrate 101 are exposed and the opening in the dummy gate 503 has a desired profile. By repeating the above treatment process and etching process, an atomic layer etching process may be achieved to form an opening with an extended upper portion in the dummy gate 503.

[0189] Once an opening is formed in the dummy gate 503, a dielectric material may be filled into the opening. The deposition method of the dielectric material may be physical vapor deposition, chemical vapor deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or the like. The dielectric material may be deposited first to overfill the opening and cover the upper surfaces of the dummy gate 503 and the interlayer dielectric 907. Thereafter, a planarization process such as chemical mechanical polishing or the like may be performed to remove the excess dielectric material from the dummy gate 503 and the interlayer dielectric 907.

[0190] In embodiments including dummy fins, the dielectric material combines with the dummy fins to divide the dummy gate 503 into different device regions (such as device region 120, the first multi-channel device region 130, and / or the second multi-channel device region 140). Thus, the combination of the dummy fins and the dielectric material that separates the dummy gate 503 may be regarded as a cut dummy gate structure formed as appropriate herein.

[0191] In embodiments without dummy fins, the opening in the dummy gate 503 can pass through the entire dummy gate 503 to expose the isolation region 401 in the opening. In other embodiments, the opening can further extend into the isolation region 401, and even can extend through the isolation region 401 to expose the substrate 101 and / or extend into the substrate 101. In these embodiments, once the dielectric material is filled into the opening, the dielectric material can separately divide the dummy gate 503 into different regions. In this way, the dielectric material that separates the dummy gate 503 can also be regarded as a cut dummy gate structure formed as the case may be here. For example, the cut dummy gate structure formed as the case may be can be located at one or more interfaces between the device region 120, the first multi-channel device region 130, and the second multi-channel device region 140. In this way, the cut dummy gate structure formed as the case may be can provide isolation between adjacent active components.

[0192] As Figure 6 , Figure 7A and Figure 7B shown, once a cut dummy gate structure (not shown) is formed as the case may be to pass through the dummy gate 503, the remaining part of the dummy gate 503 can be removed in a similar manner to the aforementioned removal of the dummy gate 503 without removing the cut dummy gate structure formed as the case may be. In this way, the dummy gate dielectric layer 501 and the cut dummy gate structure formed as the case may be are exposed between the gate spacers 905. Once the dummy gate dielectric layer 501 is exposed, the dummy gate dielectric layer 501 can be removed and replaced with the first dielectric layer 707, the second gate dielectric layer 803, and / or the outer gate dielectric layer 1001, as described in conjunction with Figure 7A , Figure 7B and Figure 10 above.

[0193] Once the dummy gate dielectric layer 501 is replaced, a metal gate 805 can be formed in the opening between the gate spacers 905, and on the cut dummy gate structure formed as the case may be, the fins 105 in the device region 120, the fins 105 in the first multi-channel device region 130, and the fins 105 in the second multi-channel device region 140, which is similar to the above method of forming the metal gate 805 in Figure 8 . In embodiments containing a cut dummy gate structure formed as the case may be, chemical mechanical polishing techniques can be used to planarize the material of the metal gate 805, the cut dummy gate structure formed as the case may be, the contact etch stop layer 903, the gate spacers 905, and the interlayer dielectric layer 907. In this way, the cut dummy gate structure formed as the case may be is similar to the cut metal gate structure shown in Figure 11A and Figure 11B and can be located between the gates 805 of adjacent active components to isolate the gates 805.

[0194] Figure 12 An integrated circuit device 800 showing other embodiments is presented. Specifically, Figure 12 It is shown that in the same step of non-conforming treatment of the channel regions of the first multi-channel device region 130 and the second multi-channel device region 140, a first gate dielectric layer 707 is formed on the fin 105 of the device region 120. In this way, the first interface treatment 700 can be carried out without first protecting the device region 120. In addition, the non-conforming treatment can be used for the first interface treatment 700, so that the first gate dielectric layer 707 has a graded thickness at the interface between the fin 105 in the device region 120 and the fins 105 and the nanostructures 601 in the first multi-channel device region 130 and the second multi-channel device region 140.

[0195] In some embodiments, the first interface treatment 700 can be used to form a first gate dielectric layer 707 with a graded thickness. By controlling each deposition cycle of the first interface treatment 700, a first gate dielectric layer 707 with a larger thickness can be formed at the interface farthest from the isolation region 401, and a first gate dielectric layer 707 with a smaller thickness can be formed at the interface closer to the isolation region 401.

[0196] In some embodiments, the interface of the first gate dielectric layer 707 at the top of the fin 105 in the device region 120 and the interface of the nanostructures 601 of the topmost channel 703 in the first multi-channel device region 130 and the second multi-channel device region 140 may have a first thickness Th1. In addition, the interface of the first gate dielectric layer 707 at the middle part of the fin 105 in the device region 120 and the interface of the nanostructures 601 of the retained channel 705 of the nanostructure stack 603 may have a second thickness Th2. In some embodiments, the interface of the first gate dielectric layer 707 at the bottom of the fin 105 in the device region 120 and the interface of the fins 105 in the first multi-channel device region 130 and the second multi-channel device region 140 may have a fifth thickness Th5, and the fifth thickness Th5 may be less than the second thickness Th2. In some embodiments, the fifth thickness Th5 may be between about and about

[0197] In some embodiments, an outer gate dielectric layer 1001 (as Figure 10 shown) can be deposited at the interface of the nanostructures 601 of the topmost channel 703 in the first multi-channel device region 130 and / or the second multi-channel device region 140, as Figure 12 ​As shown. In some embodiments, the method of forming the outer gate dielectric layer 1001 may be to first form a protective material 701 (such as photoresist) on the fins 105 and the first gate dielectric layer 707 in the device region 120. Once the device region 120 is protected, the outer gate dielectric layer 1001 can be formed using the above materials and processes. After forming the outer gate dielectric layer 1001, the protective material 701 can be removed, and the common gate stack 809 can be formed using the above materials and processes. In some other embodiments, one or more cut metal gate structures 1101 can be formed through Figure 12 the common gate stack 809 of Figure 11A to divide the common gate stack 809 into one or more isolated gate structures and / or one or more common gate structures, such as Figure 11B shown. In addition, Figure 12 any embodiment of the first gate dielectric layer 707 shown can be used in any embodiment containing a cut dummy gate structure formed as appropriate, as described above.

[0198] The embodiments disclosed herein can provide one or more of the following advantages to the semiconductor device of the integrated circuit device 800. For example, when the first critical dimension CD1 of the common gate stack 809 is at least high leakage current in the devices in the device region 120 can be avoided. In addition, the second critical dimension CD2 of the common gate stack 809 is less than or equal to about can effectively improve the device performance of the multi-channel devices in the first multi-channel device region 130 and / or the second multi-channel device region 140 without saturating the device performance. In addition, the first thickness Th1 of the first gate dielectric layer 707 surrounding the topmost channel 703 is less than or equal to about can avoid too high an operating voltage for the multi-channel device. In addition, the second thickness Th2 of the first gate dielectric layer 707 surrounding the reserved channel 705 is at least about can prevent the operating voltage of the multi-channel device from being too low.

[0199] In embodiments containing the outer gate dielectric layer 1001, the additional fourth thickness Th4 of the outer gate dielectric layer 1001 can make it easier to control the difference between the thickness of the topmost channel 703 and the thickness of the reserved channel 705 in the multi-channel device region within the desired thickness range. In this way, it is easy to control the required second critical dimension CD2 and the efficiency of the device performance and / or the operating voltage required for the multi-channel device, as described above.

[0200] In addition, by forming a fourth thickness Th4 less than or equal to about the operating voltage of the multi-channel device can be avoided from being too high. By forming at least about The fourth thickness Th4 of the multi-channel device will not cause the operating voltage of the multi-channel device to be too low. In this way, it is easy to control the operation of the multi-channel device.

[0201] In some embodiments, a method of forming a semiconductor device includes forming a semiconductor fin on a substrate; forming a multi-channel fin on the substrate, wherein the multi-channel fin includes a sacrificial material; removing the sacrificial material from the multi-channel fin without removing material from the semiconductor fin; after removing the sacrificial material, forming a stack of multiple nanostructures from the multi-channel fin; and forming a gate on the stack of nanostructures and the semiconductor fin. In some embodiments, the thickness of the sacrificial material is between about to about In some embodiments, the method further comprises: forming a first dielectric layer of a first thickness to surround a first nanostructure of the stack of nanostructures; and forming a first dielectric layer of a second thickness to surround a second nanostructure of the stack of nanostructures, and the second nanostructure is the topmost nanostructure of the stack of nanostructures, and the second thickness is greater than the first thickness. In one embodiment, the step of forming the first dielectric layer comprises performing an interface treatment on the stack of nanostructures. In one embodiment, the first dielectric layer is a native oxide. In one embodiment, the method further comprises forming a second dielectric layer of a third thickness to surround the first dielectric layer, and the first dielectric layer surrounds the topmost nanostructure, and the second dielectric layer is different from the native oxide. In one embodiment, the sum of the second thickness and the third thickness is less than or equal to

[0202] In another embodiment, a method for forming a semiconductor device includes: forming a first fin on a substrate; forming a second fin on the substrate, wherein the second fin includes a stack of semiconductor materials and a sacrificial layer on the multilayer stack; removing the sacrificial layer; forming a nanostructure from the multilayer stack after removing the sacrificial layer; and forming a gate on the first fin and the nanostructure, wherein an upper surface of the gate is separated from the first fin by a first distance and from a topmost nanostructure of the nanostructure by a second distance, and the second distance is greater than the first distance. In one embodiment, the first distance is at least In one embodiment, the second distance is at most In one embodiment, the method further comprises forming a first dielectric layer on the nanostructure, the first dielectric layer having a first thickness at a first interface of a first nanostructure of the nanostructure and having a second thickness at a second interface of a topmost nanostructure of the nanostructure, and the second thickness is greater than the first thickness. In one embodiment, the step of forming the first dielectric layer further comprises applying a first selective treatment. In one embodiment, the method further comprises forming a material layer to surround the first dielectric layer. In one embodiment, the sum of the first thickness of the first dielectric layer and the thickness of the material layer is between about to about between.

[0203] In yet another embodiment, a semiconductor device includes a semiconductor fin located on a substrate; a multi-channel device located on the substrate; a first gate dielectric layer including a first interface surrounding the topmost nanostructure of the multi-channel device and a second interface surrounding another nanostructure of the multi-channel device, and a first thickness of the first gate dielectric layer at the first interface is greater than a second thickness of the first gate dielectric layer at the second interface; and a gate located on the first gate dielectric layer at the first interface and the second interface and surrounding the first gate dielectric layer at the first interface and the second interface, and a first height of the gate on the semiconductor fin is less than a second height of the gate on the topmost nanostructure. In one embodiment, the first gate dielectric layer includes a first native oxide layer at the first interface. In one embodiment, the first gate dielectric layer includes a second material, and the second material includes a third interface surrounding and adjacent to the first native oxide layer. In one embodiment, the first height is at least about In one embodiment, the second height is less than about In one embodiment, the semiconductor fin is part of a fin field-effect transistor, and the multi-channel device is a nanosheet field-effect transistor.

[0204] The features of the above embodiments facilitate the understanding of the present invention by those skilled in the art. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor device, comprising: Forming a semiconductor fin on a substrate; Forming a multi-channel fin on the substrate, and the multi-channel fin includes a sacrificial material; Removing the sacrificial material from the multi-channel fin without removing material from the semiconductor fin; After removing the sacrificial material, forming a stack of multiple nanostructures from the multi-channel fin; Forming a gate on the stack of multiple said nanostructures and the semiconductor fin; Forming a first dielectric layer with a first thickness to surround a first nanostructure of the stack of multiple said nanostructures; And Forming the first dielectric layer with a second thickness to surround a second nanostructure of the stack of multiple said nanostructures, and the second nanostructure is the topmost nanostructure of the stack of multiple said nanostructures, and the second thickness is greater than the first thickness.

2. The method for forming a semiconductor device according to claim 1, wherein the thickness of the sacrificial material is between and .

3. The method of forming a semiconductor device according to claim 1, wherein the step of forming the first dielectric layer includes performing an interface treatment on the stack of multiple said nanostructures.

4. The method of forming a semiconductor device according to claim 1, wherein the first dielectric layer is a native oxide.

5. The method of forming a semiconductor device according to claim 4, further comprising forming a second dielectric layer with a third thickness to surround the first dielectric layer, and the first dielectric layer surrounds the topmost nanostructure, and the second dielectric layer is different from the native oxide.

6. The method for forming a semiconductor device according to claim 5, wherein the sum of the second thickness and the third thickness is less than or equal to 7. A method of forming a semiconductor device, comprising: Forming a first fin on a substrate; Forming a second fin on the substrate, and the second fin includes a multi-layer stack of multiple semiconductor materials and a sacrificial layer on the multi-layer stack; Removing the sacrificial layer; After removing the sacrificial layer, forming multiple nanostructures from the multi-layer stack; Forming a gate on the first fin and multiple said nanostructures, and an upper surface of the gate is spaced apart from the first fin by a first distance and is spaced apart from a topmost nanostructure of multiple said nanostructures by a second distance, and the second distance is greater than the first distance; And Forming a first dielectric layer on multiple said nanostructures, the first dielectric layer having a first thickness at a first interface of a first nanostructure of multiple said nanostructures and having a second thickness at a second interface of the topmost nanostructure of multiple said nanostructures, and the second thickness is greater than the first thickness.

8. The method of forming a semiconductor device according to claim 7, wherein the first distance is at least 9. The method of forming a semiconductor device as claimed in claim 8, wherein the second distance is at most 10. The method of forming a semiconductor device according to claim 7, wherein the step of forming the first dielectric layer further includes employing a first selective treatment.

11. The method of forming a semiconductor device according to claim 10, further comprising forming a material layer to surround the first dielectric layer.

12. The method for forming a semiconductor device as claimed in claim 11, wherein the sum of the first thickness of the first dielectric layer and the thickness of the material layer is between and .

13. A semiconductor device, comprising: A semiconductor fin located on a substrate; A multi-channel device located on the substrate; A first gate dielectric layer includes a first interface surrounding a topmost nanostructure of the multi-channel device and a second interface surrounding another nanostructure of the multi-channel device, and a first thickness of the first gate dielectric layer at the first interface is greater than a second thickness of the first gate dielectric layer at the second interface; and A gate is located on the first gate dielectric layer at the first interface and the second interface and surrounds the first gate dielectric layer at the first interface and the second interface, and a first height of the gate on the semiconductor fin is less than a second height of the gate on the topmost nanostructure.

14. The semiconductor device according to claim 13, wherein the first gate dielectric layer includes a first native oxide layer at the first interface.

15. The semiconductor device according to claim 14, wherein the first gate dielectric layer includes a second material, and the second material includes a third interface surrounding and adjacent to the first native oxide layer.

16. The semiconductor device according to claim 13, wherein the first height is at least 17. The semiconductor device according to claim 13, wherein the second height is at least 18. The semiconductor device according to claim 13, wherein the semiconductor fin is part of a fin field effect transistor, and the multi-channel device is a nano sheet field effect transistor.

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