Power MOS device and process method

Abstract

The present invention discloses a power MOS device, wherein the epitaxial layer includes a source region, a drain region and a body injection region of the MOS device, the surface of the epitaxial layer includes a gate structure composed of a gate oxide layer and a polysilicon gate, the body injection region also includes a heavily doped region for contacting and leading the body injection region, and the source region of the MOS device also includes a defect layer formed by argon ion injection. The defect layer formed by argon ion injection can reduce the emission efficiency of the emitter of the parasitic triode in the MOS device, thereby further reducing the risk of the parasitic triode of the MOS device being turned on, and finally achieving further improvement of the UIS capability and device reliability of the MOSFET. The present invention also discloses a process method for the MOS device, which only adds a step of argon ion injection after the source region is formed, and the process is simple and easy to implement.

Description

Technical Field

[0001] The present invention relates to the field of design and manufacture of semiconductor devices, in particular to a power MOS device. The present invention also relates to a process method for the structure of the power MOS device. Background Art

[0002] Power electronics technology is a key technology for national economic development, and power semiconductor components are the most common electronic components in power electronics. They are the core control units for energy conversion efficiency of industrial equipment, power supply systems, electric vehicles, consumer electronic devices, etc., and their importance is self-evident. Among them, MOSFET devices, as voltage-controlled multi-sub devices, are widely used due to their high input impedance, low driving power, and wide safe operating area (SOA).

[0003] The structure of common MOS devices is as follows: Figure 1 As shown, an epitaxial layer 2 is formed on a substrate 1. For an N-type MOS device, a heavily doped N-type source region 6 is located in a P-type body region 5, wherein 8 is a heavily doped P-type region, which contacts with a metal to lead out the body region, 3 is a gate oxide layer, 4 is a polysilicon gate formed by etching a polysilicon material, and 9 is borophosphosilicate glass.

[0004] Since 2000, the avalanche withstand (UIS) capability of MOSFET has become a hot topic of research. The avalanche characteristic of MOSFET refers to the maximum drain-source energy that will not damage the MOSFET when the applied voltage is greater than the breakdown voltage. In-depth research on the UIS of MOS devices helps to understand the avalanche withstand capability of MOS devices and improve product reliability.

[0005] According to research, the UIS failure of MOSFET can be divided into two categories: one is energy-related failure, that is, thermal damage, that is, when the power MOS is under the action of power pulse, the junction temperature rises due to the increase in power consumption. When the junction temperature rises to the critical value allowed by the silicon chip characteristics, failure will occur. The other is parasitic transistor conduction damage. Inside the MOS device, there is a parasitic transistor, such as Figure 1As shown in the figure, a parasitic NPN transistor is formed between the heavily doped N-type source region 6, the P-type body region 5 and the N-type substrate 1, and the heavily doped N-type source region 6 is the emitter of this parasitic transistor. Usually, the breakdown voltage of the parasitic transistor is usually lower than the voltage of the MOS. When the reverse current of the drain source begins to flow through the P-type body region 5, the equivalent resistance Rp of the P-type body region and the contact resistance Rc of the N-type source region 6 and the metal produce a voltage drop, and the voltage drop of Rp and Rc is equal to the VBEon (base-emitter turn-on voltage) of the parasitic transistor. Due to the inconsistency of local units, those weak units, due to the increase of the base current IB and the amplification of the transistor, the excessive avalanche current causes the parasitic transistor in the MOSFET to turn on. At this time, the gate voltage can no longer turn off the power MOS, realizing the failure caused by the current self-amplification, thereby causing the loss of control.

[0006] At present, the general reinforcement methods for the UIS capability of power MOS devices are mainly through the following three ways: first, reducing the parasitic resistance of the Pbody region to reduce the risk of the parasitic transistor turning on; second, changing the avalanche current flow path to reduce the risk of the parasitic transistor turning on; third, enhancing the heat dissipation capacity of the device. At present, there is still room for further improvement in the UIS capability of power MOS and the reliability of the device. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a MOS device and optimize its UIS capability.

[0008] Another technical problem to be solved by the present invention is to provide a process method for the MOS device.

[0009] To solve the above problems, the MOS device described in the present invention has an epitaxial layer of the second conductivity type on a substrate of the second conductivity type. The epitaxial layer includes two first doped regions doped with the first conductivity type. The two first doped regions are located on the surface of the epitaxial layer and are isolated by the epitaxial layer of the second conductivity type.

[0010] The first doping region of the first conductivity type further includes a second doping region of the second conductivity type, and the second doping region is respectively located in the two first doping regions.

[0011] The epitaxial surface between the two first doped regions has a gate oxide layer, and the gate oxide layer is also covered with a polysilicon gate of the MOS device.

[0012] The second doping region of the second conductivity type further has an argon ion implantation layer, which is a horizontal thin layer located in the middle of the second doping region and does not contact the boundary of one side of the channel region of the second doping region.

[0013] A further improvement is that the second doped region of the second conductivity type is the source region of the MOS device; the first doped region of the first conductivity type also has a heavily doped region of the first conductivity type, which serves as a lead-out region of the first doped region; the surface of the epitaxial layer of the second conductivity type also has a front metal, and the front metal contacts the heavily doped region through a contact hole and leads to an electrode.

[0014] A further improvement is that borophosphosilicate glass is also covered on the polysilicon gate and above the second doped region; the back side of the substrate also has a back side metal, and the back side metal is connected to the drain of the MOS.

[0015] A further improvement is that the first conductivity type is P type and the second conductivity type is N type; or the first conductivity type is N type and the second conductivity type is P type.

[0016] The present invention provides a process method for the MOS device, which comprises the following process steps:

[0017] Step 1: providing a semiconductor substrate with a second conductivity type, and depositing an epitaxial layer with the second conductivity type on the semiconductor substrate.

[0018] Step 2: forming a gate oxide layer and a polysilicon layer on the surface of the epitaxial layer, and forming a gate structure of the MOS device by etching the polysilicon layer and the gate oxide layer; and then forming a first doped region of the first conductivity type by ion implantation.

[0019] Step three, using the polysilicon gate as a shield, self-aligned implantation of second conductivity type doping ions into the source region is performed, followed by thermal annealing activation.

[0020] Step 4: perform argon ion implantation to form a defect layer in the source region, and then perform an annealing process.

[0021] Step five, performing front side processing, including performing ion implantation in the first doping region to form a heavily doped region, forming a borophosphosilicate glass layer, and depositing and etching to form a front side metal layer.

[0022] Step six, performing a back side process, depositing metal on the back side of the semiconductor substrate to form a back side metal layer and a back side electrode.

[0023] A further improvement is that in the step one, the thickness and doping concentration of the epitaxial layer are determined by the withstand voltage requirement of the MOS device. The higher the breakdown voltage, the lower the resistivity of the epitaxial layer; the higher the breakdown voltage, the thicker the epitaxial layer; the resistivity of the heavily doped semiconductor substrate is 1 to 2 mΩ*cm, and the thickness of the semiconductor substrate should be as thin as possible.

[0024] A further improvement is that in step 2, the gate oxide layer is formed by thermally oxidizing the surface of the epitaxial layer, and after depositing polysilicon, photoresist is coated, and after patterning the photoresist using a mask, the polysilicon layer and the gate oxide layer are etched to form a gate structure.

[0025] A further improvement is that in step three, the injection energy of the self-aligned injection of the second conductivity type doping ions is 60-200 keV, the injection dose is 1E15-5E15 cm-2; the thermal annealing activation temperature is 700-950°C, and the annealing time is 30-240 min.

[0026] A further improvement is that in step four, the injection energy of the argon ion defect layer is 200-800 keV, the injection dose is 1E13-5E14 cm-2, and the argon ion defect layer can reduce the emission efficiency of the source region; the annealing process is an optional step, and the high temperature of the borophosphosilicate glass during reflow in the subsequent step five can also be used for annealing repair.

[0027] A further improvement is that the first conductivity type is P type and the second conductivity type is N type; or the first conductivity type is N type and the second conductivity type is P type.

[0028] The MOS device of the present invention, without affecting the effective contact between the source region (Source) and the metal, performs argon ion implantation in the source region to form a defect layer, thereby reducing the emission efficiency of the emitter of the parasitic triode in the MOS device, thereby further reducing the turn-on risk of the parasitic triode in the MOS device, and finally achieving further improvement of the UIS capability and device reliability of the MOS device. The manufacturing process of the present invention only adds a step of argon ion implantation after the phosphorus ion or arsenic ion implantation in the source (Source), and the process is simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of a traditional MOS device;

[0030] Figures 2 to 7 It is a schematic diagram of the process steps of the MOS device of the present invention;

[0031] Figure 8 It is a process flow chart of the present invention.

[0032] Description of Reference Numerals

[0033] 1 is the epitaxial layer, 2 is the heavily doped substrate, 3 is the gate oxide layer, 4 is polysilicon, 5 is the first doping region, 6 is the second doping region (source region), 7 is the argon ion implantation layer, 8 is the heavily doped region, 9 is borophosphosilicate glass (BPSG layer), 10 is the front metal layer, and 11 is the back metal layer. DETAILED DESCRIPTION

[0034] The structure of the MOS device of the present invention is as follows Figure 7 As shown, an epitaxial layer 1 of the second conductivity type is provided on a substrate 2 of the second conductivity type. The resistivity of the epitaxial layer is related to the breakdown voltage to be achieved. The higher the breakdown voltage, the lower the resistivity of the epitaxial layer. The higher the breakdown voltage, the thicker the epitaxial layer. The epitaxial layer 1 includes two first doping regions 5 with first conductivity type doping, the first doping regions 5 are body doping regions, the two first doping regions 5 are located on the surface of the epitaxial layer, and the epitaxial layer 1 of the second conductivity type is used to isolate the two first doping regions 5.

[0035] The substrate 2 is a heavily doped substrate, and the resistivity of the substrate is usually between 1 and 2 mΩ*cm. The thickness of the substrate is usually between 250 and 300 μm for a 6-inch wafer, and is usually around 200 μm for an 8-inch wafer. In order to reduce the resistance of the substrate, it is usually hoped that the thickness of the substrate can be as thin as possible, and the substrate is connected to the drain of the device.

[0036] It should be noted that, generally, the first conductivity type is P type and the second conductivity type is N type; or, the first conductivity type is N type and the second conductivity type is P type, and the two are in a P-N correspondence relationship. In the specific embodiments of the present invention, N-type MOS devices are used as examples for description, which is also the most common device type. Therefore, corresponding to the above description, in the specific embodiments of the present invention, the first conductivity type is P type and the second conductivity type is N type. On this basis, the present invention is further described below.

[0037] The first doping region 5 of the first conductivity type also includes a second doping region 6 of the second conductivity type, and the second doping region 6 is respectively located in the two first doping regions 5. The second doping region of the second conductivity type is the source region of the MOS device, and is respectively located in the left and right first doping regions 5.

[0038] The first conductive type first doping region 5 also has a first conductive type heavily doped region 8, that is, P+ doped, as a lead-out region of the first doping region 5. The second conductive type epitaxial layer 1 also has a front metal 10 on its surface, and the front metal 10 contacts the heavily doped region 8 through a contact hole and leads to an electrode.

[0039] The surface of the epitaxial growth 1 between the two first doping regions 5 has a gate oxide layer 3 , and the gate oxide layer 3 is also covered with a polysilicon gate 4 of the MOS device.

[0040] The second doping region 6 of the second conductivity type further has an argon ion implantation layer 7. The argon ion implantation layer 7 is a horizontal thin layer located in the middle of the second doping region and does not contact the boundary of one side of the channel region of the second doping region.

[0041] The polysilicon gate and the second doped region are also covered with borophosphosilicate glass; the MOS device of the present invention uses the epitaxial layer as the drain region of the device, and the source region surrounds the drain region from a top plan view, and the drain region is in a central position. The back side of the substrate also has a back side metal. The epitaxial layer and the substrate of the same conductivity type together form a drain electrode of the MOS device through the back side metal and are led out from the back side of the silicon wafer.

[0042] The above is a specific description of the MOS device structure of the present invention. The above structure forms the NMOS device of the embodiment of the present invention. For the PMOS device, the relevant doping type or conductivity type can be changed to the opposite.

[0043] The present invention provides a process method for the above-mentioned MOS device, combined with the attached Figures 2 to 7 The description is as follows, which includes the following process steps:

[0044] Step 1, refer to the attached Figure 2 A semiconductor substrate 2 having a second conductivity type is provided. For an NMOS device, it is an N-type substrate. An epitaxial layer 1 having a second conductivity type, namely, an N-type epitaxial layer, is deposited on the semiconductor substrate. The substrate resistivity is between 1 and 2 mΩ*cm, for example, 1.5 mΩ*cm.

[0045] Step 2, such as Figure 3 As shown, a gate oxide layer 3 is formed on the surface of the epitaxial 1 by a thermal oxidation process, and a polysilicon layer 4 is deposited, and the gate structure of the MOS device is formed by etching the polysilicon layer and the gate oxide layer. Then, a first doping region of a first conductivity type is formed by ion implantation, and the first doping region is a body doping region, which provides an inversion region, i.e., a channel region, formed after a voltage is applied to the gate structure.

[0046] Step 3: Using the polysilicon gate as a shield, perform self-aligned implantation of the second conductivity type of doping ions in the source region. For N-type impurities, phosphorus or arsenic is more likely to be implanted. Then perform thermal annealing activation, such as Figure 4 The implantation energy of the second conductive type doping ion self-aligned implantation is 60-200 keV, and the implantation dose is 1E15-5E15 cm -2 , for example, the injection energy is 120keV and the injection dose is 3E15cm -2 The second doping region 6 of the MOS device, namely the source region, is formed by self-aligned implantation. The activation temperature of thermal annealing is 700-950°C, and the annealing time is 30-240 minutes, for example, annealing at 800°C for 180 minutes, to activate the impurities and repair the implantation damage.

[0047] Step 4: perform argon ion implantation to form a defect layer 7 in the source region, and then perform an annealing process, such as Figure 5 The injection energy of the argon ion defect layer is 200-800 keV, and the injection dose is 1E13-5E14 cm -2 , for example, injecting 3E14cm at 600 keV -2 The argon ion defect layer can reduce the emission efficiency of the source region 6, that is, the emitter of the parasitic transistor. The annealing process is an optional step, that is, the annealing process can be temporarily omitted after the argon ion implantation is completed, because there will also be a high temperature process when the borophosphosilicate glass is subsequently formed. The high temperature during the reflux of the borophosphosilicate glass in the subsequent step five can be used for annealing repair, thereby omitting the process steps and saving work time.

[0048] Step 5: Complete the front process, such as Figure 6 As shown, ion implantation is performed in the first doping region 5 to form a heavily doped region 8. The doping concentration of the heavily doped region 8 is much greater than the doping concentration of the first doping region 5, thereby forming a contact lead-out region of the first doping region. A borophosphosilicate glass layer is formed on the surface of the gate structure and the surface of the source region, and a front metal layer is deposited and etched to form a front metal layer. The front metal layer 10 contacts the heavily doped region 8 through the contact hole to form a lead-out electrode for the first doping region 5. Of course, the front electrode is not limited to the electrode of the first doping region 5, but also includes a gate electrode, etc., which are not shown in this figure.

[0049] Step six, performing a backside process, depositing metal on the backside of the semiconductor substrate to form a backside metal layer 11, and forming a backside electrode. For a MOS device, the backside electrode is generally connected to the drain to form a drain electrode of the MOS device.

[0050] Under the premise of not affecting the effective contact between the source region and the metal, the present invention adds a step of argon ion implantation after the phosphorus ion or arsenic ion implantation in the source region to form a defect layer, thereby reducing the emission efficiency of the emitter of the parasitic transistor in the MOS device, thereby further reducing the risk of the parasitic transistor in the MOS device being turned on, and ultimately achieving further improvement in the UIS capability and device reliability of the MOS device.

[0051] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power MOS device, comprising an epitaxial layer of a second conductivity type on a substrate of a second conductivity type, wherein the epitaxial layer comprises two first doped regions of a first conductivity type, the two first doped regions are located on the surface of the epitaxial layer, and the epitaxial layer of the second conductivity type is used to isolate the two first doped regions; The first doping region of the first conductivity type further includes a second doping region of the second conductivity type, and the second doping region is respectively located in the two first doping regions; The epitaxial surface between the two first doped regions has a gate oxide layer, and the gate oxide layer is also covered with the polysilicon gate of the MOS device; the gate oxide layer and the polysilicon gate together form a gate structure of the MOS device, and under an applied voltage, the channel region located below the gate structure is inverted so that the source and drain regions are connected; Features: The second doping region of the second conductivity type further has an argon ion implantation layer, which is a horizontal thin layer located in the middle of the second doping region and does not contact the boundary of one side of the channel region of the second doping region.

2. The power MOS device according to claim 1, characterized in that: The second doped region of the second conductivity type is the source region of the MOS device; the first doped region of the first conductivity type also has a heavily doped region of the first conductivity type, which serves as a lead-out region of the first doped region; the surface of the epitaxial layer of the second conductivity type also has a front metal, which contacts the heavily doped region through a contact hole and leads to an electrode.

3. The power MOS device according to claim 1, wherein: The polysilicon gate and the second doped region are covered with borophosphosilicate glass; the back side of the substrate also has a back side metal, and the back side metal is connected to the drain of the MOS.

4. The power MOS device according to any one of claims 1 to 3, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

5. A process for manufacturing a power MOS device as claimed in claim 1, characterized in that: The steps include: Step 1, providing a semiconductor substrate with a second conductivity type, and depositing an epitaxial layer with a second conductivity type on the semiconductor substrate; Step 2: forming a gate oxide layer and a polysilicon layer on the surface of the epitaxial layer, and forming a gate structure of the MOS device by etching the polysilicon layer and the gate oxide layer; and then forming a first doped region of the first conductivity type by ion implantation; Step 3, using the polysilicon gate as a shield, performing self-aligned implantation of second conductivity type doping ions into the source region, and then performing thermal annealing activation; Step 4, performing argon ion implantation to form a defect layer in the source region; Then an annealing process is performed; Step 5, performing a front process, including performing ion implantation in the first doping region to form a heavily doped region, forming a borophosphosilicate glass layer, and depositing and etching to form a front metal layer; Step six, performing a back side process, depositing metal on the back side of the semiconductor substrate to form a back side metal layer and a back side electrode.

6. The process according to claim 5, characterized in that: In the step 1, the thickness and doping concentration of the epitaxial layer are determined by the withstand voltage requirement of the MOS device. The higher the breakdown voltage, the lower the resistivity of the epitaxial layer; the higher the breakdown voltage, the thicker the epitaxial layer; the resistivity of the heavily doped semiconductor substrate is 1 to 2 mΩ*cm, and the thickness of the semiconductor substrate should be as thin as possible.

7. The process according to claim 5, characterized in that: In the step 2, the gate oxide layer is formed by thermally oxidizing the surface of the epitaxial layer, and after depositing polysilicon, photoresist is coated, and after patterning the photoresist using a mask, the polysilicon layer and the gate oxide layer are etched to form a gate structure.

8. The process according to claim 5, characterized in that: In step 3, the implantation energy of the second conductivity type doping ions self-aligned implantation is 60-200 keV, and the implantation dose is 1E15-5E15 cm -2 ; The activation temperature of thermal annealing is 700-950°C, and the annealing time is 30-240 minutes.

9. The process according to claim 5, characterized in that: In step 4, the injection energy of the argon ion defect layer is 200-800 keV, and the injection dose is 1E13-5E14 cm -2 , the argon ion defect layer can reduce the emission efficiency of the source region; In this step four, the annealing process is not performed temporarily, and the high temperature during the reflux of the borophosphosilicate glass in the subsequent step five is used for annealing repair.

10. The process according to any one of claims 5 to 9, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

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