Extended via semiconductor structures, devices, and methods

Abstract

A semiconductor device includes a substrate, a first conductive layer located on the substrate, a first conductive via, and an additional conductive layer and conductive via located between the first conductive via and the substrate. The first conductive via is located between the substrate and the first conductive layer and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers and has a thickness greater than about 8 Angstroms. An inductor having a high quality factor is formed in the first conductive layer and also includes the first conductive via. Embodiments of the invention also relate to methods of forming semiconductor devices.

Description

BACKGROUND

[0001] Inductors are components of integrated circuits. Inductors fabricated in integrated circuit processes typically include a conductive spiral coil, input and output traces, and pads, all of which are formed at least partially in the topmost metal layer of the integrated circuit. One performance metric for inductors is the quality or "Q" factor. In radio frequency electronics, the Q factor can be thought of as a measure of signal selectivity, i.e., the ability to attenuate interfering signals, particularly those that are adjacent to the desired frequency band, while preserving the signals of the desired frequency band. Increasing the Q factor improves signal selectivity, which is an important goal in the design of inductors fabricated in integrated circuit processes. BRIEF DESCRIPTION OF DRAWINGS

[0002] Aspects of the application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice, the various elements are not drawn to scale. In fact, the dimensions of the various elements can be arbitrarily increased or decreased for clarity of discussion.

[0003] Figure 1 is a top view of an inductor according to some embodiments.

[0004] Figure 2 is a perspective view of adjacent bends of the inductor of Figure 1

[0005] Figure 3 is a circuit diagram of the inductor of Figure 1

[0006] Figure 4 is a cross-sectional view of a structure of the inductor of Figure 1

[0007] Figures 5a-5n is a cross-sectional view of a method of fabricating a structure of Figure 4

[0008] Figure 6 is a flowchart of a method of fabricating a conductive portion according to some embodiments.

[0009] Figure 7 is a circuit block diagram of a passive radio frequency device according to some embodiments.

[0010] Figure 8 is a circuit block diagram of an active radio frequency device according to some embodiments.

[0011] Figure 9 is a circuit block diagram of a voltage controlled oscillator device according to some embodiments. DETAILED DESCRIPTION ​​​​

[0012] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Various examples of elements and arrangements are described in order to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component can include embodiments in which the first component and the second component are in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Additionally, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0013] Also for ease of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for describing an element's or component's relationship to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] The term "top metal layer" can be used herein to refer to the metal layer of an integrated circuit chip (or simply "chip") that is farthest from the chip's substrate, and / or the metal layer of the chip on which no further metal layer is formed. The term "bottom metal layer" can be used herein to refer to the metal layer of the chip that is closest to the substrate, and / or the metal layer of the chip that does not have a metal layer between itself and the substrate. The term "middle metal layer" can be used herein to refer to any metal layer that is between the top metal layer and the bottom metal layer.

[0015] The term "upper conductive via" can be used herein to refer to any conductive via that is in direct contact with the top metal layer. The term "middle conductive via" can be used herein to refer to any conductive via that is not in direct contact with the top metal layer.

[0016] On-chip inductor quality factor is closely related to various desirable performance metrics in integrated circuit design, including but not limited to radio frequency sideband rejection and voltage controlled oscillator phase noise reduction. Substrate loss and self-resonance are two environmental challenges that hinder designers' ability to produce on-chip inductors with high quality factor. Oxide capacitance C ox (the capacitance between the inductor and the substrate on which the inductor is formed) effectively reduces substrate loss and self-resonance. Oxide capacitance C ox is inversely proportional to oxide thickness t oxInversely proportional, which indicates that the quality factor can be improved by increasing the oxide thickness t ox

[0017] To reduce the substrate loss factor and self-resonance factor to increase the quality factor of an on-chip inductor, various embodiments of integrated circuit structures and process flows for increasing the oxide thickness t ox are described below. In some embodiments, the oxide thickness t ox is increased by extending the upper conductive via through at least two dielectric layers. In some embodiments, the oxide thickness is further increased by extending the upper conductive via through at least one etch stop layer located between the at least two dielectric layers. A 0.5 nanohen on-chip inductor has a Q factor greater than about 22 when using the structures and processes described herein.

[0018] Figure 1 is a top view of an inductor circuit 10 according to some embodiments. The inductor circuit 10 is an on-chip inductor in a chip. The inductor circuit 10 is fabricated in an integrated circuit fabrication process. The inductor circuit 10 is on a substrate of the chip. In some embodiments, the substrate is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped with p-type or n-type dopants or undoped. In some embodiments, the substrate is a wafer, such as a silicon wafer. An SOI substrate typically includes a layer of semiconductor material formed on an insulator layer. In some embodiments, the insulator layer is a buried oxide (BOX) layer, a layer of silicon oxide, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. In some embodiments, a multi-layer or graded substrate is used. In some embodiments, the semiconductor material of the substrate includes silicon and / or germanium. In some embodiments, the semiconductor material is a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. In some embodiments, the substrate is an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, combinations of the above can be used as the substrate.

[0019] The substrate will typically include integrated circuit devices (not shown). In some embodiments, the integrated circuit devices include transistors, diodes, capacitors, resistors, etc., or combinations thereof, formed within and / or on the substrate. Any suitable method can be used to form the integrated circuit devices.

[0020] ​The inductor circuit 10 includes an inductor 100 having any suitable shape or architecture. In some embodiments, the inductor 100 may be a symmetrical or substantially symmetrical helical inductor 100 having an octagonal coil (or simply "coil") 130. A first trace 141 and a first pad 142, as well as a second trace 143 and a second pad 144, provide input and output electrical signal connections to the coil 130. In some embodiments, such as Figure 1 As shown, the first guard ring segment 110 and the second guard ring segment 120 partially surround the spiral inductor 100. In some embodiments, the first guard ring segment 110 and / or the second guard ring segment 120 may be omitted. In some embodiments, the coil 130 is at least partially formed in the top metal layer of the chip. Forming the coil 130 in the top metal layer can reduce parasitic capacitance, which is typically related to the distance between the coil and the substrate on which the coil is formed, or the "oxide thickness" (t). ox It is inversely proportional to the others.

[0021] Throughout this specification, references to inductor circuit 10 are not limited to... Figure 1 The diagram illustrates a symmetrical spiral inductor architecture. In various embodiments, other inductor structures, including at least an asymmetrical spiral inductor, can be used as inductor 100 in inductor circuit 10, and the techniques described for improving the inductor Q-factor can be applied to other inductor architectures without imagining significant improvements. Symmetrical spiral inductors typically involve a tradeoff between a lower self-resonant frequency and higher inductance, and a higher Q-factor and lower series resistance.

[0022] In various embodiments, other inductor shapes, including at least hexagonal, square, or circular, can be used as inductor 100 in inductor circuit 10, and the techniques described for improving the inductor Q factor can be applied to other inductor shapes without imagining significant improvements. While circular inductors exhibit good Q factors, few or no semiconductor manufacturing processes support shapes with curved edges. Square inductors are generally more compact, easier to manufacture, and exhibit higher inductance for a given area, but have lower Q factors. Octagonal and hexagonal inductors achieve an ideal balance between manufacturability, Q factor, and inductance. Similarly, any shape will benefit from the application of the Q factor enhancement techniques described herein. Other examples of substantially closed geometric patterns will include box-in-box patterns (square or rectangular) or other polygonal spiral patterns, irregularly shaped spiral patterns, nested parallelograms or polygonal patterns, etc.

[0023] In some embodiments, the inductor circuit 10 has a Q factor greater than about 21, greater than about 22, greater than about 23, or greater than about 24. In some embodiments, the inductor circuit 10 has an inductance less than about 1 nanohenry, less than about 0.5 nanohenry, or less than about 0.1 nanohenry. Lower inductance can be desirable to achieve higher operating frequencies.

[0024] The spiral inductor 100 of the inductor circuit 10 includes a coil 130, a first trace 141, a first pad 142, a second trace 143, and a second pad 144.

[0025] The first coil segment 131 of the coil 130 is a first outer loop segment of the coil 130. In some embodiments, the first coil segment 131 includes at least 3 bends, at least 4 bends, or at least 5 bends. A “bend” as described herein can refer to a change in direction of one segment of the coil 130. A circular inductor will thus have an infinite number of bends, while a polygonal inductor will have a finite number of bends. In some embodiments, the first coil segment 131 is integrally formed with the first trace 141. In some embodiments, the first coil segment 131 is electrically connected to the first trace 141 by a conductive via.

[0026] The second coil segment 132 is an inner loop segment of the coil 130. In some embodiments, the second coil segment 132 includes at least 4 bends, at least 6 bends, or at least 8 bends. In some embodiments, the second coil segment 132 is integrally formed with the first coil segment 131 and / or the first trace 141, or is electrically connected to the first coil segment 131 and / or the first trace 141 by a conductive via.

[0027] The third coil segment 133 is a first bridge segment electrically connected to the first coil segment 131 and the second coil segment 132. In some embodiments, the third coil segment 133 is integrally formed with the first coil segment 131 and the second coil segment 132, or is electrically connected to the first coil segment 131 and the second coil segment 132 by a conductive via.

[0028] The fifth coil segment 135 is a second outer loop segment of the coil 130. In some embodiments, the fifth coil segment 135 includes at least 3 bends, at least 4 bends, or at least 5 bends. In some embodiments, the fifth coil segment 135 is integrally formed with the second trace 143. In some embodiments, the fifth coil segment 135 is electrically connected to the second trace 143 by a conductive via.

[0029] The fourth coil segment 134 is a second bridge segment electrically connected to the fifth coil segment 135 and the second coil segment 132. The fourth coil segment 134 crosses under the third coil segment 133 and is electrically isolated from the third coil segment 133. In some embodiments, the fourth coil segment 134 is formed in at least one intermediate metal layer.

[0030] The sixth coil segment 136 is a first inter-metal connection region that partially overlaps the second coil segment 132 and the fourth coil segment 134. In some embodiments, the sixth coil segment 136 includes one or more conductive vias and one or more metal contacts that extend from the second coil segment 132 to the fourth coil segment 134. The sixth coil segment 136 establishes an electrical connection between the second coil segment 132 and the fourth coil segment 134.

[0031] The seventh coil segment 137 is a second inter-metal connection region that partially overlaps the fifth coil segment 135 and the fourth coil segment 134. In some embodiments, the seventh coil segment 137 includes one or more conductive vias and one or more metal contacts that extend from the fifth coil segment 135 to the fourth coil segment 134. The seventh coil segment 137 establishes an electrical connection between the fifth coil segment 135 and the fourth coil segment 134.

[0032] In some embodiments, the first pad 142, the first trace 141, the first coil segment 131, the third coil segment 133, the second coil segment 132, the fifth coil segment 135, the second trace 143, and the second pad 144 (the "segments") are formed in a top metal layer of the chip. In some embodiments, the segments are also formed in at least one intermediate metal layer and / or a bottom metal layer, the metal layers included in the segments being interconnected by conductive vias. Forming the segments in more than one metal layer reduces the series resistance of the spiral inductor 100 by effectively increasing the cross-sectional area of the current path through the spiral inductor 100 (resistance is inversely proportional to cross-sectional area), which is desirable in some circuit applications.

[0033] In some embodiments, any of the first pad 142, the first trace 141, the first coil segment 131, the third coil segment 133, the second coil segment 132, the fifth coil segment 135, the second trace 143, and the second pad 144 includes at least one upper conductive via that extends from the top metal layer through at least two dielectric layers. Each upper conductive via in the spiral inductor 100 is a single continuous structure. In some embodiments, the formation of the upper conductive vias is accomplished using no more than one electroplating step.

[0034] The first guard ring segment 110 and the second guard ring segment 120 form a guard ring around the coil 130. The guard ring attenuates radio frequency noise emitted by the coil 130. The attenuation protects nearby circuitry that can be susceptible to electromagnetic interference generated by the coil 130.

[0035] Figure 2 is a perspective view of an inductor according to some embodiments Figure 1 is a perspective view of an inductor according to some embodiments Figure 3 is a circuit diagram of an inductor according to some embodiments Figure 1 is a circuit diagram of an inductor according to some embodimentsFigure 2 Two metal layers are shown in the cross-section. Other embodiments can include more than two metal layers.

[0036] The inductor portion 20 includes a substrate 240 and a dielectric layer 230 on a first side of the substrate 240. Figure 2 Portions of the first coil segment 131 and the second coil segment 132 are shown, as well as front and side cross-sectional views. For ease of description, equivalent circuit elements including an inductance 330, a resistance 331, a capacitance 332, a capacitance 340, a resistance 350, and a capacitance 360 are also shown superimposed on the perspective view of the coil 130. Figure 2

[0037] Figure 3 The equivalent circuit 30 shown is a pi-type lumped physical model for approximating the electrical behavior of an on-chip inductor, such as the spiral inductor 100.

[0038] The inductance 330 models the series inductance of the spiral inductor 100. A first terminal of the inductance 330 is electrically connected to a first terminal of the capacitance 332, a first terminal of the capacitance 340, and the first interface terminal 310. A second terminal of the inductance 330 is electrically connected to a first terminal of the resistance 331.

[0039] The resistance 331 models the series resistance of the spiral inductor 100. A first terminal of the resistance 331 is electrically connected to a second terminal of the inductance 330. A second terminal of the resistance 331 is electrically connected to a second terminal of the capacitance 332, a first terminal of the capacitance 341, and the second interface terminal 320.

[0040] The capacitance 332 represents the series capacitance of the spiral inductor 100. The capacitance 332 generally models the capacitive coupling in the spiral inductor 100. Figure 2 A type of capacitive coupling between the first coil segment 131 and the second coil segment 132 is shown in the cross-section. The total capacitive coupling represented by the capacitance 332 is generally believed to be dominated by the overlap of the third coil segment 133 and the fourth coil segment 134 of the coil 130 shown. Figure 1 A first terminal of the capacitance 332 is electrically connected to the first interface terminal 310, a first terminal of the inductance 330, and a first terminal of the capacitance 340. A second terminal of the capacitance 332 is electrically connected to a second terminal of the resistance 331, a first terminal of the capacitance 341, and the second interface terminal 320.

[0041] The capacitances 340 and 341 model the oxide capacitances of the spiral inductor 100 distributed at the first interface terminal 310 and the second interface terminal 320, respectively. The oxide capacitances of the spiral inductor 100 are generally modeled as uniformly distributed: C ox1 = C ox2 = C ox ​Capacitances 340 and 341 model the capacitance of the dielectric layer 230 between the first coil segment 131 and the substrate 240 and between the second coil segment 132 and the substrate 240, respectively.

[0042] Resistances 350 and 351 model the resistance of the substrate 240 from the dielectric layer 230 to the bias terminal 370, corresponding to the resistance from the second terminal of the capacitance 340 to the bias terminal 370 and from the second terminal of the capacitance 341 to the bias terminal 370, respectively. Capacitances 360 and 361 model the capacitance of the substrate 240 from the dielectric layer 230 to the bias terminal 370, corresponding to the capacitance from the second terminal of the capacitance 340 to the bias terminal 370 and from the second terminal of the capacitance 341 to the bias terminal 370, respectively. Resistances 350 and 351 are typically modeled as uniformly distributed: R sub1 = R sub2 = R sub Capacitances 360 and 361 are typically modeled as uniformly distributed: C sub1 = C sub2 = C sub .

[0043] The equivalent circuit 30 approximates the Q factor of the spiral inductor 100 as:

[0044]

[0045] The middle term of (1) represents the well-known substrate loss factor, which is a number less than one because the parasitic R p in the denominator dominates the second term, so it is close to one. The parasitic resistance R p extends to (2). According to (2), decreasing C ox will increase R p . The increased R p raises the substrate loss factor to close to one, which improves the Q factor.

[0046] The third term of (1) represents the well-known self-resonance factor, which is also a loss factor less than one. The parasitic capacitance C p extends to (3). If C p decreases, the self-resonance factor increases. According to (3), when C ox decreases, C p decreases.

[0047] C ox is typically obtained by the following equation:

[0048]

[0049] According to (4), C ox is proportional to the inductor area lw and the oxide dielectric constant εox is proportional to oxide thickness t ox is inversely proportional. Oxide thickness t ox increases reduce C ox , which reduces the substrate loss factor and self-resonance factor, thereby increasing the Q factor. "Oxide thickness" generally refers to the thickness of the oxide or other suitable dielectric between the spiral inductor 100 and the substrate. Oxide thickness can be measured as the distance between the surface of the spiral inductor 100 proximate the substrate and the substrate itself. Figure 4 One measure of oxide thickness, labeled "t ox ", is shown in accordance with various embodiments.

[0050] By increasing the distance between the inductor 100 and the substrate, using an extended (e.g., taller or deeper) upper conductive via effectively increases the oxide thickness t ox . To improve inductor quality factor and overall device performance, in some embodiments, the oxide thickness t ox is increased by extending the upper conductive via through at least two dielectric layers. In some embodiments, the oxide thickness is further increased by extending the upper conductive via through at least one etch stop layer located between the at least two dielectric layers.

[0051] Structures 210 and 220 are highlighted in Figure 2 , each of which includes such an upper conductive via. Figure 2 The positioning of the via 213 (upper conductive via) between the first metal wire 211 and the second metal wire 212 of the first coil segment 131 is shown. Figure 5n Structure 210 is shown in accordance with at least one embodiment. In some embodiments, the first coil segment 131 includes at least ten, at least one hundred, or more structures 210 distributed throughout the first coil segment 131. Structure 220 is included in the second coil segment 132. Structure 220 is highlighted to conceptually illustrate the position of the via 223 between the third metal wire 221 and the fourth metal wire 222 of the second coil segment 132. In some embodiments, the second coil segment 132 includes at least ten, at least one hundred, or more structures 220 distributed throughout the second coil segment 132. In some embodiments, structures similar to structure 210 or structure 220 are included in the first pad 142, the first trace 141, the third coil segment 133, the fifth coil segment 135, the second trace 143, and / or the second pad 144.

[0052] In some embodiments, the array of structures 210 or structures 220 are distributed throughout the spiral inductor 100, each structure 210 or structure 220 having a width of about 0.1 microns to about 10 microns, a length of about 0.1 microns to about 10 microns, and a pitch / pitch of the array of about 0.1 microns to about 10 microns. Other embodiments can utilize larger or smaller lengths, widths, and / or array pitches / spacing. In some embodiments, the structures 210 or structures 220 are not uniformly distributed in one or more regions of the spiral inductor 100 or inductor circuit 10.

[0053] The via 213 is an upper conductive via. The via 213 is in direct contact with the first metal line 211 and in direct contact with the second metal line 212. In some embodiments, the via 213 is or includes a metal such as tungsten, copper, aluminum, gold, silver, alloys thereof, etc., or combinations thereof, and can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable methods.

[0054] The via 223 is an upper conductive via. The via 223 is in direct contact with the third metal line 221 and in direct contact with the fourth metal line 222. In some embodiments, the via 223 is or includes a metal such as tungsten, copper, aluminum, gold, silver, alloys thereof, etc., or combinations thereof, and can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable methods.

[0055] To reduce the substrate loss factor and self-resonance factor to increase the quality factor of an on-chip inductor, various embodiments of integrated circuit structures and process flows for increasing oxide thickness are described below. In some embodiments, the oxide thickness is increased by extending an upper conductive via through at least two dielectric layers to increase the distance between the inductor 100 and the substrate. In some embodiments, the oxide thickness is further increased by extending the upper conductive via through at least one etch stop layer located between the at least two dielectric layers. When using the structures and processes described herein, an on-chip inductor has a Q factor of 0.5 nanohenrys that is greater than about 22.

[0056] Figure 4is a schematic diagram of a conductive stack 40 according to some embodiments. The stack 40 is shown, which shows: metal features 211, 212, 422, 432, 442, 452, 462, 472, 482; dielectric layers 400, 410, 415, 420, 425, 430, 435, 440, 445, 450, 455, 460, 465, 470, 475, 480, 485; a substrate 240; and conductive vias 213, 421, 431, 441, 451, 461, 471, 481 from a bottom metal layer through various intermediate metal layers to a top metal layer. Figure 4 Seven intermediate metal layers are shown. In some embodiments, fewer or more intermediate metal layers are utilized.

[0057] Figure 4 Seventeen dielectric layers are shown. For clarity of illustration, Figure 4 No intervening functional layers are shown, including etch stop layers, anti-reflective layers, etc. In some embodiments, one or more functional layers are included between one or more dielectric layers. In some embodiments, the dielectric layer 410 includes at least Figure 5n The dielectric layers 511, 512 and functional layers 501, 502, 503 are shown. In some embodiments, the dielectric layers 420, 430, 440, 450, 460, 470, 480 each have a thickness that is less than the thickness of the dielectric layer 410. In some embodiments, the dielectric layers 420, 430, 440, 450, 460, 470, 480 have a thickness that is less than 7 Angstroms.

[0058] The conductive feature 482 is a bottom metal layer contact in the dielectric layer 485. The via 481 is a bottom metal layer via in the dielectric layer 480, and directly contacts the conductive feature 482. The via 481 and the dielectric layer 485 are on the substrate 240. In some embodiments, there are no intervening metal layers between a surface of the conductive feature 482 that faces the substrate 240 and the substrate 240.

[0059] Conductive member 472 is a first intermediate layer contact in dielectric layer 475. Conductive member 472 is in direct contact with via 481. Conductive members 462, 452, 442, 432, 422, and second metal line 212 are second, third, fourth, fifth, sixth, and seventh intermediate layer conductive members, respectively. In some embodiments, conductive members 432, 442, 452, 462, 472 have substantially the same thickness. In some embodiments, conductive member 422 has substantially the same thickness as second metal line 212. In some embodiments, conductive members 432, 442, 452, 462, 472 have a thickness that is different from the thickness of conductive member 422 and second metal line 212. In some embodiments, conductive member 422 and second metal line 212 are thicker than conductive members 432, 442, 452, 462, 472. Second metal line 212 and conductive members 422, 432, 442, 452, 462, 472, 482 are or include at least one conductive material. In some embodiments, the at least one conductive material is or includes a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, and the like or combinations thereof, and can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable methods.

[0060] Via 471 is a first intermediate layer via in dielectric layer 470. Via 471 is in direct contact with conductive member 472 and conductive member 462. Via 461 is a second intermediate layer via in direct contact with conductive member 462 and conductive member 452. Via 451 is a third intermediate layer via in direct contact with conductive member 452 and conductive member 442. Via 441 is a fourth intermediate layer via in direct contact with conductive member 442 and conductive member 432. Via 431 is a fifth intermediate layer via in direct contact with conductive member 432 and conductive member 422. Via 421 is a sixth intermediate layer via in direct contact with conductive member 422 and second metal line 212. In some embodiments, vias 421, 431 have substantially the same thickness. In some embodiments, vias 441, 451, 461, 471, 481 have substantially the same thickness. In some embodiments, vias 441, 451, 461, 471, 481 have a thickness that is different from the thickness of vias 421, 431. In some embodiments, vias 421, 431 are thicker than vias 441, 451, 461, 471, 481.

[0061] Via 213 is an upper conductive via. Via 213 has a thickness that is less than the thickness of second metal line 212. Figure 4The middle mark is "t". The thickness of the via 213 is greater than the thickness of any intervening conductive via between the surface of the via 213 facing the substrate 240 and the substrate 240.

[0062] In some embodiments, the thickness of the via 213 is greater than about 8 kilo Angstroms. In some embodiments, the thickness of the via 213 is in the range of about 8 kilo Angstroms to about 30 kilo Angstroms. A thickness of the via 213 below 8 kilo Angstroms can not be sufficient to provide adequate power handling capability and can also introduce too much intermetallic capacitance between the first metal line 211 and the second metal line 212. The formation of the via 213 through a single oxide layer having a thickness exceeding 30 kilo Angstroms can adversely affect process uniformity when etching the opening of the via 213 through the single oxide layer in which the via 213 is formed.

[0063] In some embodiments, the via 213 extends through at least two dielectric layers 410 to further increase the oxide thickness by further increasing the distance between the inductor 100 and the substrate. The use of two dielectric layers separated by an etch stop layer allows for a thicker via 213 while avoiding adverse effects on process uniformity by etching the two dielectric layers in two different etching operations. In some embodiments, the thickness of the via 213 extending through the at least two dielectric layers is in the range of about 16 kilo Angstroms to 60 kilo Angstroms. In some embodiments, the via 213 has a thickness of about 48 kilo Angstroms. The via 213 having a thickness much greater than 8 kilo Angstroms effectively increases t ox thereby reducing C ox and increasing the quality factor. Other dielectric layers and etch stop layers can be introduced to further increase the thickness of the via 213. A via 213 having a thickness that is too great can introduce unnecessary stress on the lower metal layers, which can result in delamination.

[0064] Figures 5a to 5n is a schematic diagram showing an intermediate semiconductor structure that illustrates a method of fabricating the structure 210 according to some embodiments. Figure 2 and Figure 4 is a method of fabricating the structure 210 according to some embodiments. Figure 6 is a flowchart of a method of fabricating the structure 210 according to some embodiments. Figures 5a to 5j Generally involves the formation of the via 213. Figures 5k to 5n Generally involves the formation of the first metal line 211.

[0065] In Figure 5aIn some embodiments, a second metal line 212 is provided. In some embodiments, the second metal line 212 is a contact or trace in the middle metal layer. In some embodiments, the formation of the second metal line 212 is achieved by defining a feature in at least a photolithography process, removing dielectric material to form an opening substantially corresponding to the feature, depositing or plating a conductive material within and over the opening, and planarizing and / or polishing the conductive material and dielectric layer. In some embodiments, the at least one conductive material is or includes a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, etc., or combinations thereof, and can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable methods. In some embodiments, a barrier seed layer is formed in the opening prior to depositing or plating the conductive material in the opening.

[0066] Figure 5b An intermediate semiconductor structure is shown after performing Figure 6 operation 600 of flowchart 60. In Figure 5b some embodiments, a functional layer 501 is formed on the second metal line 212. In some embodiments, the functional layer 501 is a first functional layer. In some embodiments, the functional layer 501 is a first etch stop layer. For example, as shown in Figure 6 operation 600 can include forming a functional layer 501 by depositing a first etch stop layer (ESL1). Generally, an etch stop layer (ESL) provides a mechanism to stop an etch process when forming a conductive feature such as a contact or via. The ESL can be formed of a dielectric material having a different etch selectivity than adjacent layers or elements. In some embodiments, the functional layer 501 includes or is silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, silicon carbide, etc., or combinations thereof, deposited by a suitable deposition process. In some embodiments, the functional layer 501 has a thickness in a range of about 300 angstroms to 1000 angstroms. In some embodiments, the functional layer 501 is formed of silicon carbide and has a thickness of about 750 angstroms. Using a thick functional layer 501 both avoids voids from being formed in the functional layer 501 and increases the thickness of the via 213 and the oxide thickness t ox , which can be advantageous. A functional layer 501 that is too thick can increase etch time and the volume of etchant consumed by the etch through the functional layer 501.

[0067] Figure 5c An intermediate semiconductor structure is shown after performing Figure 6 operation 601. In Figure 5c some embodiments, a functional layer 502 is formed on the functional layer 501. In some embodiments, the functional layer 502 is a second functional layer. In some embodiments, the functional layer 502 is a second etch stop layer similar to the first etch stop layer. For example, as shown in Figure 6As shown, operation 601 may include forming a functional layer 502 by depositing a second etch stop layer (ESL2). In some embodiments, the functional layer 502 comprises silicon nitride, silicon carbonitride, silicon carbide, carbon nitride, silicon carbide, etc., or combinations thereof, deposited on the functional layer 501 by a suitable deposition process. In some embodiments, the thickness of the functional layer 502 is in the range of about 300 angstroms to 1000 angstroms. In some embodiments, the functional layer 502 is formed of the same material as the functional layer 501. In some embodiments, the functional layer 502 is formed of silicon carbide and has a thickness of about 750 angstroms. Using a thick functional layer 502 avoids the formation of voids in the functional layer 502 and increases the thickness of the via 213 and the oxide thickness t. ox This could be advantageous. An excessively thick functional layer 502 may increase etching time and the volume of etchant consumed by etching through the functional layer 502.

[0068] Figure 5d It shows the execution Figure 6 The intermediate semiconductor structure after operation 602. Figure 5d In this configuration, a dielectric layer 511 is formed on the functional layer 502. In some embodiments, the dielectric layer 511 is a first dielectric layer. In some embodiments, the dielectric layer 511 is formed of a dielectric material deposited on the functional layer 502 by a suitable deposition process. In some embodiments, the dielectric material may include or may be silicon dioxide, a low-k dielectric material (e.g., a material with a dielectric constant lower than that of silicon dioxide), silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicon glass (USG), fluorinated silicon glass (FSG), organosilicon glass (OSG), SiOxCy, spin-coated glass, spin-coated polymers, silicon carbide materials, compounds thereof, composites thereof, etc., or combinations thereof. For example, such as... Figure 6 As shown, operation 602 may include forming a dielectric layer 511 by depositing a first oxide layer (OX1). In some embodiments, the thickness of the dielectric layer 511 is in the range of about 4 kiloangeros to about 30 kiloangeros. In some embodiments, the thickness of the dielectric layer 511 is in the range of about 20 kiloangeros to about 30 kiloangeros. In some embodiments, the dielectric layer 511 is formed by USG and has a thickness of about 25 kiloangeros. A thicker dielectric layer 511 is advantageous for increasing the thickness of the via 213 and the oxide thickness t. ox An excessively thick dielectric layer 511 will consume more time and materials in production and may also adversely affect the uniformity of the process.

[0069] Figure 5e It shows the execution Figure 6 The intermediate semiconductor structure after operation 603. In Figure 5eIn this configuration, functional layer 503 is formed on dielectric layer 511. In some embodiments, functional layer 503 is a third functional layer. In some embodiments, functional layer 503 is a third etch stop layer. For example, as... Figure 6 As shown, operation 603 may include forming a functional layer 503 by depositing a third etch stop layer (ESL3). In some embodiments, the functional layer 503 is formed of a dielectric material. In some embodiments, the functional layer 503 comprises silicon nitride, silicon carbonitride, silicon carbide, carbon nitride, silicon carbide, etc., or combinations thereof, deposited on the dielectric layer 511 by a suitable deposition process. In some embodiments, the thickness of the functional layer 503 is in the range of about 200 angstroms to 1000 angstroms. In some embodiments, the functional layer 503 is formed of a different material than the first etch stop layer and the second etch stop layer. In some embodiments, the functional layer 503 is formed of silicon nitride and has a thickness of about 500 angstroms. Using a thick functional layer 503 avoids the formation of voids in the functional layer 503 and increases the thickness of the via 213 and the oxide thickness t. ox This could be advantageous. An excessively thick functional layer 503 could increase etching time and the volume of etchant consumed by etching through the functional layer 503.

[0070] Figure 5f It shows the execution Figure 6 The intermediate semiconductor structure after operation 604. In Figure 5f In this configuration, a dielectric layer 512 is formed on the functional layer 503. In some embodiments, the dielectric layer 512 is a second dielectric layer. In some embodiments, the dielectric layer 512 is deposited on the functional layer 503 using a suitable deposition process. In some embodiments, the dielectric layer 512 is formed of a dielectric material. In some embodiments, the dielectric layer 512 may include, or be, silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, spin-coated glass, spin-coated polymer, silicon carbide material, its compounds, its composites, etc., or combinations thereof. For example, such as... Figure 6 As shown, operation 604 may include forming a dielectric layer 512 by depositing a second oxide layer (OX2). In some embodiments, the thickness of dielectric layer 512 is in the range of about 4 kiloangeros to about 30 kiloangeros. In some embodiments, the thickness of dielectric layer 512 is greater than about 5 kiloangeros, greater than about 10 kiloangeros, greater than about 20 kiloangeros, or greater than about 30 kiloangeros. In some embodiments, dielectric layer 512 is formed of the same material as dielectric layer 511. In some embodiments, dielectric layer 512 is formed of USG and has a thickness of about 26 kiloangeros. In some embodiments, dielectric layer 512 is formed of USG and has a thickness of about 25 kiloangeros. A thicker dielectric layer 512 is advantageous for increasing the thickness of via 213 and oxide thickness t. oxA dielectric layer 512 that is too thick will consume more time and material in production and can also adversely affect process uniformity. The combination of dielectric layers 511, 512 and functional layer 503 allows for greater via 213 thickness while etching the dielectric layers 511, 512 in two separate operations, which can improve uniformity and yield.

[0071] Figure 5g An intermediate semiconductor structure is shown after performance of operation 605 of Figure 6 In 5g, a functional layer 504 is formed on dielectric layer 512. In some embodiments, functional layer 504 is a fourth functional layer. In some embodiments, functional layer 504 is a first anti-reflective layer. For example, as shown in Figure 6 operation 605 can include forming functional layer 504 by depositing a first anti- reflective layer (AR1). The first anti-reflective layer serves to mitigate reflection of the underlying layers that are reflective to the light used in subsequent photolithography processes. In some embodiments, functional layer 504 includes or is silicon oxide, silicon oxycarbide, silicon oxynitride, hydrogen-containing silicon oxide, silicon nitride, titanium nitride, tantalum nitride, titanium-containing material, tantalum-containing material, organic material, or any combination thereof. In some embodiments, functional layer 504 includes or is a nitrogen-free material, such as a nitrogen-free oxide. In some embodiments, functional layer 504 includes or is a nitrogen-free silicon oxycarbide. Functional layer 504 is deposited on dielectric layer 512 by any suitable technique, such as CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), spin-on processes, etc. In some embodiments, the thickness of functional layer 504 is in the range of about 300 angstroms to 1000 angstroms. In some embodiments, functional layer 504 is formed of silicon oxynitride and has a thickness of about 600 angstroms. The thickness of functional layer 504 can be selected to be thick enough to prevent voids, thereby providing uniform anti-reflective functionality, while also being thin enough to take into account the material of the layer and the cost of deposition, as well as the cost of etchant material and time to etch the layer and the cost of slurry material and time to planarize / remove the layer.

[0072] Figure 5h An intermediate semiconductor structure is shown after performance of operation 606 of Figure 6 In operation 606, an opening 541 is formed. Opening 541 is formed through functional layer 504, dielectric layer 512, functional layer 503, dielectric layer 511, functional layer 502, and functional layer 501. Opening 541 can be formed using a patterned photoresist layer that defines an opening pattern, followed by a suitable etching process. For example, as shown in Figure 6As shown, operation 606 may include forming opening 541 by at least one first photolithography operation and at least one first etching operation (photolithography + etching 1). The patterned photoresist layer is then removed using any suitable stripping process. Opening 541 exposes a portion of the top surface of the second metal line 212 to provide electrical connection.

[0073] Figure 5i It shows the execution Figure 6 The intermediate semiconductor structure following operation 607. Figure 5i In this configuration, a conductive plug 531 is formed in the opening 541 and on the functional layer 504. For example, as... Figure 6 As shown, operation 607 may include forming a conductive plug 531 by a first chemical copper plating process (ECP 1). The conductive plug 531 substantially fills the removed portion including the functional layer 504, dielectric layer 512, functional layer 503, dielectric layer 511, functional layer 502, and functional layer 501, and directly contacts the second metal wire 212. In some embodiments, 531 is formed of at least one conductive material. In some embodiments, the at least one conductive material is or includes a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, or combinations thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable methods. In some embodiments, the conductive plug 531 is formed using a dual damascene process. In some embodiments, the plating process is a chemical copper plating (ECP) process. In some embodiments, a seed layer is formed on the sidewall of the removed portion prior to the chemical copper plating process. In some embodiments, the seed layer is a barrier seed layer.

[0074] Figure 5j It shows the execution Figure 6 The intermediate semiconductor structure after operation 608. In Figure 5j In this process, the conductive plug 531 is planarized and / or polished to form a conductive via 213. For example, as... Figure 6 As shown, operation 608 may include polishing and / or planarizing the conductive plug 531 by a first chemical mechanical polishing (CMP 1) process. In some embodiments, after the conductive plug 531 is formed and filled into the opening 541, the chemical mechanical polishing (CMP) operation removes any excess material from the conductive plug 531 and any remaining mask, such as the functional layer 504, so that the top surface of the conductive plug 531 is substantially coplanar with the top surface of the dielectric layer 512, as shown. Figure 5j As shown. In some embodiments, after performing operation 608, the thickness of dielectric layer 512 is reduced by approximately 20%. If sufficient flatness can be achieved while polishing away less material from dielectric layer 512, the thickness of dielectric layer 512 can be reduced by less than approximately 20%.

[0075] Figure 5k It shows the execution Figure 6 The intermediate semiconductor structure following operations 609, 610, 611, and 612. Operation 609 includes forming a functional layer 505. In some embodiments, functional layer 505 is a fifth functional layer. In some embodiments, functional layer 505 is an etch stop layer. For example, as... Figure 6 As shown, operation 609 may include forming a functional layer 505 by depositing a fourth etch stop layer (ESL4). In some embodiments, the functional layer 505 is formed of a dielectric material. In some embodiments, the functional layer 505 comprises silicon nitride, silicon carbonitride, silicon carbide, carbon nitride, silicon carbide, etc., or combinations thereof, deposited on the dielectric layer 512 and the conductive via 213 by a suitable deposition process. In some embodiments, the thickness of the functional layer 505 is in the range of about 200 angstroms to 1000 angstroms. In some embodiments, the functional layer 505 is formed of a different material than the first etch stop layer and the second etch stop layer. In some embodiments, the functional layer 505 is formed of silicon nitride and has a thickness of about 500 angstroms. It may be advantageous to use a thick functional layer 505 to avoid the formation of voids in the functional layer 505. An excessively thick functional layer 505 may increase the etching time and the volume of etchant consumed by etching through the functional layer 505.

[0076] Figure 6 Operation 610 of flowchart 60 includes forming a functional layer 506. In some embodiments, functional layer 506 is a sixth functional layer. In some embodiments, functional layer 506 is an anti-reflective layer deposited on functional layer 505. For example, as... Figure 6As shown, operation 610 can include forming a functional layer 506 by depositing a second anti-reflective layer (AR2). In some embodiments, the functional layer 506 is formed of a dielectric material. In some embodiments, the functional layer 506 includes or is silicon oxide, silicon oxycarbide, silicon oxynitride, a hydrocarbon-containing silicon oxide, silicon nitride, titanium nitride, tantalum nitride, a titanium-containing material, a tantalum-containing material, an organic material, or any combination thereof. In some embodiments, the functional layer 506 includes or is a nitrogen-free material, such as a nitrogen-free oxide. In some embodiments, the functional layer 506 includes or is a nitrogen-free silicon oxycarbide. The functional layer 506 is deposited on the functional layer 505 by any suitable technique, such as CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), a spin-on process, etc. In some embodiments, the thickness of the functional layer 506 is in a range from about 200 Angstroms to 1000 Angstroms. In some embodiments, the functional layer 506 is formed of silicon oxynitride and has a thickness of about 600 Angstroms. The thickness of the functional layer 506 can be selected to be thick enough to prevent voids, thereby providing uniform anti-reflective functionality, while also being thin enough to account for the material of the layer and the cost of deposition, as well as the cost of etchant material and time to etch the layer and the cost of slurry material and time to planarize / remove the layer.

[0077] Operation 611 includes forming a dielectric layer 513. In some embodiments, the dielectric layer 513 is a third dielectric layer deposited on the functional layer 506. In some embodiments, the dielectric layer 513 includes or is silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, a spin-on glass, a spin-on polymer, a silicon-carbon material, a compound thereof, a composite thereof, etc., or a combination thereof. For example, as shown in FIG. 5, the dielectric layer 513 is a third dielectric layer deposited on the functional layer 506. Figure 6 As shown, operation 611 can include forming the dielectric layer 513 by depositing a third oxide layer (OX3). In some embodiments, the thickness of the dielectric layer 513 is in a range from about 4,000 Angstroms to about 30,000 Angstroms. In some embodiments, the thickness of the dielectric layer 513 is greater than about 5,000 Angstroms, greater than about 10,000 Angstroms, greater than about 20,000 Angstroms, greater than about 30,000 Angstroms, or greater than about 40,000 Angstroms. In some embodiments, the dielectric layer 513 is formed of USG and has a thickness of about 38,000 Angstroms. The thickness of the dielectric layer 513 can be similar to or slightly greater than a desired thickness of the top metal layer. An overly thick dielectric layer 513 will increase planarization time and material (e.g., slurry) consumed to achieve the desired thickness of the top metal layer. An overly thick top metal layer can cause unnecessary stress, which can lead to delamination in the middle or bottom metal layers.

[0078] 612 includes forming a functional layer 507. In some embodiments, the functional layer 507 is a seventh functional layer deposited on the dielectric layer 513. In some embodiments, the functional layer 507 is an anti-reflective layer. For example, as shown in FIG. 5, the functional layer 507 is a seventh functional layer deposited on the dielectric layer 513. Figure 6As shown, operation 612 may include forming a functional layer 507 by depositing a third antireflective layer (AR3). In some embodiments, the functional layer 507 comprises silicon oxide, silicon carbide, silicon oxynitride, hydrocarbon-containing silicon oxide, silicon nitride, titanium nitride, tantalum nitride, titanium-containing materials, tantalum-containing materials, organic materials, or any combination thereof. In some embodiments, the functional layer 507 comprises a nitrogen-free material, such as nitrogen-free oxides. In some embodiments, the functional layer 507 comprises nitrogen-free silicon carbide. The functional layer 507 is deposited on the dielectric layer 513 using any suitable technique, such as CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), spin coating, etc. In some embodiments, the thickness of the functional layer 507 is in the range of about 200 angstroms to 1000 angstroms. The thickness of the functional layer 507 may be selected to be thick enough to prevent voids, thereby providing uniform antireflective properties, while also being thin enough to account for the material and deposition costs of the layer, as well as the etchant material and time costs of etching the layer and the slurry material and time costs of planarizing / removing the layer.

[0079] Figure 5l It shows the execution Figure 6 The intermediate semiconductor structure following operation 613. In operation 613, an opening 542 is formed. The opening 542 is formed through functional layer 507, dielectric layer 513, functional layer 506, and functional layer 505. The opening 542 can be formed using a patterned photoresist layer that defines the opening pattern, followed by a suitable etching process. For example, as... Figure 6 As shown, operation 613 may include forming opening 542 by at least one second photolithography operation and at least one second etching operation (photolithography + etching 2). The patterned photoresist layer is then removed using any suitable stripping process. Opening 542 exposes a portion of the top surface of conductive via 213 to provide electrical connection.

[0080] Figure 5m It shows the execution Figure 6 The intermediate semiconductor structure after operation 614. In Figure 5m In this configuration, a conductive plug 532 is formed in the opening 542 and on the functional layer 507. For example, as... Figure 6As shown, operation 614 may include forming a conductive plug 532 by a second electroless copper plating process (ECP 2). The conductive plug 532 substantially fills the removed portion including the functional layer 507, dielectric layer 513, functional layer 506, and functional layer 505, which include the opening 542, and directly contacts the conductive via 213. In some embodiments, the conductive plug 532 is formed of at least one conductive material. In some embodiments, the at least one conductive material is or includes a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, or combinations thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable methods. In some embodiments, the conductive plug 532 is formed using a dual damascene process. In some embodiments, the plating process is an electroless copper plating (ECP) process. In some embodiments, a seed layer is formed on the sidewall of the removed portion prior to the electroless copper plating process. In some embodiments, the seed layer is a barrier seed layer.

[0081] Figure 5n It shows the execution Figure 6 The structure 210 follows operation 615. Figure 5n In this process, 532 is planarized and / or polished to form 110. For example, as... Figure 6 As shown, operation 615 may include polishing and / or planarizing the conductive plug 532 by a second chemical mechanical polishing (CMP 2) process. In some embodiments, after the conductive plug 532 is formed and filled into the opening 542, chemical mechanical polishing (CMP) removes any excess material from the conductive plug 532 and any remaining mask, such as the functional layer 507, so that the top surface of the conductive plug 532 is substantially coplanar with the top surface of the dielectric layer 513, such as... Figure 5n As shown. In some embodiments, the thickness of dielectric layer 513 is reduced after operation 615 is performed.

[0082] The above reference Figures 5a to 5n Explained Figure 6 In some embodiments, flowchart 60 includes... Figure 6 The process may be more or less as shown. In some embodiments, the formation of functional layer 502 corresponding to operation 601 is omitted. In some embodiments, operation 614 includes at least two electroless copper plating operations. In some embodiments, a baking operation is performed after operation 613 and before operation 614 and / or after operation 614 and before operation 615. Other embodiments may include additional functional layer deposition operations and / or baking.

[0083] Figure 7is a circuit block diagram of a passive radio frequency device 70 according to some embodiments. In some embodiments, the passive radio frequency device 70 is a radio frequency identification (RFID) transceiver of an RFID tag. Any RFID tag without an internal power source is considered "passive." Passive RFID tags draw power from a received radio frequency signal (typically from an RFID reader device) and then reuse the drawn power to transmit a response to the RFID reader device.

[0084] The passive radio frequency device 70 can include a terminal 720 for receiving a radio frequency signal. In some embodiments, the terminal 720 is electrically connected to an antenna or otherwise includes an antenna.

[0085] A terminal 730 of the passive radio frequency device 70 is an output terminal for transmitting a radio frequency signal. In some embodiments, the terminal 730 includes an antenna. In some embodiments, the terminal 730 and the terminal 720 include the same antenna.

[0086] The circuit 700 of the passive radio frequency device 70 is electrically connected to the terminal 720 and the terminal 730. In some embodiments, the circuit 700 includes one or more of a modulator, a demodulator, a power recovery / harvesting circuit, a clock, a control circuit, a processing circuit, an encoding circuit, a decoding circuit, or a memory.

[0087] The passive radio frequency device 70 includes the inductor circuit 10. In some embodiments, the inductor circuit 10 is for receiving a radio frequency signal. The inductor circuit 10 is electrically connected to the circuit 700. The inductor circuit 10 includes at least the first metal line 211 in the dielectric layer 513, and the via 213 that substantially directly contacts the first metal line 211 and extends through the dielectric layer 511, the dielectric layer 512, and the functional layer 503. As a result of the reduction in C ox , the inductor circuit 10 has an enhanced quality factor, as described above at least with respect to Figure 3 The passive radio frequency device 70 including the inductor circuit 10 has improved sensitivity when receiving a radio frequency signal, and also has improved ability to reject interfering radio frequency signals.

[0088] Figure 8is a circuit block diagram of an active radio frequency device 80 according to some embodiments. In some embodiments, the active radio frequency device 80 is a radio frequency identification (RFID) transceiver of an RFID tag. Any RFID tag having an internal power source is considered "active." Active RFID tags generally do not require power from a received radio frequency signal (typically from an RFID reader device) to obtain power, nor do they require power from the internal power source to transmit a response to the RFID reader device. As such, while the active radio frequency device 80 can include many electronic components similar to the passive radio frequency device 70, the configuration of the electronic components in the active radio frequency device 80 can be quite different from the configuration in the passive radio frequency device 70. As such, in some embodiments, the active radio frequency device 80 includes a different number of electronic components than the passive radio frequency device 70. Figure 8 Different reference numbers are used throughout.

[0089] The terminal 820 of the active radio frequency device 80 is an input terminal for receiving a radio frequency signal. In some embodiments, the terminal 820 includes an antenna.

[0090] The terminal 830 of the active radio frequency device 80 is an output terminal for transmitting a radio frequency signal. In some embodiments, the terminal 830 includes an antenna. In some embodiments, the terminal 830 and the terminal 820 include the same antenna.

[0091] The circuit 800 of the active radio frequency device 80 is electrically connected to the terminal 820 and the terminal 830. In some embodiments, the circuit 800 includes one or more of a modulator, a demodulator, a clock, a control circuit, a processing circuit, an encoding circuit, a decoding circuit, or a memory.

[0092] The power source 810 of the active radio frequency device 80 is electrically connected to the circuit 800. The power source 810 provides power to the circuit 800. In some embodiments, the power source 810 includes at least a battery. In some embodiments, the power source 810 includes a power management circuit.

[0093] The active radio frequency device 80 includes the inductor circuit 10. In some embodiments, the inductor circuit 10 is for receiving a radio frequency signal. The inductor circuit 10 is electrically connected to the circuit 800. The inductor circuit 10 includes at least the first metal line 211 in the dielectric layer 513, and the via 213 that substantially directly contacts the first metal line 211 and extends through the dielectric layer 511, the dielectric layer 512, and the functional layer 503. As a result of the reduction in C ox , the inductor circuit 10 has an enhanced quality factor, as described above at least with respect to Figure 3 The active radio frequency device 80 including the inductor circuit 10 has improved sensitivity when receiving a radio frequency signal, and also has improved ability to reject interfering radio frequency signals.

[0094] Figure 9is a circuit diagram of a voltage-controlled oscillator device 90 according to some embodiments. The voltage-controlled oscillator device 90 outputs a first clock at terminal 920 and a second clock substantially opposite the first clock at terminal 930, both of which are controlled in frequency by a control voltage at terminal 970. Figure 9 The voltage-controlled oscillator device 90 of FIG. 1 illustrates a voltage-controlled oscillator including the inductor circuit 10. In some embodiments, the inductor circuit 10 is used as an on-chip inductor in a voltage-controlled oscillator device that uses a different architecture than that shown in FIG. 1. Figure 9

[0095] The inverter 900 of the voltage-controlled oscillator device 90 outputs a first output signal at terminal 930 that is substantially opposite the first clock at terminal 920. The input terminal of the inverter 900 for receiving the first clock is electrically connected to the output terminal of the inverter 910, the first terminal of the inductor circuit 10, the first terminal of the capacitor 940, and the first terminal of the variable capacitor 950. The output terminal of the inverter 900 for outputting the second clock is electrically connected to the input terminal of the inverter 910, the second terminal of the inductor circuit 10, the second terminal of the capacitor 940, and the first terminal of the variable capacitor 960.

[0096] The inverter 910 of the voltage-controlled oscillator device 90 outputs the first clock at terminal 920 that is substantially opposite the second clock at terminal 920. The input terminal of the inverter 910 for receiving the second clock is electrically connected to the output terminal of the inverter 900, the second terminal of the inductor circuit 10, the second terminal of the capacitor 940, and the first terminal of the variable capacitor 960. The output terminal of the inverter 910 for outputting the first clock is electrically connected to the input terminal of the inverter 900, the first terminal of the inductor circuit 10, the first terminal of the capacitor 940, and the first terminal of the variable capacitor 950.

[0097] The inductor circuit 10, the capacitor 940, the variable capacitor 950, and the variable capacitor 960 form a variable LC tank circuit that is tuned by the control voltage on terminal 970. The first terminal of the inductor circuit 10 is electrically connected to the input terminal of the inverter 900, the output terminal of the inverter 910, the first terminal of the capacitor 940, and the first terminal of the variable capacitor 950. The second terminal of the inductor circuit 10 is electrically connected to the output terminal of the inverter 900, the input terminal of the inverter 910, the second terminal of the capacitor 940, and the first terminal of the variable capacitor 960.

[0098] ​The inductor circuit 10 includes at least a first metal line 211 in the dielectric layer 513, and a via 213 that substantially directly contacts the first metal line 211 and extends through the dielectric layer 511, the dielectric layer 512, and the functional layer 503. As a result of reducing C ox , the inductor circuit 10 has an enhanced quality factor, as described above at least with respect to Figure 3 . As a result of the enhanced quality factor, the phase noise of the voltage-controlled oscillator device 90 is improved.

[0099] The capacitor 940 of the LC tank circuit is a fixed capacitor. In some embodiments, the capacitor 940 is a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or the like. A first terminal of the capacitor 940 is electrically connected to an input terminal of the inverter 900, a first terminal of the inductor circuit 10, a first terminal of the variable capacitor 950, and an output terminal of the inverter 910. A second terminal of the capacitor 940 is electrically connected to an output terminal of the inverter 900, a second terminal of the inductor circuit 10, a first terminal of the variable capacitor 960, and an input terminal of the inverter 910.

[0100] The variable capacitor 950 of the LC tank circuit is a variable capacitor. In some embodiments, the variable capacitor 950 is a metal-oxide-semiconductor (MOS) capacitor. A first terminal of the variable capacitor 950 is electrically connected to an input terminal of the inverter 900, a first terminal of the inductor circuit 10, a first terminal of the capacitor 940, and an output terminal of the inverter 910. A second terminal of the variable capacitor 950 is electrically connected to a second terminal of the variable capacitor 960 and a terminal 970.

[0101] The variable capacitor 960 of the LC tank circuit is a variable capacitor. In some embodiments, the variable capacitor 960 is a metal-oxide-semiconductor (MOS) capacitor. A first terminal of the variable capacitor 960 is electrically connected to an output terminal of the inverter 900, a second terminal of the inductor circuit 10, a second terminal of the capacitor 940, and an input terminal of the inverter 910. A second terminal of the variable capacitor 960 is electrically connected to a second terminal of the variable capacitor 950 and the terminal 970.

[0102] Additionally, the integrated circuit device may include active devices located within or on the substrate 240, and directly or indirectly coupled to at least one of the active devices or inductor 100. Complementary metal-oxide-semiconductor (CMOS) devices and other active and / or passive devices may be included in the integrated circuit device and / or directly or indirectly coupled to inductor 100. Inductor 100 may be advantageous in high-frequency applications of integrated circuit devices. Moreover, implementing inductor 100 into existing manufacturing processes may be simple and cost-effective. For example, inductor 100 can be manufactured using existing manufacturing techniques, as can future technologies. Furthermore, one or more of vias 213 or first metal lines 211 may be formed simultaneously with other existing metallization layers, making it possible to integrate inductor 100 into existing designs without additional process steps.

[0103] To reduce substrate loss factor and self-resonance factor to increase the quality factor of on-chip inductors, a method for increasing oxide thickness t is described. ox Various embodiments of integrated circuit structures and process flows are described. Other embodiments of devices including passive and active radio frequency identification (RFID) transceivers and voltage-controlled oscillators (VCOs) are also described. To improve the inductor quality factor and overall device performance, in some embodiments, the oxide thickness t is increased by extending the upper conductive via through at least two dielectric layers. ox In some embodiments, the oxide thickness is further increased by extending the upper conductive via through at least one etch stop layer located between at least two dielectric layers. The Q-factor of the 0.5 Nahen on-chip inductor is greater than about 22 when using the structure and process described herein. Due to the excellent quality factor of the inductor, the sensitivity of the RFID transceiver or the phase noise of the VCO is improved.

[0104] An embodiment of the device includes a substrate, a first conductive layer, a first conductive via, a plurality of second conductive layers, and a plurality of second conductive vias. The first conductive layer is on the substrate. The first conductive via is between the first conductive layer and the substrate and is electrically connected to the first conductive layer. The thickness of the first conductive via is greater than about 8 kiloangeros. The plurality of second conductive layers are between the first conductive via and the substrate. The plurality of second conductive vias are between the first conductive via and the substrate.

[0105] An embodiment of the method includes forming a first dielectric layer on a first conductive layer. A second dielectric layer is formed on the first dielectric layer. A conductive via is formed extending through the first and second dielectric layers. A third dielectric layer is formed on the second dielectric layer. At least a first conductive portion of the inductor is formed in the third dielectric layer and is in direct contact with the conductive via.

[0106] Another embodiment of a device includes a first dielectric layer, a second dielectric layer, a first etch stop layer, a third dielectric layer, and an inductor. The second dielectric layer is on the first dielectric layer. The first etch stop layer is between the first dielectric layer and the second dielectric layer. The third dielectric layer is on the second dielectric layer. The inductor includes a conductive trace in the third dielectric layer, and a conductive via substantially directly contacting the conductive trace and extending through the first dielectric layer, the second dielectric layer, and the first etch stop layer. A circuit is electrically coupled to the inductor.

[0107] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the aspects of the application. Those skilled in the art should appreciate that they can readily use the application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the application, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the application.

Claims

1. A semiconductor device, comprising: a substrate; a first conductive layer on the substrate; a second conductive layer between the substrate and the first conductive layer; a first conductive via between the first conductive layer and the second conductive layer and the first conductive via is in contact with the first conductive layer and the second conductive layer, the first conductive via has a thickness greater than 8 kilo Angstroms; a plurality of third conductive layers between the first conductive via and the substrate; a plurality of second conductive vias between the first conductive via and the substrate; and a dielectric layer between the first conductive layer and the second conductive layer, the first conductive via extends completely through the dielectric layer, the dielectric layer comprises: a first etch stop layer on and in contact with the second conductive layer, the first etch stop layer is a different material than the second conductive layer; a second etch stop layer on and in contact with the first etch stop layer; a first oxide layer on and in contact with the second etch stop layer, the first oxide layer is a different material than the second etch stop layer; a third etch stop layer on and in contact with the first oxide layer, the third etch stop layer is a different material than the first oxide layer and has a thickness in a range from 200 Angstroms to 1000 Angstroms; a second oxide layer on the third etch stop layer, the second oxide layer is in contact with the third etch stop layer and the first conductive layer, the second oxide layer is a different material than the third etch stop layer; wherein the first conductive layer comprises a first coil segment and a second coil segment, and the first coil segment and the second coil segment are connected by the plurality of third conductive layers.

2. The semiconductor device of claim 1, further comprising an inductor formed at least partially in the first conductive layer and comprising the first conductive via. the thickness of the first conductive via is greater than 10 kilo Angstroms.

3. The semiconductor device of claim 1, wherein, the thickness of the first etch stop layer is between 300 Angstroms and 1000 Angstroms.

4. The semiconductor device of claim 1, wherein, the thickness of the first etch stop layer is 750 Angstroms.

5. The semiconductor device of claim 4, wherein, the first etch stop layer comprises silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, silicon carbide, or a combination thereof.

6. The semiconductor device of claim 1, wherein, the first oxide layer has a thickness in a range from 20 kilo Angstroms to 30 kilo Angstroms and the second oxide layer has a thickness in a range from 20 kilo Angstroms to 30 kilo Angstroms.

7. The semiconductor device of claim 1, wherein, 8. A method of forming a semiconductor device, comprising: forming a first etch stop layer on a first conductive layer; forming a second etch stop layer on the first etch stop layer; forming a first dielectric layer on the second etch stop layer; forming a second dielectric layer on the first dielectric layer; forming a third etch stop layer between the first dielectric layer and the second dielectric layer, the third etch stop layer has a thickness in a range from 200 Angstroms to 1000 Angstroms; forming a conductive via extending through the first dielectric layer and the second dielectric layer; forming a third dielectric layer on the second dielectric layer; and ​ ​ forming at least a first electrically conductive portion of an inductor in the third dielectric layer and in direct contact with the electrically conductive via, wherein the at least first electrically conductive portion includes a first coil segment and a second coil segment, and the first coil segment and the second coil segment are connected by a third electrically conductive layer under the first electrically conductive layer.

9. The method of claim 8, wherein, the electrically conductive via further extends through the third etch stop layer.

10. The method of claim 8, further comprising forming a fourth etch stop layer between the second dielectric layer and the third dielectric layer.

11. The method of claim 10, further comprising forming an anti-reflective layer between the fourth etch stop layer and the third dielectric layer.

12. The method of claim 8, wherein, a thickness of the first etch stop layer is between 300 angstroms and 1000 angstroms.

13. The method of claim 12, wherein, the first etch stop layer includes silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, silicon carbide, or a combination thereof.

14. The method of claim 8, further comprising at least one of: planarizing the electrically conductive via; or planarizing the first electrically conductive portion of the inductor.

15. A semiconductor device, comprising: a first etch stop layer; a second etch stop layer on and in contact with the first etch stop layer; a first dielectric layer on and in contact with the second etch stop layer, the first dielectric layer having a different material than the second etch stop layer; a second dielectric layer on the first dielectric layer; a third etch stop layer between the first dielectric layer and the second dielectric layer, the third etch stop layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer, the first surface opposite the second surface, the third etch stop layer being a different material than the first dielectric layer and the second dielectric layer and having a thickness in a range of 200 angstroms to 1000 angstroms; a third dielectric layer on the second dielectric layer; an inductor, comprising: an electrically conductive trace in the third dielectric layer, wherein the electrically conductive trace includes a first coil segment and a second coil segment, and the first coil segment and the second coil segment are connected by an electrically conductive layer under the first etch stop layer; and an electrically conductive via in direct contact with the electrically conductive trace and extending completely through the first etch stop layer, the second etch stop layer, the first dielectric layer, the second dielectric layer, and the third etch stop layer; and circuitry electrically coupled to the inductor and configured to send or receive electrical signals to or from the inductor.

16. The semiconductor device of claim 15, wherein, a thickness of the electrically conductive via is greater than 8,000 angstroms.

17. The semiconductor device of claim 16, wherein, the inductor has an inductance less than 1 nanohenry.

18. The semiconductor device of claim 17, wherein, the inductor has a quality factor greater than 23.

19. The semiconductor device of claim 15, further comprising an anti-reflective layer between the third dielectric layer and the second dielectric layer.

20. The semiconductor device of claim 15, further comprising a power source electrically coupled to the circuitry.

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