A light load switch control circuit, method and chip

Abstract

The present invention provides a light-load switch control circuit, method, and chip. The light-load switch control circuit includes a comparison module, a timing module, and a control module. The comparison module is used to connect to an external load circuit equipped with a switch tube. The comparison module is configured to obtain the power signal of the external load circuit and compare the power signal with a preset threshold to generate a comparison result. The timing module is configured to output a timing signal at a specified period. The control module is connected to the comparison module and the timing module respectively. The control module is configured to output an enable signal based on the comparison result and the timing signal, so that the external load circuit controls the on / off state of the switch tube based on the enable signal. This circuit can reduce noise generated by circuit frequency changes.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a light-load switch control circuit, method and chip. Background Art

[0002] At present, in order to ensure the stability of the output current / voltage, a sampling circuit is usually set in the circuit. The sampling results of the sampling circuit are compared with the preset interval, and the output current / voltage is controlled according to the comparison results, thus forming an output-feedback-output control closed loop.

[0003] In light-load mode, the so-called "hiccups" and "skip cycles" are usually used to intermittently turn the power conversion circuit on and off to reduce the power consumption of the power system when it is lightly loaded while meeting the load power supply requirements.

[0004] For example, Figure 1 and 2 As shown, the FB pin of the power control chip is introduced into the output sampling circuit to obtain the sampled voltage representing the output voltage. When the sampled voltage is less than the first voltage threshold (Vth1), enable is low, which can control the Gate pin to stop outputting the pulse signal, so that the MOS tube is in the cut-off state, thereby increasing the output voltage. When the output voltage is greater than the second voltage threshold (Vth2), enable is high, which can control the Gate pin to output the pulse signal, so that the MOS tube is in the working state, thereby decreasing the output voltage. In the output voltage control process of the above example, the rising edge moment of the enable output high level to the rising edge moment of the next high level output can be regarded as a cycle ( Figure 2 (Tskip in the output). Because the output load is constantly changing, the cycle also changes. This cycle is related to the frequency of the load change, introducing a low-frequency component into the output. When this low-frequency component approaches the resonant frequency of electronic components in the circuit (such as the transformer), resonance occurs, generating audible noise that shortens the service life of the electronic components and creates noise pollution in the circuit's surroundings, hindering product application and promotion. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the present invention provides a light-load switch control circuit, method and chip, which can reduce noise generated by circuit frequency changes.

[0006] In a first aspect, a light-load switch control circuit includes:

[0007] a comparison module, configured to be connected to an external load circuit provided with a switch tube, the comparison module being configured to obtain a power signal from the external load circuit, and compare the power signal with a preset threshold value to generate a comparison result;

[0008] A timing module is configured to output a timing signal according to a specified period;

[0009] A control module is connected to the comparison module and the timing module respectively, and is configured to output an enable signal according to the comparison result and the timing signal, so that the external load circuit controls the on-off state of the switch tube based on the enable signal.

[0010] In a second aspect, a light-load switch control method is applied to an external load circuit provided with a switch tube, the light-load switch control method comprising:

[0011] Acquire a power signal from a load circuit, and compare the power signal with a preset threshold value to generate a comparison result;

[0012] acquiring a timing signal having a prescribed period; and

[0013] An enable signal is output according to the comparison result and the timing signal, so that the external load circuit controls the on / off state of the switch tube based on the enable signal.

[0014] In a third aspect, a light-load switch control chip includes the light-load switch control circuit described in the first aspect.

[0015] It can be seen from the above technical solutions that the light-load switch control circuit, method and chip provided by the present invention can reduce the noise generated by circuit frequency changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the drawings required for the specific embodiments or the description of the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. Elements or parts in the drawings are not necessarily drawn to scale.

[0017] Figure 1 A circuit diagram of a light-load switch control circuit provided as background technology.

[0018] Figure 2 The timing diagram of the light-load switch control circuit provided as background technology.

[0019] Figure 3 A module schematic diagram of a light-load switch control circuit provided in an embodiment of the present application.

[0020] Figure 4A schematic diagram of a comparison module according to an embodiment of the present application.

[0021] Figure 5 A circuit diagram of a comparison module provided in an embodiment of the present application.

[0022] Figure 6 This is a timing diagram of the light-load switch control circuit provided in an embodiment of the present application.

[0023] Figure 7 This is a circuit diagram of a buck circuit used in an embodiment of the present application.

[0024] Figure 8 This is a circuit diagram of a boost circuit used in an embodiment of the present application.

[0025] Figure 9 Another module schematic diagram of the light-load switch control circuit provided in an embodiment of the present application.

[0026] Figure 10 A schematic diagram of a counting module according to an embodiment of the present application.

[0027] Figure 11 A schematic diagram of the principle of the timing module provided in an embodiment of the present application.

[0028] Figure 12 This is a timing diagram of adding a reset signal to the light-load switch control circuit provided in an embodiment of the present application.

[0029] Figure 13 A schematic diagram of a control module according to an embodiment of the present invention.

[0030] Figure 14 A schematic diagram of a module of a digital unit provided in an embodiment of the present application.

[0031] Figure 15 A circuit diagram of the control module provided in an embodiment of the present application.

[0032] Figure 16 This is a flow chart of a light-load switch control method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following embodiments of the technical solution of the present invention are described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore only examples and are not intended to limit the scope of protection of the present invention. It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0034] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0035] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0036] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0037] Example 1:

[0038] A light load switch control circuit 1, see Figure 3 ,include:

[0039] A comparison module 10 is configured to be connected to an external load circuit 40 having a switch tube 41. The comparison module 10 is configured to obtain a power signal from the external load circuit 40 and compare the power signal with a preset threshold value to generate a comparison result.

[0040] The timing module 20 is configured to output a timing signal according to a specified period;

[0041] The control module 30 is connected to the comparison module 10 and the timing module 20 respectively. The control module 30 is configured to output an enable signal according to the comparison result and the timing signal, so that the external load circuit 40 controls the on / off state of the switch tube 41 based on the enable signal.

[0042] It should be noted that the "external load circuit 40" described in this embodiment refers to the "external" portion relative to the light-load switch control circuit 1, not the "external" portion of the carrier housing the light-load switch control circuit 1. This does not limit the specific location of the "external load circuit 40." Similarly, the same principles apply to the external peripheral circuits and external electronic components described below.

[0043] In this embodiment, the switch tube 41 can be an NPN type switch tube, a PNP type switch tube, etc. In actual application, the manufacturer can select the corresponding type of switch tube 41 according to the actual application requirements of the load circuit 40, and then determine the connection relationship of the switch tube 41. For example, when the load circuit is as follows Figure 1 In the step-down isolation driving circuit shown, the switch tube 41 can be an N-type MOS tube. In this case, the source of the switch tube 41 can be connected to the reference ground terminal, and the drain of the switch tube 41 can be connected to the power supply terminal.

[0044] It should be noted that the light-load switch control circuit 1 provided in this embodiment is particularly suitable for controlling the switch tube 41 with a low switching frequency, that is, the light-load switch control circuit 1 can be applied to the external load circuit 40 with a relatively light load.

[0045] In this embodiment, the external load circuit 40 may include a constant voltage control circuit, a constant current control circuit, etc. It should be noted that, generally speaking, in the external load circuit 40, the current flowing through the external load circuit 40, the voltage of the external load circuit 40, etc. can be controlled by adjusting the on / off state of the switch tube 41. The specific structure of the external load circuit 40 is not specifically limited here.

[0046] In this embodiment, the power signal can be used to represent the power consumption of the external load circuit. For example, the power signal can be a voltage signal and / or a current signal.

[0047] In this embodiment, the threshold value can be set based on the power signal. For example, when the power signal is current, the threshold value can be a preset value related to the current; when the power signal is voltage, the threshold value can be a preset value related to the voltage. Furthermore, when the power signal is current, the current can be converted to a voltage, in which case the threshold value can be a preset value related to the voltage. It should be noted that the number of threshold values can be one or more, and the size of the threshold value can also be set based on actual needs. There is no specific limitation on the number or size of the threshold values herein.

[0048] In this embodiment, the timing signal may be a pulse signal having a predetermined period, and the predetermined period may be set based on actual needs. For example, the rising edge of a pulse in the pulse signal may be used as the starting time of a period, and the rising edge of the next pulse in the pulse signal may be used as the ending time of a period. Alternatively, the falling edge of a pulse in the pulse signal may be used as the starting time of a period, and the falling edge of the next pulse in the pulse signal may be used as the ending time of a period.

[0049] In this embodiment, the comparison module 10 is connected to the control module 30 and the external load circuit 40, respectively. The comparison module 10 obtains a power signal from the output of the external load circuit and compares it with a preset threshold value to generate a comparison result. The timing module 20 is connected to the control module 30 and provides a timing signal. The control module 30 obtains the timing signal and the comparison result and, based on the timing signal and the comparison result, outputs an enable signal (enable) for controlling the on / off state of the switch 41.

[0050] In this embodiment, the control module 30 may output an enable signal according to the timing signal and the comparison result, and the external load circuit 40 may control the on / off state of the switch tube 41 based on the enable signal.

[0051] For example, when the timing signal is a pulse signal with a specified period, the high level or low level of the pulse signal can be used as a valid signal. When the pulse signal is a valid signal, an enable signal corresponding to the comparison result is obtained. For example, if the comparison result includes a first comparison result and a second comparison result, when the pulse signal is a valid signal, the enable signal corresponding to the first comparison result is a high level; when the pulse signal is a valid signal, the enable signal corresponding to the second comparison result is a low level; when the pulse signal is an invalid signal, the enable signal is a low level.

[0052] In this embodiment, the light-load switch control circuit incorporates a timing signal. The control module can, upon obtaining a comparison result, refer to the high and low pulses in the timing signal to output a periodically stable enable signal. Since the timing signal has a specified period, a valid signal in the timing signal is emitted during each specified period. Therefore, when the power signal of the external load circuit 40 fluctuates slightly, the period of the enable signal can be determined to be substantially consistent with the specified period of the timing signal. This reduces the period of the enable signal from shifting, keeping the circuit's cycle frequency stable. Consequently, when configuring other electronic components in the external load circuit 40, the frequencies of the other electronic components can be prioritized to be in different ranges from the frequency of the timing signal. This prevents resonance between the frequency of the enable signal output by the control module and the frequency of the other electronic components, thereby reducing noise. Furthermore, since the period and frequency of the enable signal in the light-load switch control circuit 1 are known, it is particularly convenient to design the external load circuit 40 and the filtering circuit in a targeted manner. Furthermore, through the implementation of this embodiment, the light-load switch control circuit 1 does not need to include a circuit for changing the preset threshold, so that the period of the circuit remains substantially unchanged, thereby reducing the use of electronic components.

[0053] Further, in some embodiments, see Figure 4 , the comparison module 10 includes a first comparison unit 300 and a second comparison unit 400;

[0054] An input terminal of the first comparison unit 300 and an input terminal of the second comparison unit 400 are connected to the load circuit 40; an output terminal of the first comparison unit 300 and an output terminal of the second comparison unit 400 are respectively connected to the control module 30;

[0055] The first comparison unit 300 is configured to obtain the power signal of the external load circuit 40 and compare the power signal with a preset first threshold value to generate a first comparison result; the second comparison unit 400 is configured to obtain the power signal of the external load circuit 40 and compare the power signal with a preset second threshold value to generate a second comparison result;

[0056] In this embodiment, the control module 30 can divide the comparison results into a first result, a second result, and a third result based on the results of the first comparison unit 300 and the results of the second comparison unit 400. The first comparison result includes the power signal being greater than the first threshold and the power signal being less than the first threshold. The second comparison result includes the power signal being greater than the second threshold and the power signal being less than the second threshold. Assuming that the first threshold is greater than the second threshold, the comparison results of the comparison module include the first result, the second result, and the third result, where the first result is that the power signal is greater than the first threshold, the second result is that the power signal is between the first and second thresholds, and the third result is that the power signal is less than the second threshold.

[0057] In this embodiment, assuming that the external load circuit 40 is a constant current control circuit, the power signal is a current signal, and the first threshold value and the second threshold value may be preset values related to the current. If the external load circuit 40 is a constant voltage control circuit, the power signal is a voltage signal, and the first threshold value and the second threshold value may be preset values related to the voltage. Figure 5 , the first comparison unit 300 and the second comparison unit 400 can be comparators.

[0058] Specifically, in order to more clearly understand the working logic of the above light-load switch control circuit, the circuit is applied to the constant voltage control circuit as an example. Figure 6 :

[0059] The power signal can be the output terminal voltage of the external load circuit 40, and the preset threshold can include a first voltage threshold VthH and a second voltage threshold VthL, wherein the first voltage threshold VthH is greater than the second voltage threshold VthL, and the comparison result can include a first result, a second result and a third result, the first result is greater than the first voltage threshold VthH, the second result is between the first voltage threshold VthH and the second voltage threshold VthL, and the third result is less than the second voltage threshold VthL.

[0060] The timing signal can be a first pulse signal with a specified period. The period of the first pulse signal is a preset value. The period can be from the starting moment of the rising edge of the first pulse signal to the starting moment of the rising edge of the next pulse signal, or from the starting moment of the falling edge of the first pulse signal to the starting moment of the falling edge of the next pulse signal.

[0061] When the comparison result is the third result, the enable signal can be controlled to output a low level, regardless of whether the first pulse signal is high. In this case, the second pulse signal is not input to the gate of the switch 41, and the switch 41 is always in the off state. This circuit can use the rising or falling edge of the enable signal as a trigger level. When the trigger level of the enable signal is detected, the switch 41 in the external load circuit 40 is triggered.

[0062] When the comparison result is the second result and the first pulse signal is at a low level, the enable signal can be controlled to output a low level. At this time, the second pulse signal is not input to the gate of the switch tube 41, and the switch tube 41 is always in the off state.

[0063] When the comparison result is the second result and the first pulse signal is high, the enable signal can be controlled to output a high level. At this time, the second pulse signal is input to the gate of the switch tube 41, and the switch tube 41 is in the working state (i.e., the on-off switching state).

[0064] When the comparison result is the first result, regardless of whether the first pulse signal is high, the enable signal can be controlled to output a high level. At this time, the second pulse signal is input to the gate of the switch tube 41, and the switch tube 41 is in the working state (i.e., the on-off switching state).

[0065] Assuming that the switch 41 can be an N-type MOS transistor, the source of the switch 41 can be connected to the reference ground terminal, and the drain of the switch 41 can be connected to the power supply terminal. When the gate of the switch 41 receives a high level, the switch 41 is in an on-off switching state. When the gate of the switch 41 receives a low level, the switch 41 is in an off state.

[0066] Assuming that the switch 41 can be an N-type MOS transistor, the source of the switch 41 can be connected to the reference ground terminal, and the drain of the switch 41 can be connected to the power supply terminal. When the drain of the switch 41 is connected to the voltage terminal, the switch 41 is in the on state. When the drain of the switch 41 is connected to the ground terminal, the switch 41 is in the off state.

[0067] In the above example, since the first pulse signal of the timing signal has a specified period, when the voltage at the output end of the external load circuit 40 is not fluctuating violently, the period of the enable signal outputting high and low levels is the specified period of the first pulse signal. When the power signal is greater than the first voltage threshold VthH, the enable signal outputs a high level, thereby rapidly adjusting the power signal to between the first voltage threshold VthH and the second voltage threshold VthL, so that the period of the enable signal outputting high and low levels is close to the specified period of the first pulse signal. When the power signal is less than the second voltage threshold VthL, the enable signal outputs a low level, thereby rapidly adjusting the power signal to between the first voltage threshold VthH and the second voltage threshold VthL, so that the period of the enable signal outputting high and low levels is close to the specified period of the first pulse signal.

[0068] Since the enable signal outputs high and low levels at fixed cycles, the possibility of resonance caused by the circuit frequency of the present technical solution being the same as the frequency of the electronic components in the circuit is reduced, effectively avoiding the generation of circuit noise and simplifying the design of the output filtering scheme.

[0069] It should be noted that the above example is only one embodiment of the present technical solution. The buck circuit used in the above example is shown in FIG. Figure 7 When the power signal exceeds the first voltage threshold VthH, the control switch 41 is in the on-off switching state, causing the power signal voltage to drop. When the power signal is less than the second voltage threshold VthL, the control switch 41 is in the off switching state, causing the power signal voltage to rise.

[0070] Furthermore, in some embodiments, the present technical solution can also be applied to a boost type constant voltage control circuit, and the external load circuit 40 is shown in FIG. Figure 8 As shown, when the power signal exceeds the first voltage threshold VthH, the control switch 41 is in the off state (enable outputs a low level), causing the power signal voltage to decrease. When the power signal is less than the second voltage threshold VthL, the control switch 41 is in the off switching state (enable outputs a high level), causing the power signal voltage to increase. Therefore, this technical solution can be applied to both boost-type constant voltage control circuits and buck-type constant voltage control circuits, where the state logic of the control switch 41 is opposite.

[0071] Furthermore, in some embodiments, the present technical solution can also be applied to a constant current circuit. When the present technical solution is applied to a constant current circuit, the power signal can be the output current of the external load circuit, the preset threshold can include a first current threshold IthH and a second current threshold IthL, and similarly, the comparison result can include a fourth result, a fifth result, and a sixth result, the fourth result being greater than the first current threshold IthH, the fifth result being between the first current threshold IthH and the second current threshold IthL, and the sixth result being less than the second current threshold IthL. For the method of making the power signal current between the first current threshold IthH and the second current threshold IthL, reference can be made to the process of the above example.

[0072] In the above example, when the power signal is outside the preset interval (for example, between the first current threshold IthH and the second current threshold IthL, and between the first voltage threshold VthH and the second voltage threshold VthL), the state of the timing signal is referred to, and the enable signal is output to control the power signal to be adjusted to the preset interval, so that the period of the high and low levels output by the enable signal enable is close to the specified period of the first pulse signal, thereby providing a stable voltage or current to the load and keeping the frequency of the circuit stable.

[0073] Further, in some embodiments, see Figure 9 , the light-load switch control circuit 1 further includes:

[0074] The counting module 50 is connected to the control module 30 and is configured to obtain the number of pulses received by the switch 41 and output a count result based on the number of pulses. The count result is used to indicate the state of the trigger level in the enable signal output by the control module 30. For example, the counting module 50 can be configured to obtain the number of pulses received by the switch 41. When the pulse number is less than a pulse threshold, the counting module 50 outputs the count result. The count result is used to instruct the control module 30 to output the enable signal at the trigger level.

[0075] In this embodiment, the technical solution may also include a counting module 50, which is connected to the control module 30. The counting module 50 can determine the number of pulses by outputting the rising edge and / or falling edge of the pulse signal to the switching tube 41, and determine whether the enable signal enable outputs a high level based on the number of pulses.

[0076] Further, in some embodiments, see Figure 10 , the counting module 50 includes:

[0077] The clock unit 500 is configured to obtain a clock signal;

[0078] The timing unit 600 is connected to the control module 30 and the clock unit 500 respectively. The timing unit 600 is configured to calculate the duration of the trigger level in the output enable signal based on the clock signal, calculate the number of pulses based on the duration, and enable the control module 30 to output the trigger level when the number of pulses is less than the pulse threshold.

[0079] In this embodiment, taking the application of this technical solution to the above-mentioned step-down constant voltage control circuit as an example, when the number of pulses reaches the preset pulse threshold: if the comparison result is the third result, the enable signal enable maintains a low level; if the comparison result is the second result and the first pulse signal is a low level, the enable signal enable maintains a low level; if the comparison result is the second result and the first pulse signal is a high level, the enable signal enable maintains a high level; if the comparison result is the first result, the enable signal enable maintains a high level. It can be found that when the number of pulses reaches the preset pulse threshold, whether the enable signal enable outputs a high level is consistent with the above example.

[0080] Taking the application of this technical solution to the above-mentioned boost constant voltage control circuit as an example, when the number of pulses does not reach the preset pulse threshold: if the comparison result is the third result, the enable signal enable outputs a high level; if the comparison result is the second result and the first pulse signal is a low level, the enable signal enable outputs a high level; if the comparison result is the second result and the first pulse signal is a high level, the enable signal enable maintains a high level; if the comparison result is the first result, the enable signal enable maintains a high level. It can be found that when the number of pulses does not reach the preset pulse threshold, the enable signal enable will continue to output a high level, thereby effectively stabilizing the cycle of the enable signal enable outputting high and low levels, and preventing the enable signal enable outputting high and low levels from having too short a cycle or too high a frequency.

[0081] See also Figure 11 , when the number of pulses of the second pulse signal is not set, it is easy to happen that: the second pulse signal has only one valid level (the valid level is the level that controls the conduction of the switch tube 41, such as a high level), so that the power signal of the external load circuit 40, but because there is only one valid level, it is possible that the power signal of the external load circuit 40 quickly enters the preset interval (such as between the first current threshold IthH and the second current threshold IthL, between the first voltage threshold VthH and the second voltage threshold VthL), and thus it is necessary to control the second pulse signal to output a trigger level. As a result, the enable signal enable needs to frequently and intermittently output the corresponding trigger level, so that the frequency of the enable signal enable is higher, and the cycle of the high and low levels of the enable signal enable output is shorter, which is not conducive to the frequency of the control circuit.

[0082] When the pulse threshold is set to 3, then when the number of pulses does not reach 3, the enable signal enable continues to output a valid level, reducing the frequency of the enable signal enable and increasing the period of the high and low levels output by the enable signal enable, ensuring that the period of the high and low levels output by the enable signal enable is maintained in a relatively stable range, reducing the possibility of excessive change rate of the high and low levels output by the enable signal enable in a short period of time, and further preventing the possibility of noise generated by circuit frequency changes.

[0083] Furthermore, in some embodiments, the control module 30 is configured to generate a reset signal according to the comparison result and transmit it to the timing module 20;

[0084] The timing module 20 is configured to output a timing signal with a specified period after being reset when receiving a reset signal.

[0085] In this embodiment, see Figure 12 When the comparison result is the first result, regardless of whether the first pulse signal is at a high level, the enable signal enable is controlled to output a high level. At this time, the second pulse signal is input to the gate of the switch tube 41, and the switch tube 41 is in a working state (on-off switching state). At this time, the timing module 20 is reset, and the rising edge of the enable signal enable outputting a high level can be used as the starting time of a new cycle (the falling edge of the enable signal outputting a high level can also be used as the starting time of a new cycle), and the timing signal is re-output.

[0086] Further, in some embodiments, see Figure 13 , the control module 30 includes:

[0087] The digital unit 100 is connected to the comparison module 10, the timing module 20, the counting module 50, and the external load circuit 40 respectively. The digital unit 100 is configured to output an enable signal according to the comparison result and the timing signal;

[0088] The edge detection unit 200 is connected to the comparison module 10 , the timing module 20 , the counting module 50 , and the digital unit 100 , respectively. The edge detection unit 200 is configured to detect a trigger level of the enable signal.

[0089] In this embodiment, the trigger level may be a rising edge or a falling edge. The control module 30 may be implemented by a digital circuit, which implements the control logic and detects the rising edge or the falling edge of the enable signal through an edge detection unit.

[0090] Further, in some embodiments, see Figure 14 , the digital unit 100 includes an enable output component 2000, a first logic component 1000 and a second logic component 3000;

[0091] The enable output component 2000 is connected to the first logic component 1000, the second logic component 3000, the edge detection unit 200, and the external load circuit 40, respectively. The enable output component 2000 is configured to output an enable signal to the external load circuit 40 according to the first signal output by the first logic component 1000 and the second signal output by the second logic component 3000.

[0092] The first logic component 1000 is connected to the timing module 20, the comparison module 10, and the edge detection unit 200 respectively. The first logic component 1000 is configured to output a first signal according to the timing signal and the comparison result;

[0093] The second logic component 3000 is connected to the counting module 50 , the comparing module 10 , and the edge detecting unit 200 , respectively. The second logic component 3000 is configured to output a second signal according to the comparison result and the counting result.

[0094] In this embodiment, the control module 30 includes an enable output component 2000 , a first logic component 1000 , and a second logic component 3000 . The enable output component 2000 outputs an enable signal according to a first signal output by the first logic component 1000 and a second signal output by the second logic component 3000 .

[0095] Further, in some embodiments, see Figure 15 , the external load circuit is a step-down circuit;

[0096] The first logic component includes a first OR gate OR1, a first flip-flop D1, a first AND gate AND1, and a second OR gate OR2; an output end of the edge detection unit U4 is connected to an input end of the first OR gate OR1 and a reset end (R end) of the first flip-flop D1, the other input end of the first OR gate OR1 is connected to an output end (Q end) of the first flip-flop D1 and an input end of the first AND gate AND1, an output end of the first OR gate OR1 is connected to a timing module U1, an output end of the timing module U1 is connected to an S end of the first flip-flop D1, a first output end of the comparison module U2 is connected to the other input end of the first AND gate AND1, an output end of the first AND gate AND1 is connected to an input end of the second OR gate OR2, a second output end of the comparison module U2 is connected to the other input end of the second OR gate OR2, and an output end of the second OR gate OR2 serves as an output end of the first logic component;

[0097] The second logic component includes a third flip-flop D3 and a second AND gate AND2; the output end of the edge detection unit U4 is connected to the reset end (R end) of the third flip-flop D3, the output end of the counting module U3 is connected to the S end of the third flip-flop D3, the output end (S end) of the third flip-flop D3 is connected to one input end of the second AND gate AND2, the third output end of the comparison module U2 is connected to the other input end of the second AND gate AND2, and the output end of the second AND gate AND2 serves as the output end of the second logic component;

[0098] The enable output component includes a second trigger D2, the output end of the first logic component is connected to the S end of the second trigger D2, the output end of the second logic component is connected to the reset end (R end) of the second trigger D2, and the output end (S end) of the second trigger D2 serves as the output end of the digital unit.

[0099] In this embodiment, the timing module U1 may include a timer. The counting module U3 may include a counter. For a circuit diagram of the control module, see Figure 15 The output of the first OR gate OR1 is connected to the clear terminal (Clr) of the timer, the clock terminal (Clk) of the timer is connected to the clock signal, the output of the timer is connected to the S terminal of the first flip-flop D1, and the clear terminal (Clr) of the timer is also connected to the output of the control module. The clock terminal (Clk) of the counter is connected to Drive, and the output of the counter is connected to the S terminal of the third flip-flop D3.

[0100] When the edge detection unit U4 detects a rising edge pulse, or the output terminal (Q terminal) of the first flip-flop D1 outputs a high-level pulse, the first OR gate OR1 outputs a high-level signal. The timer starts timing based on this high-level signal and the clock signal (equivalent to clearing to zero and starting a new round of timing). At the same time, the reset terminal (R terminal) of the first flip-flop D1 receives the rising edge pulse detected by the edge detection unit U4 and resets it, causing the output terminal (Q terminal) of the first flip-flop D1 to output a low level. When the preset timing duration is reached, a high-level signal is input to the S terminal of the first flip-flop D1. Based on the high-level signal received by the S terminal, the output terminal (Q terminal) of the first flip-flop D1 outputs a high-level pulse.

[0101] When the edge detection unit U4 does not detect a rising edge pulse, if the output end (Q end) of the first trigger D1 is a high level, the first OR gate OR1 outputs a high level signal, and the timer continues to count (not reset). When the preset timing duration is reached, a high level signal is input to the S end of the first trigger D1. Based on the high level signal received at the S end, the output end (Q end) of the first trigger D1 outputs a high level pulse.

[0102] When one input terminal of the first AND gate AND1 receives a high level, and the other input terminal of the first AND gate AND1 receives a high level (the output terminal voltage is greater than the second voltage threshold VthL), the output terminal of the first AND gate AND1 outputs a high level to one input terminal of the second OR gate OR2. When one input terminal of the second OR gate OR2 receives a high level, or the other input terminal of the second OR gate OR2 receives a high level (the output terminal voltage is greater than the first voltage threshold VthH), the second OR gate OR2 outputs a high level to the S terminal of the second flip-flop D2, causing the Q terminal of the second flip-flop D2 to output a high-level enable signal.

[0103] When the output terminal voltage is greater than the second voltage threshold VthL and the output terminal (Q terminal) of the first flip-flop D1 outputs a high level, the first AND gate AND1 outputs a high level. Since the second OR gate OR2 performs an OR logic operation, when the first AND gate AND1 outputs a high level, the Q terminal of the second flip-flop D2 outputs a high level enable signal. When the output terminal voltage is greater than the first voltage threshold VthH, the Q terminal of the second flip-flop D2 also outputs a high level enable signal, regardless of whether the output terminal (Q terminal) of the first flip-flop D1 outputs a high level.

[0104] When one input terminal of the second AND gate AND2 receives a high level (the output terminal voltage is less than the second voltage threshold VthL) and the output terminal (Q terminal) of the third flip-flop D3 outputs a high level, the output terminal of the second AND gate AND2 outputs a high level. At this time, the reset terminal (R terminal) of the second flip-flop D2 receives a high level, the second flip-flop D2 is reset, and the output terminal (Q terminal) of the second flip-flop D2 outputs a low level.

[0105] Based on actual logic, at most one of the S terminal and the reset terminal (R terminal) of the second flip-flop D2 receives a high level.

[0106] The edge detection unit U4 can detect the rising edge of the enable output pulse and use it as the detection result. The detection result is input to the reset end (R end) of the first trigger D1, the other input end of the first OR gate OR1, and the reset end (R end) of the third trigger D3. When the edge detection unit U4 detects a rising edge, the output end (Q end) of the first trigger D1 outputs a high level, and the timer starts a new round of timing, thereby realizing synchronous timing and output of the timer and the first trigger D1.

[0107] When the edge detection unit U4 detects a rising edge, the reset terminal (R terminal) of the third trigger D3 receives a high level. At this time, the third trigger D3 performs a reset process and controls the output terminal (Q terminal) of the third trigger D3 to output a low level.

[0108] One input terminal Clk of the counter is connected to the PWM output terminal, the other input terminal en of the counter is connected to the second terminal of the rising edge detection unit U4, and the output terminal of the counter is connected to the S terminal of the third trigger D3. When the edge detection unit U4 detects a rising edge, the other input terminal en of the counter receives a high level, and the counter starts counting, for example, counting the number of PWM pulses output by the PWM output terminal. When the number of pulses reaches a preset number of pulses, the output terminal of the timer outputs a high level to the S terminal of the third trigger D3. At this time, the output terminal (Q terminal) of the third trigger D3 outputs a high level to the other input terminal of the second AND gate AND2.

[0109] The PWM output terminal may be an interface for the control module to output a PWM signal.

[0110] Furthermore, in some embodiments, the prescribed period and the resonant period of the external load circuit are in different intervals.

[0111] In this embodiment, the prescribed period of the timing signal and the resonance period of the external load circuit are in different intervals, which can better prevent the circuit from resonating with other electronic components and reduce noise.

[0112] Example 2:

[0113] A light load switch control method is applied to an external load circuit with a switch tube, see Figure 16 , light load switch control methods include:

[0114] S1: Acquire a power signal from a load circuit, compare the power signal with a preset threshold, and generate a comparison result;

[0115] S2: Acquire a timing signal having a prescribed period; and

[0116] S3: Output an enable signal according to the comparison result and the timing signal, so that the external load circuit controls the on / off state of the switch tube based on the enable signal.

[0117] Preferably, after generating the comparison result, the method further includes:

[0118] generating a reset signal according to the comparison result; and

[0119] It is reset according to the reset signal and outputs a timing signal with a specified period after reset.

[0120] It should be noted that the method provided in the embodiment of the present invention can be consistent with the working principle of the light-load switch control circuit 1 provided in Example 1. For the sake of brief description, for parts not mentioned in this embodiment, reference can be made to the corresponding content in the aforementioned Example 1.

[0121] Example 3:

[0122] A light-load switch control chip comprises the above-mentioned light-load switch control circuit.

[0123] The chip provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference may be made to the corresponding contents in the aforementioned embodiment.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and description of the present invention.

Claims

1. A light-load switch control circuit, characterized in that: include: a comparison module, configured to be connected to an external load circuit provided with a switch tube, the comparison module being configured to obtain a power signal from the external load circuit, and compare the power signal with a preset threshold value to generate a comparison result; the power signal includes a voltage signal and / or a current signal; A timing module is configured to output a timing signal according to a specified period; a control module, connected to the comparison module and the timing module respectively, the control module being configured to output an enable signal according to a comparison result and a timing signal, so that the external load circuit controls the on / off state of the switch tube based on the enable signal; The control module, upon obtaining the comparison result, outputs a periodically stable enable signal based on the high and low conditions of the pulses in the timing signal; When the timing signal is a pulse signal with a specified period, the high level or low level of the pulse signal is used as a valid signal. When the pulse signal is a valid signal, an enable signal corresponding to the comparison result is obtained; wherein the comparison result includes a first comparison result and a second comparison result. When the pulse signal is a valid signal, the enable signal corresponding to the first comparison result is a high level; when the pulse signal is a valid signal, the enable signal corresponding to the second comparison result is a low level; when the pulse signal is an invalid signal, the enable signal is a low level; When the switch tube receives a high level, the switch tube is in the on-off switching state; when the switch tube receives a low level, the switch tube is in the off state; The light-load switch control circuit further includes: A counting module is connected to the control module, and the counting module is configured to obtain the number of pulses received by the switch tube and output a counting result based on the number of pulses. The counting result is used to indicate the state of the trigger level in the enable signal output by the control module.

2. The light-load switch control circuit according to claim 1, characterized in that: The control module is configured to generate a reset signal according to the comparison result and transmit the reset signal to the timing module; The timing module is configured to output a timing signal with the prescribed period after being reset when receiving a reset signal.

3. The light-load switch control circuit according to claim 2, characterized in that: The control module includes: a digital unit, connected to the comparison module, the timing module, the counting module, and the external load circuit, respectively, the digital unit being configured to output an enable signal according to the comparison result and the timing signal; An edge detection unit is connected to the comparison module, the timing module, the counting module, and the digital unit respectively, and is configured to detect a trigger level of the enable signal.

4. The light-load switch control circuit according to claim 3, characterized in that: The digital unit includes an enable output component, a first logic component and a second logic component; The enable output component is connected to the first logic component, the second logic component, the edge detection unit, and the external load circuit respectively, and the enable output component is configured to output the enable signal to the external load circuit according to the first signal output by the first logic component and the second signal output by the second logic component; The first logic component is connected to the timing module, the comparison module, and the edge detection unit respectively, and the first logic component is configured to output the first signal according to the timing signal and the comparison result; The second logic component is connected to the counting module, the comparison module, and the edge detection unit respectively, and is configured to output the second signal according to the comparison result and the counting result.

5. The light-load switch control circuit according to claim 4, characterized in that: The external load circuit is a step-down circuit; The first logic component includes a first OR gate, a first flip-flop, a first AND gate, and a second OR gate; the output end of the edge detection unit is connected to an input end of the first OR gate and a reset end of the first flip-flop, the other input end of the first OR gate is connected to the output end of the first flip-flop and an input end of the first AND gate, the output end of the first OR gate is connected to the timing module, the output end of the timing module is connected to the S end of the first flip-flop, the first output end of the comparison module is connected to the other input end of the first AND gate, the output end of the first AND gate is connected to an input end of the second OR gate, the second output end of the comparison module is connected to the other input end of the second OR gate, and the output end of the second OR gate serves as the output end of the first logic component; The second logic component includes a third flip-flop and a second AND gate; the output end of the edge detection unit is connected to the reset end of the third flip-flop, the output end of the counting module is connected to the S end of the third flip-flop, the output end of the third flip-flop is connected to one input end of the second AND gate, the third output end of the comparison module is connected to the other input end of the second AND gate, and the output end of the second AND gate serves as the output end of the second logic component; The enable output component includes a second trigger, the output end of the first logic component is connected to the S end of the second trigger, the output end of the second logic component is connected to the reset end of the second trigger, and the output end of the second trigger serves as the output end of the digital unit.

6. A light load switch control method, characterized in that: The method is applied to an external load circuit provided with a switch tube, the external load circuit being connected to the light-load switch control circuit according to claim 1, the light-load switch control circuit comprising a comparison module, a timing module, and a control module, and the light-load switch control method comprising: Acquire a power signal from a load circuit, and compare the power signal with a preset threshold value to generate a comparison result; acquiring a timing signal having a prescribed period; and outputting an enable signal according to the comparison result and the timing signal, so that the external load circuit controls the on / off state of the switch tube based on the enable signal; and outputting a periodically stable enable signal with reference to the high and low conditions of the pulses in the timing signal when the comparison result is obtained; When the timing signal is a pulse signal with a specified period, the high level or low level of the pulse signal is used as a valid signal. When the pulse signal is a valid signal, an enable signal corresponding to the comparison result is obtained; wherein the comparison result includes a first comparison result and a second comparison result. When the pulse signal is a valid signal, the enable signal corresponding to the first comparison result is a high level; when the pulse signal is a valid signal, the enable signal corresponding to the second comparison result is a low level; when the pulse signal is an invalid signal, the enable signal is a low level; When the switch tube receives a high level, the switch tube is in the on-off switching state; when the switch tube receives a low level, the switch tube is in the off state; After generating the comparison result, the method further includes: The control module generates a reset signal according to the comparison result; and The timing module is reset according to the reset signal, and outputs a timing signal with the prescribed period after being reset.

7. A light-load switch control chip, characterized in that: The invention comprises the light-load switch control circuit according to any one of claims 1 to 5.

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