Adjustable Current Mode Relaxation Oscillator

Abstract

The present invention discloses a relaxation oscillator, comprising an adjustable reference circuit generator for generating a reference current applied to a charging circuit. The charging circuit is configured to charge a capacitive node according to the reference current and the capacitance of an adjustable capacitor operably coupled to the capacitive node. A comparator has an input terminal operably coupled to a reference voltage node and a capacitive node to generate a comparator output. A control circuit can alternately enable the charging circuit to charge and discharge the capacitive node in response to changes in the comparator output. In addition, the oscillation period of the oscillator output signal output by the control circuit varies with the adjustable capacitance and the adjustable reference current.

Description

Technical Field

[0001] The present invention relates to an oscillator with adjustable current mode, which includes a relaxation oscillator, and is specifically an adjustable current mode relaxation oscillator used in a frequency circuit of an integrated circuit. Background Art

[0002] Integrated circuit products often include oscillators for generating frequency signals. One type of oscillator is called a relaxation oscillator, an example of which is described in Chang, et al., "A Submicrowatt 1.1-MHz Relaxation Oscillator With Temperature Compensation", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–II: EXPRESS BRIEFS, Vol. 60, No. 12, December 2013, pages 837-841.

[0003] Conventional methods of known relaxation oscillators have poor flexibility with respect to adjusting the output period (or frequency) while maintaining temperature compensation to produce a stable output period over an operating temperature range.

[0004]

[0006] It would therefore be desirable to provide an oscillator suitable for use in an integrated circuit that can be adjusted with precision and with a low temperature coefficient over a significant frequency range. Summary of the invention

[0005] The present invention describes an oscillator circuit suitable for generating a frequency signal on an integrated circuit. The oscillator circuit can be adjusted with high accuracy over a wide frequency period range. At least some embodiments of the oscillator circuit maintain a stable output over a certain operating temperature range.

[0006] The oscillator described herein includes an adjustable reference circuit generator for generating a reference current applied to a charging circuit. The charging circuit is configured to charge the capacitive node according to the adjustable reference current and the capacitance of an adjustable capacitor operably coupled to the capacitive node. The comparator has an input terminal operably coupled to a reference voltage node and a capacitive node to generate a comparator output. The control circuit can alternately enable the charging circuit to charge and discharge the capacitive node in response to changes in the comparator output. In addition, the oscillation period of the oscillator output signal output by the control circuit varies with the adjustable capacitance and the adjustable reference current.

[0007] In some embodiments of the oscillator circuit, there are two capacitive nodes and two comparators that are operated out of phase and in coordination with the control circuit to produce the oscillator output.

[0008] The control circuit may be coupled to control registers that store parameters for adjusting the oscillator, including, for example, digital parameters that set a state of the adjustable capacitor and a magnitude of the adjustable reference current.

[0009] Embodiments are described in which the capacitance of an adjustable capacitor has a first state of an oscillator period in a first range and a second state of the oscillator period in a second range. When operating in conjunction with an adjustable reference current, the oscillator period can be adjusted within the first range and the second range with a step size in the output period for each step in the digital value of a control parameter used to set the output period, wherein the step sizes of the first range and the second range are more uniform than the step sizes in a system without an adjustable capacitor.

[0010] Embodiments are described in which the adjustable capacitor comprises a switchable MOS capacitor having a first capacitance in a first state and a second capacitance in a second state.

[0011] Additionally, embodiments are described in which an adjustable reference current generator and a control circuit have respective temperature coefficients, and the temperature coefficient of the adjustable reference current generator offsets the temperature coefficient of the control circuit, thereby producing an output oscillator period that is stable and varies only slightly over the operating temperature range.

[0012] Other embodiments and advantages of the present invention will become apparent after reviewing the following drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Schematic diagram of a current-mode relaxation oscillator circuit with adjustable output period.

[0014] Figure 2A , Figure 2B as well as Figure 2C for Figure 1 . A timing diagram of the oscillator circuit shown in FIG.

[0015] Figure 3 To show the circuit (such as Figure 1 A graph showing the output period of a relaxation oscillator circuit as a function of an adjustable reference current.

[0016] Figure 4is a schematic diagram of an alternative embodiment of a current-mode relaxation oscillator circuit with an adjustable output period.

[0017] Figure 5 An adjustable capacitor comprising a MOS capacitor is shown.

[0018] Figure 6 is a graph of the capacitance of a MOS capacitor as a function of gate voltage and well voltage.

[0019] Figure 7 To illustrate Figure 4 A graph of delay time versus temperature for a circuit element over an operating temperature range.

[0020] Figure 8 Schematic diagram of an alternative embodiment of a current mode relaxation oscillator circuit with adjustable output period and digital parameter input.

[0021] Fig. 9 is the frequency period and frequency step (clock step) relative to the circuit (such as Figure 8 A graph of the input digital parameters of a circuit).

[0022] Fig. 10A For application Figure 8 Schematic diagram of an adjustable reference current generator of a circuit.

[0023] Fig. 10B For control Fig. 10A Schematic diagram of the temperature coefficient adjustable resistor in the circuit.

[0024] Fig.11 To illustrate a circuit with a negative temperature coefficient (such as Fig. 10A A graph of the adjustable reference current versus temperature for a circuit of FIG. 1 .

[0025] Fig.12 To illustrate Figure 8 A graph of the delay of the comparator circuit versus temperature of the circuit.

[0026] Fig.13 is the delay of the relaxation oscillator relative to the circuit (e.g. Figure 8 A graph of the temperature of a circuit).

[0027] Fig.14 A graph of temperature versus delay of a relaxation oscillator is shown for multiple sets of adjustable reference currents.

[0028]

Explanation of symbols

[0029] 100, 800: Adjustable reference current generator

[0030] 101: Reference voltage generator

[0031] 102: First comparator

[0032] 103: Second comparator

[0033] 104: Charging circuit

[0034] 105: Control circuit

[0035] 110:D flip-flop

[0036] 111:NAND Gate

[0037] 112: Inverting buffer

[0038] 404: Charging circuit

[0039] 410, 412: capacitor element

[0040] 411, 413, 530, 531, 1001, 1002: switch

[0041] 500: substrate

[0042] 501: Isolation well

[0043] 502: Channel Trap

[0044] 505 source terminal

[0045] 506: Drain terminal

[0046] 507: Gate terminal

[0047] 510, 520: Contact

[0048] 801: Digitally adjustable current mirror circuit

[0049] 810: Control register

[0050] 1010:Resistance Strip

[0051] 1011, 1012: tap

[0052] 1021, 1022, M0, M1, M2, M3(0), ..., M3(k-1), N1, N2: transistors

[0053] b, b[4:0], b[5], b[5:0]: control signals

[0054] C1, C2: adjustable capacitors

[0055] CLK: output frequency period

[0056] CLK_STEP: Adjustment step

[0057] cmp1, cmp2: output

[0058] k / n IREF: output current

[0059] CTAT, PTAT: absolute temperature

[0060] D: Input

[0061] D0: Second reference voltage

[0062] D1: First capacitive node

[0063] D2: Second capacitive node

[0064] EN, ENB: enable signal

[0065] IREF: Adjustable reference current

[0066] N0: n-channel MOS transistor

[0067] P0, P1, P2, P3, P5, P6, P7: p-channel MOS transistors

[0068] Pwell: Channel well

[0069] Q: Output

[0070] QB: Inverting output

[0071] R0, R1: adjustable resistors

[0072] RES: Resistor

[0073] S1: Second control signal

[0074] S2: first control signal

[0075] TC: Temperature coefficient

[0076] T CMP , T RC :time

[0077] T RO :Frequency period

[0078] T SW :Switch time

[0079] VDD: supply voltage

[0080] VR: First reference voltage

[0081] / b: Complement code DETAILED DESCRIPTION

[0082] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0083] refer to Figures 1 to 14 A detailed description of embodiments of the present invention is provided.

[0084] Figure 1 Schematic diagram of a relaxation oscillator that is adjustable over a wide range of output periods, embodiments of which can operate stably over a wide temperature range.

[0085] exist Figure 1 In the example, the relaxation oscillator includes: an adjustable reference current generator 100; a reference voltage generator 101, which generates a first reference voltage VR and a second reference voltage D0; a charging circuit 104, which includes an adjustable capacitor C1 and an adjustable capacitor C2 configured to charge and discharge two capacitive nodes according to the adjustable reference current and the capacitance of the adjustable capacitor C1 and the adjustable capacitor C2; and a control circuit 105, which is used to alternatively enable the charging circuit to charge and discharge the capacitive nodes in response to changes in the outputs of the two comparators and to provide an oscillator output signal, wherein the oscillator output signal has a frequency and a period that vary with the adjustable capacitance and the adjustable reference current.

[0086] The adjustable reference current generator 100 includes p-channel MOS transistors P0 to P3 configured in a current mirror configuration. Transistor P0 has a drain coupled to an adjustable current source IREF and a source coupled to a supply voltage VDD. The gate and drain of transistor P0 are connected together and to the gate of each of transistors P1 to P3. Each of transistors P1 to P3 mirrors a current to a corresponding output of the adjustable reference current generator, the magnitude of which varies according to the size of transistors P1 to P3 relative to transistor P0.

[0087] The reference voltage generator 101 is coupled to the output of the adjustable reference current generator 100 driven by the transistor P1. The reference voltage generator 101 includes an n-channel MOS transistor N0 having its gate and drain coupled to the node D0 at the drain of the transistor P1, and having its source connected to VSS (in the example herein, VSS is ground, but it can be another reference voltage level) via a resistor RES. Thus, a constant voltage equal to the voltage VR across the resistor RES plus the threshold voltage of the transistor N0 is generated at the node D0.

[0088] The charging circuit 104 includes a first capacitive node D1 and a second capacitive node D2 at the drains of the transistors P2 and P3 , respectively. The first capacitive node D1 and the second capacitive node D2 drive the output of the adjustable reference current generator 100 .

[0089] The first capacitive node D1 is connected to the first terminal of the adjustable capacitor C1 via the transistor N1, and the second terminal of C1 is coupled to VSS. The transistor N1 has its gate connected to the reference voltage at the node D0. The source of the transistor N1 and the first terminal of the adjustable capacitor C1 are connected via a first switch controlled by an enable signal ENB, and the enable signal ENB can connect or disconnect the first terminal of the adjustable capacitor C1 with VSS. In addition, the source of the transistor N1 and the first terminal of the adjustable capacitor C1 are connected via a second switch controlled by a first control signal S2, and the first control signal S2 can connect or disconnect the first terminal of the adjustable capacitor C1 with VSS.

[0090] The second capacitive node D2 is connected to a first terminal of an adjustable capacitor C2 via a transistor N2, and a second terminal of C2 is coupled to VSS. The transistor N2 has its gate connected to a reference voltage at a node D0. The source of the transistor N2 and the first terminal of the adjustable capacitor C2 are connected via a third switch controlled by a second control signal S1, which can connect or disconnect the first terminal of the adjustable capacitor C2 from VSS.

[0091] The first comparator 102 has a first input terminal connected to the first capacitive node D1 and a second input terminal connected to the reference voltage at the node D0. The second comparator 103 has a first input terminal connected to the second capacitive node D2 and a second input terminal connected to the reference voltage at the node D0. The outputs cmp1 and cmp2 of the first comparator 102 and the second comparator 103 are used as inputs supplied to the control circuit 105.

[0092] In this embodiment, the control circuit 105 includes a D flip-flop 110, a NAND gate 111, and an inverting buffer 112. The comparator output cmp1 and the comparator output cmp2 are supplied to the input of the NAND gate 111. The output of the NAND gate 111 is applied to the frequency input terminal of the D flip-flop 110. The D input of the D flip-flop 110 is connected to the inverting output QB of the D flip-flop 110. The output Q of the D flip-flop 110 is the second control signal S1. The inverting output QB of the D flip-flop 110 is the first control signal S2. The restart input of the D flip-flop 110 is driven by the enable signal EN. The input of the inverting buffer 112 is the enable signal EN, and its output is the enable signal ENB.

[0093] In this circuit, the components are connected between the supply voltage VDD and VSS. It should be understood that in other embodiments, the supply voltage and VSS can be replaced by any suitable power supply voltage and reference voltage. For example, the VSS reference voltage node can be connected to DC ground. In other embodiments, the VSS reference voltage node can be connected to AC ground. In other embodiments, the VSS reference voltage node can be connected to other voltage references, which have relative voltage levels determined according to the supply voltage level of a particular embodiment and other embodiments. For example, see U.S. Patent No. 9,876,502, entitled CLOCK INTEGRATED CIRCUIT, issued by Chen et al. on January 23, 2018, which is generally incorporated by reference as if fully described herein.

[0094] See FIG. 2A to FIG. 2C To understand Figure 1 The operation of the circuit, where Figure 2A shows the voltage on the adjustable capacitor C1 and the adjustable capacitor C2 with respect to time, Figure 2B shows the voltage on the capacitive node D1 and the capacitive node D2 with respect to time, and Figure 2C The timing of the second control signal S1 and the first control signal S2 is shown.

[0095] exist FIG. 2A to FIG. 2C In the sequence shown in , the second control signal S1 and the first control signal S2 start from the supply voltage VDD and VSS, respectively, and the adjustable capacitor C1, the adjustable capacitor C2, the first capacitive node D1 and the second capacitive node D2 all start from VSS. When the enable signal EN is set, the enable signal ENB becomes low, which turns off the ENB switch. At this time, the node D1 is allowed to charge as the voltage across the adjustable capacitor C1 gradually increases due to the adjustable reference current through the transistor P2. The voltage at the node D1 is clamped at a level approximately equal to the first reference voltage VR due to the gate voltage of the transistor N1. The voltage at the node D1 continues to increase until it crosses the level D0 as shown by the output cmp1 of the first comparator 102. When the output cmp1 becomes high, the output of the NAND gate 111 changes so that the D flip-flop times the value at the inverted output QB, thereby triggering the change of the second control signal S1 and the first control signal S2. When the second control signal S1 becomes low, the third switch coupled to the adjustable capacitor C2 is opened, and when the first control signal S2 becomes high, the second switch coupled to the adjustable capacitor C1 is closed, thereby grounding the first terminal of the adjustable capacitor C1.

[0096] Therefore, the voltage at the node D1 is maintained at VSS, while the voltage at the node D2 is as follows Figure 2A. Similarly, the voltage at node D1 is grounded, causing the output cmp1 to switch to a low level, while the voltage at node D2 gradually increases. Node D2 gradually increases until the voltage crosses the reference voltage at node D0, at which time the second comparator 103 causes a transition on the signal cmp2. This transition again clocks the D flip-flop, causing transitions in the second control signal S1 and the first control signal S2 to start the next cycle. This situation continues until the enable signal EN goes low.

[0097] The signal on one or both of the Q output and the QB output of the D flip-flop 110 has a frequency period T that varies with the adjustable reference current IREF and the capacitance of the adjustable capacitors C1 and C2. RO .

[0098] In this example, the duty cycle of the frequency is 50%, which is produced by the configuration of the adjustable capacitor and the comparator so that charging and discharging occur at substantially the same rate on both sides of the circuit. In other embodiments, different duty cycles can be implemented using unbalanced capacitors and / or comparators. That is, in some embodiments, the relaxation oscillator can operate relying on a single capacitive node.

[0099] The charging rate of the capacitive node D1 and the capacitive node D2 varies with the current output by the current mirror driven by the transistor P2 and the transistor P3, and the transistor P2 and the transistor P3 can mirror the adjustable reference current IREF, and the adjustable reference current IREF can be adjusted to adjust the period of the output frequency signal. In addition, the charging rate of the capacitive node D1 and the capacitive node D2 varies with the capacitance of the adjustable capacitor C1 and the adjustable capacitor C2, and the adjustable capacitor C1 and the adjustable capacitor C2 can be adjusted to adjust the period of the output frequency signal.

[0100] An adjustable reference current generator and an adjustable capacitor are used in combination in the shown embodiment in a manner that allows a wide adjustment range and a small temperature coefficient.

[0101] Frequency period T RO The characteristic of is based on the time T required to charge the node D1 or the node D2 to the first reference voltage VR when the transistor N1 or the transistor N2 operates in the linear mode. RC plus the time T required to charge the nodes D1 and D2 from the first reference voltage VR to the second reference voltage D0 when the transistor N1 or the transistor N2 is in a saturated state. CMP In addition, the switching time T for changing the control signal cmp1, the control signal cmp2, ​​the control signal S1 and the control signal S2 SWIn this example, the charging circuit is set to operate at a 50% duty cycle, so the delay in the charging cycle of the adjustable capacitor C1 is the same as the delay in the charging cycle of the adjustable capacitor C2, so the output signal T RO The frequency period is equal to the time T RC , time T CMP And the switching time T SW twice the sum of .

[0102] Figure 3 In the case of a constant capacitance on the adjustable capacitors C1 and C2, in the range of about 14.5 μA to 2 μA, the time T CMP A graph is plotted against an adjustable reference current IREF in microamperes (μA). In addition, Figure 3 The diagram is used to determine the time T according to the circuit model CMP The equation represents two components, a first linear factor based on the ratio of the threshold voltage of the transistor divided by the adjustable reference current IREF, and a second nonlinear factor based on β multiplied by the inverse of the square root of the adjustable reference current IREF. As can be seen, the time T CMP is a nonlinear function of the adjustable reference current IREF. Figure 3 Also shown is the contribution delay time T CMP The trace of the nonlinear factor of the adjustable reference current IREF and the contribution delay time T CMP It can be seen that the nonlinear factor closely tracks the delay time T in this model. CMP .

[0103] The nonlinear nature of this trace shows that the output frequency period T can be precisely adjusted. RO is difficult or impractical because for lower adjustable reference currents and longer periods, the time T CMP The nonlinear trace of becomes steeper. Figure 3 In the example circuit model in the figure, the delay time T CMP becomes relatively linear with reference current IREF. However, in the range of 6 microamperes to 2 microamperes, the delay time T CMP It becomes extremely steep with the reference current IREF.

[0104] In the steep region, precise adjustment of the output period of the frequency will require extremely fine adjustment capability of the adjustable reference current IREF, because small step adjustments in the adjustable reference current IREF will cause large changes in the output period. Using digital parameters to set the reference current level in order to implement small step adjustments in the reference current IREF requires a large number of bits in the digital parameters and a complex circuit structure, which may not be practical in some systems.

[0105] The use of adjustable capacitors C1 and C2 can be used to make the curve steeper in the response regions (e.g. Figure 3 This shifting of the graph can be achieved by changing the capacitance for different ranges of output frequency cycles, an example of which is shown in Figure 4 and Figure 8 middle.

[0106] Figure 4 For similar Figure 1 Schematic diagram of a relaxation oscillator, wherein the charging circuit is modified using an adjustable capacitor C1 and an adjustable capacitor C2 implemented by a MOS capacitor having two states. Figure 1 ), in Figure 4 The same reference numerals are used throughout, and these elements are not described again. Figure 4 The charging circuit 404 shown in FIG. 4 includes a transistor N1 and a transistor N2 connected in series with the MOS capacitor C1 and the MOS capacitor C2, respectively. Figure 4 In the embodiment, the adjustable capacitor C1 and the adjustable capacitor C2 include a capacitor element 410 and a capacitor element 412 respectively connected to a switch 411 and a switch 413, through which the second terminals of the capacitor elements are coupled to VSS or to a supply voltage VDD through the switch 411 and the switch 413 in response to a control signal b.

[0107] Figure 5 A structure of a MOS capacitor with two states is shown. Figure 4The structure represented by capacitor element 410 and capacitor element 412 and corresponding switch 411 and switch 413 can be implemented using a MOS transistor structure as shown. The structure is usually formed in a substrate 500 with a light p-type doping. An isolation well 501 is formed in the substrate 500, including an n-type doped region. A channel well 502 with p-type doping is arranged inside the isolation well 501. The substrate 500 and the isolation well 501 are biased (biased) to, for example, VSS and a supply voltage VDD via contacts 510 and 520. In order to form a MOS capacitor, a source terminal 505 and a drain terminal 506 are connected together and form a second terminal of the capacitor in combination with the channel therebetween. A bias is applied to the source terminal 505 and the drain terminal 506, which is also biased to the channel well 502. The first terminal of the capacitor element is formed by the gate terminal 507.

[0108] Switch 530 and switch 531 are connected between isolation well contact 520 and substrate contact 510, respectively. Control signal b and its complement / b are used to control switch 530 and switch 531. When control signal complement / b is high, switch 531 is closed and switch 530 is open, thereby connecting the second terminal of the capacitor to VSS. When control signal b is high, switch 530 is closed and switch 531 is open, thereby connecting the second terminal of the capacitor to supply voltage VDD.

[0109] Similar to Figure 5 The capacitance values ​​of the MOS capacitor C1 and the MOS capacitor C2 in the structure are plotted on Figure 6 As can be seen, when the channel well (channel well Pwell in the graph) is connected to the supply voltage VDD, the capacitance value has a first state at about 600 femtofarads (fF) when the gate voltage is between about zero volts and 1.5 volts. When the channel well is connected to VSS, for example, when the gate voltage is between about 0.5 volts and 2 volts, the capacitance value has a second state at about 100 femtofarads.

[0110] Thus, the adjustable capacitor can be switched between a first capacitive state and a second capacitive state by means of a bias voltage on the source terminal and the drain terminal of the MOS capacitor.

[0111] Figure 7 To plot the delay component contributing to the adjustable period of the relaxation oscillator versus temperature. For a relaxation oscillator, it is desirable to have a temperature coefficient TC that is close to zero across the desired operating range. For the example circuit analyzed for the purpose of this graph, the component T of the delay attributable to the switching time of the control circuit when the comparator switches is SWIt has a slightly negative temperature coefficient, so that the delay value decreases slightly in the temperature range between -40 degrees Celsius and +125 degrees Celsius. The component T attributable to the charging circuit when transistor N1 or transistor N2 is in linear mode RC has a slightly positive temperature coefficient that increases slightly over the temperature range. The component T attributable to the charging circuit when transistor N1 or transistor N2 is in saturation CMP Has a slightly negative temperature coefficient.

[0112] The time T with a temperature coefficient can be established CMP The reference current generator is implemented in a delayed manner. The temperature coefficient offset can be used to make the component T SW and weight T RC The temperature coefficient is shifted so that the component T CMP , Component T SW and weight T RC The combination can have a combined temperature coefficient close to zero.

[0113] This offset is Figure 7 The half period of the relaxation oscillator 0.5×T is marked on the curve using the “x” mark. RO As illustrated by the curve of FIG. 1 , the offset is substantially constant at about 7.9 nanoseconds over the plotted temperature range, where substantially constant means varying by less than 10% over the operating range of temperatures from minus 40 degrees Celsius to plus 125 degrees Celsius.

[0114] Thus, embodiments of the present invention include an adjustable reference current generator that adjusts the components in the circuit for temperature coefficients that cause the balanced combined temperature coefficient (component T SW and weight T CMP ) offset to achieve a very low temperature coefficient.

[0115] Figure 8 For similar Figure 4 Schematic diagram of a relaxation oscillator, wherein an adjustable reference current IREF is used to modify an adjustable reference current generator 800, the relaxation oscillator including a digitally adjustable current mirror circuit 801 in the example shown. Figure 4 ), in Figure 8 The same reference numerals are used throughout, and these elements are not described again. Figure 8The adjustable reference current generator 800 shown in FIG. 8 includes a digitally adjustable current mirror circuit 801 that provides an output current k / n IREF, where n is a constant factor of the adjustable reference current IREF and k is a digitally controlled parameter of the output of the digitally adjustable current mirror circuit 801. Other types of digitally adjustable reference current generators may also be utilized.

[0116] Also in Figure 8 Schematically shown in FIG. 8 is a control register 810 , which may be implemented on the same integrated circuit as the relaxation oscillator circuit, which applies a control signal b[5:0] to set the output frequency period.

[0117] The control register 810 may include non-volatile memory and, in some embodiments, may include write-once memory. In other embodiments, the control register 810 may be a volatile memory such as SRAM. In some embodiments, the frequency cycle is changed during the relaxation oscillator circuit output frequency cycle by writing to the control register 810 to change one or more bits of the control signal b[5:0].

[0118] In this example, the output current k / n IREF has a magnitude set by the control signal b[4:0]. The five-bit control establishes an adjustable reference current IREF in 32 steps.

[0119] The capacitance of adjustable capacitors C1 and C2 are set in this example for two capacitance states by control signal b[5], which in combination with the 32 steps set by the adjustable reference current generator establish 64 adjustable settings for the relaxation oscillator.

[0120] In other embodiments, the adjustable capacitor may be implemented using a passive capacitor combination that is adjusted by a switch. In addition, other types of adjustable capacitors may also be utilized. In this embodiment, only two states of the adjustable capacitor are utilized. In other embodiments, more than two states may be implemented to establish the desired range for adjusting the relaxation oscillator.

[0121] Fig. 9 FIG. 4 is a graph showing the output frequency period CLK and the adjustment step CLK_STEP relative to the setting of the parameter b[5:0] from 0 to 63. FIG.

[0122] In the first range, with parameter settings between zero and 24 (b5=0), the frequency step remains relatively constant at approximately 0.2 nanoseconds per step, and the frequency period increases linearly. In the range of about 25 to 31 program codes, it can be seen that the frequency step increases significantly, and the frequency period also begins to change in a nonlinear manner.

[0123] In the second range, with parameter settings between 32 and about 56, the frequency step size remains relatively constant at about 0.2 nanoseconds, and the frequency period increases linearly. For parameter settings beyond 56, the frequency step size increases significantly, and the frequency period also begins to change in a nonlinear manner.

[0124] To implement an embodiment having a relatively constant step size over a range of output frequency periods from 13 nanoseconds to 21 nanoseconds, the parameter register may be set to a program code value between 0 and 20 (b5 is 0) to set an output period between 13 nanoseconds and 17 nanoseconds, and to a program code value between 40 and 56 (b5 is 1) to set an output period between 17 nanoseconds and 21 nanoseconds. Program code values ​​between 21 and 39 and between 57 and 63 may be omitted because they cause the circuit to operate in a nonlinear regulation step.

[0125] Fig. 10A For application Figure 8 Schematic diagram of an adjustable reference current generator in a circuit of , which can be adjusted to have a temperature coefficient that offsets the temperature coefficients of other components of the relaxation oscillator, thereby producing an overall temperature coefficient close to zero.

[0126] In this example, p-channel MOS transistors P5, P6, and P7 have a source connected to a supply voltage VDD and a gate connected together. In addition, the gate of transistor P7 is connected to the drain. The drains of transistors P5, P6, and P7 are respectively connected to the drains of n-channel transistor M1, n-channel transistor M0, and n-channel transistor M2. The gates of transistors M1 and M0 are connected together and connected to the drain of transistor M1. In addition, the drain of transistor M0 is connected to the gate of transistor M2. The source of transistor M0 and the source of transistor M2 are connected to VSS. The source of transistor M1 is connected to an adjustable resistor R1. The gates of transistors M0 and transistor M1 are connected to VSS via adjustable resistor R0.

[0127] The circuit causes the generation of a reference current IREF at the drain of transistor P7 to transistor M2, thereby having a temperature coefficient TC that can be adjusted by adjusting the values ​​of resistors R0 and R1.

[0128] Fig. 10A The adjustable reference current generator has a gate-to-source voltage based on transistor M0 and resistor R0 (V GS_M0 / R0) and is based on the difference in gate-to-source voltages of transistors M0 and M1 and the value of resistor R1 (ΔV GS(M0,M1)The absolute temperature CTAT and the absolute temperature PTAT operation are maintained through negative feedback of transistors M0, M1 and M2.

[0129] In this circuit, an adjustable current mirror circuit including transistors M3(0) to M3(k-1) is used to generate output current k / n IREF. For example, the transistor width of each of transistors M3(0) to M3(k-1) may have a width equal to that of transistor M2. In this case, output current k / n IREF is a multiple of IREF in transistor M2, which is determined by the number of switches 1001, 1002 that are open or closed. This relationship between output current k / n IREF and reference current IREF can be implemented using transistors of different sizes and various combinations of the magnitude of the control signal as desired.

[0130] Therefore, we can use Figure 8 The digital parameters are used to adjust the output current k / n IREF.

[0131] The temperature coefficient of this circuit is a function of the resistances R0 and R1. The values ​​of the resistances R0 and R1 can be determined for a particular implementation by testing using adjustable resistors and varying the resistances to find the desired result. Alternatively, the values ​​can be determined by simulation or other techniques.

[0132] Fig. 10B An example of an adjustable resistor that can be used in testing to find the proper setting is shown.

[0133] In this example, the adjustable resistor includes a resistive strip 1010 connected to VSS and having a plurality of taps 1011, 1012. In addition, transistors 1021 and 1022 are connected along the resistor from VSS to corresponding taps. The resistance value can be set by establishing the value on the gate of the transistor.

[0134] In the model described herein, using resistor R0 = 252 kOhm and resistor R1 = 23 kOhm, a slightly negative temperature coefficient is obtained which can be used to offset the temperature coefficients of other components of the relaxation oscillator described above.

[0135] Fig.11 FIG. 4 is a graph of adjustable reference current IREF versus temperature for this embodiment, which shows that the adjustable reference current IREF decreases slightly with temperature within the temperature range of -40°C to +125°C.

[0136] For comparison purposes, Fig.12The delay parameter T is shown for the selected embodiment of resistance R0 = 252 kOhm and resistance R1 = 23 kOhm and for the alternative embodiment of resistance R0 = 243 kOhm and resistance R1 = 21 kOhm used in the test operation. CMP Relationship with respect to temperature. As shown, the alternative embodiment has a slightly positive temperature coefficient, while the selected embodiment has a slightly negative temperature coefficient.

[0137] Fig.13 Shows the use of Fig.12 1 . The effect of different embodiments on the period of the output frequency of the relaxation oscillator is plotted in FIG. 1 . As can be seen, for the embodiment with resistance R0 = 252 kOhms and resistance R1 = 23 kOhms, the output period remains substantially constant over the temperature range, varying by less than 0.1 nanoseconds. However, for another embodiment with resistance R0 = 243 kOhms and resistance R1 = 21 kOhms, the output period varies by more than 1 nanosecond over the temperature range.

[0138] Fig.14 To illustrate the simulation under multiple output cycle settings Fig. 10A As can be seen in the curves, each of the settings has a substantially constant frequency period T over the entire temperature range. RO For program code = 12 to program code = 16, some constant frequency period T from 15.39 nanoseconds to 16.36 nanoseconds RO Both have been demonstrated for R0 = 252 kOhm and R1 = 23 kOhm. The same applies to the entire adjustable range, and adjustable resistor R0 and adjustable resistor R1 may be adjusted to produce the desired result.

[0139] A relaxation oscillator is described that can be adjusted across a wide range of output frequency periods, and that can be implemented in a manner that establishes a low temperature coefficient for the range of output frequency periods over a wide range of temperatures.

[0140] A relaxation oscillator is provided that can be adjusted while maintaining a low temperature coefficient, thereby increasing the flexibility and range of applications in which oscillators of this type may be utilized.

[0141] The adjustable relaxation oscillator described herein can be used in a variety of integrated circuit components, including integrated circuit memory components, microcontrollers, mixed signal integrated circuits, system-on-chip (SoC) components, application-specific integrated circuits, field programmable gate arrays, microprocessors, and other components that require an accurate frequency period.

[0142] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An oscillator, wherein: include: an adjustable reference current generator, used to generate an adjustable reference current; a charging circuit including an adjustable capacitor for charging a capacitive node as a function of the adjustable reference current and a capacitance of the adjustable capacitor operably coupled to the capacitive node; a comparator having an input operatively coupled to a reference voltage node and the capacitive node to generate a comparator output; as well as a control circuit for alternately enabling the charging circuit to charge and discharge the capacitive node in response to changes in the comparator output to provide an oscillator output signal having an oscillator period that varies with the adjustable capacitance and the adjustable reference current; The adjustable capacitor comprises: a switchable MOS capacitor having a gate connected to a first capacitor terminal and source and drain terminals connected to a second capacitor terminal; and a switch which connects the second capacitor terminal to a first voltage in response to an input signal to set a first capacitance state for setting an oscillator period within a first range, or to a second voltage to set a second capacitance state for setting an oscillator period within a second range.

2. The oscillator according to claim 1, wherein The adjustable reference current generator and the adjustable capacitor are adjustable in response to digital parameters including the corresponding input signal.

3. The oscillator according to claim 1, wherein: The adjustable reference current generator and the control circuit have respective temperature coefficients, and the temperature coefficient of the adjustable reference current generator offsets the temperature coefficient of the control circuit.

4. The oscillator according to claim 1, wherein: The adjustable reference current generator includes a current mirror circuit having a plurality of output terminals that generate respective currents having different magnitudes, and the adjustable reference current generator switches in response to an input parameter to enable and disable selected output terminals of the plurality of output terminals.

5. The oscillator according to claim 1, wherein The adjustable reference current generator includes a plurality of output terminals that generate respective currents having different magnitudes and is switched in response to an input parameter to enable and disable selected output terminals of the plurality of output terminals.

6. The oscillator according to claim 1, wherein A reference voltage generator is included to generate the reference voltage which varies with the adjustable reference current and a resistor.

7. The oscillator according to claim 1, wherein: A register is included that provides an input to the adjustable reference current generator to set the magnitude of the adjustable reference current and provides an input to the adjustable capacitor to set the state of the adjustable capacitor.

8. The oscillator according to claim 1, wherein The adjustable reference current generator and the control circuit have respective temperature coefficients, and the temperature coefficient of the adjustable reference current generator offsets the temperature coefficient of the control circuit.

9. An oscillator, wherein: include: an adjustable reference current generator, used to generate an adjustable reference current; a charging circuit for charging the first capacitive node as a function of the adjustable reference current and a first capacitance of a first adjustable capacitor operably coupled to the first capacitive node, and for charging the second capacitive node as a function of the adjustable reference current and a second capacitance of a second adjustable capacitor operably coupled to the first capacitive node; a first comparator having input terminals operably coupled to a reference voltage node and the first capacitive node to generate a first comparator output; a second comparator having input terminals operably coupled to the reference voltage node and the second capacitive node to generate a second comparator output; as well as a control circuit for alternately enabling the charging circuit to charge and discharge the first capacitive node and charge and discharge the second capacitive node in response to changes in the first comparator output and the second comparator output, and for providing an oscillator output signal having an oscillator period that varies with the first and second adjustable capacitances and the adjustable reference current; The first adjustable capacitor and the second adjustable capacitor include respective switchable MOS capacitors, each having a gate connected to a first capacitor terminal and source and drain terminals connected to a second capacitor terminal, and a switch that connects the second capacitor terminal to a first voltage to set a first capacitance state for setting the oscillator period within a first range, or to a second voltage to set a second capacitance state for setting the oscillator period within a second range in response to a corresponding input signal.

10. The oscillator according to claim 9, wherein The adjustable reference current generator and the first and second adjustable capacitors are adjustable in response to a digital parameter including the corresponding input signal.

11. The oscillator according to claim 9, wherein The adjustable reference current generator and the control circuit have respective temperature coefficients, and the temperature coefficient of the adjustable reference current generator offsets the temperature coefficient of the control circuit.

12. The oscillator according to claim 9, wherein: The adjustable reference current generator includes a current mirror circuit having a plurality of output terminals that generate respective currents having different magnitudes, and the adjustable reference current generator switches in response to a programmable parameter to enable and disable selected ones of the plurality of output terminals.

13. The oscillator according to claim 9, wherein: The adjustable reference current generator includes a plurality of output terminals that generate respective currents having different magnitudes and is switched in response to a programmable parameter to enable and disable selected ones of the plurality of output terminals.

14. The oscillator according to claim 9, wherein: A reference voltage generator is included to generate the reference voltage which varies with the adjustable reference current and a resistor.

15. The oscillator according to claim 9, wherein A register is included that provides input to the adjustable reference current generator to set the magnitude of the adjustable reference current and provides input to the first and second adjustable capacitors to set states of the adjustable capacitors.

16. The oscillator according to claim 9, wherein: The adjustable reference current generator and the control circuit have respective temperature coefficients, and the temperature coefficient of the adjustable reference current generator offsets the temperature coefficient of the control circuit.

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